Isolation

ISOLATION. –
• Because of the closeness of components in ICs, ISOLATION from each
other becomes a very important factor.
• Isolation is the prevention of unwanted interaction or leakage between
components.
- Because: this leakage could cause improper operation of a circuit.
 How to improve Isolation:
- Techniques are being developed to improve isolation.
- most prominent technique is the use of silicon oxide, which is an
excellent insulator.
- With progress in isolation techniques, the reliability and efficiency of
ICs will increase rapidly.

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 Introduction
The individual components that make up the circuit on a monolithic
die need to have electrical isolation from each other in order to
function properly.
The main idea is to build transistors on the same substrate, that are
electrically isolated from each other.
For this the transistors are
• either surrounded by a reverse biased pn junction
• or surrounded by an insulator
• or in the case of MOS devices ―ringed‖ by a thick oxide layer.
Isolation Techniques
The most common techniques used for achieving component isolation
during wafer fabrication include the following:
1) by employing reverse-biased p-n junctions;
2) through a process called mesa isolation;
3) by wafer bonding to an insulating substrate;
4) by oxide isolation;
5) by trenching; and
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6) through a combination of any of these processes.
 p-n Junction Isolation

↔The most widely used isolation method is based on the fact that :
• a reverse-biased p—n junction in either Si or GaAs has an extremely low
leakage current (in the pico-ampere range at room temperature).
• Thus at room temperature two regions of a semiconductor are effectively
isolated to direct current if they are of the opposite conductivity type and
are suitably reverse-biased.
• The significant coupling between these regions is capacitive in nature,
-hence its effect on the microcircuit has to be considered at high frequencies
only.

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o Historically used for bipolar
o Currently used to isolate NMOS from PMOS through a well

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• Isolation of Resistors:
• The p-n junction is an inherent part of all components and devices.
• Resistor is formed by making a diffusion into a semiconductor substrate of
opposite impurity type
• This Resistor is isolated from substrate as long as a reverse (or zero bias is
maintained across the junction formed in this way.
• Moreover, any number of resistors, placed side by side, will be isolated from
the substrate as well as from each other, provided that this junction bias is
maintained.
• In either silicon or GaAs the reverse-biased p-n junction has an extremely low
leakage current (in the pico-ampere range at room temperature), hence it is
commonly used as an isolation technique during wafer fabrication.
• Thus :
- by doping two adjacent regions with opposite types of conductivity and
providing them with adequate reverse biasing, they become effectively 5
isolated from each other.
• FET Isolation:
• The condition of self-isolation is also met by silicon and GaAs FET
transistors, since all of their regions (source, drain, and channel) are either
reverse- or zero-biased with respect to the substrate.
• Thus no special arrangement has to be made for these devices.
Examples of FET Isolation:
N-Well:
P-Well :
The substrate is N-Type. The N-Channel
device(NMOS) is built into a P-Type well
within the parent N-Type substrate. The P-
channel device is built directly on the
substrate. Vise-Versa Fig. FET Isolation using n-well

• BJT Isolation:
• In silicon-based microcircuits, BJTs are formed by the successive
fabrication of a base and an emitter in a semiconductor substrate.
• All the transistors share a common collector, so that these BJTs are not
self-isolating.
• Thus, each BJT must be put in an appropriately biased separate tub of
opposite conductivity type to the substrate. 6
• This can be done in a number of different ways.
 1. A series of n-type tubs are diffused into a p-type substrate.
• A transistor is made in each tub by two additional diffusions, which form its active
regions.
• Circuit arrangements must be made to ensure that the tubs are reverse- or -zero-
biased.
• This scheme is shown in Fig. 1a, shows a typical dimensions for a conventional diffused
transistor structure in silicon.
• Transistor is called -triple-diffused transistor – have poor performance since their
collector series resistance is excessively large, and are difficult to make, because the
base region is delineated (represented pictorially) by the placement of three diffusions.
• Thus wide-base (2—3 μm) structures are required in this process.
• Recently, new technologies involving precise ion implants , oxide isolation and
refractory contacts have enabled the production of devices with improved gain-
bandwidth product (GBW). P-tub :
The substrate is N-
tubs
refractory contact =a high Type. The N- device
melting point metal, usually is built into a P-Type
tungsten or a mixture of similar well within the
metals in paste form, which is parent N-Type
screen printed onto unfired substrate. The P-type
ceramic sheets (green sheets) in device is built
order to produce metallized directly on the
areas in ceramic packages. substrate. Vise-Versa
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Fig1(a)-Triple diffused junction isolation scheme
2. A second approach is to form isolated tubs by diffusing, through the slice
from both sides.
• each tub contains uniformly doped starting material.
• advantage : the transistors fabricated in them can be of the conventional type.
• However, even with relatively thin substrates, this diffusion step requires at least 40—
50 h at 1250°C.
• This process results in excessive contamination and consequently soft junctions.
• Fig.1b shows a schematic cross section for this process.
• The first bipolar microcircuits were fabricated in this manner, so that it is of historical
importance.
• The modern BJT is fabricated by the double diffused epitaxial (DDE) process.

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Fig1(b)- Two-sided diffused junction isolation scheme
3. In the (double diffused epitaxial) DDE process,
• A thin n-layer is epitaxially grown on a p-type substrate, and isolated tubs are formed in
it by p+ diffusions from the top surface.
• Subsequent ‗base‘ and ‗emitter‘ diffusions result in transistors as shown in Fig. 1( c ).
• The process is similar to the configuration resulting from the two-sided diffused process
of Fig.l (b).
• The single, but all important, difference is in the thickness of the active n-layer.
• This greatly reduces (1)the time required to diffuse the isolation tubs, (2) the wasted area
due to lateral diffusion.
• DDE process is used in the fabrication of those silicon integrated circuits which are based
on the use of BJT devices.
Tub of P+
Thin n-layer diffusions
epitaxially grown

+ + +

substrate

Fig.1 (c) Junction isolation schemes using double-diffused epitaxial process. 9

Isolated tubs are used for fabricating both active and passive components.
 Mesa Isolation:
• Mesa isolation is another technique for achieving component isolation. In this
technique components are build on an active film which was grown on an
insulating (or semi-insulating) film, and then moats are etched around the
components.
• This results in the components becoming individual 'islands', or 'mesas', Gandhi
hence the name 'mesa isolation' given to this isolation technique.
• Circuits fabricated on silicon on insulators, as well as those made on epitaxial
GaAs over semi-insulating (SI) GaAs substrate, are examples of applications
of mesa isolation.
Wafer Bonding
Wafer bonding to an insulative substrate is a variant of mesa isolation.
This isolation technique takes advantage of the fact that any two flat, smooth,
clean, and hydrophilic surfaces can be bonded at ambient temperature
without the use of external forces.
Wafer bonding can be applied to widely dissimilar materials.
Once the moats are etched around the 'mesas', isolation is provided by the
insulating substrate. 10
 Basic Principle: Oxide isolation − Used in early days of MOS
• Oxide isolation techniques consist of a series of − Field can’t be implanted
material deposition and removal steps that leads for parasitic transistor Vt
control
to the formation of active single-crystal tubs that − Step height is too much
are completely surrounded by an oxide layer. mask
• Such oxide layers, once formed, provide near-
perfect isolation between the active tubs. Single crystal Si

Oxide Isolation Process:

• Isolation in silicon-based microcircuits are obtained by the
Single crystal Si
formation of individual tubs of active material, which are
lined with an oxide layer.
• Most practical techniques are based on this process.
Single crystal Si
The process sequence is as follows:
1. An n-type (100) silicon slice is masked with Si02, as
shown in Fig. a, and etched so as to result in the structure
of Fig. b.
• Anisotropic etching, with windows oriented along (110) Single crystal Si

directions, are used to delineate (outline) the V-shaped 11

grooves.
 2. After removal of the mask, an n+ -Layer is diffused across the entire slice.
This layer is heavily doped so as to provide a low-resistance ohmic contact to this region.
3. A thermal oxide is now grown across the wafer.
This oxide becomes the isolation between the single-crystal and the subsequent
polycrystalline silicon, which is next deposited (Fig. d) to a thickness of 250—500 μm.
Considerable stress, accompanied by deformation of the slice, can result from this step.
Sometimes the insulating support can be made with a sandwich of alternating layers of
polysilicon and silicon dioxide to control this stress.
4. The single-crystal side of the slice is now thinned, resulting structure is shown in Fig. e.
• The resulting slice consists of a series of tubs of single crystal silicon, isolated from each
other by a layer of Si02.
• Various active components may be fabricated within these tubs as desired.
• Each tub is lined with an n+ layer which provides a collector connection with a low
parasitic resistance, and is essential if high-performance BJTs are fabricated in them.
Single crystal Si

(e) 12
Advantages & Disadvantages:
• This oxide isolation process results in near-perfect isolation between these
single-crystal tubs.
• Its disadvantage is that considerable thinning of the single-crystal silicon is
required to form the active layer.
• For the thinning, the technique; commonly used is, mechanical polishing in
the early stages, followed by chemical etching with an etch stop layer.
• An alternative approach is to use an electrochemical etch which will stop at
the appropriately doped layer.

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 Self Aligned Mask
Problems of mask alignment during device fabrication:
At the masking stage:
• An overlap is necessary to accommodate tolerances in mask alignment during device
fabrication; essential for MOS device operation.
• But, a parasitic capacitance is caused by overlapping of the gate and drain electrodes
which, limits the high-frequency gain of MOS transistors.
 eg; the MOS transistor, shown in Fig. 1(a).
• Here the overlap ‗L‘ is governed by (i) gate length, (ii) distance between the oxide cuts for
the source and drain, (iii) the lateral diffusion of these regions.
• All of these factors must be carefully controlled to keep the overlap ‗L‘ to a minimum.
• It is also required that the source and drain diffusions be made quite deep (≈2μm), to
ensure that there will be a finite overlap due to lateral diffusion effects.
• But, this increases the parasitic drain capacitance with a further deterioration in device
performance.

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Fig1(a) Conventional masking technique
 Self-aligned Mask:
• The problems caused by overlapping of gate and drain electrodes can be removed if the
gate material can be used as a mask during the source and drain implantations and/or
diffusions.
• Refractory materials (tungsten, titanium and their silicides), capable of withstanding
diffusion and post-implant annealing temperatures, are often used for masking
purposes in microcircuit fabrication.
• The use of a refractory material of this type ensures that there always will be some
overlap between the gate and the source and drain regions, regardless of the amount of
misalignment or lateral diffusion.
• Extremely shallow depths (0.2μm) can be used for the source and drain regions, with a
concurrent reduction in the overlap.
• In addition, these junctions have lower parasitic capacitances and result in smaller area
devices, which produce additional speed advantages.
• Another advantage of using the gate material as a mask is that the overlap is not
dependent on its accurate placement with respect to the field oxide.

• It is shown in Fig.l (b), where

a grossly displaced mask still
yields a satisfactory device.
• Masks of this type are
referred to as ‗self-aligned‘
for this reason.
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Fig.1. Masking techniques. (b) self-Aligned.
 BJT : Self Alignment Techniques
• Self-alignment techniques are important
in VLSI fabrication technology they contact metal

reduce the difficulties of precise

alignment, and allow considerable
shrinkage of the device size.
• One example of this technique is the use
of a washout emitter in a BJT, to form an
ohmic contact to this region.
• This is shown in Fig., where an emitter
contact of this type is compared to one of
the same contact area, made by a separate
alignment step.
Fig. Emitter contact schemes.
• The advantages of this technique are that (a) Conventional. (b) Self-aligned washout emitter.

it reduces the area of the emitter region

by a factor of nine to ten and eliminates
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an additional mask and alignment step.
 Self-alignment cntnd---

Polysilicon gate MOS : Self Alignment Techniques

• Many self-aligned techniques are based on the use of masking materials
which can withstand high-temperature processing steps.
• One such technique, is widely used in the fabrication of polysilicon gate MOS
devices.
• Here a polysilicon mask defines the gate region during source and drain
diffusions.
• This serves to form these regions so that the gate oxide overlaps them (Fig. a),
even when extremely shallow diffusions are used.
• In addition, the gate becomes heavily doped, thus avoiding an additional
process step.

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 Local Oxidation of Silicon (LOCOS)
• LOCOS: localized oxidation of silicon using silicon nitride as a mask against
thermal oxidation.
• This technique - called local oxidation of silicon (LOCOS)
- allows selective growth of thick oxide layers
• CMOS and BiCMOS processes employ LOCOS to grow a thick field oxide over
electrically inactive regions of the wafer

Basic Principle:
• Basic principle of the fundamental oxide isolation structure for ICs is that
thermally grown oxide on silicon can reduce the leakage current by
passivating the surface.
• A breakthrough in the field of isolation technology came in 1970 when it was
realized that Si3N4 was resistant to oxidation.
• This concept applied to selectively oxidize silicon and develop the ‗Local
Oxidation of Silicon‘, or LOCOS, process to electrically isolate devices.

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 LOCAL OXIDATION :PROCESS
• The LOCOS process is based on the fact that
Si3N4 can be used as a mask against thermal
oxidation.
• Si3Ni4 oxidation rate in steam (95°C H20) is about
30 times slower than that of silicon.
• Etches, such as H3P04 can remove Si3N4 but not
attack Si02.
• Figure 1. shows two basic LOCOS structures.
• In both, a layer of Si3N4 is deposited on the
silicon substrate and patterned.
• The processes differ in the pre-etch of the silicon
that is done prior to the local oxidation (Fig. 1b).-
-Resulting structures show that, in each case, the
oxide is countersunk in the silicon.
• As a result, the area of unoxidized silicon is
smaller than the original nitride mask.
• This unoxidized silicon is used to form an active
device.
• Reduced area of unoxidized silicon is an advantage
over regions formed by diffusion, which are larger Fig. 1. Locally oxidized structures. (a)
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than the window that is cut in the mask. Partially recessed. (b) Fully recessed.
 Isolation in BJTs using LOCOS: and its Advantages
-BJTs of equal emitter area, built by
conventional processes and by local oxidation,
are compared in Fig. 3a and 3b.
-The main differences in these structures are
seen in the collector—base junction.
-The device of Fig. 3b has a smaller area
resulting in smaller size and less parasitic
capacitance.
- it has less junction curvature, so that its
breakdown voltage is higher.
-Thus the locally oxidized structure is smaller,
has superior electrical characteristics.

Improved technique:
Thus double nitride masking and oxidation
steps can be used to form the BJT of Fig. 3c,
where both the emitter-base and collector-
base can be made between the counter-sunk
oxide.
Fig. 3. BJT. (a) Conventional. (b) LOCOS.
This produces a reduction in the emitter 20
(c) Doubly oxidized.
capacitance as well.
 Isolation between MOS devices using LOCOS
Isolation between MOS devices in a microcircuit is conventionally obtained by
the growth of a field oxide, which is usually ≥ 1 μm in thickness.
Thus step coverage of the interconnection metal is a particularly severe
problem.
The use of recessed oxides presents an especially powerful approach in this
o
situation, is extensively used for this reason. Figure 4 shows one version
A of a
MOS device formed by this technique.

Field Oxide

Fig.4. MOS device made by local oxidation.

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 Local Oxidation: Advantages
Local oxidation in selected areas is often required in IC fabrication, for example
as isolation regions between adjacent transistors in a MOS process.
An important feature of the LOCOS process is that the nitride film can be used
as a mask against impurity diffusion, as well as oxidation.
Silicon nitride can stop the passage of oxygen so that oxidation is forbidden
under the nitride.
Here the localized oxidation of silicon (LOCOS) serves as the starting point in a
technology that shrinks 4 device size and improves device performance.
In addition, variations of this approach result in preserving the planarity of the
overall microcircuit, thus greatly reducing problems associated with the step
coverage of metal.
• The greatest impact of local oxidation technology has been in VLSI applications
of MOS-based microcircuits.
• This is because all of the advantages of this technology can be simultaneously
exploited here.
• These include: recessed oxides to provide a planar surface; field inversion
channel stops by diffusion or ion implantation, followed by local oxidation; and
extensive use of self-aligned techniques, using Si3N4 as a mask for ion
implantation, diffusion, and local oxidation. 22
 o
Technological Problems of LOCOS technology: A

There are a number of technological problems which arise during the application
of local oxidation technology.
(1) the oxidation of silicon proceeds slightly under the nitride as well.
(2) There is a large mismatch in thermal expansion coefficients of Si3N4 and Si,
which results in damage to the semiconductor during local oxidation.
It has been shown that this damage can be greatly reduced by growing a thin
pad layer of Si02 prior to placement of the Si3N4 mask.
Typically, a 100- to 200- Ao thickness is sufficient for this purpose.
(3) But, this enhances the penetration of oxide under the nitride-masked region,
resulting in structures of the type shown in Fig. 5. These oxide penetrations,
referred to as ―bird beaks,‖ are shown for three different conditions of etching
prior to local oxidation. The bird‘s beak becomes more prominent as the oxide
is made more recessed (indentation or small hollow).

more & more recessed

More recessed
recessed 23
Fig.5. Development of bird beak and crest. (a) No pre-etch.
(b)1000-Ao pre-etch. (c) 2000-Ao pre-etch (fully recessed).