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A high frequency transformer isolation 110V/220V input voltage UPS system

Conference Paper · April 2006

DOI: 10.1109/APEC.2006.1620563 · Source: IEEE Xplore

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 A High Frequency Transformer Isolation 110V/220V
Input Voltage UPS System
René P. Torrico-Bascopé1, Demercil S. Oliveira Jr.2, Carlos G. C. Branco3, Fernando L. M. Antunes4, Cícero M. T. Cruz5
Energy Processing and Control Group, Electrical Engineering Department
Federal University of Ceará
P.O. Box: 6001 – Campus of Pici - 60.455-760 - Fortaleza – CE - BRAZIL
1
rene@dee.ufc.br, 2demercil@dee.ufc.br, 3cgustavo@ieee.org, 4fantunes@dee.ufc.br, 5cicero@dee.ufc.br

Abstract – This paper proposes a double conversion UPS system
with power factor correction, high frequency transformer
isolation and 110V/220V input voltage characteristics. It’s suitable
for rack type structure because it has small size and reduced
weight. For both input voltages, the proposed converter has
almost the same efficiency processing the same output power.
Other relevant features of this structure are: soft commutation of
the controlled switches of the chopper and of the boost stage,
simple control strategy that can be implemented with well-known
integrated circuits and the use of few batteries in series due to
step-up stage. Qualitative analysis and experimental results
obtained from 2kVA laboratory prototype are presented.
I. INTRODUCTION
Nowadays uninterruptible power supply systems are being
used to protect sensitive loads against a wide range of utility
voltage disturbances and power outages. A large amount of
these systems consists in the double conversion UPS
configuration that operates normally with a low frequency
isolation using a silicon-steel core transformer. Such
transformer is placed at the input or at output depending on the
topology arrangement. The addition of this magnetic
component increases both weight and volume, and also add
costs and difficulties in the transportation to the installation
place.
The UPS shown in Fig. 2 was studied in [3]. The circuit is
composes by, a modified PFC current-fed full-bridge pre-
regulator and a voltage source full-bridge inverter, similar to
the previous one. This topology has the advantages of reduced
amount of semiconductors in series during power transfer,
contributing for reduction of conduction losses and improving
efficiency. The disadvantages are hard commutation of the
controlled switches, and many batteries in series to achieve
high DC bus voltage that feed the inverter.
Fig. 3 shows the series-parallel resonant system with
galvanic isolation between the input, the output and the battery
proposed in [4]. This system has the advantages of power
factor correction, single pre-regulator stage, soft commutation
of the controlled switches and few batteries in series. On the
other hand, the disadvantages are: the complex control strategy
and resonant parameters adjustment.
In [5], as shows Fig. 4, a two power conversion stages UPS
was studied. The first stage consists of a PFC-DCM flyback
converter with integrated battery charger, and the second stage
consists of a boost inverter. Due to the discontinuous
conduction mode operation of the flyback converter, the
system is suitable for low power applications (<500W).
L1

During 1990s, the evolution of semiconductors (diodes and T1 T3 T5 T7

transistors) and other components have allowed the C1 Vbat

L2
Vi
development of devices with near-ideal characteristics, making C2 Vo
research on UPS systems with high frequency isolation HF
possible [1-6]. T2 T4 Transf. T6 T8

Several high frequency isolation UPS topologies were

proposed in the literature and some of them are here analyzed. Fig. 1. UPS system proposed in [1, 2].
The UPS scheme shown in Fig.1 was studied in [1-2], and it
consists of a power factor correction (PFC) current-fed full- T1 T3 T5 T7
L1
bridge pre-regulator and a voltage source full-bridge inverter.
L2
In this circuit, hard commutation of the controlled switches Vi
C1
C2 Vo
worsens efficiency and many batteries placed in series
connection are necessary to achieve the high DC bus voltage. HF
T8
T2 T4 Transf. T6
Also, the current drawn by the battery bank is pulsed degrading
the reability of the battery bank.
Fig. 2. UPS system proposed in [3].
This work was supported by Brazilian Research and Projects Financing –
FINEP and CNPQ.

0-7803-9547-6/06/$20.00 ©2006 IEEE. 362

 Lo
Q1 C2 Q5 Q7
T7
L3
L1 L1 C4
Cp/2 Co C1
Vi C6
C1 Vo Vo
Cp/2 HF
T8 Q2 C3 Transf. Q6 Q8
Co

Lin Lb
T1 T3 T5 Q3
Ls1 Ls2 Cs2
Cs1 Vbat L2
Vi Vbat C5
C2
Q4
HF T4 T6
Cs1 T2 Transformer
Fig.5. UPS system proposed in [6].

Fig. 3. UPS system proposed in [4].

The disadvantage of the structure is the necessity of many
batteries in series connection to achieve an adequate inverter
S1
+ bus voltage level, when the battery bank supplies the load,
Lf D1 Do L C
R Vo
because of the bi-directional converter that operates as buck.
Co
S2 In Brazil, utility low-voltage levels are 110V or 220V,
L1 L3 -
Cf
single-phase rms voltage. Therefore, to satisfy such
Vi
Q1 requirements, a flexible input voltage UPS system is proposed
Q2 S3
in Fig. 6.
L C
The advantages of the proposed system shown in Fig. 6 are
Q3
S4 soft commutation of the controlled switches of the chopper and
Vbat boost stages, avoiding snubber circuits and EMI problems,
HF
L2
Transf. power factor correction, high frequency operation of the
transformer with both input voltages, use of well-known
Fig. 4. UPS system proposed in [5]. conventional PWM control techniques and few batteries in
series due to step-up stage. As a disadvantage, there are three
Fig. 5 shows a detailed circuit diagram of the UPS reported power stages, which could imply in reduction of the system
in [6]. The circuit consist basically of, a ZCS partial series overall efficiency.
resonant DC-DC converter, a dynamic power compensator The operation with two input voltage levels, the cascade
given by a bi-directional converter, and a voltage source full- operation of the chopper and the boost stage, and the
bridge inverter. Advantages of the circuit are: power factor possibility of achieving soft commutation of the chopper
correction, soft commutation of the ZCS-PSRC converter and switches using coupling inductors, were obtained from [3,8,9].
inverter switches that operates with 50Hz commutation
frequency.

Vi Vab Vcd Vbus Vo

0 t 0 t 0 t 0 t 0

RECTIFIER CHOPPER Dr1 Lb Db BOOST INVERTER

a c
D1 D2 S3 S7 S5 Lfi
Lf S1 Lr1
Cf1 R1
S
220V Np Ns R3
SS M +
Vi Cb Cfi Vo
110V Sb
Np Ns +
R4
R2
Tr Dr2 Batteries
Cf2 Lr2
S2 S4 S6
D3 D4 S8
b d
Sb S5 S6 S7 S8
S1 S2 S3 S4 Sample Input
Voltage
Boost Inverter
Chopper
Control Control
Control + +
Vi - Vrefb - Vrefi

Fig. 6. Proposed UPS system.

363
 L = Lr1 = Lr 2 . (5)
II. DESCRIPTION OF THE PROPOSED TOPOLOGY
Substituting (2), (3), (4), and (5) in (1), ∆D is obtained, as in
The proposed UPS is shown in Fig. 6, it is composed by the 2 Lr1 f s nI Lb ( pk ) sin(θ )
following parts: a full-bridge rectifier given by diodes D1-D4; a ∆D = , (6)
full-bridge chopper given by controlled switches S1-S4, high Vi ( pk )110V sin(θ )
frequency transformer Tr, commutation coupled inductors Lr1- where Lr1 is the commutation inductance, fs is the commutation
Lr2, and rectifier diodes Dr1-Dr2; a classical boost circuit given frequency, n is the transformer turns ratio, ILb(pk) is the peak
by inductor Lb, switch Sb, diode Db and capacitor Cb; a full- current through boost inductor, and Vi(pk) is the input peak
bridge inverter given by controlled switches S5-S8, inductor Lfi, voltage. The rms chopper output voltage that also feed the
and capacitor Cfi; and, a high frequency input filter given by boost converter is given by:
inductor Lf and capacitors Cf1 and Cf2. 1π
( )
2
Vcd ( rms ) = ∫ 2 ( D − ∆D ) nVi ( pk )110V sin (θ ) dθ . (7)
III. ANALYSIS OF THE CHOPPER OPERATION WITH INPUT π 0
VOLTAGE EQUAL TO 110V Simplifying (7) yields
A. Principle of Operation Vcd ( rms ) = nVi ( pk )110V ( D − ∆D ) , (8)
The chopper operates with fixed duty cycle (D≅0.5) using where Vcd(rms) is the rms chopper output voltage, and D is the
PWM modulation obtained from integrated circuit UC3525A. duty cycle. The inductor peak current is calculated using
The control strategy allows the application of high frequency 2 Po
voltage pulses to the primary windings of the transformer Tr, I Lb ( pk ) ≅ , (9)
Vcd ( rms )
enabling the use of a high frequency transformer.
When the input voltage is 110V, the selector switch SS where Po is the active output power of the UPS.
iS1
(manual or automatic) must be turned on and adjusted to the S3 S1
+
vS1
110V position point. Under this condition, diodes D2 and D4 Lf
D1 D2
Cf1 -
Dr1 c
are always reverse biased. 220V Lr1
iLr1+ vLr1 -
SS Ns
During the positive semi-cycle of the input voltage, in one Vi
M
Np

switching period, the converter presents mainly two power 110V

Np Ns
ILb

transfer intervals as shown in Fig. 7 according to the iLr2 Lr2 Dr2

- vLr2 +
waveforms in Fig. 8. The operation of the topology in the D3 D4
Cf2
S2
d
S4
negative semi cycle of the input voltage is analogous to the
positive one. Interval (t1-t2)
During the commutation intervals, mutual energy iS1
+
transference occurs between the coupled commutation D1 D2
S3 S1 vS1
Cf1 -
inductors Lr1 and Lr2 in order to charge and discharge the Lf
220V Lr1-
Dr1 c

iLr1+vLr1
output intrinsic capacitances of the controlled switches of the SS
Np Ns
110V M
chopper, and so to guarantee ZVS commutation of them. Such Vi
ILb

commutation intervals are explained in [9]. iLr2 Lr2

Np Ns
Dr2
When the input voltage is 110V, the input current is twice Cf2
- vLr2 + d

than in 220V, so that the output power is maintained. As one D3 D4 S2 S4

can see in Fig. 7, only one controlled switch of the chopper is

involved during energy transference, and consequently Interval (t5-t6)
Fig. 7. Operating stages of the chopper circuit when the input voltage is 110V.
conduction losses are reduced.
In the chopper, the duty cycle reduction, ∆D, occurs due to
Ts/2 Ts
S1, S2
S3, S4 t
the linear variation of the current through the commutation DTs
t

inductors (Lr1, Lr2) and transformer leakage inductances. ∆ DTs

During this condition, there is no power transfer from the input. VLr1
iLr1
Vi
nILb

The duty cycle reduction is reflected in the transformer

secondary voltage. The duty cycle reduction is found from the t

inductor voltage equation given by VLr2

Vi -Vi
iLr2
∆iL
vL = L , (1)
∆t t

where -nILb

vL = Vi ( pk )110V sin (θ ) ,
-Vi

(2) vS1
iS1 vS1
2Vi

nILb
iS1
∆iL = 2nI Lb ( pk ) sin(θ ) , (3)
t

∆t = ∆DTs , (4)
to t1 t2 t3 t4 t5 t6 t7 t8

Fig. 8. Main theoretical waveforms when the input voltage is 110V.

364
 IV. ANALYSIS OF THE CHOPPER OPERATION WITH INPUT S1, S2 Ts/2 Ts

VOLTAGE EQUAL TO 220V S3, S4

t

A. Principle of Operation VLr1 Vi/2

t

iLr1 nILb/2

In this mode, the selector switch SS must be set to the 220V

t
position point. The control strategy is the same one used when -nILb/2

input voltage is 110V. VLr2

iLr2
Vi/2 -Vi/2

During the positive semi-cycle of the input voltage, the nILb/2

proposed topology presents mainly two power transfer t

-nILb/2
intervals as shown in Fig. 9, according to the waveforms in Fig. -Vi/2
10. The commutation process is similar to that presented for vS1
iS1 vS1
Vi

full-bridge ZVS-PWM DC-DC converters. The operation of iS1

nILb/2

the topology in the negative semi cycle is analogous to the t

positive one. Although the current flows simultaneously

through both inductors when the chopper operates with 220V,
to t1 t2 t3 t4 t5 t6 t7 t8

Fig. 10. Main theoretical waveforms when the input voltage is 220V.
the equivalent commutation inductance, considering the mutual
inductance and coupling coefficient next to unity, is equal to c Lb Ls Db
four times Lr1 or Lr2 i.e. Lreq = 4 Lr1 = 4 Lr 2 . +
ILb Cs1
According to Fig. 9, there are always two controlled +
+
semiconductors involved in power transference. Although the Vcd Sb Cs2 Snubber
Co Vbus
input voltage is twice that in Section III, the current through the
semiconductors is reduced to a half. Therefore, losses are -

approximately equal when the converter operates with 110V. d

Fig. 11. Boost converter stage.

V. BOOST CONVERTER STAGE
VI. BATTERY CHARGER STAGE
A classical boost converter, shown in Fig. 11, was
connected to the output of the chopper. It is responsible for The battery charger is based on a small non-isolated buck
regulation of the output voltage, power factor correction, and converter as shown in Fig. 12. The converter operates in
the step of battery bank voltage up to the output voltage Vbus. continuous conduction mode (CCM) of the current through the
Additionally, this stage provides an active filtering to block the filter inductor and is supplied with the output voltage of the
pulsating current of the non-linear load (inverter stage) from boost converter.
the battery bank. Switch Sb operates with zero voltage As the voltage across terminals c-d is chopped and
switching in a wide range of output power using a passive non- modulated in 120Hz, a controlled switch St is necessary due to
dissipative snubber circuit [10]. The Boost converter is the voltage characteristic at this point. For this application, the
controlled using conventional average current-mode-control thyristor device is used. Switch St is turned-on when AC main
implemented with the well-known PWM integrated circuit voltage is off or out of input voltage range and it is turned-off
UC3854 for power factor correction [7]. when AC main voltage is suitable for operation.
iS1
+
D1 D2
Cf1
S3 S1
-
vS1 VII. INVERTER STAGE
Lf Lr1 Dr1 c
220V
SS iLr1+ vLr1
- In the output of the boost stage, a classical voltage source
Vi M
Np Ns
full-bridge inverter was connected to convert the DC bus
ILb
110V
Np Ns
voltage in AC output voltage to feed the load. In order to
iLr2 Lr2 Dr2 control the output voltage, sinusoidal PWM technique with
- vLr2 +
D3 D4
Cf2
S2
d
unipolar voltage switching was applied. The inverter presents
S4
hard commutation of the controlled switches. To protect the
switches against over-voltages, a RCD clamping snubber
Interval (t1-t2)
iS1
circuit was placed in each inverter leg.
+
S3 S1
D1 D2 Db
Lf
Cf1 - c c Lb BOOST
Lr1 Dr1
220V -
SS + +
iLr1 vLr1
Ns
M Np St Sb
Vi ILb
110V
Np Ns Vbus
iLr2 Lr2 Dr2 Lch Sch
+ + +
Cf2 - vLr2 +
d Vbat Cch Dch Cb
D3 D4 S2 S4 BATTERIES
-

d BATTERY CHARGER
Interval (t5-t6)
Fig. 9. Operating stages of the chopper circuit when the input voltage is 220V. Fig. 12. Battery charger scheme.

365
 VIII. SIMPLIFIED DESIGN EXAMPLE 2 ⋅110 ⋅ 0.048
Lr1 = Lr 2 = = 3.85µ H .
2 ⋅ 50000 ⋅1 ⋅19.36
A. Preliminary Specifications
The input filter capacitances must be small, so are arbitrarily
The design specifications of the proposed UPS system are chosen as C f 1 = C f 2 = 6.6µ F . Thus, the filter inductance is
shown in Table I. The switching frequency of the converters
1
was assumed fs=50kHz. Lf = ≅ 137.18µ H . (11)
C f ( eq ) ( 0.94 f s )
2
TABLE I. UPS SPECIFICATION
Mains input voltage Vi = 110Vac / 220Vac C. Design Procedure of the Boost Converter Circuit
AC mains frequency fr = 60Hz
The boost inductor and filter capacitor are obtained
Output voltage Vo = 110Vac according to [7]. Thus,
Maximum active output power Po = 1400W 2Vcd ( rms ) Dboost
Maximum apparent output power So = 2kVA Lb = = 338.60 µ H , (12)
f s ∆ILb max
AC output frequency fo = 60Hz
2 Po ∆t
The design parameters of the UPS system stages are listed in Co = = 2167.9µ F , (13)
Vbus 2 − V12
Table II.
TABLE II. DESIGN PARAMETERS OF THE UPS STAGES
where,
• Chopper Circuit: 2Vcd ( rms )
Dboost = 1 − = 0.34 . (14)
Transformer turns ratio n = Ns / N p = 1 Vbus
Maximum duty cycle Dmax = 0.48 D. Design Procedure of the Battery Charger Circuit
Maximum duty cycle reduction ∆Dmax = 0.048 The inductance of the filter inductor is substituting the
Input filter resonant frequency f f = 0.15 f s design parameters values in
• Boost Circuit: V (1 − Dch )
Lch = bat = 11.01mH . (15)
Boost inductor current ripple ∆ILb max = 0.15ILb ( pk ) f s ∆I ch
DC link output voltage Vbus = 220V The capacitance of the filter capacitor and equivalent series
Hold-up time ∆t = 8.333 × 10 −3 s resistance are calculated using
Minimum DC link output voltage V1 = 190V ∆I ch
Cch = = 1.25µ F , (16)
• Battery Charger Circuit: 8 f s ∆Vbat
Maximum battery voltage Vbat = 108V
∆Vbat
Maximum battery charge current I ch = 1A Rse ≤ ≤ 2Ω . (17)
Current ripple through the filter inductor ∆I ch = 0.1A ∆I ch
Duty cycle of the buck converter Dch = 0.49 The prototype was implemented with an electrolytic
Voltage ripple across battery bus ∆Vbat = 0.2V capacitor of 100µF/250V.
• Inverter Circuit: E. Design Procedure of the Voltage Source Inverter Circuit
Modulation index ma = 0.71
The inductance of the filter inductor is obtained substituting
Filter inductor ripple current ∆IL fi = 2.7 A
the design parameters values in
B. Design Procedure of the Chopper Circuit
L fi ≅
(Vbus − 2Vo ma ) = 170µ H . (18)
The rms output voltage of the chopper is calculated using 2 f s ∆IL fi
(8). Thus,
The resonance frequency of the inverter output LC filter
Vcd ( rms ) = 1⋅ 2 ⋅110 ⋅ ( 0.48 − 0.048) = 102.25V . applying unipolar voltage switching technique is given by
The peak output current of the chopper is determined using 2f
(9). Substituting, f fi ≤ s . (19)
10
2 ⋅1600 From (19), the inverter output filter capacitor must be higher
I Lb ( pk ) ≅ ≅ 19.36 A .
102.25 than Cfi ≥ 14.7µF. The prototype was implemented with a
The coupled inductors inductance is obtained from (6) metalized polypropylene film capacitor of 30µF/250Vac.
considering θ = π 2 . Therefore, the corresponding equation is
given by IX. EXPERIMENTAL RESULTS
Vi ( pk )110V ∆Dmax In order to verify the feasibility and performance of the
Lr1 = Lr 2 = . (10) proposed UPS system, a laboratory prototype was implemented
2 f s nI Lb ( pk )
and evaluated. The experimental results consist of relevant
Substituting values in (10), the inductances of the coupled voltage and current waveforms, and also efficiency and power
inductors are given by factor curves.

366
A. Waveforms and Curves for 110V Input Voltage
Fig. 13 shows the input voltage and input current waveforms
where high power factor is observed. Fig. 14 shows the voltage
and the current waveforms though switch S1, where soft
commutation details are observed. The output voltages and
currents of the inverter are shown in Figs. 15 and 16, where it
can be seen a high quality sinusoidal voltage waveform,
independently of the characteristic of the connected load. Fig.
17 shows efficiency curve, as a function of output power.
Finally, Fig. 18 illustrates the power factor behavior as a
function of the output power.
B. Waveforms and Curves for 220V Input Voltage
The corresponding waveforms for 220V input voltage are
shown from Figs. 19 to 24. The analysis of the waveforms and
curves is similar to the case when the input voltage is 110V.

Fig. 13. Mains input voltage and current Fig. 14. Voltage and current of the chopper switch Fig. 15. Output voltage and current of the inverter
(50V/div.; 10 A/div.; 2ms/div.) S1 (100V/div.; 10 A/div.; 5us/div.) for linear load (50V/div., 10A/div.; 2ms/div.)
η 92 PF 1
0.98
91
0.97
90
89 0.95
88 0.94
87 0.93
86 0.91
85 0.9
84 0.88
83 0.86
82
0.85
0 200 400 600 800 1000 1200 1400 1600 0 200 400 600 800 1000 1200 1400 1600
Po[W] Po[W]
Fig. 16. Output voltage and current of the inverter Fig. 17. Efficiency of the UPS system as a Fig. 18. Power factor as a function of the output
for non-linear load (50V/div., 20A/div.; 2ms/div.) function of the output power. power.

Fig. 19. Mains input voltage and current Fig. 20. Voltage and current of the chopper switch Fig. 21. Output voltage and current of the invert
(100V/div.; 5 A/div.; 2ms/div.) S1 (100V/div.; 5 A/div.; 4us/div.) for linear load (50V/div.; 10 A/div.; 2ms/div.)

η 92 PF 1
91 0.98
90 0.97
89 0.95
88 0.94
87 0.93
86 0.91
85 0.9
84 0.88
83 0.86
82 0.85
0 200 400 600 800 1000 1200 1400 1600 0 200 400 600 800 1000 1200 1400 1600
Po[W] Po[W]
Fig. 22. Output voltage and current of the inverter Fig. 23. Efficiency of the pre-regulator circuit as a Fig. 24. Power factor as a function of the output
for non-linear load (50V/div., 20A/div.; 2ms/div.) function of the output power. power.

367
 The main parameters of the implemented prototype are experimental results obtained from 2kVA output power
summarized in Tables III, IV and V. prototype have also been presented.
TABLE III. PARAMETERS OF UPS RECTIFIER AND CHOPPER STAGE For both input voltages, chopper switches S1–S4 present zero
Rectifier Diodes GBPC3508A voltage switching, avoiding the use of snubber circuits. The
Input Filter Inductor Lf = 137.18µH proposed system efficiency is the same for both input voltages,
Input Filter Capacitors Cf1 = Cf2 = 3 x 2.2µF / 400Vdc
because semiconductors losses at the primary side of the
transformer are also almost the same. The chopper operates
Switches S1 - S4 IXFX44N60
with fixed pulses of D≅0.5 obtained from conventional PWM
Coupled Inductors Lr1 = Lr2 = 3.9µH integrated circuit.
NEE-65/39 (Thornton Ipec) The boost converter performs power factor correction,
High Frequency Transformer
Np=12 turns; Ns=12turns
regulates the output voltage and steps the battery bank voltage
Diodes Dr1 and Dr2 HFA30PA60C
up to the DC bus output voltage that feed the inverter. It is
TABLE IV. PARAMETERS OF UPS BOOST STAGE controlled in closed loop using average current-mode control,
Boost Inductor Lb = 338.60µH and implemented with conventional PWM integrated circuit.
Output Capacitor Co = 3 x 680µF / 450V The voltage source full-bridge inverter converts DC bus
Diode Db HFA25PB60 voltage in AC voltage. It’s controlled using unipolar voltage
technique. In this circuit, the controlled switches of the inverter
Switch Sb IXFX44N60
stage present hard commutation degrading efficiency.
Resonant Inductors LS = 0.9µH
CS1 = 120nF ACKNOWLEDGMENT
Polypropylene Film Capacitors
CS2 = 6.8nF
The authors would like to thank Texas Instruments,
Diodes Da1, Da2 and Da3 MUR460
International Rectifier, On Semiconductor, Cree and Epcos for
TABLE V. PARAMETERS OF UPS FULL BRIDGE INVERTER STAGE supplying the samples.
Output Filter Inductor Lfi = 170µH
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Output Filter Capacitor Cfi = 30µH
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Switching Features”. in APEC 2001 – IEEE Applied Power Electronics
Fig. 25. Photograph of the implemented UPS system. Specialists Proceedings, vol. 02, pp. 722 – 727, 2001.
[10] F. K. A. Lima, C. M. T. Cruz, F. L. M. Antunes, “A Family of Turn-On
and Turn-Off Non-Dissipative Passive Snubbers for Soft-Switching
X. CONCLUSION Single-Phase Rectifier with Reduced Conduction Losses”, in PESC 2004
– IEEE Power Electronics Specialists Conference Proceedings, vol. 01,
A new high frequency transformer isolation UPS topology pp. 3745 – 3750, 2004.
capable of operating in a wide input voltage range is presented. [11] R. P. Torrico-Bascopé, D. S. Oliveira Jr., C. G. C. Branco, F. L. M.
Other important features of the proposed system are: unity Antunes, “A PFC Pre-Regulator with 110V/220V input voltage and high
power factor, simple control scheme using conventional control frequency isolation for UPS applications”, in IECON’05 – IEEE
Industrial Electronics Society Annual Conference Proceedings, vol. 01,
technique and soft commutation. High frequency isolation 2005.
reduces the volume and weight of the system. The qualitative
analysis of the UPS for 110V and 220V input voltages and

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