EGR347/EGE340 SEMICONDUCTOR TECHNOLOGY

Laboratory 2 : Surveying wafer structures using an optical microscope

Objectives: 1) Introduction and Identification of different structures on the wafer.

2) Usage of microscope.

3) Identify simple schematic by looking at the structure.

Apparatus: Microscope, wafers

Part 1 and 2
Parametric structures as well as other monitoring structures are placed on the wafer to
monitor the process. By measuring all these structures, any process excursions can
be discovered eraly and prevent loss of money as well as time.

Both the parametric and monitoring structures are placed on the scribe line in 1 reticle.
These are basically unsed area at the edge of every die.

Param structures

Dies

There are many different monitoring structures and they are used while the wafer is
running in the wafer fab for monitoring purpose.

Paramteric structures, on the other hand, are used normally after the wafer completed
its full process (or after metal layer is deposited) They are used to monitor the electrical
performance of the wafer. E.g. Vt, Idsat, resistance.
All these structures will be sawed off after the wafer is sent for packaging into chips.

1
In this lab, students are expected to observe and note down the details of the structures.

We will identify the monitor structures and electrical structures together.

Monitor Structures:-
Fill in the blanks
Structure Outlook Purpose Describe how it
achieve the designated
purpose

How many dies are there in the reticle? (Hint, 1 set of structure in 1 reticle. Look at how
many dies repeated before the apperance of 1 structure)

(LxW)

2
Parametric Structure:-
Fill in the blanks
Structure Outlook Purpose Describe how it
achieve the designated
purpose
To determine the
resistance of vias,
contacts, metal line.

For measurement of
transistor
characteristics, such as
Id, Vt, Sub Vt etc.

Part 3
Design of logic gates have been taught in different lectures. A transistor basically looks
as follow:
gate

Contacts

source drain

But it is usually not as easy to identify the transistor when it is on the wafer. There are
many layers on top of the structure and well are normally not clear and defined unless
when the transistor is delayed.

Below are how the structure looks on a actual wafer with metal layers on top.

3
 Label the numbers below to identify the
PMOS INVERTER

1. Input Pin
2. Output Pin
3. Vss
4. Gnd

Identify Pin 1, 2, 3, 7 and 8.

1.
2.
3.
7.
8.

Draw out the stick diagram for the structure.

4
Reference structures
1) Inverter (NOT gate)

An inverter can be implemented in various electronic configurations as shown

in the following stick diagrams.

CMOS NOT gate BJT NOT gate

2) NAND gate (using PMOS and NMOS)

STICK DIAGRAM (NAND GATE)