www.ietdl.

org
Published in IET Power Electronics
Received on 10th January 2010
doi: 10.1049/iet-pel.2010.0150

ISSN 1755-4535

New zero-voltage-switching bridgeless PFC, using

an improved auxiliary circuit
M. Ramezani S.M. Madani
Electrical and Computer Engineering, Isfahan University of Technology, Esfahan 84156-8311, Iran
E-mail: mehdiramezanipine@gmail.com

Abstract: This study presents a new zero-voltage-switching (ZVS) single-phase bridgeless PFC, using an improved auxiliary
circuit to achieve ZVS for all main switches and diodes. Compared to other ZVS bridgeless PFC converters with no extra
voltage and/or current stresses, the converter presented here uses lower component count. Since the presented PFC uses a
bridgeless rectifier, there are only two semiconductor components in the main current path instead of three in conventional
single-switch configurations. This property decreases the conduction losses, significantly. Moreover, ZVS removes switching
loss of all main switches and diodes. Furthermore, since resonant current passes only through the auxiliary circuit, there is no
extra current and/or voltage stress on the main switches and diodes. The auxiliary switch operates in zero-current conditions;
therefore it does not introduce any switching loss. The presented converter just needs a simple non-isolated gate drive
circuitry to drive all switches. Nine stages are explained for each ZVS switching period. Design considerations and a control
strategy are also explained. Finally, the converter operation is verified by simulation and experimental results.

1 Introduction circuitry, in [6 –10], increase the converter volume and

Since the international regulations (such as IEC 61000-3-2)
limits the converters distortion currents, so many converters
have been presented to comply rectifiers’ input current with
these regulations. Off-line switching power supplies uses a
large capacitor as front-end rectification that causes an
excessive peak current and high current distortions, and can
achieve a low power factor of about 0.5– 0.7 [1]. Further
increasing the power factor of a diode bridge input can be
done by adding a boost converter to shape the input current,
Fig. 1a [2 – 4]. In this configuration, the input current always
passes through three semiconductors. To reduce the
conduction losses, the bridgeless PFC of Fig. 1b is
introduced [5]. In bridgeless topology, the input current
always passes through two semiconductors, which results in
less conduction loss. Moreover, the reverse diode voltage
drop and its loss, while the switch gate is on, are smaller
than conventional diodes. To increase power density and
decrease the input current distortions of the converter,
switching frequency should be increased. However, this
increases the switching losses and electromagnetic
interference (EMI) noise. So, several zero-voltage switching
(ZVS) and zero-current switching (ZCS) topologies have
been presented to solve these problems [1, 6 –25]. In the
ZVS condition, the drain-source capacitive losses are
eliminated by holding its voltage at zero, during turn-on.
Therefore this method is used for MOSFETs which have a
big drain-source junction capacitor [26]. In the ZVS
converter of [6 – 14], an additional dc voltage source is used
in the auxiliary circuit. This voltage source is implemented
by means of a voltage transformer or a dc – dc converter. The
employed voltage transformer and its demagnetising
complexity. References [11 – 14] use dc – dc converter (as a
voltage source or sink) to implement soft switching, which
limits the converter voltage conversion ratio [15]. In [16, 17],
the main switches turn on and off in the ZVS condition. The
auxiliary switch turns on in the ZCS conditions, but it is not
turned off in soft conditions. Although, the collector-emitter
voltage of the auxiliary switch is clamped to the output
voltage, it introduces some extra loss. Moreover, because of
large dv/dt and di/dt these circuits have high EMI noises. In
[1], the converter main switches operate in the ZVS condition
and the auxiliary switch operates in the ZCS condition. In
[15], the main switches turn on in the ZCS condition and turn
off in the ZVS condition. But, both converters [1, 15] require
higher number of components. ZCS methods can eliminate
the tailing current power loss of the switches. Therefore this
method is used for insulated-gate bipolar transistors (IGBT)
that suffer from tailing current losses. In ZCS conditions the
current of switch is zero during the switching transitions [18–
25]. Some of the proposed ZCS topologies need extra
semiconductor element in the main power path [18, 24]. This
removes the main feature of the bridgeless converter (which is
low semiconductor components count in the main power path)
in some of their operation modes. Some others topologies
introduce extra current or voltage stress on the main switch,
which increases the rating of the switches and the whole cost
[20, 22, 25]. In [19], the auxiliary circuit dissipates some of
the input power and there is a coupled inductor in that circuit
which increases the converter complexity.
This paper presents a new ZVS bridgeless PFC with improved
auxiliary circuit and lower component count than the other
similar presented ZVS converters, Fig. 2a. In this converter, all
the main switches and diodes operate in ZVS conditions, and

732 IET Power Electron., 2011, Vol. 4, Iss. 6, pp. 732 –741
& The Institution of Engineering and Technology 2011 doi: 10.1049/iet-pel.2010.0150
 www.ietdl.org

Fig. 1 Rectifiers with boost PFC

a Conventional single-switch PFC
b Bridgeless two switch PFC

Fig. 2 Proposed converter and its model

a Proposed ZVS bridgeless PFC
b Equivalent circuit in one switching cycle

the auxiliary switch (AXsw) which is an IGBT, operates in the
ZCS condition. Therefore the switching loss of all switches and
diodes are removed. In subsequent sections, after analysing the
converter, a design strategy is presented. Finally, these analysis
and designs are verified by simulation and experimental results.
output voltage and input current is constant during one
switching period. Therefore we can model the input current
with a dc current source and output voltage with a dc voltage
source, as illustrated in Fig. 2b. Also assume that when the
main switch is on, all auxiliary capacitor voltages and
inductor currents are zero.

2 Principle of the proposed ZVS bridgeless

2.1 Operating stages of the proposed PFC
PFC
Each switching cycle of the converter can be divided into nine
The proposed converter is shown in Fig. 2a. The converter
stages. The equivalent circuits of all stages are shown in Fig. 3,
consists of Lin, MOS1,2 , D3 , D4 , Co , as the original bridgeless
and the theoretical wave forms are shown in Fig. 4. Here, one
PFC converter, and Cr1 , Cr2 , Cr3 , D5 , D6 , D7 , Lr1 , Lr2 , AXsw
switching cycle stages during the positive half-cycle are
with small ratings as improved auxiliary circuit for providing
explained. The negative half-cycle stages are the same.
ZVS for MOS1,2 , D3 , D4 . For simpler switching, the gate-
Stage 1 [Fig. 3a, t0– t1]: During this stage, the MOS1 is on
driver signal drives the gates of MOS1,2 , simultaneously.
and the input current flows through it in the forward direction
Therefore both gates turn on and off in both positive and
and body diode of the MOS2 in reverse direction. The
negative half-cycle of the input voltage. However, just one of
duration of this stage is ton in each switching period, which
the switches turns on in each half-cycle of the input voltage.
controls the input current.
This is because the drain-source voltage of only one of the
Stage 2 [Fig. 3b, t1– t2]: This stage starts when the MOS1
MOSFETs is positive at each power line half-cycle. Therefore
is turned off. Because of drain-source parallel capacitor Cr1
in positive half-cycle when the MOS1 is on, the input current
the switch drain-source voltage increases slowly, and so the
flows through MOS1 in forward direction, the body diode of
switch turning off is ZVS. Owing to the fixed input current,
MOS2 in reverse direction and charges Lin. Also in this time,
Cr1 voltage increase linearly. Equivalent circuit of this stage
the gate-driver signal of the MOS2 is on; therefore its body
is shown in Fig. 3b. The time duration of this stage is
diode has smaller voltage drop which decreases the reverse
diode conduction loss. When the MOS1 is turned off, Lin
discharging-current flows to the load through the diode D3 Cr1 vo
t2 − t1 = (1)
and body diode of MOS2 . D4 is off in the entire positive half- iin
cycle. In the negative half-cycle of the input voltage, the
converter operates in the same way, but the MOS2 conducts in Stage 3 [Fig. 3c, t2– t3]: This stage starts when the voltage
forward direction and MOS1 conducts in reverse direction across the capacitor Cr1 reaches the output voltage. At this
through its body diode. D4 conducts when MOS2 is off. D3 is time the diode D3, turns on in zero-voltage condition.
off in the entire negative half-cycle. To simplify the analysis, During this stage, the power flows from source to the load,
assume that: the converter is in the steady state conditions, through D3 and MOS2 reverse diode.

IET Power Electron., 2011, Vol. 4, Iss. 6, pp. 732–741 733

doi: 10.1049/iet-pel.2010.0150 & The Institution of Engineering and Technology 2011
www.ietdl.org

Fig. 3 Equivalent circuits of one switching stages

a Stage 1
b Stage 2
c Stage 3
d Stage 4
e Stage 5
f Stage 6
g Stage 7
h Stage 8
i Stage 9

Stage 4 [Fig. 3d, t3 – t4]: This stage starts when AXsw is and the Cr3 voltage form beginning of this stage until (t7 ) is
turned on. Owing to series inductors Lr1 , Lr2 , the switch v t 
current raises, gradually. So, AXsw turns on in zero-current VCr3 = 2VO sin 1 (7)
condition. Owing to resonant among Lr2 , Cr3 , the resonance 2
current increases to its maximum and starts decreasing. The 1
output voltage is applied on the resonant inductor Lr1 and v1 =  (8)
Lr2 Cr3
its current increases linearly, which decreases D3 current
with the same rate. This stage ends when Lr1 current Stage 5 [Fig. 3e, t4–t5]: This stage starts when the Lr1 current
reaches the input current. The time duration of this stage is reaches to input current and diode D3 turns off. Then, a resonant
occurs among Cr1 and Lr1 , and the Lr1 current increases to its
iin× Lr1 maximum, owing to the voltage across Cr1 . The Cr1 voltage
t3 − t4 = (2)
vo decreases to zero and the voltage across diode D3 increases
with the same rate and reaches the output voltage.
and Lr1 , Lr2 and AXsw currents are At this instant the body diode of MOS1 turns on, which is
the end of this stage. During this stage, the Cr3 voltage
Vo reaches to its peak value of (2Vo ) and then starts
iLr1 = t (3) decreasing. The resonant current among Lr2 , Cr3 becomes
Lr1
reversed. The AXsw current, which is the sum of the
Vo Lr1 , Lr2 currents, starts decreasing, but it is still positive. At
iLr2 = sin(v1 t) (4) this stage, the Lr1 current is
Zr1
vO
iLr1 = sin(v0 t) + iin (9)

Lr2 Zr0
Zr1 = (5)
Cr3 
Lr1
Zr0 = , C = Cr2 (10)
iAxsw = iLr1 + iLr2 (6) Cr1 r1

734 IET Power Electron., 2011, Vol. 4, Iss. 6, pp. 732 –741
& The Institution of Engineering and Technology 2011 doi: 10.1049/iet-pel.2010.0150
 www.ietdl.org
diode and D7 turn on in zero-voltage condition. The Lr1
freewheeling current flows through body diodes of MOS1,2 ,
D6 , D7 , Lr1 , AXsw . So, the MOS1 can be turned on in zero-
voltage – zero-current (ZVZCS) conditions. The resonant
current of Lr2 , Cr3 continues to rises in the negative
direction. This stage ends, when the sum of Lr1 and Lr2
currents which is the AXsw current reaches zero for the first
time. The time duration of this stage and the Lr1
freewheeling current amount can be described as

 
1 iin + (vo /Zr0 ) p i × Lr1
t6−t5 = −1
sin − − − in (13)
v1 vo /zr1 2v0 vo

vO
iLr1f = + iin (14)
Zr0

Stage 7 [Fig. 3g, t6 – t7]: This stage starts when the

current of the AXsw become negative. During this stage,
the negative resonant current among Lr2 , Cr3 , which is
bigger than Lr1 freewheeling current, continues. So, the
body diode of AXsw is on and passes the difference of Lr1
and Lr2 currents. As AXsw body diode is on, the AXsw
voltage and current are both zero. Therefore during this
stage, the AXsw can be turned off in ZVZCS conditions.
MOS1 is still in ZVZCS condition that can be turned on
in either stage 6 or stage 7. It must be noted that the peak
of Lr2 , Cr3 resonant current should be designed to be
bigger than Lr1 freewheeling current, to allow AXsw
become negative. The resonant current reaches to its
negative peak and starts decreasing. This stage ends when
the resonant current among Lr2 , Cr3 again become equal
to the Lr1 freewheeling current. The equivalent circuit of
this stage is shown in Fig. 3g. The AXsw current which is
negative and time duration of this stage can be described as

Vo V
iAXsw = iin + + o sin(v1 t) (15)
Zr0 Zr1

3p − 2 sin−1 −(iin + (Vo /Zr0 )/(Vo /Zr1 ))

t7−t6 = (16)
v1

The derivate procedure of the time duration of last two

stages is mentioned in Appendix.
Stage 8 [Fig. 3h, t7 – t8]: This stage starts when the body
diode of the AXsw turns off. Since the AXsw has already
Fig. 4 Theoretical wave forms of one switching stages been off, inductors Lr1 and Lr2 , which have same current,
become series and resonate with Cr3 their current starts
and the time duration of this stage can be described as decreasing, while the MOS1 current increases with the same
rate. This resonant continues until the voltage across Cr3
p reaches zero, which is the end of this stage. The Cr3 voltage
t5 − t4 = (11) and Lr1 + Lr2 current can be described as
2v0
1
v0 =  (12) v t 
Lr1 Cr1 VCr3 = 2VO sin 2
+ VCr3 (t7 ) cos(v2 t) + Zr2 iLr (t7 ) sin(v2 t)
2
Stage 6 [Fig. 3f, t5– t6]: This stage starts when MOS1 body (17)

IET Power Electron., 2011, Vol. 4, Iss. 6, pp. 732–741 735

doi: 10.1049/iet-pel.2010.0150 & The Institution of Engineering and Technology 2011
www.ietdl.org

VCr3 (t7 ) − VO
 converter. With the rating values of the converter that are
iLr = sin(v2 t) + iLr (t7 ) cos(v2 t) (18) specified in step 1, the calculated maximum input current is
Zr2
(iin, max = 16.5 A) and the switches and diodes voltage stress
LT = Lr1 + Lr2 (19) is 400 V.
Step 3: The resonant parameters are calculated in this step.
 The resonant period should be negligible compared to the
LT switching frequency period, to minimise the effect of the
Zr2 = (20)
Cr3 resonant circuit on the main converter. So, the resonant
frequency of the Zr1 is selected as fr1 /fs ≃ 6.3.
1
v2 =  (21) 1
LT Cr3 fr1 =  = 5.03 × 105 (Hz) (27)
2p Lr2 .Cr3
iLT (t7 ) = iLr1 (t7 ) = iLr2 (t7 ) (22)
Cr1 and Cr2 should be selected large enough to provide a
Stage 9 [Fig. 3i, t8 – t9]: This stage starts when the voltage capacitor charge time for the maximum input current, (1),
across the Cr3 reaches zero. At this instant, there is a current bigger than the fall time (tf ) of MOS1,2 . However, this time
through inductor LT ; this current exists because the capacitor should be less than the resonant period of the Zr1 . Therefore
Cr3 , cannot absorb all the energy that has been added to the it can be selected as
auxiliary circuit in stages 4 – 6. The inductors current turns
the diode D5 on in the zero-voltage condition. Thus, the iin, max tf 2piin, max
, Cr1,2 , (28)
output voltage is applied on the inductor LT . These inductor Vo v1 Vo
current decreases linearly to zero and D5 turns off,
while MOS1 current increases in the same rate and Selecting the maximum of iLr1 = 1.2iin, max from (14) the Lr1
reaches the input current. During this stage, the LT current, can be selected as
the voltage across the AXsw and the time duration of this
stage are  2
5VO
Lr1 = Cr1 (29)
Vo iin, max
iLT = iLT (t8 ) − t (23)
LT
where iin is the maximum input current. For Zr1 current to
VL provide ZCS condition for AXsw , the following condition is
VAXsw = o r1 (24)
LT necessary

iLT (t8 )LT Vo

t9−t8 = (25) iZr1, max . iin, max + (30)
Vo Zr0

At the end of this stage, the AXsw voltage reaches the output where
voltage. Thus, the converter returns to the first stage of the
next switching cycle. Vo
iZr1 , max = (31)
Zr1
3 Design steps
So, Lr2 and Cr3 can be designed using (27) and (32).
The PFC converter can be designed in a four-step procedure.

Step 1: Input voltage, output voltage and output current Lr2 vo
should be given. The rms of input voltage of this converter , (32)
Cr3 iin, max + (vo /zr0 )
varies between 96– 265 V, the output dc voltage is 400 V
and maximum output power is 1000 W.
Step 2: The switching frequency should be selected much Using the above equations, Cr1,2 , Cr3 , Lr1 and Lr2 are
higher than the input voltage frequency, to reduce input calculated as 5 × 10−9 (F), 20 × 10−9 (F), 40 × 10−6 (H)
current low-frequency distortion. For this converter the and 10 × 10−6 (H), respectively. Values here are over-
switching frequency is chosen at 80 kHz, which is high designed to show the results, clearly. The maximum
enough to satisfy the IEC 61000-3-2 standard (higher voltage stress across the AXsw is Vo and its maximum
frequencies can result in more losses as a result of more current is
wires skin effect). By selecting the maximum input current
ripple of 10%, we can calculate the maximum input current Vo V
which is the maximum current stress of the switches iAXsw, max = iin, max + + o (33)
Zr0 Zr1
MOS1,2 and diodes D3,4
√ The peak current of diodes D6,7 is the same as that of iLr1 ,
2p0. max Diin and their maximum voltage is Vo . D5 ’s maximum voltage
iin. max = + (26)
vin. max 2 is 2Vo and its maximum current is the same as that of iLt
in (23).
The maximum voltage stress of these switches and diodes is Step 4: One of the design possibilities of this converter
equal to the output voltage, which is an advantage of this is to operate in continuous current mode (CCM) that

736 IET Power Electron., 2011, Vol. 4, Iss. 6, pp. 732 –741
& The Institution of Engineering and Technology 2011 doi: 10.1049/iet-pel.2010.0150
 www.ietdl.org

Fig. 5
a Simplified diagram of peak current controller
b Real controller used for control experimental results

Fig. 6 Circuit simulated in PSIM

reduces the amount of high-frequency distortions, and minimising the output voltage ripple, using [27], Lin and Co
consequently EMI filter size (other modes have their own are calculated as Lin = 650 mH and Co = 940 mF,
features). So by choosing 10% input current ripple and respectively.

IET Power Electron., 2011, Vol. 4, Iss. 6, pp. 732–741 737

doi: 10.1049/iet-pel.2010.0150 & The Institution of Engineering and Technology 2011
www.ietdl.org

Fig. 7 Simulation result key wave forms

a Input voltage and input current
b Input current harmonics
c Diode D3 voltage and current
d MOS1 voltage and current
e Voltage and current of AXsw
f Lr1 and Lr2 currents

Table 1 Proposed and single-switch converter elements

Elements Proposed converter Single-switch converter

core EE70 EE70

wire NO-10(AWG) NO-10(AWG)
Lin turns 14 14
diodes MUR8100(×2) MUR8100(×1)
input diode bridge not used MB156
switching frequency 80 kHz 80 kHz
main switch IRFP460(×2) IRFP460(×1)
1
capacitive energy loss during each hard switching turning on – C V 2 = 1.2 × 10−3 (J)
2 D−S o
output filter capacitor 940 mF, 400 V 940 mF, 400 V
auxiliary circuit used not used
Diodes MUR8100(×3) –
Lr1 40 mH –
Lr2 10 mH –
Cr1,2 5 × 1029 F –
Cr3 20 × 1029 F –
auxiliary switch IRGIB7B60KD –
t7
conduction energy loss during each switching cycle 2.2 × |iAXsw |dt –
t3

2.64 × 10−6 (J)

4 Control strategy For 50 Hz input voltage frequency, it is necessary to select

The proposed converter is controlled with a peak current
mode controller. Fig. 5a shows a simplified diagram of the
peak current controller. It also can be controlled with a
conventional average current PFC controller IC, such as
UC3854 (with additional logic part shown in Fig. 5b).
This controller has two feedback loops: a voltage feedback
loop to control the average output voltage; and a current
feedback loop to shape the input current. The voltage
control loop has a limited bandwidth, small enough to
cancel the effect of output voltage ripple on the controller.
the bandwidth of the voltage control loop much less than
100 Hz [28]. The input voltage is sensed and its absolute
(rectified) value is used as synchronous signal. This
synchronous signal is multiplied by the voltage-controller
output signal, to make the current reference signal. The
input current is also sensed and its absolute (rectified)
value is compared with the current reference signal, using
a comparator. This comparator output is used as the ‘Set’
signal for an asynchronous rising-edge-triggered S-R flip-
flop. An oscillator is used to reset this S-R flip-flop, which
also determines the switching frequency. The flip-flop

738 IET Power Electron., 2011, Vol. 4, Iss. 6, pp. 732 –741
& The Institution of Engineering and Technology 2011 doi: 10.1049/iet-pel.2010.0150

output is used as the input of a simple logic circuit to
produce the switching signals of MOS1 and AXsw . The
main switches’ (MOS1,2) must be turned on after an
appropriate delay from the AXsw switch on-signal, to let
stages 4 and 5 passed. This delay is produced by a time
delay block in the controller, as shown in Fig. 5. MOS1,2
stay in the ZVS condition, until the end of the stage 7. On
the other hand, during stage 7, the AXsw is in the ZVZCS
conditions and is ready to be turned off. Therefore the
required time delay for MOS1,2 and the AXsw on-time
duration can be determined by
(t5 − t3 ) , tdelay , (t7 − t3 )
(t6 − t3 ) , Ton,AXsw , (t7 − t3 )
The AXsw gating on-signal (Ton,AXsw) is produced by a
rising-edge monostable. The minimum durations of the
tdelay and Ton,AXsw occur when the rms input voltage is at
its minimum (i.e. 96 V) and consequently, the input
current is at its maximum (i.e. 16.5 A). According to (34),
Fig. 8 Experimental result key wave forms
a Input voltage and input current 50 v/div and 6 A/div, time:5 m (s)/div
b MOS1 drain-source voltage 250 v/div and its gate signal, time: 2 m(s)/div
c MOS1 current 6 A/div, time: 1 m(s)/div
d Diode D3 voltage and current 250 v/div and 6 A/div, time: 1 m(s)/div
e AXsw voltage 250 v/div and its base signal, time: 1 m(s)/div
f AXsw current 7 A/div and its gate signal, time: 1 m(s)/div
g Lr2 current 10 A/div, time: 2.5 m(s)/div
h Lr1 current 10 A/div, time: 2.5 m(s)/div
i Cr3 voltage 250 v/div, time: 1 m(s)/div
IET Power Electron., 2011, Vol. 4, Iss. 6, pp. 732–741
doi: 10.1049/iet-pel.2010.0150
www.ietdl.org
(35) the durations tdelay and Ton,AXsw are selected to be
2.2 × 1026 s and 2.1 × 1026 s, respectively. The applied
control circuit diagram is shown Fig. 5b.
5 Simulation results
The proposed converter is simulated; using power SIM
(PSIM) (the simulated circuit diagram is shown in Fig. 6).
The parameters settings are set as calculated in Section
3. The simulation parameters and quantities are chosen as:
step size: 1 × 1028 s; input voltage: 120 Vrms , 50 HZ; the
output voltage 400 V DC; the output power: 400 W; and
(34)
the switching frequency fsw: 80 kHz. The converter wave-
forms are shown in Fig. 7. Fig. 7a shows that the input
(35) current is very close to sinusoidal and is in phase with the
input voltage. Fig. 7b shows the input current harmonics
that are below the ‘IEC 6 1000-3-2 class A’ requirements
[29]. Fig. 7c and d show soft-switching of the main diode
and switch, respectively. The main switch turns off in
ZVS condition and turns on in ZVZCS conditions. Fig. 7e
shows the AXsw voltage, current, its ZCS turn on and its
739
& The Institution of Engineering and Technology 2011
www.ietdl.org
ZVZCS turn off. Fig. 7f shows the resonant inductors
currents.
6 Experimental results
The proposed converter has been implemented to verify the
theoretical results. Table 1 shows the proposed and single-
switch converter elements. The prototype was tested under
input voltage of 120 Vrms , output voltage of 400 Vdc and
the output power of 400 W (this power is chosen to be
comparable with other references). Fig. 8 shows the key
wave forms of the converter. Fig. 8a shows the input
voltage and current.
As shown, they are in phase and the power factor measured
is 0.96. If the voltage source of the lab was a perfect
sinusoidal wave, the power factor would have been closer
to unity. Fig. 8b shows the drain-source voltage of the
MOS1 and its gate signal. It is clear that this switch turns
on and off in the ZVS condition. Fig. 8c shows the MOS1
current and its gate signal. It can be clearly seen that this
switch turns on in ZCS condition. Therefore MOS1 turns on
in ZVZCS conditions and turns off in the ZVS condition.
As mentioned in Section 2, the MOS2 operates in the same
way as MOS1 , because of the circuit symmetry. Fig. 8d
shows the soft switching of the diode. The ringing at the
diode turn on moment is caused by some non-idealities
such as parasitic inductors or capacitors of the connections
and forward voltage drop of the power diode. Fig. 8e shows
the base signal and the voltage across the AXsw . This figure
clearly shows the ZVS turn off of AXsw . Fig. 8f shows the
base signal and the current of AXsw . It is clear that this
switch turns on and off in ZCS conditions. Therefore AXsw
turns on in ZCS and turns off in ZVZCS conditions.
Fig. 8g – i show the Lr2 and Lr1 currents and Cr3 voltage,
respectively. The ringing at Lr1 and Lr2 currents are caused
by the forward voltage drop of the power diode D5 , at its
turn on moment (t8 ). The measured converter efficiency at
input voltage of 120 Vrms against output power is shown in
Fig. 9. This figure shows that the efficiency is higher than a
conventional single-switch PFC. As explained in Table 1,
the auxiliary switch conduction loss is negligible compared
to capacitive loss of the main switches in the hard-
switching condition. Moreover, the auxiliary switch
operates in the ZCS condition and does not introduce any
switching loss.
Fig. 9 Measured efficiency comparison of proposed PFC and
conventional single-switch PFC
740
& The Institution of Engineering and Technology 2011
7 Conclusion
This paper presents a new ZVS bridgeless PFC converter.
This converter uses an improved auxiliary circuit, to
achieve soft-switching condition for all switches and
diodes. All of the main switches and diodes operate in the
ZVS condition and the auxiliary switch AXsw operates in
the ZCS condition, which removes the switching losses. In
addition, since the proposed PFC converter is bridgeless,
the converter conduction loss is lower than the conventional
single-switch PFC converters, since there are only two
semiconductors in the main current path instead of three in
the conventional ones. The proposed converter has no extra
voltage and/or current stress on the converter main switches
and diodes. Moreover, a simple non-isolated drive circuit
can be used to drive all switches. The switching stages are
explained, and design steps have been described in this
paper. A control strategy is also presented. The theoretical
results have been verified with simulation and experimental
results. The measured converter efficiency at input voltage
of 120 Vrms and different load conditions is between 90.5
and 95.5%. The measured power factor at the 400 W output
power is 0.96.
8 References
1 Wang, C.-M.: ‘A novel zero-voltage-switching PWM boost rectifier
with high power factor and low conduction losses’, IEEE Trans. Ind.
Electron., 2005, 52, (2), pp. 427–435
2 Kazerani, M., Ziogas, P.D., Joos, G.: ‘A novel active current wave-
shaping technique for solid-state input power factor conditioners’,
IEEE Trans. Ind. Electron., 1991, 38, (1), pp. 72– 78
3 Kazerani, M., Ziogas, P.D., Joos, G.: ‘Programmable input power factor
correction methods for single phase diode rectifiers’. Proc. IEEE
PESC’90, 1990, pp. 177– 184
4 Prasad, A.R., Ziogas, P.D., Manias, S.: ‘An active power factor
correction technique for three-phase diode rectifiers’, IEEE Trans.
Power Electron., 1991, 6, (1), pp. 83– 92
5 Martinez, R., Enjeti, P.N.: ‘A high-performance single-phase rectifier
with input power factor correction’, IEEE Trans. Power Electron.,
1996, 11, (2), pp. 311–317
6 Martins, D.C., Seixas, F.J., Barbi, I., Brilhante, J.A.: ‘A family of DC-to-
DC PWM converters using a new ZVS commutation cell’. Proc. IEEE
Power Electronics Specialist Conf., 1993, pp. 524– 530
7 Gegner, J.P., Lee, C.Q.: ‘Zero-voltage-transition converters using an
inductor feedback technique’. Proc. IEEE Ninth Annual Applied
Power Electronics Conf., 1994, vol. 2, pp. 862– 968
8 Gegner, J.P., Lee, C.Q.: ‘Zero-voltage-transition converters use a simple
magnetic feedback technique’. Proc. IEEE Power Electronics specialists
Conf., 1994, pp. 590–596
9 Lee, F.C., Lin, R.L., Zhao, Y.: ‘Improved soft-switching ZVT converters
with active snubber’. Proc. IEEE Applied Power Electronics Conf.,
1998, vol. 2, pp. 1063–1069
10 Souza, A.F.D., Barbi, I.: ‘A new ZVS-PWM unity power factor rectifier
with reduced conduction losses’, IEEE Trans. Power Electron., 1995,
10, (6), pp. 746–752
11 Filho, N.P., Farias, V.J., Feritas, L.C.: ‘A novel family of dc– dc PWM
converters using the self-resonance principle’. Proc. IEEE Power
Electronics Specialists Conf., 1994, pp. 1385– 1391
12 Costa, A.V., Terviso, C.H.G., Feritas, L.C.: ‘A new ZCS-ZVS-PWM
boost converter with unit power factor operation’. Proc. IEEE Applied
Power Electronics Conf., 1994, pp. 404–410
13 Iang, Y., Jovanovi, M.M.: ‘High-power-factor soft switched boost
converter’, IEEE Trans. Power Electron., 2006, 21, (1), pp. 98–104
14 Kim, Y.H., Park, K.S.: ‘A high-efficiency soft switching zero-voltage-
transition converter using combined inductor energy recovery circuits’.
Proc. ISIE 2001 IEEE INTNATIONAL SAMP, June 2001,
pp. 712–717
15 Martins, M.L.D.S., Hey, H.L.: ‘Self-commutated auxiliary circuit ZVS
PWM converters’, IEEE Trans. Power Electron., 2004, 19, (6),
pp. 1435– 1445
16 Tasi, H.Y., Hsia, T.H., Chen, D.: ‘A novel soft-switching bridgeless
power factor correction circuit’. Proc. European Conf. Electronics and
Applications, September 2007, pp. 1 –10
IET Power Electron., 2011, Vol. 4, Iss. 6, pp. 732 –741
doi: 10.1049/iet-pel.2010.0150
 www.ietdl.org
17 Kim, I.D., Nho, E.C., Choi, S.H., Lai, J.S.: ‘Simple ZVT PWM single- This is the sum of the time durations of stages 4 – 6. Therefore
phase rectifier with reduced conduction loss and unity power factor’. the time duration of stage 6 can be described as (13). The time
Proc. 37th IEEE PESC Conf., 2006, pp. 1– 7
18 Cansesin, C.A., Bari, I.: ‘A novel single-phase ZCS-PWM high-power- duration of stage 7 can be derived using the following
factor boost rectifier’, IEEE Trans. Power Electron., 1999, 14, (4), procedure.
pp. 629–634 The time duration from t3 to the minus peak of the Lr2
19 Hwu, K.I., Li-Tasi, C., Fan Lin, K.: ‘A simple passive ZCS circuit for current is
PFC converter’. APEC 2008, 23 Annual IEEE, Applied Power
Electronincs Conf. and Exposition, pp. 1022– 1026
20 Souza, A.f.D., Barbi, I.: ‘A new ZCS quasi-resonant unity power factor
rectifier with reduced conduction losses’, IEEE PESC Rec., 1995, 2, 3p
pp. 1171– 1177 Dt = (38)
21 Stein, C.M.D.O., Pinheiro, J.R., Hey, H.L.: ‘A ZCT auxiliary
2v1
commutation circuit for interleaved boost converters operating in
critical conduction mode’, IEEE Trans. Power Electron., 2002, 17,
(6), pp. 954– 962 That is the sum of the time duration of (37) and half of the
22 Kim, I., Bose, B.I.: ‘A new ZCS turn-on and ZVS turn-off unity power
factor PWM rectifier with reduced conduction loss and no auxiliary
stage 7 time duration. Therefore stage 7 time duration can
switches’, Proc. Inst. Electr. Eng. Elect. Power Appl., 2000, 147, (2), be described by (16).
pp. 146–152 To analyse the converter conduction losses, suppose that
23 Wang, C.m.: ‘A novel ZCS-PWM power-factor preregulator with the diode and the switch voltage drops during conduction
reduced conduction losses’, IEEE Trans. Ind Electron., 2005, 3, are Vd , Vs , respectively. So, for a conventional single-switch
pp. 689–700
24 Mahdavi, M., Farzanehfard, H.: ‘Zero-current-transition bridgeless PFC PFC (Fig. 1), during the duty cycle (DT) of the main
without extra voltage and current stress’, IEE Trans. Ind. Electron., switch, two diodes of the input rectifier and the main switch
2009, 56, (7), pp. 2540– 2547 are in the main current path. When the main switch is off
25 Mahdavi, M., Farzanehfard, H.: ‘Self commutation self switched (during DT), two diodes of the input rectifier and the output
bridgeless PFC without any extra switch’. IEEE Second Int. Power
and Energy Conf., Johor Baharu, Malaysia, December 2008,
diode are in the main current path. Therefore neglecting
pp. 1441– 1445 common losses (such as input inductor and output capacitor
26 Hua, G., Leu, C.S., Lee, F.C.: ‘Novel zero-voltage-transition PWM resistances losses which are equal for both configurations),
converters’. Proc. Virginia Power Electronics Conf., 1991, pp. 81– 88 the conduction energy loss during one switching cycle is
27 (Unitrode product and Application Handbook 1995–1996, unitrode
Corp., Merrimack, NH, 1995, pp. 10-303– 10-322
28 Erickson, R.W., Maksimović, D.: ‘Fundamentals of power electronics’
(University of Colorado, Boulder, Colorado, 2nd edn.) Wcl = [(2Vd + Vs )D + (3Vd )D′ ]T , iin .T (39)
29 International Electro Technical Commission Geneve, IEC 61000-3-2,
1998

where T is the switching period, , iin .T is average of the

9 Appendix input current during one switching period. However, for a
bridgeless PFC converter (as shown in Fig. 3), during the
This appendix derivates stages 6 and 7 time duration; briefly
DT, one of the main switches and the body diode of the
analyses the conduction losses of the proposed and
other switch is in the main current path. When the main
conventional single-switch converter; and compares these
switch is off (during DT), one of the main diode and a
two conduction losses.
switch body diode are in the main current path. Therefore
During stage 6, AXsw current can be described as
neglecting common losses (as mentioned before), the
conduction energy loss of one switching cycle is
Vo V
iAXsw = iin + + o sin(v1 t) (36)
Zr0 Zr1
Wcl = [(Vrd + Vs )D + (Vrd + Vd )D′ ]T , iin .T (40)
This stage ends when this current reaches zero for the first
time after t3 . So, the time duration from t3 to t6 can be
described as
where Vrd is the voltage drop of a switch body diode. It is
  clear that the amount of the conduction energy loss for each
1 i + (vo /Zr0 )
t6 − t3 = sin−1 − in (37) switching period in (40) is smaller than that of (39), for the
v1 vo /zr1 average same input current.

IET Power Electron., 2011, Vol. 4, Iss. 6, pp. 732–741 741

doi: 10.1049/iet-pel.2010.0150 & The Institution of Engineering and Technology 2011