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SpyGlass Power

Complete solution Overview

for power estimation Power management techniques, which were once only deployed for wireless
applications, have now become ubiquitous. All IC designers now need to configure
and exploration at their RTL for efficient power partitioning along with reduced static and dynamic
RTL consumption. This is especially true for more advanced technology nodes. These
configurations involve iteratively performing power estimation and exploration to
assess and improve the power efficiency of the design.

Introduction
Every milliwatt of power matters, regardless of the application. Designers can no longer
wait for the final netlist to get accurate power numbers, as full visibility is needed as
soon as RTL coding starts, when the most rewarding modifications can be made. At
smaller technology nodes, dynamic power is becoming increasingly more dominant
and the reduction of overall activity has become a necessity. As designs become vastly
larger, designers need a tool that pinpoints the major power gluttons while suggesting
modifications with the highest ROI.

SpyGlass RTL Signoff

Lint

Clock domain crossing verification

Reset domain crossing verification

Power estimation and exploration

Design for test

Figure 1: SpyGlass RTL signoff solution

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Features and Benefits
• Integrated solution covering all aspects of power analysis including early RTL estimation and exploration
• Input agnostic
––Works at RTL or gate-level
––Supports dynamic activity through FSDB, VCD and SAIF
• Proven accuracy of power estimation through calibration and use of existing data from reference design
• Various actionable profiling metrics such as Clock Gating Ratio (CGR) and Clock Gating Efficiency (CGE)
• Wide breadth of power exploration techniques including fine and coarse grain clock gating, micro-architectural modifications and
memory access optimization
• Complementary to downstream implementation tools as it prepares RTL for better inferred clock gating during synthesis
• RTL signoff solution (power budget and CGE efficiency)

Reference Optional
PR
netlist Initial RTL

Power Power Power Estimation

calibration estimation • Fast power numbers at RTL
for early visibility
Power Exploration
• Process of focusing on improved
clock gating efficiency
Power
exploration
• Metrics driven power analysis

Power
improved
RTL

Figure 2: SpyGlass Power exploration flow

Robust Methodology
The SpyGlass® Power methodology leverages the GuideWare™ methodology to:

• Audit the design for power bugs using activity data (FSDB, VCD)
• Estimate leakage and dynamic power early in the design at RTL
• Leverage the power profiling and exploration capabilities to analyze Clock Gating Ratio and Efficiency
• Integration with Verdi HW/SW Debug and exploring potential enables to improve Clock Gating Efficiency
• Integration with other SpyGlass capabilities targeted for RTL such as Lint, constraints, CDC and DFT

The SpyGlass Predictive Analyzer® technology significantly improves design efficiency for the world’s leading semiconductor and
consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area
requirements of the complex SoCs fueling today’s consumer electronics revolution.

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