LEC # 9

8086/8088 MICROPROCESSOR
AND THEIR SUPPORTING CHIPS

Chapter 10 from reference book

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Microprocessors
 Microprocessors come in all kinds of varieties from the
very simple to the very complex
 Depend on data bus and register and ALU width µP
could be 4-bit , 8-bit , 16-bit, 32-bit , 64-bit
 All µPs have
 Address bus
 Data bus
 Control Signals: RD, WR, CLK , RST, INT, . . .

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8088 pin outs and the pin functions 8088 CPU

• The 8088 microprocessor is housed in a 40-pin DIP Vcc A19/S6

chip. GND A18/S5
• Power is supplied between the Vcc and the GND pins. A17/S4
The voltage at Vcc should be +5V ±10%. CLK A16/S3
RESET
• The clock at the CLK pin provides the basic timing to
the microprocessor. The clock must have a 33% duty READY A15
cycle.
• The microprocessor is reset if the RESET pin is held NMI A8
high for at least four clock periods. Whenever the INTR AD7
microprocessor is reset, it begins executing INTA'
instructions at memory location FFFF0H. AD0
• The READY signal is used to insert wait states, to HOLD
enable the communication between the HLDA ALE
microprocessor and slower memory or peripheral DEN'
devices. MN/MX' DT/R'
• Interrupts are supported by the signals NMI (Non- TEST' RD'
Maskable Interrupt), INTR (Interrupt Request) and SS0' WR'
INTA (Interrupt Acknowledge). IO/M'
• The HOLD and HLDA (Hold Acknowledge) signals
are used to enable DMA (Direct Memory Access).
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8088 pin outs and the pin functions
• The 8088 can operate in a minimum mode (MN/MX=1)
or in a maximum mode (MN/MX=0). The maximum 8088 CPU
mode is used in multiprocessor applications or when a Vcc A19/S6
math coprocessor is used.
GND A18/S5
• The 8088 has a 20 bit address bus and an 8-bit data A17/S4
bus. CLK A16/S3
• The address lines A0..A7 are multiplexed with the data RESET
lines D0..D7 on the pins AD0..AD7. READY A15
• The address lines A16..A19 are multiplexed with status
lines. NMI A8
• If the ALE (Address Latch Enable) signal is activated INTR AD7
(logic 1), the AD0..AD7 pins carry the addresses A0..A7. INTA'
• The DEN (Data Enable) signal is used to enable the AD0
external data bus buffers. HOLD
• The DT/R (Data Transmit/Receive) signal is used to HLDA ALE
specify the direction of the external data bus buffers. DEN'
• The IO/M’ signal is used to select between I/O and MN/MX' DT/R'
memory devices. TEST' RD'
• The RD’ and WR’ signals are used in the Read and SS0' WR'
Write cycles. IO/M'

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8086 pin outs and the pin functions
• Most of the 8086 pins/signals function 8086 CPU
the same way as the 8088 pins/signals. Vcc A19/S6
GND A18/S5
• The main differences between the 8088 A17/S4
and the 8086 are: CLK A16/S3
RESET
– The 8086 has a 16-bit data bus. READY
– The address lines A0..A15 are multiplexed with the AD15
data lines D0..D15 on the pins AD0..AD15. NMI
INTR
– The BHE (Bus High Enable) signal is used to INTA'
enable the most significant data bus bits (D8 AD0
..D15) during a read or write operation. HOLD
HLDA ALE
– The IO/M signal is inverted in the 8086
DEN'
microprocessor, that is a memory is enabled if the MN/MX' DT/R'
IO/M is high, while an I/O device is enabled if the TEST' RD'
IO/M signal is low. BHE' WR'
IO'/M

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8086 vs 8088
Only external bus of 8088 is 8_bit
U? U?
33 16 33 16
MN A D0 15 MN A D0 15
22 A D1 14 22 A D1 14
19 REA DY A D2 13 19 REA DY A D2 13
21 CLK
RESET
A D3
A D4
12 21 CLK
RESET
A D3
A D4
12 8_bit Data Bus
11 11
18 A D5 10 18 A D5 10
INTR A D6 9 INTR A D6 9
A D7
A D8
8 16_bit Data Bus A D7
A8
8
A D9
7
6 20_bit Address A9
7
6 20_bit Address
A D10 5 A 10 5
A D11 4 A 11 4
A D12 3 A 12 3
A D13 2 A 13 2
A D14 39 A 14 39
A D15 38 A 15 38
A 16/S3 37 A 16/S3 37
A 17/S4 36 A 17/S4 36
A 18/S5 35 A 18/S5 35
A 19/S6 A 19/S6
34 34
BHE/S7 SSO
26 26
DEN 27 DEN 27
DT/R 28 DT/R 28
30 M/IO 30 IO/M
31 HLDA 32 31 HLDA 32
17 HOLD RD 29 17 HOLD RD 29
23 NMI WR 25 23 NMI WR 25
TEST A LE 24 TEST A LE 24
INTA INTA

8086 8088
8086 MIN 8088 MIN

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 8086 Minimum Mode
Ready A16/S3 – L
Clock A19/S6 A
4 T
Reset
C
BHE/S7 H
8086
NMI Microprocessors L
AD0–AD15 A
INTR T
16
RD C
TEST MN/ MX=1 H
GND
vcc
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Operation of the Reset Circuit
+5V VRES
On/Off
R1
10K
R2:100 VRES
Reset
Reset C1
10uF

Switch ON Reset Button Pressed Reset Button Released Switch OFF

• Initially the capacitor is uncharged. When power is switched on, the

Reset signal is at logic 1. The capacitor starts charging with time
constant (10K*10uF). When the voltage across the capacitor becomes
equal to the minimum High voltage of the 8284 (2V), the Reset
signal goes to logic 0.
• If the Reset button is pressed, the capacitor is discharged through the
switch. When the Button is released, the capacitor starts charging as
before.
• Resistor R1 is used to reduce the current through C1 when the Reset
button is pressed, thus avoid damaging C1. The diode is used to short
circuit R1 during switch off, thus discharge C1 fast.
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Clock/Reset/Ready Circuit
• The 8284 chips serves 8284 8086/8088
3MHz
three purposes: X1 PCLK
15MHz
– Generates the main 15MHz
OSC
clock (CLK) for the
processor (fc/3 with 33% X2 CLK
5MHz
CLK
duty cycle) and the clock +5V
for the peripheral
On/Off
devices (fc/5).
– Provides the Reset pulse 10K

according to the state of 100

RES RESET RESET
the RC circuit connected
at the RES input. Reset
– Provides the Ready 10uF
signal to insert wait
states whenever the READY READY
processor is accessing RDY
slow memory or
peripheral I/O ports. Wait State Circuit

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 8254 Clock Generator Chip Internal
Structure

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A17/S4, A16/S3 Address/Status Signal

A17/S4 A16/S3 Function

0 0 Extra segment access
0 1 Stack segment access
1 0 Code segment access
1 1 Data segment access

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RESET Operation results

CPU component Contents

Flags Cleared
Instruction Pointer 0000H
CS FFFFH
DS, SS and ES 0000H
Queue Empty
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 Status Signals
S2 S1 S0 Characteristics
Interrupt
0 0 0
acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive State
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 Timing Diagram Conventions
Timing diagrams are the key to understanding digital circuits and
systems. Timing diagrams illustrate how the signals of a circuit
vary as a function of time, as well as the inter- play between the
signals. They are the starting point in describing the way a circuit
or a system ought to work, and after a circuit has been designed,
the timing diagrams tell the readers how the circuit or the system
works. In turn, if this circuit is being used as a sub- system in a
larger design, its associated timing diagram will determine how it
fits into the larger system or how the larger system is to be
designed to accommodate the smaller sub- circuit. (Figure 1.4.)

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AD0 - AD15: Address Data Bus

AD0 – AD15 Data

Address

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 Bus Demultiplexing
• The processor loads on the address bus (AD0 to AD7 and A8 to A19) the address to be
used, and sets the ALE. Thus the address signals A0 to A7 are latched on the 74LS373.
• On the next clock the processor resets the ALE and the AD0 to AD7 lines are used to carry
data (D0 to D7). The DEN enables the buffers of the 74LS245, while the DT/R specifies the
direction (read/write)

CLK
AD7 LS373 A7
AD6 A6
AD5 D Q A5
AD4 A4 A8..A15 A8..A15
EN
AD3 A3
AD2 A2
AD1 A1 Float
AD0..AD7 A0..A7 D0..D7
8088 CPU

EN OE
AD0 A0

ALE
ALE
LS245 D7
D6
D5 RD'
Read Data
D4
D3 DT/R'
D2
D1
DIR G D0 DEN'
DT/R'
DEN' Timing Diagram for a Memory Read Cycle

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 A fully buffered/demultiplexed 8086 system

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A fully buffered/demultiplexed 8088 system
8088 CPU LS373
D Q
8284 Vcc
3MHz A19/S6 EN
X1 PCLK GND
15MHz A18/S5 x8 A16 . . A19
15MHz A17/S4
OSC EN OE
A16/S3
On/Off
X2 5MHz
CLK CLK
+5V
A15 LS244
A14
A13 4
10K
A12
100 RESET RESET A8 . . A15
A11 4
RES A10
Reset A9
10uF A8 E1 E2

READY READY
AD7 LS373
RDY2
AD6
AEN1 AD5 D Q
AD4
CS from memory devices EN A0 . .A7
AD3
RDY1
AD2 x8
7w 6w 5w 4w 3w 2w 1 w 0w AD1
EN OE
AD0
ALE

HOLD LS245
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 HLDA x8
D0 . . D7
LS164 (Shift Reg.) CLK
CLR SI '1'
MN/MX' DIR G
DT/R'
TEST' DEN'
SS0' LS244
RD' 4

WR' RD, WR, IO/M

NMI IO/M' 4
INTR
INTA' E1 E2

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SIMPLIFIED 8086/88 WRITE BUS CYCLE
•During the first clocking period (T1), the address is sent to the address
and address/data connections, and the ALE, DT/R΄ and IO/M΄or M/ΙΟ΄
signals are also output
•During T2 the WR΄, DEN΄are asserted, and data appear on the bus
•In T4 all bus signals are deactivated in preparation for the next bus cycle,
and the WR΄ signal returns to logic 1.

ADDRESS/DATA

WR

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SIMPLIFIED 8086/88 READ BUS CYCLE
•During the first clocking period (T1), the address is sent to the address and
address/data connections, and the ALE, DT/R΄ and IO/M΄or M/ΙΟ΄ signals are
also output
•During T2 the RD΄, DEN΄are asserted
•In T3 the READY signal is sampled and if low, T3 becomes a wait state, to
allow time to the memory to access data
•The bus is sampled at the end of T3
•Finally, the RD΄ signal is deactivated
ONE BUS CYCLE

1 2 3 4 5 6
Clock

ADDRESS VALID ADDRESS

ADDRESS/DATA ADDRESS DATA FROM MEMORY

RD

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BASIC BUS OPERATION
 The 8086/88 processors use the memory and I/O in
periods called bus cycles
 Each bus cycle equals four system-clocking periods
(T1-T4)
 For a 5 MHz clock, one bus cycle lasts 800 ns

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READ CYCLE
➢HERE WE WILL SEE THE ACTIVITIES
CARRIED OUT ON 8086 BUSES AT VARIOUS
TIME INSTANTS WHEN IT READS FROM A
MEMORY LOCATION OR FROM A PORT.

➢HERE WE WILL ASSUME THAT THE 8086 IS

OPERATED IN A MINIMUM MODE.

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 T1 T2 T3 TW T4

CLK

M/IO

ALE

ADDR/ MEMORY ACCESS TIME

DATA A15-A0 RESERVED VALID
D15-D0
FOR DATA

ADDR/
STATUS A19-A16

RD

READY

DT/R

DEN
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WRITE CYCLE

➢HERE WE WILL SEE THE ACTIVITIES

CARRIED OUT ON 8086 BUS AT VARIOUS
TIME INSTANTS WHEN IT WRITES TO A
PORT OR A MEMORY LOCATION.

➢HERE WE WILL ASSUME THAT THE 8086

IS OPERATED IN IS MINIMUM MODE.

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 T1 T2 T3 TW T4

CLK

M/IO

ALE

ADDR/
DATA A15-A0 DATA OUT (D15-D0)

ADDR/
STATUS A19-A16

WR

READY

DT/R

DEN
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THE READY SIGNAL AND WAIT STATES
 A wait state (Tw) is an extra clocking period, inserted between T2 and T3, to
lengthen the bus cycle, allowing slower memory and I/O components to
respond.
 The READY input is sampled at the end of T2, and again, if necessary in the
middle of Tw. If READY is ‘0’ then a Tw is inserted.
 At the end of T2 is sampled on the falling clock edge, while in the middle of
Tw, it is sampled on the rising clock edge.

Tw
1 2 3 4
Clock

READY

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Wait state generator circuit
• Wait states are extra clock pulses
inserted when the processor is CS from memory devices
accessing slow memory or I/O RDY1

devices. AEN1
0 w 1 w 2w 3w 4w 5 w 6 w 7 w
RDY2
• The 8088/8086 allow
approximately 3 clock pulses for a 8284
memory read or memory write. If
the access time of the memory Q 0 Q 1 Q2 Q3 Q 4 Q 5 Q 6 Q 7
(including the delays inserted by CLK CLK LS164 (Shift Reg.)
the bus buffers and address Ready
'1' SI CLR
decoders) is longer than the access
time of the processor (3/f) then
wait states are needed. Ready

• The circuit shown adds 1 wait state CLK

in each memory read or write 8088 RD'

cycle. The number of wait states 8086 WR'
can be changed by changing the INTA'
position of the jumper on the
outputs of the 74LS164 shift
register.
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Self Study
From Book: The 80x86 IBM PC and Compatible
Computer
Chapter 10 Sections 10.10,10.2, 10.3, 10.4
Exercise Work
Problem 13-16,20-26, 27,29

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