Dynamic Performance of PWM STATCOMS Operating under Unbalance and Fault Conditions in Distribution Systems

Su Chen G6za Jobs

Luis T. Moran
Dept. of Electrical Engmeermg Umversidad de Conception Casilla 53-C, Conccpcion, Chile Tel: (56)-41 -203514 Fax: (56)-41-246999 lmoran@manet.d] e.udec.cl Dept. of Electrical and Computer Engineering Concordla Unwers@-1 455 de Maisonneuve W Montreal, Quebec, Canada H3G I M8 Tel: (514)-848-3080 Fax: (514)-848-2802 e-mail: ches@ece concordla ca, geza@ece.concordla.

ca,

Abstract: Static shunt compensation,

voltage

based

on PWM

synchronous

sources, is becoming a viable solution for improving power quality in distribution systems, including voltage regulation at the load bus. This paper describes the operating principles and control techniques of PWM STATCOMS under non-ideal conditions including faults. Negative and zero sequence components are taken mto account, and compensator response time is addressed. Two voltage regulation schemes are proposed and evaluated: the first is the direct voltage control scheme, with a parallel current limiting loop; the second scheme is based on the current controlled voltage source mverter concept, which decouples the voltage and current control functions. Steady state and transient performance obtained on an experimental STATCOM prototype are given for balanced, unbalanced and fault conditions. It is demonstrated that both the proposed schemes can satisfactorily operate under most operating conditions found m distribution systems. The inner current loop scheme enhances system performance, however, the system dynamic response may exhibit instability under certain conditions.
Keywords: Reactive power compensation, shunt compensation, power system faults, power quality, voltage sag, voltage flicker, controller design.

The paper describes the operation principle, and control technique of the var compensator, system response time is addressed. The power circuit topology is shown in Fig. 1. The dc bus capacitor is selected based on the backup energy storage requirement, and the output LC filter is used to satisfy PCC (point of common coupling) voltage and current THD requirements.
ac Source [ v.,, I-&--+ [ lJahc / i I Pointof CommonCouphng 2=1 La 1md ----

I.

INTRODUCTION Fig. 1. Power cmcult of three-phase four-wire STATCOM

Distribution systems, sensitive industrial loads and critical industrial computer-based controllers are affected by various types of outages and service interruptions, which can generally be classified as power quality related problems. They are caused by voltage sags and swells, lightning strikes, partially grounded phases, and other related disturbances. Active power conditioners have been proposed to handle these power quality problems [1-2]. The shunt var compensator based on the synchronous voltage sources and known as the STATCOM, which is mostly used for var compensation, can provide a costeffective solution to improve voltage regulation and apparent short circuit strength without increasing the required interrupting rating of system protective equipment. In this paper, the design of the STATCOM is based on the general case of a three phase four wire power system [5], so the zero sequence component should be taken into account. This is often the case in grounded three phase transmission and distribution systems.

When the var compensator is controlled using only the voltage regulation loop, fast dynamic response is obtained. However, inverter over-current protection must be performed indirectly by means of the voltage controller saturation limiter and the synchronous link reactor. An alternative scheme uses an inner current loop, which decouples the voltage and current control functions, and enhances system performance. But the system response time is limited in this latter configuration, unlike the case where only reactive var compensation is required. This is due to the presence of the relatively large line reactance. Practical controllers are proposed in the paper, considering the faults encountered in distribution systems. They are based on the extraction of instantaneous voltage sequence components using a per-phase based dqO transformation [4]. The superposition theorem is applied and positive, negative and zero sequence compensation are controlled separately. Experimental results demonstrate the feasibility of the proposed schemes. II.
PRINCIPLES OF OPERATION

The proposed STATCOM is coupled to the power system through a transformer. It injects sinusoidal current of variable

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magnitude at PCC, as shown in Fig. 2. The injected current is almost in quadrature with the line voltage, therefore, emulates an inductive or capacitive source at the point of connection, This feature is used to regulate the line voltage. When voltage sag occurs, the STATCOM acts as a capacitor, it injects current into the system to support the PCC bus voltage. In over voltage cases, the STATCOM acts as an inductor, The voltage regulation is directly effected by the voltage drop in the line reactance Xl, Fig. 2.

+ F
jIcl X, ~. -----------------------------

Ppcc

icl JICI xc ~:--+

k===+ ------------->---++---Pcc III.

regulated by injecting only quadrature current ig, and no power swing occurs within a certain frequency range. The control algorithms in this paper are based on this principle, which makes the controller design simple. The output voltage of the compensator is always synchronized to the PCC bus is voltage, and only q-axis current iCq required to regulate the PCC bus voltage. But this choice also limits the maximum dynamic response of the compensator to less than 20 Hz. Otherwise, power system oscillation will occur due to the neglected dq component coupling. CONTROLSTRATEGYIMPLEMENTATION

vC2

j~,2 XC

Fig. 2. Vector diagram for under-voltage

and over-voltage compensation

The voltage support capability of the STATCOM depends on the available line impedance back to the ac mains, and the dynamic response of the STATCOM is directly affected by the line parameters, resistance r, and reactance GoL1. his is T the result of the d-g coupling of the three phase components. In order to simplify the controller design, the d-q components are considered decoupled, with the assumption that the reactance is much greater than the resistance [7], as shown in Fig. 3, where rl = 0.02 pu, and COL1 0.2 pu. =

The control algorithm is based on the superposition theorem the unbalanced three phase four wire power system is represented by means of instantaneous symmetrical sequence components. A number of techniques are applicable in sequence components extraction, including: per-phase based cLq-O transformation [4], phase-locked-loop zero crossing detection, DSP hardware dependent instantaneous space-vector transformation and FFT acceleration algorithm, short data-time window algorithm [3], etc. The main criteria are the computational delays and the ability to remove the effects of unbalances and harmonics. In this paper, the per-phase based d-q-O frame transform is employed, which is proposed in [4]. It eliminates the need for three-phase symmetry, the delay time of the PLL is a half to one cycle of the fundamental frequent y (8 to 17 ins).

A.

Direct Voltage Control Method

,,

100

lK

10K

10

100 Freq.ency (Hz)

,K

1.K

Fig. 3. Frequency response of d-q components direct-gain and cross-gain,

The Bode plot of Fig. 3 shows the relationship between the current component i~ and the voltage components Vd and v~. Similar results can be derived by for the effect of i,f on regulating the voltages Vdand v~. In the low frequency range (f< 20 Hz), the cross coupling between i, and Vd is much greater than the direct gain of i~ to Vq.This means the PCC bus voltage (assuming it is synchronized with Vd) can be

Fig. 4 depicts the block diagram for this technique. The superposition theorem is applied to positive, negative and zero sequence regulation loops respectively. The system exhibits fast response. In the positive-sequence voltage regulation loop, another angle regulation loop is used, in addition to magnitude regulation, to make the STATCOM absorb or supply real power fromlto the ac mains, so as to control the dc bus voltage. Regarding to this 8 phase-shift control, when the output voltage of the inverter lags the line voltage by a small angle, the inverter absorbs a small amount of real power to charge the dc bus capacitor and compensate internal and switching losses. The converse is true when the dc bus voltage is too high, Regarding the dc bus voltage control, we know that: (i) There is second-order harmonics superimposed in the dc bus voltage under unbalance conditions. (ii) The response of the de-bus voltage control loop is limited to less than 15 Hz, to avoid the effect of the second harmonic. Within this range, the open-loop power stage can be modeled as a first order low-pass filter. The mathematical model is analyzed in detail in [1], and the transfer function is

Vdc(,s) 0.612. ?nO ZC~o(rC2 oJ~L~) 0.375 rnoOoLc l~co ~ + + (1) 6(s) = (r~C+ o~L~C+ 0.375. m($LC)s+ 0.375m~rc .
where m. is the modulation index, iC~O the steady state is injected current, and V~CO the steady state dc bus voltage, is and C is the value of the dc bus capacitor.

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I [V,y

+ 9 d-axis Ivdo+l

3
[Vy

lx+

VSI
Inverter

I 02

Fig. 4. STATCOM positive and negative (zero sequence loop not shown) voltage regulation loops with direct voltage control scheme

B.

Voltage and Current Cascaded loop Control Method

A current control loop provides inherent over-current dynamics. The protection and linearizes the converter cascaded control loops are shown in Fig. 5. The design procedure for the current and voltage loops is based on their respective time response requirements. Since the transient response of the STATCOM is determined by the current control loop, its time response has to be fast enough to follow the current reference waveform closely. The voltage loop should be slower, so the two loops can be decoupled. The current reference waveform is phase-shifted by nearly 90 (leading or lagging) with respect to the corresponding PCC voltage, as demonstrated in vector diagram of Fig. 2. The required compensation current is generated through changing the inverter output voltage with modulation index control.

where i,p is the inphase component of compensator injected current. Since the real power absorbed should be zero in steady state, if a small perturbation A V,f. is applied, the reference current will also require a small amount of AICP about its steady state operating point, and the transfer function of the power stage is derived as

~dc = (~)
Icp
(S) S .

3.VC

C . Vdc

(3)

Based on the same design considerations as that in the direct voltage control scheme, the second order harmonics in the de-bus voltage should be filtered out. A low-pass filter is used in the dc bus voltage control loop, the corner frequency of the low-pass filter is set at 15 Hz. IV.
DVNAMIC RESPONSE TIME CONSTRAINTS

Qi$-lti
A
Current Regulator 1, ZIC(S) Eq.(6) or (7)

The design criteria of STATCOMS include the steady state (accuracy) and dynamic (response time, overshoot and stability) characteristics. The response time of the two proposed methods is investigated in this section.

A.
VPcc
b

Direct Voltage Control Method

For this control scheme, the equivalent circuit for the power stage is shown in Fig. 6, and superposition theorem can be applied in the analysis.

Fig. 5. STATCOM control scheme with cascaded outer voltage loop and inner current loop.

The dc bus voltage control is no longer regulated through 8 phase-shift as in the prior case, because the required current for dc bus voltage regulation only accounts for a very small portion of the total compensation current. In this scheme, the dc bus voltage control is carried out by injecting a small amount of in-phase current component into the current reference. The controller design is based on the instantaneous power relationship between the compensator and the ac mains, which is expressed as:

Fig. 6. Equivalent circuit for voltage regulation and restoration.

dVdc p=3. vc. icp Gvdc. cT

(2)

The transfer function of the power stage is obtained from (5), and based on the compensator parameters in Table 1, the frcquczwy rmponm (without controll~r) is shown in Fig, 7. The power stage frequency response can be treated approximately as a constant dB value in the whole frequent y range (with an error of less than 2.5 dB).

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Table 1, Inverter-load power stage parameters, p. u. values Real values \ 4.69 (Q)
140.6(Q)

Load resistance rj Load reactance Lz Link resistance r. Link reactance L,

0.9

0.436
0.02

180.7 (rnH)
3.12 (0)

0.2

82.9

(mH)

remain at a small value, but not necessarily zero. A proportional controller RV2(S)is adopted, and the bandwidth is the same as that of the positive component regulation loop. For the auxiliary dc bus voltage control loop, based on the analysis in Section III, its dynamic response is limited by the requirement of removing the second-order harmonics. In order to decouple this auxiliary loop horn the PCC bus voltage regulation loop, the dynamic response time is moved to 38 ms.

B. Modified Control With Inner Current Loop

When an inner current loop is added, the instantaneous equivalent circuit for the power stage is as in Fig. 8.

li-l.bc

Frequency (rad/see) Fig. 7. STATCOM power stage frequency response (gain and phase) with the direct voltage control method.

Fig. 8, Equivalent circuit for voltage compensation regulation loop.

with inner current

The VSI inverter with high switching simplified as a constant gain with delay, GinV(s) =

frequency

can be

vmo~(s)

J-c(~) _ O.svdc ~ Vtyj

~tm .s

(4)

where the time ccmstant tm= 1/(6f~w), i.e, one sixth of the switching cycle time. For this systen+ the overall response time is constrained by the slowest unit, which is the per-phase based instantaneous dqO component extraction block. According to the prior analysis, the time delay of this block is around 10 ms. The overall system response time should not exceed 15 ms. The voltage control is accomplished by using three separate loops for positive, negative and zero sequence respectively. On the positive component regulation loop, a PI controller Rvl(s) is designed to eliminate steady state error. The design procedure is given in [2]. For negative and zero sequence components, we can apply the same design procedure as that of the positive sequence component. But we should notice the following differences: (i) There is no angle regulation (no 8 phase-shift). (ii) When these two components are very near zero, their phase angle will oscillate between -180 and 180, and this requires a very fast system response to regulate. (iii) Normally their values are small (slightly unbalanced). So the emphasis is on the positive sequence compensation, and the static error of negative and zero sequence components is allowed to be
Vpcc (.) L,L2

The corresponding transfer fi.mction of the converter power stage is given b y (6), With the same parameters as in Table 1, and with the capacitor Cf open circuited, the frequency response of the power stage is shown in Fig. 9. Since the current of the inductive components can not be changed instantaneously, the system frequency response shows that the power stage is susceptible to oscillate in the high frequency region.

Frequency

(rad/see)

Fig. 9. Frequency response (gain and phase) of the power stage with current controlled STATCOM.

The equivalent transfer function of the power stage in the frequency range of interest (within 1000 ra&s region) is derived by replacing the parameters of Table 1 into (6)
(5)
(rl+r2)rc)

.s2

+(L,.z +Lzq)~+q.z
l+r2)Lc+Llr 2+L2rl)$+(,l~2+

(s) Vc Jfpcc (s)

((L~+L2)Lc+ L,L~)f2+(

(Ll+L2)rc+(r

LlL2s2+(

r2L*+q. L2)s+qr2
q. L2)s 2+( Cf.

(6)
q.r2+Ll+L2)S+~+r2

It(s)

= cj.

LJ.L2. s3+(cf. r2.L1+cf

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Vpcc(s)
GjP~ (S)=

Ic

z 4.47.
(S)

1+ S .0.025
1

(7)

The controller consists of an inner current loop and an outer voltage loop. In the current loop, a constant switching frequency PWM is adopted in order to simplify the ripple LC filter design. The current loop bandwidth is designed to be one third of the switching frequency. In our proposed system, the switching fi-equency is 63 pu, then the bandwidth of the current loop has been chosen to be 1200 Hz. Regarding the outer voltage loop, its dynamic response is greatly restricted by the characteristics of the power stage, which tends to oscillate in the frequency range beyond 8 Hz. Therefore, the response time of the voltage loop is chosen at 300 ms. At the chosen crossover fi-equency, the phase shift of the power stage is leading rather than lagging, an integrator controller is used for the positive sequence voltage regulation. Based on the same reasons as stated in the prior control scheme, the negative and zero sequence control loop is composed of a proportional controller and a low-pass filter with a corner frequent y of 3.5 Hz. The resulting steady state error is around 2.2 A,rather than zero. For the auxiliary de bus voltage control loop, the design considerations are based on the filtering of the second order harmonic and the mathematical model in (3). v. EXPERIMENTALRESULTS

ms) than that of scheme 2 with inner current loop (300 ins), but the two control methods exhibit the same steady state performance. Both schemes can limit the injected current within the rated value, but in scheme 1, the current is limited indirectly by voltage controller saturation limiter and synchronous link reactor, therefore, parameter changes will affect the current limit. In scheme 2, the injected current is automatically limited, I I I / I 1 I

(a)

Curve 1 to 3: positive, negative and zero sequence voltage components, 100 V/div, bottom 4: fault trigger, -time: 100 ms/div. I

A laboratory prototype has been built, based on the following criteria: (i) limiting the current and voltage of the STATCOM within rated values; (ii) obtaining a large instantaneous di/dt capacity; (iii) reducing ripple in the dc bus voltage; (iv) satisfying the harmonic suppression requirements according to the IEEE-519 standard, i.e. TffD of the PCC voltage after compensation of less than 5/0. Simulation studies are carried out to predict the performance of the STATCOM, and experimental results are obtained to validate the theoretical considerations. The base quantities are set as line voltage 208 V and power 5,0 kVA, the compensation capability of the compensator is 0.5 pu. Fig. 10 shows the dynamic performance of the compensator with the direct voltage control method, in the case of a source voltage single-phase to ground fault. From Fig. 10 (a), the positive sequence voltage is maintained at 208 V, and negative and zero components are kept at nearly zero even under fault conditions. Fig. 10 (b) shows the transient voltages at the PCC and de-bus voltage, and (c) shows the injected current waveforms. Fig. 11 shows the transient waveforms of the compensator with cascaded voltage and current control loops, in the case of utility double-line to ground fault, Fig. 11 (a) shows that the positive sequence voltage is maintained around 208 V, and negative and zero components are kept at nearly zero under fault conditions. Fig. 11 (b) shows the waveforms at the PCC and de-bus voltage. Fig. 12 gives the steady state PCC bus voltage waveforms, both control methods giving the same result. It is shown that the harmonic distortion is small. Results show that scheme 1 with direct voltage control has faster dynamic response (15

(b)

Top: PCC bus voltage 100 V/div, middle: dc bus voltage 50 V/div, bottom: fault trigger, time: 100 ms/div. 1 I I

J.

(c)

Top: injecting current 5 A/div, middle: dc bus \oltage bottom: fault trigger, time: 100 ms/div,

50 V/div,

Fig. 10. Performance of the proposed compensator with direct voltage control method, in the case of single phase partially grounded fault,

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d+

+.m.=++-

+++

+1!

The transient response of directly voltage control method is faster than that of the alternative method with cascaded voltage and current control loop. This is the result of the use of an inner current loop. In the steady state, both schemes demonstrate almost the same performance, The compensator with inner current loop has inherent over-current protection, but at the cost of a slower dynamic response. For faults on adjacent feeders, the compensation capacity depends upon the reactance back to the ac mains. VII. ACKNOWLEDGMENTS

,.

--%+d
~

4?+-

Wf#
(a)
Cume

1 to 3: positive, negative and zero sequence voltage components, 100 V/div, bottom 4: fault trigger, time: 100 ms/div.

The authors wish to thank Mr. Fabrice Crttette from IRESTE France, for support in the experimental set-up, and the National Sciences and Research Council of Canada for financial support. VIII. REFERENCES

[1] G. Joos, L. Moran, P.D. Ziogas, Performance

analysis of a PWM inverter var compensator: IEEE Trans. on Power Electronics, vol. 6, no. 3, July/August 1991, pp. 380-391.

[2]

A. Campos, G. Joos and J. F. Lindsay, Dynamic analysis and design of a static series compensator for unbalanced AC voltage supplies, in ConJ Rec. IEEE IAS94. pp. 954-961. K. Haddad, G, Joos, A fast algorithm for voltage unbalance compensation and regulation in faulted distribution systems, in Conf Rec. IEEE APEC 98. Feb. 1998, New York, USA, pp. 963-969. C. Hochgraf, R. H. Lasseter, STATCOM controls for operation with unbalanced voltages, IEEE Trans. Power Delivery, vol. 13, no.2, April 1998, pp. 538-544.

[3]

(b)

Top: PCC bus voltage 100 V/div, middle: dc bus voltage 50 V/div, bottom: fault trigger, time: 100 ms/div,

< R;:~ ~~~~ ~L

[4] [5]
w

I.k

A.k411

M. Aredes, J. Hafner, K. Heumann, Three phase four wire shunt active filter control strategies: IEEE Trans. Power Electronics, vol. 12, no,2, March 1997, pp. 311-318. of STATCOM vol. 13, no, 4,

[6]

Fig. 11. Performance of the compensator with cascaded voltage and current control loops, in the case of double-line partially grounded fault.

P. W. Lehn, M. R. Iravani, Experimental evaluation closed loop dynamics, IEEE Trans. Power Delivery, October 1998, pp. 1378-1384.

[7]

Q. Yu, S. Round, L. Norum, T. Undeland, Dynamic control of a unified power flow controller, in Conf Rec. PESC 96, pp. 508-514.

Ix.

BIOGRAPHIES

Su Chen received the B. SC. and M. SC. degrees from the Department of Electrical Engineering, Zhejiang University, China, in 1987 and 1989 respectively. He is currently working towards the Ph.D. degree in the Department of Electrical and Computer Engineering, Concordia University, Montreal, P. Q., Canada, where he is engaged in research and application of custom power devices for mitigating power quality problems. From 1990 to 1998, he was a Design Engineer with U-TOP Video-Communication Equipment Company, Guangzhou, China.

Fig. 12. Steady state performance of the PWM STATCOM. Top: PCC bus voltage 100 V/div, bottom: dc bus voltage 50 V/div, time: 5 ms/div.

G&zaJoos (M78 SM89) received the M.Eng. and Ph.D. degrees from McGill University, Montreal, P. Q., Canada, in 1974 and 1987, respectively .Since 1988, he has been with the Department of Electrical and Computer Engineering, Concordia University, Montreal, P. Q., Canada, where he is engaged in teaching and research in the area of power converters, with applications to power systems and electrical drives. From 1975 to 1978, he was a Design Engineer with Brown Boveri Canada and from 1978 to 1988, he was a professor at the Ecole de Technologies Sup&-ieure, Montreal, P. Q., Canada.
Luis T. Moran (S78 M81) received the M. SC. degree m electrical engineering from University of Conception, Conception, Chile in 1982 and the Ph.D. degree in electrical and computer engineering, Concordia University, Montreal, P. Q., Canada in 1990. From 1982 to 1985 and since 1990, he has been with the Department of Electrical Engineering of the University of Conception, where he is engaged in teaching and research in the area of static power converters.

VI.

CONCLUSIONS

STATCOM is shmvu to perform effective voltage support, in addition to var compensation. The system operates under non-ideal source and load conditions, to restore the PCC bus voltage following short-term fauhs.

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