Electrical Characteristics

ＩＮＴＥＬ　ＨＭ５Ｘ　时序图

8.8 Power Management Timing Diagrams

Figure 8-1. G3 w/RTC Loss to S4/S5 Timing Diagram

Source Destination Signal Name

Board PCH VccRTC t226

t200
Board PCH RTCRST#
t225

Board PCH VccSUS

t201
Board PCH RSMRST#
t202
PCH Board SUSCLK toggling

PCH Board SLP_S5# Only for S4 after G3

Figure 8-2. S5 to S0 Timing Diagram

Source Dest Signal Name

PCH Board SLP_S5#

PCH Board SLP_S4# t203

PCH Board SLP_S3# t204

PCH Board SLP_M# Could come up as early as before SLP_S5#

or as late as SLP_S3#, but no later

Board PCH VccME

t229
Board PCH Vcc

Board Processor VCC_CPU

Processor
PCH SYS_PWROK No required ordering w.r.t. PWROK, but
VRM SYS_PWROK will typically be first

t205
Board PCH PWROK t230
t206
t207
Board PCH MEPWROK MEPWROK may come up earlier
than PWROK, but no later

Board PCH LAN_RST# LAN_RST# may come up earlier than or at the same time as PWROK, or it
may be statically grounded for platforms not using Intel LAN

PCH Processor DRAMPWRGD

Ramps to ‘1’ with

PCH Clock Chip STP_PCI# Vcc power

Clock Chip
Clock Chip PCH stable
Outputs
t208

t209
PCH Processor PROCPWRGD

PCH Board SUS_STAT# t210

Processor/
PCH PLTRST# t211
Board

Datasheet 363
 ＩＮＴＥＬ　ＨＭ５Ｘ　时序图 Electrical Characteristics

Figure 8-3. S3/M3 to S0 Timing Diagram

Source Dest Signal Name

PCH Board SLP_S5#

PCH Board SLP_S4#

PCH Board SLP_S3#

PCH Board SLP_M#

Board PCH VccME

Board PCH Vcc

Board Processor Vcc_cpu

Processor
PCH SYS_PWROK No required ordering w.r.t. PWROK, but
VRM SYS_PWROK will typically be first

t205
Board PCH PWROK t206

Board PCH MEPWROK

Board PCH LAN_RST#

PCH Processor DRAMPWRGD

Ramps to ‘1’ with
PCH Clock Chip STP_PCI# Vcc_main

Clock Chip
Clock Chip PCH stable
Outputs
t208

t209
PCH Processor PROCPWRGD

PCH Board SUS_STAT# t210

Processor/
PCH PLTRST# t211
Board

Figure 8-4. S5/Moff - S5/M3 Timing Diagram

Source Dest Signal Name

PCH Board SLP_S5#

PCH Board SLP_S4#

PCH Board SLP_S3#

PCH Board SLP_M#

Board PCH VccME, VccLAN

t207
Board PCH MEPWROK

Board PCH LAN_RST# LAN_RST# will come up at the same time as MEPWROK, or it may
be statically grounded for platforms not using Intel LAN

t212

SPI
PCH SPI
Flash
t213
PCH Controller Link CL_RST1#

364 Datasheet
Electrical Characteristics
ＩＮＴＥＬ　ＨＭ５Ｘ　时序图
Figure 8-5. S0 to S5 Timing Diagram

Source Dest Signal Name

DMI DMI Message L2/L3

PCIe* normal
PCH PCIe Ports L2/L3
Devices operation

PCH Board SUS_STAT# t214

t215
Clock Chip &
PCH STP_PCI#
Integrated Clk
PCH Board PLTRST# t216

PCH Board PROCPWRGD t217

CPU PCH THRMTRIP# honored ignored

t218
PCH Board Clocks valid
t219

PCH Board SLP_S3#

t220
PCH Board SLP_S4#
t221
PCH Board SLP_S5#
t222
Board PCH PWROK
May drop before or after
SLP_S4/5# and DRAMPWRGD

Board PCH SYS_PWROK

PCH Processor DRAMPWRGD

PCH Board SLP_M# Intel® ME-Related Signals

Going to M3: stay high
Going to MOFF: go low
MEPWROK /
Board PCH
LAN_RST#
Controller
PCH Link
CL_RST#1

Figure 8-6. DRAMPWRGD Timing Diagram

Source Destination Signal Name

PCH Board SLP_S4#

Board PCH PWROK

PCH Processor DRAMPWRGD t223 t224

Datasheet 365