SE. SEM Ill CHOICE BASED / ELTL / DIGITAL SYSTEM DESIGN /22.05,2818 Wa) 2018 NB: Qu Q2 Q3 Q4 Qs Qs qa) Q) @ 4) a) If F(A,B,C)= 5 m(03,5,7) with its truth table and express F in SOP and Hours) 80 Marks Question No. 1 is compulsory. Solve any three questions from the remaining five Figures to the right indicate full marks ‘Assume suitable data if necessary and mention the same in answer sheet. POS form ) Compare TTL and CMOS Logic families ) Perform the following operation using 2's compliment i) Mo -O5)o ii) 60)» CA) Comment on results of (i) and (ii) 4) Compare SRAM with DRAM a) Implement following Boolean function using 8:1 multiplexer, 10) F(A,B.C,D) = ABD + ACD+ BCD+ AED 'b) Design 3 bit Binary to Gray code Converter (10) 8) What are shift registers? How are they clasSified? Explain working of any [10] one type of shift register. b) Write VHDL code for 3 bit up counters [10] a) Explain Master slave IK Flip flop 6) b). Convert T flip flop to D flip flop, 61 ©) Minimize the following expressioflusing Quine McClusky Technique (19) F(4,B,C,D)= ¥m(13,7,9,10,1113,15) a) State and prove Demergan’s theorem (5) ») b) Convert (532.125)s into decimal, binary and hexadecimal. &) ©) Explain Full Adder circuit using PLA having three inputs, 8 product terms [10] and two outputs, a) Prove that NANDaand NOR gates are universal gates, (10) ) Draw anidexplain 3 bit asynchronous binary counter using positive edge [10] triggered JK flip flop. Draw the waveforms. 2FEE6430A725D77A0463A 14AS3DABFF6