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  • Quanta DAKL2FMB8F0 Lenovo Y460P 2

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    ougeyf
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    The document provides a diagram of the power management system for a laptop. It shows the connections between the battery, charger circuit, power management integrated circuit, and other components. The power management integrated circuit monitors the battery, charger, and power signals from components to control power states and resets. It provides power good signals to indicate stable power supplies to key subsystems like the CPU, memory, graphics card, and peripherals.

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    The document provides a diagram of the power management system for a laptop. It shows the connections between the battery, charger circuit, power management integrated circuit, and other components. The power management integrated circuit monitors the battery, charger, and power signals from components to control power states and resets. It provides power good signals to indicate stable power supplies to key subsystems like the CPU, memory, graphics card, and peripherals.

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    © All Rights Reserved
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    50 views1 page

    Quanta DAKL2FMB8F0 Lenovo Y460P 2

    Uploaded by

    ougeyf
    The document provides a diagram of the power management system for a laptop. It shows the connections between the battery, charger circuit, power management integrated circuit, and other components. The power management integrated circuit monitors the battery, charger, and power signals from components to control power states and resets. It provides power good signals to indicate stable power supplies to key subsystems like the CPU, memory, graphics card, and peripherals.

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    © All Rights Reserved
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    of 1

    5 4 3 2 1

    Huron River
    1 5VPCU 5VPCU
    12 HWPG(All Power GOOD)
    VTTPWRGOOD
    ADP IN Charger
    VIN 5 5V_S5 16 PM_DRAM_PWRGD
    Circuit MAX17020ETJ+ 1 3VPCU SYS_PWROK SM_DRAMPWROK
    15
    BAT
    ISL88731A AO6402A
    17 H_PWRGOOD
    UNCOREPWRGOOD
    4
    3VPCU
    HWPG(3/5VPCU) S5_ON PLTRST#
    1a 18
    RSTIN# Madison
    D 5 3V_S5 D

    26 GPU_RST#
    3VPCU AO6402A GPU_RST#

    3VPCU 5VPCU
    DGPU_HOLD_RST#

    PLTRST#
    13

    DRAMPWROK
    2 WRST_8512# 25 +VCC_CORE
    R WRST# 6 VT1316M
    RSMST# RSMRST#
    470K GPIO +
    C 0.1U 7 SIO_PWRBTN# 14
    PWRBTN# VT1317S

    3 NBSWON#
    EC 8a PM_SLP_S4# SYS_PWROK
    15
    SYS_PWROK
    IMVP_PWRGD
    VR1_READY
    VRON
    13 +VCC_GFX

    8b PM_SLP_S3# PWROK
    MEPWROK
    ITE-8518 GPIO
    19a DGPU_PWR_EN#
    PCH

    0ohm
    R
    GPIO 24 GFXPG_R
    12 HWPG(All Power GOOD)
    DELAY 99mS
    13 ECPWROK

    12a VRON

    1a HWPG(3/5VPCU)
    VIN

    C C
    10a HWPG(+1.5VSUS)

    TPS51116REGR
    9a SUSON 10a +1.5V_SUS VIN
    10b +1.05V_VTT

    10d
    0.75VSMDDR_VTERM
    OZ8115
    LDO 11b HWPG(+1.05V_VTT)

    10c +1.5VCPU_PG
    5VPCU VIN
    10b +1.05_PCH
    HWPG(All Power GOOD)

    10a 5VSUS
    AO6402A OZ8115
    11b HWPG(+1.05V_VTT)

    3VPCU
    VIN
    10b +1.8V

    10a 3VSUS
    AO6402A
    OZ8115
    11b HWPG(+1.8V)

    9b MAINON
    VIN
    10b +0.85V
    B B

    VIN
    OZ8115
    20a 11b HWPG(+0.85V)
    19c GFX_CORE
    19a
    DGPU_PWR_EN# MAX8792
    5VPCU
    19b
    10b +5V
    20b
    AON7410
    GFXPG_1V_EN

    1.5VSUS
    21a
    +1V_GFX_PCIE 3VPCU
    LDO
    10b +3V
    RT9018B
    AON7410

    +3V
    21b
    1.5VSUS
    22a +3.3V_DELAY
    +1V_PCIE_PG

    10b +1.5V
    AO6402A
    AO6402A
    1.5VSUS
    A A
    22a
    +1.5V_GPU
    1.5VSUS
    TPCA8030-H
    10b +1.5VCPU
    10c +1.5VCPU_PG
    AO6402A Delay
    +1.8V
    PROJECT : KL2D
    23a 12 HWPG
    24 GFXPG_R Quanta Computer<Project
    Inc. Name>
    +1.8V_GPU
    AO6402A Delay Size Document Number Rev
    23b DGPU_PWROK POWER SEQUENCE DIAGRAM 1A

    Date: Saturday, July 24, 2010 Sheet 2 of 47


    5 4 3 2 1

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