Reveil (Moore)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Use ieee.numeric_std.all;
Use ieee.std_logic_unsigned.all;
entity reveil2017 is
PORT( clock,Key,Trip :IN BIT;
Ring :OUT BIT);
end reveil2017;
architecture Behavioral of reveil2017 is
TYPE typetat IS (Armed, Off, Ringing);
SIGNAL etat : typetat;
BEGIN
-- partie séquentielle
PROCESS (clock)
BEGIN -- partie séquentielle
IF( Clock ='1' AND Clock'EVENT )THEN
CASE etat IS
WHEN Off => IF key ='1' and Trip='0' THEN etat<= Armed;
ELSE etat<= Off;
END IF;
WHEN Armed => IF Key = '0' THEN etat<= Off;
ELSIF Trip ='1' THEN etat<= Ringing;
ELSE etat<= Armed;
END IF;
WHEN Ringing => IF Key ='0' THEN etat<= Off;
ELSE etat<= Ringing;
END IF;
END CASE;
END IF;
END PROCESS;
-- partie combinatoire
PROCESS(etat)
BEGIN
IF etat = Ringing THEN Ring<='1';
ELSE Ring <='0';
END IF;
END PROCESS;
end Behavioral;

Jeux lumière (Moore)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Distributeur is
port(m,H : in std_logic;
 S: out std_logic_vector(2 downto 0));
end Distributeur;

architecture Behavioral of Distributeur is

type typetat is (initial, E1, E2, E3,E4);
signal etat : typetat;
begin
process (H)
begin
if (H'event and H='1') then
case etat is
when initial=> if (m='1' ) then etat <= initial;
else if(m='0') then etat <= E1;
end if;
end if;
when E1=> if (m='1' ) then etat <= E1;
else if(m='0') then etat <= E2;
end if;
end if;
when E2=> if (m='1' ) then etat <= E2;
else if(m='0') then etat <= E3;
end if;
end if;
when E3=> if (m='1' ) then etat <= E3;
else if(m='0') then etat <= initial;
end if;
end if;
when others=> etat<=initial;
end case;
end if;
end process;
--Logique combinatoire
process (etat)
begin
if (etat = initial) then S <="000";
end if;
if (etat = E1) then S <="100";
end if;
if (etat = E2 ) then S <="101";
end if;
if (etat = E3 ) then S <="001";
end if;
end process;
end Behavioral;

Distributeur (Mealy)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Distributeur is
port(X,Y,H : in std_logic;
B : out std_logic_Vector(1 downto 0));
end Distributeur;

architecture Behavioral of Distributeur is

type typetat is (initial, E1, E2, E3, E4);
signal etat : typetat;
begin
process (H)
begin
if (H'event and H='1') then
case etat is
when initial=> if (X='0' and Y='0') then B <="00" ; etat <= initial;
else if(X='0' and Y='1') then B
<="10";etat <= initial;
else if(X='1' and Y='0') then
B <="00";etat <= E1;
end if;
end if;
end if;
when E1=> if (X='0' and Y='0') then B <="00";etat <= E1;
else if(X='0' and Y='1') then B
<="01";etat <= initial;
else if(X='1' and Y='0') then
B <="00";etat <= E2;
end if;
end if;
end if;
when E2=> if (X='0' and Y='0') then B <="00";etat <= E2;
else if(X='0' and Y='1') then B
<="01";etat <= initial;
else if(X='1' and Y='0') then
B <="00";etat <= E3;
end if;
end if;
end if;
when E3=> if (X='0' and Y='0') then B <="00";etat <= E3;
else if(X='0' and Y='1') then B
<="01";etat <= initial;
else if(X='1' and Y='0') then
B <="00";etat <= E4;
end if;
 end if;
end if;
when E4=> if (X='0' and Y='0') then B <="00";etat <= E4;
else if(X='0' and Y='1') then B
<="01";etat <= initial;
else if(X='1' and Y='0') then
B <="10";etat <= initial;
end if;
end if;
end if;
end case;
end if;
end process;

end Behavioral;