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Circuito de Fuente
Circuito de Fuente
Circuito de Fuente
6 8
RT C1
Oscillator Q Q1
CT 9
5 Flip–Flop E1
Dead–Time
11
Comparator
+ CK Q C2
0–12 V Q2
4 10
–
Dead–Time E2
Control 0.7 V
+
–
P.W.M.
0.6 mA Comparator Gnd Reference
+ + 12
VCC
1 2
– Error Amplifier – Vref
1 2 3 15 16 7 14
Feedback/P.W.M. 5.0 V
Comparator Input
Figure 1. TL494 Block Diagram
Capacitor CT
Feedback/P.W.M. Comp.
(Pin 3)
Dead–Time Comp. (Pin 4)
Flip–Flop
Clock Input
Flip–Flop
Q
Flip–Flop
Q
Output Q1
Emitter (Pin 9)
Output Q2
Emitter (Pin 10)
Output Mode
Control (Pin 13)
The pulse width modulator comparator provides a means a thermal drift of less than 50 mV over an operating
for the error amplifiers to adjust the output pulse width from temperature range of 0 to 70°C.
the maximum percent on–time, established by the
dead–time control input, down to zero, as the voltage at the APPLICATION OF THE TL494 IN A
400 OFF–LINE POWER SUPPLY
feedback pin varies from 0.5 to 3.5 V. Both error amplifiers
have a common mode input range from –0.3 V to (VCC – A 5 V, 80 A line operated 25 kHz switching power supply,
2 V), and may be used to sense power supply output voltage designed around the TL494, is shown in Figure 3, and the
and current. The error amplifier outputs are active high and performance data is shown in Table 1. A brief explanation
are ORed together at the inverting input of the pulse width of each section of the power supply is as follows:
modulator comparator. With this configuration, the AC Input Section
amplifier that demands minimum output on time, dominates The operating ac line voltage is selectable for nominal of
control of the loop. 115 or 230 volts by moving the jumper links to their
When capacitor CT is discharged, a positive pulse is appropriate positions. The input circuit is a full wave voltage
generated on the output of the dead–time comparator, which doubler when connected for 115 VAC operation with both
clocks the pulse steering flip–flop and inhibits the output halves of the bridge connected in parallel for added line–surge
transistors, Q1 and Q2. With the output mode control capability. When connected for 230 VAC operation, the input
connected to the reference line, the pulse–steering flip–flop circuit forms a standard full wave bridge.
directs the modulated pulses to each of the two output The line voltage tolerance for proper operation is –10,
transistors alternately for push–pull operation. The output +20% of nominal. The ac line inrush current, during power
frequency is equal to half that of the oscillator. Output drive up, is limited by resistor R1. It is shorted out of the circuit by
can also be taken from Q1 or Q2, when single–ended triac Q1, only after capacitors C1 and C2 are fully charged,
operation with a maximum on–time of less than 50% is and the high frequency output transformer T1, commences
required. This is desirable when the output transformer has operation.
a ringback winding with a catch diode used for snubbing.
When higher output drive currents are required for Power Section
single–ended operation, Q1 and Q2 may be connected in The high frequency output transformer is driven in a
parallel, and the output mode control pin must be tied to half–bridge configuration by transistors Q3 and Q5. Each
ground to disable the flip–flop. The output frequency will transistor is protected from inductive turn–off voltage
now be equal to that of the oscillator. transients by an R–C snubber and a fast recovery clamp
The TL494 has an internal 5 V reference capable of rectifier. Transistors Q2 and Q4 provide turn–off drive to Q3
sourcing up to 10 mA of load currents for external bias and Q5, respectively. In order to describe the operation of
circuits. The reference has an internal accuracy of ±5% with Q2, consider that Q6 and Q3 are turned on. Energy is
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coupled from the primary to the secondary of T3, forward output, which will prevent the crowbar SCR from
biasing the base–emitter of Q3, and charging C3 through destruction due to over dissipation. Automatic over voltage
CR1. Resistor R3 provides a dc path for the ‘on’ drive after reset is achieved by connecting jumper ‘A’. The control
C3 is fully charged. Note that the emitter–base of Q2 is section will cycle the power supply output every 2 seconds
reverse biased during this time. Turn–off drive to Q3 until the fault has cleared. If jumper ‘B’ is connected, SCR
commences during the dead–time period, when both Q6 and Q12 will inhibit the output until the ac line is disconnected.
Q7 are off. During this time, capacitor C3 will forward bias
the base–emitter of Q2 through R3 and R2 causing it to turn Low Voltage Supply Section
on. The base–emitter of Q3 will now be reverse biased by the A low current internal power supply is used to keep the
charge stored in C3 coupled through the collector–emitter of control circuitry active and independent from external
Q2. loading of the output section. Transformer T2, Q9 and CR2
form a simple 14.3 V series pass regulator.
Output Section
The ac voltage present at the secondaries of T1 is rectified Control Section
by four MBR 6035 Schottky devices connected in a full The TL494 provides the pulse width modulation control
wave center tapped configuration. Each device is protected for the power supply. The minimum output dead–time is set
from excessive switching voltage spikes by an R–C snubber, to approximately 4% by grounding Pin 4 through R5. The
and output current sharing is aided by having separate soft start is controlled by C5 and R5. Transistor Q11 is used
secondary windings. Output current limit protection is to discharge C5 and to inhibit the operation of the power
achieved by incorporating a current sense transformer T4. supply if a low ac line voltage condition is sensed indirectly
The out–of–phase secondary halves of T1 are cross by Q10, or the output inhibit line is grounded.
connected through the core of T4, forming a 1–turn primary. Error amplifier 1 and 2 are used for output voltage and
The 50 kHz output is filtered by inductor L1, and capacitor current–level sensing, respectively. The inverting inputs of
C4. Resistor R4 is used to guarantee that the power supply both amplifiers are connected together to a 2.5 V reference
will have a minimum output load current of 1 ampere. This derived from Pin 14. By connecting the two inputs together,
prevents the output transistors Q3 and/or Q5 from cycle only one R–C feedback network is needed to set the voltage
skipping, as the required on–time to maintain regulation into gain and roll off characteristics for both amplifiers. Remote
an open circuit load is less than that of the devices storage output voltage sensing capability is provided, and the supply
time. Transformer T5 is used to reduce output switching will compensate for a combined total of 0.5 V drop in the
spikes by providing common mode noise rejection, and its power busses to the load. The secondary of the output
use is optional. current sense transformer T4, is terminated into 36 and
The MC3423, U1, is used to sense an overvoltage peak detected by BR1 and C6. The current limit adjust is set
condition at the output, and will trigger the crowbar SCR, for a maximum output current of 85 amperes.
Q8. The trip voltage is centered at 6.4 V with a programmed The oscillator frequency is set to 50 kHz by the timing
delay of 40 s. In the event that a fault condition has caused components RT and CT. This results in a 25 kHz two phase
the crowbar to fire, a signal is sent to the control section via output drive signal, when the output mode (Pin 13) is
jumper ‘A’ or ‘B.’ This signal is needed to shut down the connected to the reference output (Pin 14).
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Output
5 V 80 A 5 V SEN 5 V SEN RTN 5 V RTN Inhibit All Capacitors in F
10 10 All Resistors in Ohms 1/4 Watt
1/2 W 1/2 W
(unless otherwise noted)
2200 10 V
Output
+
Voltage Adj.
1N4001 7.5 k 5.1 k
8.2 k 4.7 k 5k
50 V 10 Turn
1 7
1 50 V 5 Vm 25 0.001
MC3423 36
4
OUTPUT SECTION
+ U1 50 V 1W
3 BR1
‘A’ 50 V
8 0.0033
‘B’ 1k 1k + C6 0.001
22 16 V
1 MEG
4.7 10 W T5 1 15 0.01
R4 + C4 2 50 V
46000 10 V
14
L1 TL494 13 10 k 10 k
T4 U2
10
MBR6035
MBR6035
12 9
0.05
0.05
0.05
0.05
0.1
MBR6035
MBR6035
7
1/2 W
1/2 W
1/2 W
1/2 W
47
50 V
10
10
10
10
C5 8 11 4 R5
MPS 18 k
A 55
T1 50 V Q11
CONTROL SECTION
4 200 V 4 200 V 8.2 k 1N4001 0.001
1N4936 +
1N4936 1 330 16 V
100 0.001 4.7 k
100 0.001
POWER SECTION
5W 1 kV 10
5W MPS
1 kV A 70 1N4001
Q3 Q5 Q10
330 330
TIP31 10 V TIP31 10 V 5.1 k
MJ13015
MJ13015
Q2 Q4
+ +
C3 1.5 k 2.2 k 560
R2 R3 1N4933
33 3W 5
1N4933
33 5 T3
3W Q7
1N4933
TIP32
CR1 +
1000 16 V
10 k 10 k TIP32
Q6
5W C2 5W 560
C1 2400 200 V
1N4933
AC INPUT SECTION
2400
115
Q9
LOW VOLTAGE SUPPLY SECTION
200 V
TIP31
MDA 390 1W 1N4744
230
2504 T2 +
2200 35 V
6–8
115
120 200
10 W
1/2 W R1
230
MAC Q1
15–6
White R.F.I. Filter MDA
115
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Transformer Data
T1 Core: Ferroxcube EC 70–3C8, 0.002″ gap in each leg
Bobbin: Ferroxcube 70PTB
Windings: Primary (Q3, Q5): 50 turns total, #17 AWG Split wound about secondary.
Primary (Q1): 4 turns, #17 AWG.
Secondary, 4 each: 3 turns, #14 AWG Quad Filar wound.
Shield, 2 each: Made from soft alloy copper 0.002″ thick.
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Notes
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Notes
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ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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