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    LAB 7 Open Ended - 1

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    Mahnoor Mansoor
    This document describes designing an 8x8 carry lookahead adder. It discusses implementing carry lookahead logic to reduce propagation delay compared to a ripple carry adder. The design is implemented in Verilog software and the results show that carry lookahead adds can predict carries for next bits before calculating the sum, reducing propagation delay time.

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    LAB 7 Open Ended - 1

    Uploaded by

    Mahnoor Mansoor
    11 views6 pages
    This document describes designing an 8x8 carry lookahead adder. It discusses implementing carry lookahead logic to reduce propagation delay compared to a ripple carry adder. The design is implemented in Verilog software and the results show that carry lookahead adds can predict carries for next bits before calculating the sum, reducing propagation delay time.

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    LAB 7 open ended_1

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    This document describes designing an 8x8 carry lookahead adder. It discusses implementing carry lookahead logic to reduce propagation delay compared to a ripple carry adder. The design is implemented in Verilog software and the results show that carry lookahead adds can predict carries for next bits before calculating the sum, reducing propagation delay time.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
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    Download as docx, pdf, or txt
    11 views6 pages

    LAB 7 Open Ended - 1

    Uploaded by

    Mahnoor Mansoor
    This document describes designing an 8x8 carry lookahead adder. It discusses implementing carry lookahead logic to reduce propagation delay compared to a ripple carry adder. The design is implemented in Verilog software and the results show that carry lookahead adds can predict carries for next bits before calculating the sum, reducing propagation delay time.

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    Download as docx, pdf, or txt
    of 6

    Sec b lab 7 Roll No: 2020-CE-052

    LAB 7
    OPEN ENDED:
    CARRY LOOKAHEAD ADDER
    Objective: Design 8x8 Carry Look ahead Adder.
    Hardware/Software Required:
    Software required is ISE Verilog.
    Working:

    8x8

    pg. 1
    Sec b lab 7 Roll No: 2020-CE-052

    pg. 2
    Sec b lab 7 Roll No: 2020-CE-052

    4x4

    pg. 3
    Sec b lab 7 Roll No: 2020-CE-052

    pg. 4
    Sec b lab 7 Roll No: 2020-CE-052

    Methodology:
    A carry look-ahead adder reduces the propagation delay by introducing more
    complex hardware. In this design, the ripple carry design is suitably transformed
    such that the carry logic over fixed groups of bits of the adder is reduced to two-
    level logic. Let us discuss the design in detail. 

    pg. 5
    Sec b lab 7 Roll No: 2020-CE-052

    Results:
    By Carry Lookahead Adder we can get carry before the sum hence we can predict
    the carry for the next bits before the sum. Hence, it reduces the propagation
    delay time.
    Conclusion:
    In this we have designed a code using Verilog and found the sum for 8 bits of
    data.

    pg. 6

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