Lecture-3

Von Neumann Vs Harvard architecture 1/3

• A Von Neumann (Princeton) architecture has only one bus which is

used for both data transfers and instruction fetches

• Harvard architecture has separate data and instruction busses,

allowing transfers to be performed simultaneously on both busses.

• Tradeoff?
von Neumann architectures 2/3
Harvard Architecture 3/3
General Architecture of Microprocessor and
Microcontrollers CH-1
CPU Architecture 1/2
CPU Architecture 2/2
• The CPU uses registers to store information temporarily.
• ALU (arithmetic/logic unit).
• The function of the program counter is to point to the address of the
next instruction to be executed
• The function of the instruction decoder is to interpret the instruction
fetched into the CPU
Internal working of CPUs 1/5
• step-by-step analysis of the process a CPU.
• Add three numbers (21H+42H+12H)
• Let
• CPU has registers called A, B, C, and D. It has an 8-bit data bus and a 16-bit
address bus.
• The action would be
Internal working of CPUs 2/5
• Put hexadecimal value 21H into register A
• Then add to register A the values 42H and 12H
• Assume that the code for the CPU to move a value to register A is
(B0H) and the code for adding a value to register A is (04H).
• So
Internal working of CPUs 3/5
• necessary steps and code to perform these operations are as follows.
Internal working of CPUs 4/5
• If the program to perform the actions listed above is stored in
memory locations starting at 1400H, the following would represent
the contents for each memory address location:
Internal working of CPUs 5/5
• Actions performed by the CPU as follow
• Program counter must be set to the value 1400H
• CPU puts 1400H on the address bus and sends it out.
• 0xB0, to be put on the data bus and brought into the CPU.
• CPU decodes it with instruction decoder.
• Next controller circuitry bring value 21H from memory location 1401,
• After completing program counter points location 1402H
• And so on…
RISC VS CISC 1/4 CH-1

• RISC = Reduced Instruction Set Computer.

• CISC = Complex Instruction Set Computer.
• RISC has less instructions but apparently faster execution and less
complex microcode.
• CISC has more instructions increasing the complexity of the
microcode possibly slowing the speed.
Example 2/4
• Multiplying two numbers.
• CISC Approach
• MULT 2:3, 5:2

• RISC Approach
• LOAD A, 2:3
LOAD B, 5:2
PROD A, B
STORE 2:3, A
 Summary 3/4
CISC
Emphasis on hardware
Includes multi-clock
complex instructions
Memory-to-memory:
"LOAD" and "STORE"
incorporated in instructions
Small code sizes,
high cycles per second
Transistors used for storing
complex instructions
RISC
Emphasis on software
Single-clock,
reduced instruction
Register to register:
"LOAD" and "STORE"
are independent instructions
Low cycles per second,
large code sizes
Spends more transistors
on memory registers
Performance Equation 4/4
• The difference between CISC and RISC becomes evident through the
basic computer performance equation:

• RISC systems shorten execution time by reducing the clock cycles per
instruction (i.e. simple instructions take less time to interpret)
• CISC systems shorten execution time by reducing the number of
instructions per program.
Microprocessors
• Only CPU, no RAM, no ROM and no I/O ports
• Examples
• Pentium, PowerPC
• Advantage
• Versatility, designer choice
• Disadvantage
• bulkier and much more expensive
Microcontroller
• CPU (a microprocessor) in addition to a fixed amount of RAM, ROM,
I/O ports, and a timer all on a single chip.
• Ideal for many applications in which cost and space are critical.
• Examples
• AVR, ARM, Atmel
• Advantage
• Cheap and Small in size
• Disadvantage
• Low processing power, application specific.
Embedded Systems
• An embedded system is controlled by its own internal microprocessor
( or microcontroller).
• The microcontroller's ROM is burned with a purpose for specific
functions.
• In an embedded system, typically only one application software is
burned into ROM.
• Examples
• Printer, Microwave oven, keyboard, printer, modem, disk controller, sound
card, CD-ROM driver, mouse,
Embedded System Requirements
• Decrease power consumption and space.
• Also Linux and Windows standardization, many embedded systems
using x86 PCs.
General-Purpose Microprocessors
• Intel
• Freescale Semiconductor (Motorola)
• AMD (Advanced Micro Devices, Inc.)
• ARM (Advanced RISC Machine)
• When a company targets a general-purpose microprocessor for the
embedded market it optimizes the processor used for embedded
systems. For this reason these processors are often called
high-end embedded processors
Microcontroller Selection 1/5
• 5 major 8-bit microcontrollers.
• Freescale Semiconductor's 68HC08/68HCI 1,
• Intel's 8051,
• Atmel's AVR,
• Zilog's 28,
• PIC from Microchip Technology.
• Not compatible with each other due to unique Instruction Set
Choosing a microcontroller 2/5
• Criteria
• Computing needs w.r.t efficiency and cost.
• Availability of software and hardware development tools.
• Wide availability and reliable sources of the microcontroller.
Computing Power 3/5
• Speed
• Packaging
• Power consumption.
• Amount of RAM and ROM
• Number of I/O pins and timer
• Ease of upgrade
• Cost per unit
Availability of software 4/5
• How easy it is to develop products around it.
• C language compiler, an emulator, technical support.
• Hand on Expertise
Reliable sources 5/5
• Ready availability needed quantities.
• Diversified (multiple source) suppliers
AVR microcontroller
AVR Microcontroller History 1/3

The basic architecture of AVR was designed by two

student of Norwegian Institute of Technology and
then was bought and developed my Atmel
Corporation in 1996.
You may ask what AVR stands for?
AVR can have different meanings for different
people! Atmel says its nothing more than a product
name, but it might stand for Advanced Virtual RISC
AVR microcontroller compatibility 2/3
• Mostly 8-bit microcontrollers.
• AVR microcontrollers is not all 100% compatible in terms of software
when going from one family to another family
• To run programs written for the ATtiny25 on a ATmega64, we must
recompile the program and possibly change some register.
Why Atmel’s AVR Microcontroller? 3/3
1. RISC architecture with mostly fixed-length instruction, load-store memory access, and 32
general-purpose registers. Harvard architecture
2. A two-stage instruction pipeline that speeds up execution.
3. Majority of instructions take one clock cycle
4. Up to 20-MHz clock operation
5. Wide variety of on-chip peripherals, including digital I/O, ADC, EEPROM, Timer, UART, RTC
timer, pulse width modulator (PWM), etc
6. Internal program and data memory
7. In-system programmable
8. Available in 8-pin to 64-pin package size to suit wide variety of applications
9. Wide operating voltage from 2.7 V to 6.0 V.
10. Designed from the ground up for efficiency with C code

32
AVR microcontroller program ROM
• In microcontrollers, ROM is used to store programs
• Also known as program or code ROM
• The program ROM size can vary from IK to 256K, but It has ROM
space of 8M (for future expansion)
• The AYR was one of the first microcontrollers to use on-chip Flash
memory for program storage.
AVR microcontroller
Architecture
AVR Packaging Variations

35
AVR family overview (Extra) 1/5
• Classic AVR (AT90Sxxxx)
• Mega AVR (ATmegaxxxx)
• Tiny AVR (ATtinyxxxx)
• Special purpose AVR

• Page/49
AVR family 2/5
• Classic AVR (AT90Sxxxx)
• Original AVR chip,
• AT90S2313, AT90S2323, AT90S4433
AVR family 3/5
• Mega AVR (ATmegaxxxx)
• powerful microcontrollers with more than 120 instructions.
• Large peripheral capabilities.
• 4K to 256KByt prog ROM : 28 to 100 pins etc
• ATmega8,16,32,64,1280
AVR family 4/5
• Tiny AVR (ATtinyxxxx)
• 1K to 8KByt prog ROM : 8 to 28pins, Limited instruction set
• ATtiny13,25,44,84
AVR family 5/5
• Special purpose AVR
• Designing for specific applications.
• USB controller, CAN controller, LCD controller, Zigbee, Ethernet controller,
FPGA, and advanced PWM.
In-system programmable flash AVR controllers
Other microcontrollers
Atmega 328/P 1/6
• Atmel AVR 8-Bit Processors come in a variety of configurations and
packages
• They all share a common core – registers, instructions, basic I/O capabilities
• Our focus is the Atmega 328/P
• Advanced RISC Architecture
• 131 Powerful Instructions
• 8-channel 10-bit ADC in TQFP
• 23 Programmable I/O Lines
• Clock speed 1 MHz up to 16 MHz
• 32K programmable flash (instructions)
• 1K EEPROM
• 2K internal SRAM
• Timers, serial and parallel I/O, ADC
Complete pin structure of Atmega 328/P 2/6
AVR Microcontroller Architecture 3/6
Complete
Architecture
of AVR 4/6
1. The CPU components are
shaded blue.
2. The memory components are
shaded green.
3. The clock components are
shaded in yellow.
4. The I/O components are
shaded in purple.
AVR CPU 5/6
• PC: address of next
instruction
• IR: prefetched
instruction
• ID: current instruction
• GPR: R0-R31
• ALU: Note internal data
path

47
AVR Memory 6/6
• Flash: Machine instructions
go here
• SRAM: For runtime data
• Note bus independence for
data and instructions
• EEPROM: Secondary
storage
• EEPROM and Flash
memories have a limited
lifetime of erase/write cycles

48
Instruction Cycle
• The CPU repetitively performs the instruction cycle:
• Fetch
• The PC holds the address in memory of the next instruction to execute
• The address from memory is fetched and stored in the IR
• The PC is incremented to fetch the next instruction (unless told otherwise)
• Decode
• The CPU determines what instruction is in the IR
• Execute
• Circuitry interprets the opcode and executes the instruction
• Moving data, performing an operation in the ALU, etc.
• May need to fetch operands from memory or store data back to memory
AVR microcontroller I/O pins
AVR microcontroller I/O pins
AVR I/O Ports
• 4 x 8-bit bi-directional I/O port
• Port-A, Port-B, Port-C, Port-D
• Port SFR’s
• DDR: The DDxn bit in the DDRx Register selects the direction of this pin. If
DDxn is written logic one, Pxn is configured as an output pin. If DDxn is
written logic zero, Pxn is configured as an input pin.
• PORT
• PIN
Port SFR’s

ATmega16A [DATASHEET] 64
DDRx
• DDR: The DDxn bit in the DDRx Register selects the direction of this
pin.
• If DDxn is written logic one, Pxn is configured as an output pin.
• If DDxn is written logic zero, Pxn is configured as an input pin.
PORTx
• PORTxn is use to write O/P pin high or low.
• If PORTxn is written logic one when the pin is configured as an input
pin, the pull-up resistor is activated.
• To switch the pull-up resistor off, PORTxn has to be written logic zero
or the pin has to be configured as an output pin.
• The port pins are tri-stated when a reset condition becomes active,
even if no clocks are running.
PINx
• Read only register
• Status of I/P pins are read from PIN register.
Port Pin Configurations summary

DDxn PORTxn Comment

0 0 I/P tristate/floting
1 0 O/P low
0 1 I/P pull up
1 1 O/P Hi