....- ,..

CS-304(CBGS)
@) B.Tech., III Semester
EXAMINATION, November 2019
Choice Based Grading System (CBGS)
DIGITAL SYSTEMS
'.\ote : (i) Attempt any five questio n s.
(ii) All questions carry equal marks.
t. Convert the followin g numbers as directed - 14
(a) (41.5 13) 10 into binary, octal and hexadecimal
(b) (2C6B.F2)1 6 into base 2 , 8 and 10 numbers.
(See Unit-I, Page 14, Prob.7)
2. (a) Simplify the Boolean function u sing K-map. 7
F(wxyz)= L_(0, 1,2,4,5,6,8,9 ,12, 13, 14).
(See Unit-I, Page 59, Prob.35)
(b) Impleme nt a function F=A(B+CD)+ BC' with NAND gates. 7
(See Unit-I, Page 39, Prob.24)
3. (a) Write steps of designing a digital circuit a nd design a full adder
circuit. (See Unit-II, Page 73, Q.6)7
(b) What is decoder? Design a 3 x 8 decoder. 7
(See Unit-II, Page 97, Q.39)
4. (a) How do deisgn a 8 x I MUX using two 4 x I MUX ? Draw the
circuit. 7
(h) Diffe re ntiate combinational and sequential circuits. 7
(See Unit-Ill, Page 108, Q.i)
(a) Draw logic diagram of JK ll ip-flop and give its characteristics table
' and equation. (See llnit-111, Page 113, Q.9) 7
{h) Differentiate static and dyn amic RAM . 7
(Sl'l' l 'nit-111, Page 167 Q
._ . . . , .59)
r- ., . t\i . workin g o f to\low m ~ d1 g11a\ circui·ts
6. , , raw anu ex p 1atn '-' ~ 14
(a) A ID con vi:rtc r (Scl' l lnit-1\'. Pa~c 175 Q l)
(23) • .
I _11111
Digital Systems (CS/ CSIT-Branch)

(b) Bistable multivibrator (Sec Unit-JV, Page 201. Q.3i)

(c} Schmitt trigger. (See Unit-IV, Page 209. Q.43)

7. (a) Draw block diagram of PCM system and explain it. 7
(See Unit-V, Page 253. Q.10)
(b) Explain the terms sampling, quantization and quantization error. 7
(See Unit-V, Page 258, Q.16)
8. Write short notes on any two of the followings - 14
(a) IC 555 (See Unit-IV, Page 210. Q.44)
fbJ TTL family (See Unit-IV, Page 220. Q.54)

( c) Sampling theorem. (See Unit-V, Page 242. Q.3)

 14 Digital systems (CS, cs!T)
Lo 7 t..) - (0.54)x
i.e.. (0·"'' . · JO ~ I i:;4)R
Hen,·c. (41 68 75)10 (. ·-
1 ) (41 N P '))r o ( )1"
(11 ( \ lllH'r"1nn nf i11tcgc1 pnr1 (4 1)I()
k e ma inder
sucrl''"'~h ,. l) h Mon
9
I( ,
I(,
l ~I
~
2
()
1 ,' • ( ➔ I ) 1o ( 29) I 6
<... '"'11 , cr~1,1n ll f fr:ictronal pai1 (0.6875) 10
0.6~ 75 x 16
11l'ITT
I
B
Henc~. (-4 1. 6875) 10= (29.8)16
Prob.-. Com•ert the following numbers as directed -
octal and hexadecimal
(i) (4 /.513Jio into binary,
2, 8, and JO numbers.
(ii) (1C6B.Fl) 16 into base
(R. G.P. V., Nov. 2
Sol (i) ( a ) (41.513)JO = (?)2
Conversion of Integer Part (41) 10 - Refer the sol. of Prob. 6 (i).
Con\- ersion of fractional part (0.5 I 3)10 -
o. 513 ,,. 2 r 0.026 y 2 r 0.052 x 2 , O.104 x 2
1.026 =-i 0.052 :_j 0. 104 =--.l 0.208
'I '
O ~
O 0'
It' .. (0. 5 JJ)JO = (0 .1000 ... )2
Hence (41.51 3) 10 = (101001.1000 ...)i A
( b) (41.513Jiu = (?)8
Conversion of In teger Part (41)rn _ Refer the sol. Prob.6 (ii).
(omtrs1on of fractional part (0 .5 l 3 ) io _
0 513_~ ~ , O. J04 A 8 r 0.832 xx
4.104 _J O XTJ _J -- ··· · ·
f ' - 1 .656
-1 () 6
i.e., ( (J.5 13 ) 10 (<J .4 0(1 . )x
M
Hence (41 513)10 (51.406... )
8
...
 U ni t - I 15

(c ) (4 1 .5 13) 10 = (? ) 16
(4 1) - R ef er th e sol. o f Prob.6 (iii).
P a rt
Co n ,·e rs ion o f Integer
10

rs io n o f fr ac ti on al p ar t (0.513 ) 10 -
C onve
0 8 x _
16 , 0 .3 2 8 x 16 , 0 .248 x 16
0 .5 13 x 1~ 1 0 .2 5 .248 =- ._J 3.968
3 .3 2 8 =-.J
8 .2 0 8 = -i f f
f ♦ 3
3 5
8
3 5 3 ... .) 16
.e ., (0 .5 1 3 ) 10 = (0 .8 A n s.
(2 9 .8 3 5 3 ... )
H en ce (4 1 .5 13 ) 10 = 16
2)
2 ) = ( 2 C 6 B . F
(ii) (a ) (2 C 6 B .F 16 i
i i i i i
1 0 11 0 0 011 0 101 1 . 1111 0 0 I 0
00
1. 11 11 00 10 )2 A n s.
= (0010110 00 11 01 01
6 B . F 2
2 C
(b) (2 C6 B .F2 ) 16 =
0 10 11 0 0 011 0 1 011 . 1111 0 0 l 0
0

,o;o,T ,or, T T ·T 1 1 7
,1 0, ,1 0,
4 4
1 5 3 ·
2 6
A n s.
= (26153.744)8 1
2 + 6 x 16 +
= 2 x 16 +3 C x 16
(c ) (2 C'6B .F2) 16 1 + 2 x 16- 2
8 x 16 ° + F x 16 -
6 2 + 6 X 16 1 +
- 2 X I 6J + J 2 X ]

6o I 5 x I 6 - I + 2 x 16 ~
I J x I -I
A n s.
- ( JJ3 7 L 94 53 1) 1o
 60 D ig ita l Sy stem s (C S, CS
IT)
So l Fu nc tio n F ha s four yz
a fo ur va ri ab le m ap m us
K -m ap of given function F
fig. 1.40.
variables so
t be used.
is shown in
wX
w'x'

w'x
-.·ay'z'
0

4
y'z

1
5
1
yz

7
3
yz'

-
1
r- -6
L
2
~

12
T he m in im iz ed ex pr es si wx J
1 15 14
on 1s given 1 1 it
be lo w - wx' 18 1
9 11 10

F = y' + w'z' + xz' Ans. y i- -

Fig. 1. 40
 Fi g. 1.1 8

Pro b.24. Im ple ment a fun cti on F =

A (B + CD) + BC' wit h /t"A.1VD
(R. G.P. V.. 1\'o v. 2 01 9)
ates.
nta tio n of giv en fun cti on usi ng NA ND ga te is sho\.\n in fig .
So l Impleme
. 19.
A., __ _ _ _ _ ____.

e -- -- -- -- 1
c -- -- ,
o --- --,
n --- --- ,
c- --- -,
Fi):. I. / 9
 Q.2. Explain the design procedure of combinational circuits.
Ans. The design of combinational circuits starts from the specificatio n o f
the problem and culminates in a logic circuit diagram or a set of Boolean
functions from which the logic diagram can be obtained. The procedure involves
the following steps -
(i) From the specifications of the circuit, determine the required
number of inputs and outputs and assign a symbol to each.
(ii) Derive the truth table that defines the required relationship
between inputs and outputs.
 l O Digital Systems (CS, CSIT)

(iii) Obtain the simplified Boolean functions for each output as a

function of the input variables. 1
(iv) Draw the logic diagram and verify the correctness of the design.
A truth table for a combinational circuit consists of input columns and output
columns. The input columns are obtained from the 2° binary numbers for then
input variables. The binary values for the outputs are determined from the stated
specifications. The output functions specified in the truth table give the exact
definition of the combinational circuit. It is important that the verbal specifications
be interpreted correctly in the truth table. Word specifications are often incomplete
and any wrong interpretation may result in an incorrect truth table.
IR r. P V n,w ,n1?1
 Or
D .
H' a f ul / ad de r circuits. (R. GP. V., Dec. 20 I j
es,gn an d dra
ing binary addition of thJt.i
b. -~~ ful Al-a dd er is a de vic
ca
e
ny
ca pa
-in
ble
(C
of
in)
pe
an
rfo
d
rm
ge nerates a su m ou tpu t and a;
lfl3.C) clig ns . su ch as A, Ba nd
t ca rry ( C J. Th e block diagra m of full-adder is sh ow n in fig. 2. 7.
outpu 00

A B Cin

. . - - - - Sum (S) Ca rry Ou t (Coutl

A <>- --f
B t>- -_. Fu ll-
add er
c in ~ - _ . Ca rry Ou t (C00 t)
~ - ~ hm (~ aA ~B $ ~

Fig. 2. 7 Block Diagram of Fig. 2.8 Realization of a Full-adder

a Full-adder Using Various Logic Gates

lization of full-ad de r us ing thr ee input EX-OR gate, three ti

Th e rea
D ga tes and on e thr ee inp ut OR ga te is shown in fig. 2.8.
input AN
r the ful J-a dd er circu it is sh ow n in table 2.3. The billl'
The tru th table fo
lue of the least sig nif ica nt bit of the sum and the bin:
variable S gives the va
variable Cout gi ves the output carry.
Table 2.3 Truth Table of Full-adder ~

Inpu ts Outputs --
Carryout
Auge11d Bit Addend Bit Carry-in Sum
(SJ (Co11t )
(A) (BJ· (C;nJ
J
0
0
0 0 0
0
0 0 J 1
0
1 0 1
0 1
I l 0
) 0 I
 Unrt - II 73

1 0 0 0
l 0 1 0 1
l l 0 0
l l 1 l
The K-map for the output S and Cout are given in fi gs. 2 .9 (a) and (b).
respectively.
The simplified logic expression for output S and Cout can be '.vri tten as
- - -- --
s = ABCin +ABC in+ ABC in + ABC in ... {i )
Cout = AB+ BCin + AC in ... \ ii )

AB Cin A ii Cin
AB AB
Cm 00 11 10 Cin 00 Ot tt 10 AB
0 6 0 2 6 4
0 0

A C in
t 3 7 5
1 1
1 l 1

AB Cin AB Cin BCin - --

(a) K-map of Output S (b) K-n,ap of Outp11t ( . .out

Fi,.:. 2.9
 (,\ee ll11it -l/'4 /':1J:l' l(Jli, Q.2)
,~,) \)ra\\ \,Jgtc dia gra n1 of JK llip-f1op and give its clwrac.:tcristic.-., tabl
• e
~,nu equation. (S('{' l/11it -III. l'Jlf.!(' 113. (j.YJ 7

~\l) Diffcrent,atc static and dynami c R/\M. 7

(Set· l fnit- 111, 1';1:.:c 167, Q.59 )
table and equation. (R.G.P. V., Nov. 1019)
Ans, Fig. 3.9 shows the logic diagram of J-K flip-flop using S-R flip-tlop.
In the state of an S-R flip-flop when S = R = 1 can be eliminated by converting
it into a J-K flip-flop. The data inputs are J and Kwhich are ANDed with Q and
Table 3.5 Excitation Table for J-K
Flip-flop PRESET

Present State Inputs Next State S=JQ

J S-R
Qn J K Qn+l Flip-flop
Q
CLK
0 0 0 0
0 0 1 0 K
(..)
0 l 0 1 R= KQ
0 1 1 1
1 CLE.: \ R
0 0 1
l 0 1 0
l Fi.~. J. 9 J-A Flip-jlop
l 0 1
I 1 I 0 using S-R Flip-llor
-
 11 4 Dig ta, Stslems (CS. CS/ T)

c). n.·:-pcctl\ d~. ll) lJbtain S ,111 d I"J 111 11t1I'-• ,I ' ··I.
' ...(,,
S J() . table 3.5.
},,.I) ·ven in
R ." . n1 -noP is ~ 1 NAN D gates as shown
The e,c1tat1on '. able for J-Kfli ~nop using ut to J-K inputs. The . . . ''
No\, \\e obtain the J-K ctions frorn ~u~t ThetruthtableofJ-I(~ •
fiu. J. I 0. There are cross conne d to I< !OP · I~
.. . . connecte
connected to J input while Q ts
flop is gi\ en in table 3.6. Table 3.6 Truth Table for J-K Jilin..n.
PRESET ,,,._,

Inputs Output
J K Qn+J
CLK O O Qn (No change)
O 1 0 (Reset)
1 0 !._ (set) /
CLEAR 1 Qn (Toggle) /
Fig. 3.10 J-K Flip-flop using Nand Gates
From the excitation table in table 3.5, a K-map for the next state transitior l
(On~I) can be drawn as depicted in fig. 3. l l.
From the K-map in fig. 3. 11 , the minimized characteristic equation of H
flip-flop can be written as -
JK
00 01 11 10
0 2
Working - When J = K = 0, 6 4
0
the inputs to the basic flip-flop are
S == 0 and R = 0. This condition 3 7 5
fon:e, the nip-flop into the same
~late . If J == 0. K = I and the
prev_ious state of the flip-flop is Fig. 3.1 J K-map for J-K Flip-flop
set'l.C.,
Q - 1 -
Q - 0 th S
applicatio; of a' 1 nk- ' en == Oand R == 1. The flip-flop resetsonme
. coc pulse.lfJ == l K- .
nop 1s reset i c Q _ _ · - 0 and the prev10us state of thefl1~
' · ·, n - 0 and Q - . ·1
set on the appl · ., • n - I , then S = 1 and R = O. The fltp-fiopwil
. icat1on of a clock .
of the 01p-nop · , . pulse. If J = I, K == I and the previous 51811
fl ts a set I e Q _ - .
op reset on the .' ·. ·, 11 - I, Qn == 0 , then S = Oand R = I. The tlir·
app11cat1on f
set state to reset state. o a clock pulse, i.e., the flip-flop togglesfroin
Q.JO. What ·
using d is the race /vtJ
e ge triggering and -around condition ? How call this be so//)
tnaster-s/ave /lip-flops ? (R.G.P. V., Dec. JO
show n 111 1· 1g • ., . , L. .

Q.59. Diff eren tiate static and dyna ,nic RAM. (R.G P. V., 1Vov. 1019 )
rni...:
Ans. In s ta tic 1ne mory , the conte nt does not c hange with time : in dyna
mem ory, its conte nt ch a n ge s with tirne . Dyn an1ic mem o ry
cells use th('
tnr is n~t.·d~d
capac ita nce of a trans isto r as the stora ge dev ice. O nl y one t ran~i ...
pcrit )dicd l~
to store one bit of info rma ti o n. T he capa c itor n1ust be rc frl·:--hl·d
witho ut be ing di scha rged in orde r to prev e nt loss or in fon11at it1n
. Si.lli ~ llh'nh)TY
, appli "·d
devices requ ire no re fresh ing, a nd ho ld da ta as long a~ D.C·. f'4-'\' 1..'t ,