Digital Fundamental Lab 2015 - v2

TON DUC THANG UNIVERSITY
FACULTY OF ELECTRICAL-ELECTRONICS ENGINEERING

DIVISION OF ELECTRONICS-TELECOMMUNICATIONS
DIGITAL FUNDAMENTAL
Laboratory Manual
Source: Lab-Volt Systems, Inc
Edited by Division of Electronics-Telecommunication
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Table of Contents
1. Unit 1 - Fundamental Logic Elements ........................................................................................... 5
EXERCISE 1-1: AND/NAND Logic Functions ................................................................................... 8
EXERCISE OBJECTIVE ............................................................................................................... 8
DISCUSSION ............................................................................................................................... 8
PROCEDURE ............................................................................................................................. 11
REVIEW QUESTIONS ................................................................................................................ 14
EXERCISE 1-2: OR/NOR Logic Functions ..................................................................................... 15
EXERCISE OBJECTIVE ............................................................................................................. 15
DISCUSSION ............................................................................................................................. 15
PROCEDURE ............................................................................................................................. 18
2. Unit 2 - EXCLUSIVE-OR/NOR Gates.......................................................................................... 22
EXERCISE 2-1: EXCLUSIVE-OR (-NOR) Gate Functions.............................................................. 24
DISCUSSION ............................................................................................................................. 24
PROCEDURE ............................................................................................................................. 25
EXERCISE 2-2: Dynamic Response of XOR/ XNOR Logic Gates .................................................. 28
DISCUSSION ............................................................................................................................. 28
PROCEDURE ............................................................................................................................. 30
3. Unit 3 - Flip-Flops........................................................................................................................ 32
EXERCISE 3-1: S/R Flip-Flop ........................................................................................................ 35
DISCUSSION ............................................................................................................................. 35
PROCEDURE ............................................................................................................................. 38
EXERCISE 3-2: D Flip-Flop ............................................................................................................ 42
DISCUSSION ............................................................................................................................. 42
PROCEDURE ............................................................................................................................. 44
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4. Unit 4 - JK Flip-Flop .................................................................................................................... 48
EXERCISE 4-1: Static Operation .................................................................................................... 51
PROCEDURE ............................................................................................................................. 51
EXERCISE 4-2: Dynamic Operation ............................................................................................... 55
DISCUSSION ............................................................................................................................. 55
PROCEDURE ............................................................................................................................. 57
5. Unit 5 - The MULTIPLEXER and DEMULTIPLEXER .................................................................. 60
EXERCISE 5-1: MULTIPLEXER .................................................................................................... 66
DISCUSSION ............................................................................................................................. 66
PROCEDURE ............................................................................................................................. 68
EXERCISE 5-2: DEMULTIPLEXER................................................................................................ 71
DISCUSSION ............................................................................................................................. 71
PROCEDURE ............................................................................................................................. 74
6. Unit 6 - ASYNCHRONOUS RIPPLE COUNTER ......................................................................... 77
EXERCISE 6-1: Basic Counter Control Functions .......................................................................... 79
DISCUSSION ............................................................................................................................. 79
PROCEDURE ............................................................................................................................. 82
EXERCISE 6-2: Ripple Counter Waveforms ................................................................................... 85
DISCUSSION ............................................................................................................................. 85
PROCEDURE ............................................................................................................................. 87
7. Unit 7 - 4-BIT COMPARATOR .................................................................................................... 90
EXERCISE 7-1: Fundamental Binary Comparisons ........................................................................ 94
DISCUSSION ............................................................................................................................. 94
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PROCEDURE ............................................................................................................................. 96
EXERCISE 7-2: Comparators And Counter Modulus Control ....................................................... 100
EXERCISE OBJECTIVE ........................................................................................................... 100
DISCUSSION ........................................................................................................................... 100
PROCEDURE ........................................................................................................................... 102
REVIEW QUESTIONS .............................................................................................................. 104
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1. Unit 1 - Fundamental Logic Elements
UNIT OBJECTIVE
At the completion of this unit, you will be able to determine the input/output relationship of logic elements
on the DIGITAL LOGIC FUNDAMENTALS circuit board.
DISCUSSION OF FUNDAMENTALS
In TTL digital circuits, there are two fundamental voltage levels, or logic states: a high state, called a
logic high and equal to +5 Vdc, and a low state, called a logic low and equal to 0 volts.
For practical circuits, each state consists of a minimum and a maximum voltage level. Outside of this
range, the logic circuit cannot reliably determine which logic state to assign. Figure 1-1 illustrates the
operating limits of typical TTL circuits.
Figure 1-1. Operating levels of TTL circuits
In the figure, a voltage level between 0.8 and 2 volts represents an unknown logic state. Logic levels
that operate near the threshold can generate intermittent results because any noise that adds to the
signal will move the input of the gate to the unknown logic state.
Logic high values, represented by 1, range between 2 and 5 Vdc. Logic low values, represented by 0,
range between zero and 0.8 Vdc.
Ones (1) and zeros (0) are used to define the operational tables of standard logic gates and circuits.
Figure 1-2 illustrates two fundamental logic concepts.
Figure 1-2. Logic Concepts
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In Figure 1-2(a), switches A and B must be closed to illuminate the lamp. Switch A AND switch B must
be activated. If either switch is opened (not activated), the lamp goes off.
In Figure 1-2(b), either switch A or switch B can be closed to illuminate the lamp. Switch A OR switch B
must be activated. Both switches must be opened (not activated) to turn the lamp off.
Switch positions can be related to logic levels. Logic levels are represented by highs (1) or lows (0);
therefore, the standard AND and OR logic functions can be stated with highs and lows (ones and zeros).
This relationship is illustrated by Table 1-1.
Table 1-1
Logic
Switch state
Level State
OFF LOW 0
ON HIGH 1
Boolean equations used to define the input/ output relationships of logic circuits. In place of ones and
zeros, Boolean equations take the form of A and B = C. Figure 1-3 illustrates this circuit notation.
Figure 1-3. Boolean form of notation
In the figure, the Boolean equation A and B = C defines the circuit operation. The expression states that
both switches A and B must be activated (on or high) to illuminate the lamp (C). If a lamp-on condition
is considered a logic high, then both A and B must be high to generate a high output.
Basic logic functions can be complemented. The complement of a logic state is its opposite state. Logic
high and low levels (1 and 0) are complements of each other. Zero (0) is the ones complement of one
(1), while 1 is the ones complement of 0.
The complexity of an IC package determines its classification. In general, IC packages having 12 or less
logic gates are classified as Small Scale Integration (SSI) devices.
IC classification types range from SSI to Very Large Scale Integration (VLSI) and beyond. The
relationship between gate count and classification is illustrated in Figure 1-4.
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Figure 1-4. IC classification and gate count
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EXERCISE 1-1: AND/NAND Logic Functions
EXERCISE OBJECTIVE
When you have completed this exercise, you will be able to determine the operation of an AND and a
NAND logic gate. You will verify your results by generating truth tables for each function.
DISCUSSION
Figure 1-5 shows the schematic symbols of two-input AND and NAND gates.
Figure 1-5. AND and NAND gates
Signal inputs are labeled A and B. Gate outputs are labeled C. The output of the NAND gate is the
complement of the AND operation.
The Boolean equation for the AND gate states that C is high when A and B are high. The AND operation
is indicated by the dot between A and B.
NOTE: A·B and AB without the "·" are identical.
The Boolean equation for the NAND gate states that C is low when A and B are high. The bar over AB
represents the complement of AB.
The NAND gate function has a bubble drawn at the output side of the gate. This bubble indicates a
complement.
Figure 1-6 shows the pin-out configuration for the 74LS00 NAND, SSI IC used in this exercise.
Figure 1-6. 74LS00 NAND, SSI IC
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In the figure, pins 14 and 7 supply power to the IC. The IC provides four separate two-input NAND gates,
labeled A through D. Each gate provides one output.
For the 74LS00 IC, inputs may be tied to other inputs or outputs may be connected to inputs; however,
outputs cannot be connected to one another.
Unused inputs generally are pulled high (connected to Vcc) through a pull-up. The nominal value of pull-
up resistors used in LS devices is 18 K-Ohms.
Two NAND gates can be cascaded (connected in series) to generate an AND operation. This
configuration is represented by Figure 1-7.
Figure 1-7. AND gate operation
In the figure, output C provides a NAND response to the circuit inputs (A and B). Output C is
complemented by the action of GATES 2 and 3. In turn, these gates generate AND operations (outputs
D and E) for the same circuit inputs (A and B).
Table 1-2 provides the circuit truth table.
Table 1-2
Outputs
Inputs
NAND AND
B A C D or E
1 1 0 1
1 0 1 0
0 1 1 0
0 0 1 0
In the table, the outputs are complements of each other. Output column C provides the NAND function
truth table, and output columns D and E provide the AND function truth table.
There are two circuit inputs (A and B). Four unique input conditions test all possible combinations.
A low level at any input disables an AND or a NAND gate. A high level at one input of a two-input AND
or NAND gate enables the gate.
Figure 1-8 illustrates the disable and enable combinations for an AND and a NAND gate.
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Figure 1-8. AND/NAND gate control combinations.
The truth tables in the figure show that a disabled AND gate locks out its other input and generates a
low level (0) output. A disabled NAND gate also locks out its other input but generates a high level (1)
output.
Enabled AND or NAND gates allow their outputs to be determined by the circuit inputs, as demonstrated
in Figure 1-8.
The operating principles of a two-input AND or NAND gate apply to gates having more than two inputs.
Figure 1-9 shows an eight-input NAND gate (74LS30).
NOTE: Remember that a high

logic level turns on an LED. You
can verify the state of a signal,
as indicated by a circuit LED, by
connecting your multimeter to
the appropriate test point.
Figure 1-9. 8-input NAND gate.
The output of this gate is low only when all inputs are high. Any input at a low level locks out the other
inputs (and output is high).
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PROCEDURE
1. Locate the AND/NAND circuit block, and connect the circuit shown in Figure 1-10. Activate
BLOCK SELECT. Place both toggle switches in the DOWN position.
Figure 1-10
2. What are the logic levels at the AND gate inputs?

NOTE: In Figure 1-10, circuit input A is connected
to one input (A) of the AND gate and one input (A)
of the NAND gate. Circuit input B is connected to
the other input of each gate.
3. What are the logic levels at the NAND gate inputs?
A= ___________ B= ____________
4. Do the circuit input LEDs confirm your answers to steps 2 and 3?
A= ___________ B= ____________
5. What is the logic level at the output of each gate?
AB = _________ AB = _________
6. Do the output LEDs confirm your answer to step 5?
7. If either toggle switch A or B (not both) were placed in the UP position, what would the effect on
the output be?
8. Place toggle switch A in the UP position. Observe the circuit outputs. Do your results agree with
your step 7 answer?
9. Place toggle switch A in the DOWN position and switch B in the UP position. Observe the circuit
outputs. Do your results agree with your step 7 answer?
10. With the current switch settings, which gate is enabled and which is disabled?
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11. Place switch A in the UP position. Observe the circuit output LEDs. Are both gates enabled?
12. Does your observation of the AND gate output indicate that the inputs are high or low?
13. Does your observation of the NAND gate output indicate that the inputs are high or low?
14. Based on your data, are the AND and NAND gates used to detect high or low logic levels?
15. Use the toggle switches and LEDs of your circuit board to complete the truth tables of Figure
1-11.
Figure 1-11. AND and NAND truth tables.
16. Are the outputs of the AND and NAND gates complements of each other?
17. Modify your test circuit as shown in Figure 1-12. Connect channel 1 of your oscilloscope to circuit
input B. Use channel 2 to monitor other circuit points as required.
NOTE: LEDs will appear to be constantly on
due to the pulse train input signal. This action
does not alter the expected circuit operation.
You may disable the circuit block LEDs by
removing BLOCK SELECT
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Figure 1-12
18. Place switch A in the DOWN position. Circuit input signal B is a square wave pulse train
(oscilloscope channel 1 ). Are the gates enabled or disabled? Are the AND and NAND outputs
high or low?
19. Place switch A in the UP position. Monitor the output of each gate. Are the gates allowing the
input signal to pass through because the gates are disabled or enabled by the high input at A?
20. Compare the circuit outputs with the circuit input. What are the signal phase relationships? Refer
to Figure 1-13.
WITH AN INPUT AT A
HIGH LEVEL IGATES
ENABLED)
Figure 1-13
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REVIEW QUESTIONS
1. The output of an AND gate is high
a. all of the time.
b. when any input is low.
c. when any input is high.
d. when all inputs are high.
2. The output of a NAND gate is low

a. all of the time.
d. when all inputs are high.
3. In the circuit of Figure 1-14, output levels A through D are, respectively,

a. low, high, low, and low.
b. low, high, low, and high.
c. high, low, low, and low.
d. disabled due to the circuit pull-ups and to common connection on the last gate.
Figure 1-14
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EXERCISE 1-2: OR/NOR Logic Functions
EXERCISE OBJECTIVE
When you have completed this exercise, you will be able to determine the operation of an OR and a
NOR logic gate. You will verify your results by generating truth tables for each function.
DISCUSSION
Figure 1-15 shows the schematic symbols of two-input OR and NOR gates.
Figure 1-15. OR and NOR gates
Signal inputs are labeled A and B. Gate outputs are labeled C. The output of the NOR gate is the
complement of the OR operation.
The Boolean equation for the OR gate states that C is high when A or B is high. In the equation, the +
symbol indicates OR.
The Boolean equation for the NOR gate states that C is high when A and Bare high. The bar over A+B
indicates the complement of A+B. The NOR gate function has a bubble at the output side of the gate.
This bubble indicates a complement.
Figure 1-16 shows the pin out configuration for the 74LS02 NOR, SSI IC used in this exercise.
Figure 1-16. Typical 74LS02
In the figure, pins 14 and 7 supply power to the IC. The IC provides four separate two-input NOR gates,
labeled A through D. Each gate provides one output.
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For the 74LS02 IC, inputs may be tied to other inputs, and an output may be connected to inputs;
however, outputs cannot be connected to one another.
Unused inputs are generally pulled low (connected to ground).
Two NOR gates can be cascaded (connected in series) to generate an OR operation, as shown in
Figure 1-17.
Figure 1-17. OR circuit operation
In the figure, outputs D and E both represent OR functions because of the complementary action of
GATES 2 and 3. Each configuration provides the OR circuit function.
Table 1-3 provides the circuit truth table.
Table 1-3. OR/NOR circuit truth table
OUTPUTS
INPUTS
NOR OR
B A C D or E
1 1 0 1
1 0 0 1
0 1 0 1
0 0 1 0
In the table, the outputs are complements of each other. Output column C provides the NOR function
truth table, and output columns D and E provide the OR function truth table.
Figure 1-18 illustrates the disable and enable combinations for an OR and a NOR gate.
The operating principles of a two-input OR or NOR gate apply to gates having more than two inputs.
Figure 1-19 shows a three-input NOR gate (74LS27).
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Figure 1-18. OR/NOR gate control combinations
Figure 1-19. 3-input NOR gate
The output of this gate is low when any one input is high. Any one input at a high level locks out the
other inputs (output low).
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PROCEDURE
1. Locate the OR/NOR circuit block, and connect the circuit shown in Figure 1-20. Activate BLOCK
SELECT. Place both toggle switches in the DOWN position.
NOTE: Remember that a high logic level turns on an LED. You can verify
the state of a signal, as indicated by a circuit LED, by connecting your
multimeter to the appropriate test point.
Figure 1-20
2. What are the logic levels at the OR gate inputs?

NOTE: In Figure 1-20, circuit input A is connected to one input (A)
of the OR gate and one input (A) of the NOR gate. Circuit input B
is connected to the other input of each gate.
A = _________ B = _________
3. What are the logic levels at the NOR gate inputs?

A= __________ B = _________
4. Do the circuit input LEDs confirm your answers to steps 2 and 3?
5. What is the logic level at the output of each gate?
A+B = __________ A+B = __________
6. Do the circuit output LEDs confirm your answer to step 5?
7. If either toggle switch A or B (not both) were placed in the UP position, would the OR and NOR outputs
be locked high or low?
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8. Place toggle switch A in the UP position. Observe the circuit outputs. Do your results agree with your
step 7 answer?
9. Place toggle switch A in the DOWN position and switch Bin the UP position. Observe the circuit
outputs. Do your results agree with your step 7 answer?
10. With the current switch settings, which gate is enabled and which is disabled?
11. Place switch A in the UP position. Observe the circuit output LEDs. Are both gates disabled?
12. Observe the OR gate output. Does a high on any input lock out the other input? Is the gate output
forced to a high or a low level?
13. Observe the NOR gate output. Does a high on any input lockout the other input? Is the gate output
forced to a high or a low level?
14. Based on your data, are the OR and NOR gates used to detect high or low logic levels?
15. Use the toggle switches and LEDs on your circuit board to complete the truth tables of Figure 1-21.
Figure 1-21. OR and NOR truth tables
16. Are the outputs of the OR and NOR gates complements of each other?
17. Modify your test circuit as shown in Figure 1-22. Connect channel 1 of your oscilloscope to circuit
input B. Use channel 2 to monitor other circuit points as required.
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Figure 1-22
18. Place switch A in the DOWN position. The circuit input signal is a square wave pulse train
(oscilloscope channel 1). Are the gates enabled or disabled? Does input B pass through to the output?
19. Place switch A in the UP position. Monitor the output of each gate. Are the gates allowing input B to
pass through? Are the gates enabled or disabled?
20. Compare the circuit outputs with the circuit input. What are the signal phase relationships?
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REVIEW QUESTIONS
1. The output of an OR gate is high
a. all of the time.
d. when all inputs are low.
2. The output of a NOR gate is low

a. all of the time.
d. when all inputs are low.
3. In the circuit of Figure 1-23Figure 1-25, output levels A through D are, respectively,
a. low, high, low, and low.
b. low, high, low, and high.
c. high, low, low, and low.
d. disabled due to the circuit pull-up and common connections.
Figure 1-23
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2. Unit 2 - EXCLUSIVE-OR/NOR Gates
UNIT OBJECTIVE
At the completion of this unit, you will be able to determine the input/output relationship of logic elements
on the DIGITAL LOGIC FUNDAMENTALS circuit board by exercising EXCLUSIVE-OR/NOR gates.
An exclusive type gate is considered to be an arithmetic logic element because it can be used to perform
binary addition or comparison.
Exclusive gates take two forms: EXCLUSIVE-OR (XOR) and EXCLUSIVE-NOR (XNOR).
The schematic symbol for each gate type is shown in Figure 2-1.
Figure 2-1. EXCLUSIVE OR/NOR schematic symbols.
The double curved lines at the gate inputs differentiate the exclusive function from a conventional
OR/NOR function.
To generate the XNOR output, invert (apply the complement of) the output of the XOR gate.
Figure 2-2 shows the operation, symbolized by , of an XOR gate.
Figure 2-2. EXCLUSIVE-OR operation
The figure shows that a high output (C) is generated when the gate inputs (A and B) are complements
of each other (not equal to one another). Expressed in Boolean form, 𝐶 = 𝐴̅𝐵 + 𝐴𝐵 ̅.
Figure 2-3 shows the operation of an XNOR gate. The symbol is used in addition to a bubble
(inversion or complement function) at the gate symbol.
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Figure 2-3. EXCLUSIVE-NOR operation
The figure indicates that a high output (C) is generated when the gate inputs (A and B) equal to each
other. Both inputs may be high or low. Expressed in Boolean form, C = AB + AB .
Table 2-1 provides the truth tables for each type of gate operation.
Table 2-1. Truth tables for XOR and XNOR functions.
Inputs Outputs
Input condition
A B XOR XNOR
EQUALITY 0 0 0 1
INEQUALITY 0 1 1 0
INEQUALITY 1 0 1 0
EQUALITY 1 1 0 1
The table shows that an XOR circuit detects conditions of inequality of its inputs. The XNOR circuit
detects conditions of equality of its inputs. Two XOR gates can be combined to generate both XOR and
XNOR output signals. This gate combination is shown in Figure 2-4.
In the figure, the second XOR gate performs an XNOR operation due to the action of the pull-up resistor.
The table in Figure 2-4 shows the operation of the complete circuit.
NOTE: The circuit in Figure 2-4 shows the actual electrical connection of the XNOR gate on your circuit board.
Figure 2-4. Using XOR gates to complement.
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EXERCISE 2-1: EXCLUSIVE-OR (-NOR) Gate Functions
EXERCISE OBJECTIVE
When you have completed this exercise, you will be able to determine the operation of an EXCLUSIVE-
OR and an EXCLUSIVE-NOR logic gate. You will verify your results by generating truth tables for each
function.
DISCUSSION
Figure 2-5 shows the pin-out configuration for the 74LS136 IC used in this unit.
Figure 2-5. Typical 74LS136
Pins 14 and 7 supply power to the IC. The IC has four separate two-input XOR gates, labeled A through
D. Each gate provides one output. For the 74LS136 IC, inputs may be tied to other inputs, and an output
may be connected to inputs. Unlike the 74LS00 and 74LS02, outputs of the LS136 can be connected to
other outputs. In addition, output terminals of the LS136 require pull-up resistors. The LS136 is an open
collector type IC. This design feature is covered in detail in another unit of this manual. Figure 3-6
illustrates a typical open collector pull-up required for the LS 136 IC. (An output terminal pull-up resistor
differs in value from a nominal input terminal pull-up.) In Figure 2-6(a), the gate output is pulled up to
Vcc by a 10 kQ resistor. Figure 2-6(b) illustrates the internal gate structure by showing the output
transistor. Notice that the transistor's open collector is the gate's output terminal. The open collector
circuit must have a source of power. The pull-up resistor provides this required power source. On your
circuit board, pull-up resistors are provided for each output terminal of the IC. These resistors are located
within the circuit block, but not all are identified on the silk-screen.
Figure 2-6. Open collector pull-up
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PROCEDURE
1. Locate the XOR/XNOR circuit block, and connect the circuit shown in Figure 2-7. Activate BLOCK
SELECT. Place both toggle switches in the DOWN (low) position.
Figure 2-7.
2. What are the logic levels at the XOR gate inputs?

A = _________ B = _________
3. What are the logic levels at the XNOR gate inputs?
C = _________ D = _________
4. Based on the input levels of each gate, what should the output levels be?
XOR Output XNOR Output
5. Determine the gate output levels. Do your readings agree with the answer in step 4?
6. Use the toggle switches in conjunction with your circuit to complete truth Table 2-2.
Table 2-2. Truth table for XOR and XNOR logic gates.
7. Based on Table 2-2, which gate is used to detect for inequality when a low output indication is
required?
8. Based on Table 2-2, which gate is used to detect for inequality when a high output indication is
required?
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9. Based on Table 2-2, which gate is used to detect for equality when a low output indication is required?
10.Based on Table 2-2, which gate is used to detect for equality when a high output indication is
required?
11. Based on your data, how can you determine which exclusive gate to use for a specific application?
12. What is the relationship of the XOR output level with respect to the XNOR output level?
13. Can you use either input of the XOR gate to lock out the other input?
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REVIEW QUESTIONS
1. Which symbol represents an EXCLUSIVE-OR function?
a. . b. +
c. d. x
2. Which schematic symbol represents an EXCLUSIVE-OR gate?
3. Using a two-input XOR gate to generate a complement

a. requires that one input be pulled up.
b. will not provide reliable results.
c. requires that one input be pulled down.
d. requires one input to be locked out by the other.
4. The output terminals of the open collector gate used in this exercise
a. must remain floating.
b. should be connected directly to Vcc·
c. cannot connect to other outputs.
d. generally require some form of pull-up.
5. In the circuit of Figure 2-8,
a. output D is locked out by the action of the pull-up resistor.
b. outputs C and D are complements of each other.
c. outputs C and D are in phase.
d. both outputs generate an EXCLUSIVE-OR operation.
Figure 2-8
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EXERCISE 2-2: Dynamic Response of XOR/ XNOR Logic Gates
EXERCISE OBJECTIVE
When you have completed this exercise, you will be able to determine the response of exclusive type
gates to a square wave input waveform. You will verify your results by observing circuit waveforms.
DISCUSSION
One input of a two-input XOR gate cannot be used to disable the gate.
One input of a two-input XNOR gate cannot be used to disable the gate. Figure 2-9 shows two two-input
XOR gates, each with static and dynamic inputs.
Figure 2-9
In Figure 2-9(a), the output waveform is a complementary version of the input waveform. In Figure
2-9(b), the output waveform is in phase with the input waveform.
Figure 2-10(a) shows the circuit that generates the XNOR function in the XOR/XNOR circuit block of
your circuit board.
In Figure 2-10(b), with one input pulled up to Vcc, the XOR output waveform is the complementary
version of the input waveform, while the XNOR output waveform is in phase with the circuit input
waveform.
In Figure 2-10(c), with one input grounded, the XOR output waveform is in phase with the input
waveform, while the XNOR output waveform is the complementary version of the input waveform.
Figure 2-9 and Figure 2-10 show that the input/output phase relationship of a gate is determined by the
logic level at the static input of that gate. The square wave input is not locked out (gate disabled) for
either level (high or low) of static input.
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Figure 2-10
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PROCEDURE
1. Locate the XOR/XNOR circuit block. and connect the circuit shown in Figure 2-11. Place both toggle
switches in the DOWN (low) position. Connect channel 1 of your oscilloscope to circuit input B.
2. Monitor the output waveform of the XOR gate on channel 2 of your oscilloscope. Place toggle switch
A in its UP, then DOWN position. Can the XOR gate be disabled by the action of the toggle switch?
Figure 2-11
3. Monitor the output waveform of the XNOR gate on channel 2 of your oscilloscope. Place toggle switch
A in its UP and then DOWN position. Can the XNOR gate be disabled by the action of the toggle switch?
4. Measure the input/output waveform phase relationship of each gate (with respect to the circuit input
waveform) for each toggle switch A position indicated in Table 2-3. Complete the table.
Table 2-3
TOGGLE SWITCH INPUT/ OUTPUT PHASE

POSITION XOR XNOR
UP
DOWN
5. Does the position of the toggle switch (circuit static input level control) determine which gate
complements the circuit input waveform?
6. Does the level at circuit input A prevent any part of the input waveform from passing through to the
circuit outputs?
7. Based on your observations, are the circuit block gates constantly enabled or disabled?
8. What is the overall (input to output of XNOR gate) phase shift when toggle switch A is high?
9. What is the effect of a double complement (two cascaded circuits that both complement)?
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REVIEW QUESTIONS
1. One input of a two-input XOR gate is connected to Vee through a pull-up resistor; therefore, the gate
a. is disabled.
b. output complements the circuit input.
c. output does not complement the circuit input.
d. inputs are locked out.
2. An XOR gate
a. cannot complement a signal.
b. can operate only on static signals.
c. will provide only a high output level.
d. None of the above.
3. If the input signal of an XOR circuit is a square wave, the output signal
a. is a square wave.
b. is rectified.
c. converts to a static signal.
d. causes the circuit to oscillate.
4. In Figure 2-12, outputs C and D
a. are in phase.
b. are not related.
c. are complements of each other.
d. match inputs A and B.
Figure 2-12
5. In Figure 2-12, output E

a. is in phase with input B.
b. is locked out by the action of the pull-up resistor.
c. is the complement of input B.
d. follows input A.
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3. Unit 3 - Flip-Flops
UNIT OBJECTIVE
At the completion of this unit, you will be able to configure and operate several types of flip-flops on the
DIGITAL LOGIC FUNDAMENTALS circuit board by using a 74LS00 and 74LS76 TTL IC.
Flip-flop circuits derive their name from an ability to remain in either a high or low state.
FIip-flops are bi-stable which means they remain in one state until switched to the complement of that
state.
Flip-flops can be used as storage elements, synchronizing circuits, dividers, and system reset elements.
Flip-flop circuits can be configured with basic logic gates or with an IC having many gates.
There are several types of flip-flop operations available. Examples are set/reset flip-flops or RS flip-
flops, toggle flip-flops, and D-type flip-flops.
A flip-flop can be used to debounce, the action of a toggle or other type of switch. The "bounce" of a
switch refers to the mechanical make-and-break action that occurs until the switch settles to its new
position.
In general, flip-flop circuits provide complementary outputs labeled Q . The Q, or true, output is low
and goes high when activated. The Q , or false, output is high and goes low when activated.
The output action of a flip-flop circuit is illustrated in Figure 3-1.
Figure 3-1. Flip-Flop output action
In the figure, the outputs are complements of each other. Both outputs change their state at the same
time.
The condition of a flip-flop is determined with respect to its true, or Q, output terminal.
To set or preset a flip-flop is to put its Q output in a high state.
To clear or reset a flip-flop is to put its Q output in a low state.
Flip-flop circuits require a clock to initiate an output state change. A cross-coupled gate flip-flop circuit
is self-clocking (a separate clock input signal is not required).
32
Figure 3-2 shows the clock waveform symbols used to denote the characteristics of typical flip-flop clock
signals.
Figure 3-2. Flip-flop clock symbols
Figure 3-2(a), the outputs of the flip-flop change states on the positive of the clock waveform.
In Figure 3-2(b), the outputs change states on the negative transition of the clock waveform.
In Figure 3-2(c), the outputs change states on the negative transition of the clock waveform. This figure
shows a complete pulse width for its clock. Figure 3-2(c) represents a type of flip-flop called a master-
slave flip-flop. For this type, the positive edge of the clock conditions the output circuits to "read" the
input states and decide if the circuit outputs must change. The negative edge of the same clock pulse
initiates an output state change .
Figure 3-3 illustrates the relationship between the input, clock, and output signals of a flip-flop
circuit element.
Figure 3-3. Flip-flop signal relationships.
Flip-flop outputs remain in one state until the conditions at the circuit input can no longer maintain the
output state. When the circuit input is altered, the output changes state with the next clock transition.
When the circuit inputs remain constant, the output states are not affected by clock transitions.
Figure 3-4 illustrates a cross-coupled NAND gate configured to provide a set/reset flip-flop (and switch
debounce) action.
Note that the gate symbol used in the figure (OR gate with inverting inputs) is equivalent to a NAND
gate (AND gate with inverting output). The logic function and truth table for both gate symbols are exactly
the same.
33
Figure 3-4. Set/Reset flip-flop.
There are four circuit inputs: one from each switch pole and one from each gate output. The gates
provide feedback inputs and the two circuit outputs. Vee and ground (IC power supply) are understood
and are not usually indicated.
For this self-clocking circuit, the outputs change state when the switch is moved to its other position.
Switch bounce is not passed through to the gate outputs, nor do the output states change as the switch
moves between its pole positions.
Figure 3-5 illustrates the circuit symbol of a D-type flip-flop (D-flop) with preset and clear functions.
Figure 3-5. D-type flip-flop.
There are four input control signals and two output signals. Vcc and ground are understood and are not
usually indicated.
The PR (preset) input sets Q high when it detects a low state. Once Q is set high, it remains high until a
new set of input conditions is detected by the circuit.
The CLR (clear) input resets Q low when it detects a low state. Once Q is reset low, it remains low until
a new set of input conditions is detected by the circuit.
D (data) and CLK (clock) inputs work in conjunction to determine the output state of the flip-flop.
The two outputs, Q and Q are complements of each other.
34
EXERCISE 3-1: S/R Flip-Flop
EXERCISE OBJECTIVE
When you have completed this exercise, you will be able to determine the operational characteristics of
cross-coupled gates configured for RS and switch debounce operation. You will verify your results by
measuring the circuit level at each phase of operation.
DISCUSSION
Figure 3-6 shows a schematic representation of an OR gate with inverting inputs.
Figure 3-6. Inverting-input OR gate.
The circuit notation (bubbles at inputs) indicates that the gate output (C) will be high for any low input at
A or B. The truth table verifies the gate operation and shows that the symbol of Figure 5-6 is actually a
NAND gate.
A NAND gate can detect input highs (both inputs must be high to force the output low) or low inputs
(either input low forces a high output). Refer to Figure 3-7.
Figure 3-7: NAND gate and inverting-input OR gate symbol functions
In practice. this type of circuit "shorthand" indicates the logic state (high or low) that is expected to
activate the gate.
35
Figure 3-8 shows a flip-flop configured with inverting-input OR (NAND) gates connected in a cross-
coupled feedback pattern.
Figure 3-8. Gate configured flip-flop.
For the circuit shown, output C will be high if either input of gate C is low. Output D will be high if either
input of gate D is low. This circuit action ensures that only one output at a time is in its high state. Outputs
C and D are complements of each other.
Figure 3-9 shows a flip-flop that provides a set/reset and switch debounce function.
Figure 3-9. Set/reset flip-flop.
With the switch placed in its SET position, Q is high. Both inputs of gate B are high (Q feedback and
pull-up RB), and the gate B output ( Q ) is low.
36
The Q feedback to gate A locks the gate A output (Q) high. This feedback path maintains the current
output states as the switch moves from its SET position to its RESET position (switch detail in Figure 3-
9).
During the OPEN/OPEN time of the switch travel, the circuit is locked by the 0 feedback (low input) to
gate A.
As the switch makes initial contact with its RESET pole, the input of gate B goes low. The low input
forces the gate B output (Q) high. Both inputs of gate A are high (Q feedback and pull-up RA), and the
gate A output (Q) is low.
With the gate A output (Q) low, feedback to gate B locks the gate B output high. The circuit does not
change output states until the switch moves back to its SET position.
Due to the mechanical action of the switch, it physically bounces (makes and breaks) as its wiper makes
contact with the RESET pole. The circuit states change and lock at the switch's initial contact; therefore,
subsequent makes and breaks at the RESET pole do not cause the circuit outputs to move.
The cycle repeats itself as the switch is moved from its RESET to its SET position. No circuit action is
evident until the switch makes initial contact with its SET pole.
37
PROCEDURE
1. Locate the SET/RESET FLIP-FLOP circuit block, and connect the circuit shown in Figure 3-10. Place
a two-post connector in the S (SET) circuit position.
Figure 3-10.
2. With your multimeter, measure the voltages on your circuit at the points indicated by Figure 3-11.
Insert the proper high or low circuit states on the figure.
3. Based on Figure 3-11, what is the effect of the two-post connector on the output states of the circuit?
Figure 3-11. Set circuit states.
4. If the two-post connector were removed from the circuit, what change would occur in the output states
of the circuit?
5. Remove the two-post connector from your circuit. Monitor the circuit outputs. Do your results agree
with your answer to step 4?
38
6. How do you explain the circuit action after removal of the two-post connector?
7. Place the two-post connector in and out of the SET position several times. Monitor one of the circuit
outputs as you exercise the set function. Why is the circuit stable?
8. Do the repetitive set requests (action of the two-post connector) simulate the circuit response to switch
bounce?
9. Can this flip-flop circuit be used to debounce a switch contact?
10. Does the circuit indicate an ability to store its set condition after the SET command is removed (two-
post connector removed)?
11. How can the circuit be reset (Q output to low state)?
12. Place the two-post connector in the R (RESET) position, and monitor the circuit output. Record the
circuit state levels on Figure 3-12.
13. What specific action occurred to gate Bin order to flip the state of the circuit?
14. Do the results of steps 12 and 13 agree with your step 11 answer?
15. Remove the two-post connector from your circuit. Does the circuit . state change? Why or why not?
16. Monitor the circuit output as you place the two-post connector in and out of the RESET position
several times. Is the circuit responding to repetitive RESET commands?
17. Can the circuit be used to debounce switch action on both set and reset functions?
18. Does the circuit exhibit reset memory?
19. Based on your data, what is the relationship between the circuit outputs?
39
20. Connect the circuit shown in Figure 3-12. Place both toggle switches in the DOWN position.
NOTE: This input condition is invalid. It is
used only to point out circuit stability.
21. Which output is in the correct state to lock out the circuit?
22. Simultaneously place toggle switches A and B in the UP position . Does the circuit revert to either a
set or a reset state?
Figure 3-12
23. Move switch B down and then up while monitoring the Q output. Then move switch A down and
then up. Does switch A set the flipflop and switch B reset it?
40
REVIEW QUESTIONS
1. In the set state, the Q output is
a. low.
b. unknown.
c. high.
d. midway between low and high.
2. In the reset state, the Q output is

a. low.
b. unknown.
c. high.
d. midway between low and high.
3. The SET/RESET FLIP-FLOP circuit can debounce a mechanical switch because

a. of the circuit pull-up resistors.
b. its outputs are in phase.
c. a two-post connector replaces the switch.
d. of low state signal feedback.
41
EXERCISE 3-2: D Flip-Flop
EXERCISE OBJECTIVE
When you have completed this exercise, you will be able to determine the operational characteristics of
a D-type flip-flop. You will verify your results by measuring the circuit level at each phase of operation.
DISCUSSION
A D-type flip-flop requires a minimum of two inputs: a data input (high or low) and a clock input.
The data input must be stable before the flip-flop is clocked. Clocking the flip-flop results in updating the
states of the circuit output.
Once a D-type flip-flop is clocked, input data changes do not affect the circuit outputs until the flip-flop
is clocked again.
D-type flip-flop (D-flops) can be used as registers that store bits of data. Figure 3-13 shows a typical D-
type negative edge-triggered flip-flop with preset (PR) and clear (CLR) inputs.
Figure 3-13. D type flip-flop.
In practical circuits, the PR and CLR inputs are tied to Vee through a resistive pull-up.
The PR input pulsed low sets the flip-flop (Q = high). The CLR input pulsed low resets the flip-flop (Q =
low).
PR and CLR inputs override the normal clocking action of the flip-flop. If either input remains in a low
state, the flip-flop is locked in either its set or reset state.
The flip-flop outputs change on the negative transition of the clock pulse. Q follows the D (data) input.
Q and Q are complements of each other.
Table 3-1 is the truth table for the flip-flop shown in Figure 3-13.
42
Table 3-1: D type flip-flop true table
43
PROCEDURE
1. Locate and connect the circuit blocks shown in Figure 3-16. Do not activate the PR or CLR inputs of
the D-type flip-flop. Place toggle switch A in the DOWN position. Activate the SET function of the
SET/RESET FLIP-FLOP.
Figure 3-14
2. Monitor the D-flop outputs with your multimeter. Did the device power up in a set or a reset mode?
NOTE: During the next four steps of this
procedure, verify that the circuit outputs are
complements of each other.
3. What should the effect of activating the PR input be?
4. Activate the PR input by inserting a two-post connector. Does the circuit output perform as indicated
by your answer to step 3?
5. What should the effect of activating the CLR input be?
6. Activate the CLR input by inserting the same two-post connector used in step 4. Does the circuit
output perform as indicated by your answer to step 5?
44
7. Are the output states of the D-flop complements of each other?
8. Remove the two-post connector from the D-TYPE FLIP-FLOP circuit block. Move toggle switch A up
and down several times as you monitor the Q output of the D-flop. Does the output state change? Why
or why not?
9. Place toggle switch A in the DOWN position. Momentarily activate the PR circuit of the D-flop. Based
on the circuit conditions you have initialized, what should occur after a positive transition on the CLK
input?
10. Activate the R input of your SET /RESET FLIP-FLOP (do not activate S). Does the output state of
the D-flop change?
11. Do the answers to step 9 and 10 agree?
12. Activate the S input of your SET /RESET FLIP-FLOP. Does the output state of the D-flop change?
Why or why not?
13. As you monitor the D-flop output, repeat the S-to-R-to-S clocking function on the SET /RESET FLIP-
FLOP circuit block. Does the Dflop output again change state? Why or why not?
14. Place toggle switch A in the UP position. Again monitor the output of the D-flop as you generate a
new clock cycle. Does the output change its state? Why or why not?
15. Modify your test circuit by connecting the CLK (clock) input of the D-TYPE FLIP-FLOP circuit block
to the CLOCK circuit block. Use your oscilloscope to monitor the outputs of the D-flop.
16. Do the circuit outputs change if the D (data) input remains in one state?
17. Do the circuit outputs change after the D input state is changed?
18. Do the circuit outputs reflect the pulse waveform of the CLOCK circuit, or are they equal to the
steady state level at the D input?
19. Based on your observations, which output of the D-flop follows the state of the D input?
45
20. Activate the PR and CLR inputs in turn, and move toggle switch A up and down several times. Based
on your oscilloscope, do the PR and CLR inputs override the clocking action of the D-flop?
21. Based on your observation, can the PR or CLR inputs of the D-type flip-flop be used to initialize the
device before data and clock inputs can be used?
46
REVIEW QUESTIONS
1. A D-type flip-flop
a. immediately passes all input data state changes to its output.
b. does not react to input data changes until clocked.
c. must be triggered to accept PR or CLR inputs.
d. cannot be used as an RS flip-flop.
2. The Q output of a D-type flip-flop

a. follows the state of the PR input.
b. follows the state of the CLR input.
c. follows the state of the D input.
d. is pulsed if the CLK input is pulsed.
3. If the CLK input of the D-type flip-flop is at a low state,

a. the output follows all input data changes.
b. PR and CLR inputs are locked out.
c. Q and Q outputs are no longer complements.
d. the D-flop output reflects the data input from the last clock transition.
47
4. Unit 4 - JK Flip-Flop
UNIT OBJECTIVE
At the completion of this unit, you will be able to determine the functional characteristics of a JK flip-flop
circuit on the DIGITAL LOGIC FUNDAMENTALS circuit board by using a 74LS76 JK flip-flop with preset
and clear inputs.
JK flip-flops can be configured as RS, D-type, or toggle flip-flops.
Toggle flip-flops change their output states in a high-low-high-low pattern. One state change occurs for
each clock cycle.
One state change per clock cycle results in an output frequency equal to half of the clock frequency.
JK flip-flops are available in master-slave configurations. A master-slave flip-flop requires a square pulse
(rising and falling edge) clock waveform. Standard JK flip-flops are available with positive or negative
clock transition circuits.
Figure 4-1. JK flip-flop with preset and clear Inputs.
IC power supply voltages (Vcc and ground) are assumed but are not usually shown.
In practice, the IC supply lines are bypassed, and the PR and CLR inputs are connected to Vcc through
resistive pull-ups.
PR and CLR inputs are used to set or reset (respectively) the flip-flop.
Data inputs are connected to terminals J and K.
48
Output states change after the negative transition of the clock input.
Clocking the flip-flop does not produce output state changes when the input conditions are constant.
Figure 4-2 shows typical circuit connections for a JK flip-flop.
Figure 4-2
In Figure 4-2(a), the JK flip-flop operation is equivalent to that of the D-type flip-flop you exercised in
Unit 5.
The NOT gate ensures that inputs J and K are always complements of each other.
In Figure 4-2(b). the outputs toggle for each negative transition on the clock input line. Q and 𝑄̅ are
complements of each other.
The configuration in Figure 4-2(c) illustrates the general purpose connections available.
Figure 4-3 shows the pin-out diagram of a 74LS76 JK flip-flop.
The IC is comprised of two separate flip-flops in one 16-pin dual-in-line package.
49
Figure 4-3. Pin outs for a 74LS76 flip-flop.
50
EXERCISE 4-1: Static Operation
PROCEDURE
1. Locate and connect the circuit blocks shown in Figure 4-4. Do not activate the PR or CLR inputs of
the J-K flip-flop. Place toggle switch A/B in the DOWN position. Activate the SET function of the
SET/RESET FLIP-FLOP.
Figure 4-4
2. Monitor the J-K flip-flop outputs with your multimeter. Did the device power up in a set or a reset
mode?
NOTE: During the next four steps of this procedure, verify
that the circuit outputs are complements of each other.
3. What should the effect of activating the PR input be?
4. Complete the PRESET circuit. Monitor the flip-flop outputs. Is the device set or reset? How can you
tell?
5. Generate a CLK pulse from the SET /RESET FLIP-FLOP circuit block. Did the JK flip-flop output
change? Explain your answer.
NOTE: To generate a pulse on the SET/ RESET FLIP-FLOP
circuit block, move the two-post connector .from the S position
to the R position and hack.
51
6. Open the PRESET circuit. Generate a CLK input. Does the output state of the LS76 flip-flop change?
7. Does the overriding PRESET directly control the output state of the flip-flop?
8. How can the PRESET input be used to lock out the effects of the J, K, and CLK inputs?
9. Repeat steps 4 through 6, using the CLEAR input in place of the PRESET input. Do your results
support the answers given in steps 6 through 8?
10. With respect to the output state of the LS76 flip-flop, what is the difference between the actions ofthe
PRESET and CLEAR operation?
11. Activate both overriding inputs of the JK flip-flop. What are the output stages of Q and Q-NOT?
12. Remove either the PRESET or the CLEAR two-post connector from your circuit. Do the output states
observed in step 11 persist?
13. Repeat steps 11 and 12 for whichever overriding input you did not select in step 12. Do the output
states change when one overriding input is removed?
NOTE: For the remainder of this procedure, observe the
circuit LEDs to determine the logic states of your circuit.
You may verify the various states with your multimeter.
14. Momentarily activate the overriding inputs to set the JK flip-flop. Describe the LED indications which
support the set state of the flip-flop.
Q LED is ________ Q-NOT LED is ________
15. Move the two-post connector on the SET /RESET FLIP-FLOP circuit block from the S position to
the R position, but not back. Does the JK flip-flop output change? Explain.
16. Move the two-post connector on the SET /RESET FLIP-FLOP circuit block back to the S position.
Does the JK flip-flop output change? Why or why not?
17. Generate several clock cycles. Based on the JK FLIP-FLOP circuit block LEDs, how do you describe
the circuit operation?
52
18. Clear the JK flip-flop. Use toggle switches A and 8, the clock generation ability of the SET /RESET
circuit block, and the LEDs on the JK circuit block to complete Table 4-1.
Table 4-1
19. Which operation [(1) through (6)] of the table generate output changes?
20. Why doesn't operation (2) generate an output change?
21. Why doesn't operation (4) generate an output change?
22. Why does operation (6) generate an output change even though inputs J and K did not change
between operations (5) and (6)?
23. Based on your observations, which inputs of the LS76 flip-flop are considered to be control inputs?
24. Based on your observations, which inputs of the LS76 flip-flop are considered to be data inputs?
53
REVIEW QUESTIONS
1. The PR and CLR inputs of JK flip-flop are
a. Vcc and Ground inputs.
b. data inputs.
c. overriding output controls.
2.A JK flip-flop in its toggle mode of operation

a. complements the output state on a valid clock transition.
b. sets both Q and Q-NOT high.
c. resets both Q and Q-NOT low.
d. locks out the effects of the overriding inputs.
3. The Q output of a flip-flop is determined with respect to its
a. PR input.
b. CLR input.
c. J input.
d. K input.
4. In Figure 4-5, DATA is high. After the negative transition of the clock,
a. the overriding inputs are pulled low.
b. Q is low and Q-NOT is high.
c. Q and Q-NOT are both high.
d. Q is high and Q-NOT is low.
Figure 4-5
5. In Figure 4-5, DATA is low. After the negative transition of the clock,
a. the overriding inputs are pulled low.
b. Q is low and Q-NOT is high.
c. Q and Q-NOT are both high.
d. Q is high and Q-NOT is low.
54
EXERCISE 4-2: Dynamic Operation
EXERCISE OBJECTIVE
When you have completed this exercise, you will be able to determine how a toggle flip-flop affects the
frequency of the circuit block. You will verify your results by comparing the input and output waveforms
of a JK flip-flop.
DISCUSSION
Figure 4-6 illustrates a typical clock waveform.
Figure 4-6
In Figure 4-6(a), one complete cycle has an initial positive transition followed by a negative transition at
the mid-point. Between the START /MID-POINT and MID-POINT /END sections of the waveform, the
level is constant.
In Figure 4-6(b), the positive and negative transition sections of the waveform are expanded. Recall that
rise and fall times are measured between the 10 and 90 percent points of the waveform.
Figure 4-6 shows that one complete cycle of the waveform consists of one positive and one negative
transition.
When the waveform illustrated in Figure 4-6(a) drives the clock input of an LS76 JK toggle flip-flop, the
output changes state on every negative transition.
55
The negative transition represents one out of two waveform transitions available for each complete clock
cycle. Therefore, the output waveform is divided by two. The divide-by-2 ability of a JK flip-flop is
illustrated in Figure 4-7.
Figure 4-7. Divide action of a toggle flip-flop.
Figure 4-8 shows the waveforms and the circuit configuration required to generate a divide-by-2
operation.
Figure 4-8. Toggle flip-flop circuit.
In this configuration, the PR and CLR inputs retain their override capability. The Q and Q outputs are
complements of each other. J and K must be pulled up to Vee.
The operation of a JK flip-flop is not reliable if the PR and CLR inputs are not terminated to, or cannot
"see," a solid logic high level.
56
PROCEDURE
1. Locate and connect the circuit blocks shown in Figure 4-9. Place both toggle switches A and B in the
UP position. Set or reset the flip-flop and verify the condition.
2. What circuit inputs did you use to establish a definite flip-flop state?
Figure 4-9
3. How did you verify the set or reset state of the flip-flop?
4. Connect channel 1 of your oscilloscope to the CLK input of the JK circuit block. Connect channel 2 to
the Q output. Is the JK flip-flop in a stable state?
5. Modify your circuit by adding a test lead between the CLK input of the J K FLIP-FLOP circuit block
and the output of the CLOCK circuit block.
6. Compare the input and output waveforms displayed on your oscilloscope. What is the frequency
relationship of the two waveforms?
7. The J and K LEDs are on due to the pull-up action of toggle switches A and B. Why aren't the CLK,
Q and 𝑄̅ LEDs as bright?
8. Connect the PR input to ground. Does this connection affect the CLK input waveform?
9. Does the PR input affect the toggle operation of the flip-flop? If so, how?
57
10. Place the flip-flop into a reset state. Is the CLK input waveform affected?
11. Is the toggle operation of the flip-flop affected? If so, how?
12. Do the Q and Q-NOT LEDs revert to normal brightness while the flip-flop is set or reset?
13. Based on your observations, can circuit LEDs be used to determine the operating state of a flip-
flop?
14. Open both PR and CLR circuits. Place toggle switch B in the DOWN position. Is the CLK input
waveform affected?
15. Why doesn't the circuit output toggle?

NOTE: Observe the Q output on channel 2.
16. Place toggle switch A in the DOWN position and toggle switch B in the UP position. Is the flip-flop
set or reset? Why?
17. Do the Q and Q LEDs show complementary outputs?
18. Restore the circuit to its toggle configuration. What is the phase relationship of the output
waveforms?
19. Based on your observations, does the JK flip-flop distort either the leading or trailing edge of the
CLK input waveform?
58
REVIEW QUESTIONS
1. The PR input of your circuit
a. overrides the CLK input.
b. cannot override the CLK input unless it is static.
c. must be low for toggle operation.
d. should be floating for toggle operation.
2. A flip-flop configured for toggle operation

a. alters its output states twice for each complete CLK cycle.
b. alters its output states once for each complete CLK cycle.
c. alters its output states for every CLK transition.
d. forces Q and Q-NOT to be in phase.
3. The circuit of Figure 4-10

a. cannot operate because the PR and CLR inputs are not identified.
b. divides the clock input and toggles the outputs.
c. is reset and does not toggle.
d. is set and does not toggle.
Figure 4-10
59
5. Unit 5 - The MULTIPLEXER and DEMULTIPLEXER
UNIT OBJECTIVE
When you have completed this unit, you will be able to locate, operate, and control a multiplexer and
demultiplexer circuit.
DISCUSSION
A multiplexer allows the selection of one data source from a group.
Figure 5-1 illustrate the concept.
Figure 5-1
The output can be connected to any of the input data sources (A through D) by positioning the
multiplexer pointer.
In Figure 5-1, input data source C is selected. This input data passes through the multiplexer pointer to
the output. Data sources A, B, and D have no effect on the multiplexer output.
The 74LS151 multiplexer on your circuit board operates much the same way; however, the pointer
movement on the 74LS151 is electrically provided through a register select process.
Internal registers allow selection of a specific data input. The register are driven by TTL level (high and
low) inputs. Figure 5-2 illustrates register control of the selection process.
60
Figure 5-2
Each register is enabled by a select (SEL) line. If SELC enables REG C (register C), the C data passes
through to the output.
On the LS151 multiplexer, the select lines are buffered and decoded to ensure that only one data at a
time is selected. The decoding process disables all non-selected registers.
Part of the selectrion process deals with output enable control line. This strobe line is driven by a TTL
level. On the LS151, the strobe input disables or enables all data registers simultaneously.
Figure 5-3 illustrates the control process of one multiplexer register.
Figure 5-3
Data A and SELA have no effect on the output if the STRB input is high. STRB high disables register
A.
If STRB is low, the register can be selected, in which case data A is passed through to the output.
The equivalent circuit of your LS151 multiplexer comprises NOT and AND gates and one NOR gate.
Figure 5-4 illustrates the NOT gates used to control register selection.
61
Figure 5-4
The NOT gates of Figure 5-4 buffer the register select inputs. Six output lines, connected to the internal
AND registers, control the selection process.
Figure 5-5 illustrates two of the internal AND registers of your multiplexer and the selection control
process.
Figure 5-5
Register A is enabled when the register select inputs equal binary 111 (C-B-A). Register B is disabled
since A is high and A is low.
Register B is enabled when the register select inputs equal binary 110 (C-B-A). Register A is disabled
since A is low.
Either data input is selected and passed through to the NOR gate. The NOR date output is high or low
depending on the level of the selected data input.
Figure 5-6 illustrate the strobe control over the AND gate registers.
62
Figure 5-6
Both REG AND gates are enabled if STRB is low; both REG gates are disabled if STRB if high.
A multiplexer allows the selection of one data source from a group. A demultiplexer reserses the process
and allows one data source to selectively drive individual elements of a group. This concept is illustrated
by Figure 5-7.
Figure 5-7
In the Figure, six lines of data are multiplexed down to one line. In turn, the data on this line is placed
on any one of six lines at the demultiplexer output.
In Figure 5-7, the select control inputs determine which input line passes its data through to the
demultiplexer and which output receives that data.
An advantage of this circuit configuration is that one line (in place of six lines) transfers all information
between input and output.
Figure 5-8 illustrates the basic operating principle of the 74LS155 demultiplexer.
63
Figure 5-8
In Figure 5-8, the data on the strobe (or DATA IN) line can be placed on any one output line. The single-
pole switches represent registers that are selected by the register select inputs. Only one register at a
time can be enabled (selected).
The 74LS155 comprises NOT, NOR, and NAND gates. Figure 5-9 illustrates the gate control circuit of
two internal registers of your demultiplexer.
Figure 5-9
64
In Figure 5-9(a), REG B is enabled, and the STROBE (data) is passed to the output. The NOT gate
disables REG A.
In Figure 5-9(b). REG A is enabled, and the STROBE (data) is passed to the output. The NOT gate
enables REGA. SELB disables REGB.
Figure 5-9 shows one data input used to drive two outputs. Each output follows the level of the data
input. However, the selection process enables only one gate at a time.
If the SEL2 input is high, then neither REG gate is enabled and both outputs are high (the STROBE
input has no effect on the registers).
65
EXERCISE 5-1: MULTIPLEXER
EXERCISE OBJECTIVE
When you have completed this exercise, you will have a working knowledge of a multiplexer. You will
gain this knowledge by exercising a one-of-eight multiplexer.
DISCUSSION
The 74LS151 data selector/multiplexer is a monolithic integrated circuit (IC) with full on-chip binary
decoding. On-chip decoding allows the IC to select the desired data source.
Figure 5-10 shows the functional block diagram of the LS1 51 used on your circuit board.
Figure 5-10
Based on the Figure, the multiplexer has eight input data lines. Each line may be high or low. Only one
line at a time can be selected to appear at the output.
Figure 5-10 shows complementary outputs; if Y is high, then Y is low. The multiplexer outputs are
active only when STRB is pulled low (IC enabled). If STRB is high (IC disabled), then Y is low and
Y is high.
If the multiplexer is disabled, the inputs have no effect on the IC outputs.
Input data selection is controlled by the binary inputs applied to the data select inputs. The three data
select lines have a binary range of 000 through 111, or 0 through 710.
Figure 5-11 shows the relationship between the data select input lines and the data line selected.
66
Figure 5-11
The binary input code corresponds to the decimal number assigned to each specific data input line. For
example, binary select input 011 (310) selects input 3 (data line D3).
When a data input line is selected, the TTL level at that input is reflected on the output Y line of the
multiplexer. If the input data is low, output Y is low; if the input data is high, output Y is high. Y always
complements Y.
Figure 5-12 shows the circuit schematic for the select and STRB inputs at your multiplexer.
Figure 5-12
The pull-up resistors ensure a proper high TTL level when two-post connectors are not inserted into a
specific circuit. The pull-up resistors are not shown on the circuit block silkscreen drawing.
67
PROCEDURE
1. Make sure the power supplies are off. Insert the DIGITAL CIRCUIT FUNDAMENTALS 2 circuit board
into the base unit. Turn on the +15 Vdc and -15 Vdc power supplies.
2. Place the toggle switch on the PULSE GENERATOR circuit block in the UP position.
NOTE: This toggle switch increments
your COUNTER circuit.
3. Connect the circuit shown by Figure 5-13. Do not activate the BLOCK SELECT function on the circuit
block.
NOTE: The COUNT or MOD inputs
initially reset your counter output. MOD
sets a modulus of 10.
Figure 5-13
4. Based on your binary select code, which multiplexer data input is selected?
5. Use your multimeter or oscilloscope to measure the Y output level. Should the DO input level agree
with your measurement?
6. Use your multimeter to scan inputs D1 through D7 of your multiplexer. Are any of these inputs
reflected at the multiplexer outputs?
7. What is the level at multiplexer output Y ?
8. Monitor output Y of your multiplexer. Remove the two-post connector from select input A of your
multiplexer.
68
9. Why is output Y of your multiplexer high?
10. Remove the two-post connector from the STRB input of your multiplexer.
11. Why is output Y of your multiplexer low?
12. Return the two-post connector to the STRB position on your circuit. Verify that input D1 and output
Y are at high levels.
13. Generate one pulse output from the PULSE GENERATOR circuit block.
NOTE: Cycle the toggle switch down-up.
14. Why is the output of your multiplexer low?
15. Remove the two-post connector from select input C. Place a two-post connector in the BLOCK
SELECT position on the BCD/DECIMAL DECODER circuit block (the left side of the circuit block).
NOTE: Outputs O through 7 of the decimal
decoder are hardwired to inputs O through 7
of your multiplexer.
16. Monitor output Y with a multimeter. Momentarily reset your COUNTER output (remove then insert
the MOD two-post connector).
17. Slowly generate 10 pulse outputs from your PULSE GENERATOR circuit block. Observe your meter
reading after each toggle switch cycle.
NOTE: A specijic output of your decimal
decoder, and therefore the respective input of
your multiplexer is low when an LED in the
decoder block is on.
18. Which multiplexer input is passed through to output Y?
NOTE: If you are not sure, repeal steps 16
and 17.
19. Does output Y follow the TTL data level at input D5?
20. Do any of the other inputs of the multiplexer force Y low?

NOTE: If you are not sure. repeat steps 16 and
17.
21. Based on your observations, does your multiplexer select one of eight date sources?
69
REVIEW QUESTIONS
1. On the multiplexer shown by Figure 5-14,
a. simultaneous inputs can be selected for Y and Y.
b. only one output at a time can be enabled by STRB.
c. the select inputs pass through one input at a time.
d. the select inputs pass through one input for each outpul
Figure 5-14
2. The select lines shown by Figure 5-14

a. require a 3-bit binary input.
b. must be driven by three zero-to-nine decimal inputs.
c. can be driven by a single two-digit hexadecimal number.
d. can be internally connected directly to the outputs.
3. Based on the circuit configuration of Figure 5-14,

a. both outputs are disabled.
b. input data line D2 is selected.
c. Y is low and Y is high.
d. both outputs are enabled.
4. Based on the circuit configuration of Figure 5-14, if the input lines are driven by a high-low-high data
stream, the Y and Y output patterns are
a. high-low-high and low-high-low, respectively.
b. high-low-high for both outputs.
c. low-high-low for both outputs.
d. low-high-low and high-low-high, respectively.
5. A multiplexer allows
a. one line to selectively drive a group of lines.
b. one line to be driven by any number of lines.
c. Either of the above.
70
EXERCISE 5-2: DEMULTIPLEXER
EXERCISE OBJECTIVE
When you have completed this exercise, you will have a working knowledge of a demultiplexer. You will
gain this knowledge by exercising a one-to-eight demultiplexer.
DISCUSSION
The 74LS155 data demultiplexer is a monolithic IC with full on-chip binary decoding and strobe inputs.
On-chip decoding allows the IC to route the data input to a selected output line.
Figure 5-15 shows the functional block diagram of the LS1 55 used on your circuit board: a dual 2- to 4-
lane decoder configured as a one-to-eight demultiplexer.
Figure 5-15
Based on the figure, the demultiplexer has eight output lines. Each line is active low and drives its
respective LED on when in the low state. 1Y3 is the most significant bit (MSB) and 2Y0 is the least
significant bit (LSB).
Input data is applied to the data input terminal (2G and 1 G of the IC). These are the strobe inputs of
the IC.
The output select control lines are driven with binary inputs. Each binary input code uniquely selects
only one output line. When an output line is selected, its level follows that of the input data (applied to
the 2G and 1G strobe lines of the IC).
Figure 5-16 shows the relationship between the binary select input codes and the demultiplexer outputs.
71
Figure 5-16
The binary input code corresponds to the decimal number assigned to each specific output line. For
example, binary select input 011 (310) selects output 2Y3.
When a data output line is selected, the TTL level on that line is low if the 1G and 2G inputs are low.
The output level is high if the 1G and 2G inputs are high.
Figure 5-17 shows the electrical circuit that controls the input data level on your circuit board.
Figure 5-17
The pull-up resistor generates a high input level. A two-post connector is used to generate a low input
level. You can ignore the connection to the multiplexer circuit.
On your circuit board, the select input lines of your demultiplexer are hardwired to the output lines on
the COUNTER circuit block. The functional electrical diagram is shown in Figure 5-18.
Figure 5-18
72
Based on the figure. COUNTER output lines OC through GA are used as a select input for the
dernultiplexer. The QD line is not required since the demultiplexer requires a 3-bit binary input.
The LS1 55 can be used as a demultiplexer or as a decoder (do not confuse a decoder with a
multiplexer). Figure 5-19 illustrates the difference between each function.
Figure 5-19
In Figure 5-19(a), a selected output line follows the data level at inputs 2G and 1G. This is the
demultiplexer mode of operation: one input can be selectively directed to any one of eight outputs.
In Figure 5-19(b), inputs 2G and 1G (permanently pulled low) act as a strobe input. When an output is
selected, it goes low. Outputs not selected are high. This is the decoder mode of operation: any one of
eight outputs can be selected (forced low) by a 3-bit binary input code.
73
PROCEDURE
NOTE: Outputs QC. QB. and QA of your COUNTER
circuit block are hardwiredto inpuu 2C/1C, SELS, and
SELA of your demultiplexer. Use your COUNTER binary
output code lo select the demultiplexer output line.
into the base unit. Turn on the +15 Vdc and -15 Vdc power supplies.
2. Place the toggle switch on the PULSE GENERATOR circuit block in the UP position. The output of
the circuit clocks your COUNTER circuit block.
3. Place the toggle switch of the COUNTER circuit block in the STEP position.
4. Place a two-post connector in the COUNT position of your COUNTER circuit block.
5. Use a two-post connector to enable the BLOCK SELECT function on your DEMULTIPLEXER circuit
block.
6. Refer to Figure 5-20 for an overall view of the Circuit used in this procedure. Output QD is not required
for the 3-bit demultiplexer binary select input.
Figure 5-20
7. Based on the binary output of your COUNTER (also the select input to your demultiplexer), which
output is selected?
8. Use a two-post connector to set the data input of your demultiplexer to a low level (inputs 2G and 1G
on your circuit).
NOTE: The outputs ofyour demulliplexer are active low.
The LEDs are on when a respective IC output is low.
9. Does output 2Y0 reflect the data input of your demultiplexer?
10. What is the state of the other (nonselected) IC outputs?
11. Remove the data input two-post connector from your circuit block. What is the level at output 2Y0?
NOTE: A pull-up resistor ensures that the data input is at a
proper TTL level.
74
12. Use the PULSE GENERATOR circuit block and your COUNTER to select several demultiplexer
outputs. As each output is selected, vary the data input low and high.
13. How many demultiplexer outputs can b. simultaneously selected?
14. Does each selected output follow the level at the demultiplexer input?
15. Connect the input of your demultiplexer to COM. Use a two-post connector at cWcult input 2G/1G.
16. Reset your COUNTER output (binary 0000) by momentarily removing the two-post connector from
Its COUNT position.
75
REVIEW QUESTIONS
1. A 1 -Iine-to-8-line demultiplexer
a. can simultaneously connect 1 input line to a maximum of 8 output lines.
b. can simultaneously connect a maximum of 8 input lines to 1 output line.
c. can connect 1 input line to any single selected output line.
d. requires only 1 binary select line.
2. If the LS155 demultiplexer is configured for a decoder, its input data line
a. should be set for a high TTL level.
b. should be set for a low TTL level.
c. may be switched between high and low levels.
d. should not be connected at all but should remain floating.
3. The required binary input select range of the LS155 is

a. 1111 through 0000.
b. 1111 through 1000 or 0111 through 0000 but not both.
c. 111 through 000.
d. x111 through 1000. where x must be set low.
4. In Figure 5-21, LED 1

a. is on for binary 110 and off for all other codes.
b. is off for binary 110 and on for all other codes.
c. can never be on.
d. can never be off.
Figure 5-21
5. In Figure 5-21, LED 2

a. is on when both OR gate inputs are high.
b. is on when either OR gate input is low.
c. cannot be driven on by the OR gate.
d. is always driven on by the OR gate.
76
6. Unit 6 - ASYNCHRONOUS RIPPLE COUNTER
UNIT OBJECTICE
When you have completed this unit, you will have a working knowledge of an asynchronous ripple
counter configured from JK flip-flops.
A rippIe couter consists of two or more flip-flops interconnected so that the output of each flip-flop is
wired to the input of the follov/ing flip-flop. This daisy-chained configuration is illustrated in Figure 6-1.
Figure 6-1. Ripple Counter block diagram.
The initial input is called CLOCK. Each flip-ffop has an output. The output of flip-flop A is connected
tothe input of flip-flop B. The output of 8 is connected to the input of C.
A ripple counter is also called an asynchronous counter because the circuit outputs do not change
simultaneously with a common clock.
The asynchronous counter may also be referred to as a serial counter because each flip-flop is triggered
one at a time.
For example, the output of flip-flop B in Figure 6-1 does not change until the output of flip-flop A clocks
it. In turn, flip-flop C does not change until clocked by the output from B.
Ripple counters can be made to count up or down.
A JK flip-flop used to construct a ripple counter is configured as a T, or toggle/flip-flop. This configuration
is illustrated in Figure 6-2.
Figure 6-2. Toggle-configured JK flip-flop.
In the figure, the J and K inputs are pulled to Vcc- The outputs, Q and Q , are complements of each
other. Ripple counters may have complementary outputs.
77
Ripple counters can be set or cleared.
To set the flip-flop, PR (or preset) is momentarily pulled low. When the flip-flop is set Q is placed
in a high state; Q the complement of Q, is placed in a low state.
To clear the flip-flop, CLR (or clear) is momentarily pulled low. When the flip-flop is cleared, Q is placed
in a low state; Q is placed in a high state.
The maximum number of counts of a ripple counter may be controlled by feedback. The count control
is referred to as the modulus (sometimes abbreviated MOD) of the counter.
78
EXERCISE 6-1: Basic Counter Control Functions
EXERCISE OBJECTIVE
When you have completed this exercise, you will be able to control the function of an asynchronous
ripple counter. You will verify your results by operating a 4- bit ripple counter.
DISCUSSION
Figure 6-3 illustrates a basic 4-bit ripple counter.
Figure 6-3. Basic 4-bit ripple counter.
The four output bits are labeled BIT1 through BIT4, BIT1 is the least significiant BIT (LSB). This output
alternates between high and low states,once for each input CLOCK cycle BIT1 divides the CLOCK input
by two. Two CLOCK inputs generate one output cycle at BIT1.
BIT2, the next counter output, does not change its state until clocked by BIT1. BIT1 must complete one
cycle before BIT2 changes its state.
BIT2 divides the CLOCK input by four. Four CLOCK inputs generate one output cycle at BIT2.
CLOCK division continues for each successive section of the counter. BIT3 divides the CLOCK input by
eight. BIT4, the most significant BIT (MSB), divides the CLOCK input by sixteen.
Each counter section divides its respective input by two. However, the relationship between weighted
counter outputs and the CLOCK input is on a divide by 2,4,8 and 16 basis.
Although the circuit of Figure 6-3 is electrically correct, it is awkward to place the MSB on the right side
of the illustration. Figure 6-4 shows the usual ripple counter presentation, with the LSB on the right side.
79
Figure 6-4. Typical ripple counter illustration
The four output BITs of the ripple counter form a nibble, or half of an 8-BIT binary word. The nibble can
be converted to a decimal or hexadecimal equivalent.
Table 6-1. Nibble, decimal, and hexadecimal relationship
BIT 4 BIT 3 BIT 2 BIT 1 DECIMAL HEX

1 1 1 1 15 F
1 1 1 0 14 E
1 1 0 1 13 D
1 1 0 0 12 C
1 0 1 1 11 B
1 0 1 0 10 A
1 0 0 1 9 9
1 0 0 0 8 8
0 1 1 1 7 7
0 1 1 0 6 6
0 1 0 1 5 5
0 1 0 0 4 4
0 0 1 1 3 3
0 0 1 0 2 2
0 0 0 1 1 1
0 0 0 0 0 0
Figure 6-5 highlights the training functions of your circuit. BLOCK SELECT powers the circuit
LEDs.
80
Figure 6-5
You will pulse the CLOCK input to control the counting sequence of the ripple counter.
SET and CLEAR inputs are used to determine the initial counter state.
MOD (modulus) input is used to enable the maximum countfunction of your counter.
The circuit LEDs provide a visual count indication: U for up-count and D for down-count. The outputs
from each counter section are complementary.
This complementation provides the simultaneous up/down-count capability.
On your circuit block, the ripple counter Is oriented in a north-south position. The top JK flip-flop
generates the MSB of your counter, while the lower JK flip-flop generates the LSB of your counter.
81
PROCEDURE
into the base unit. Turn on the +15Vdc and -15Vdc power supplies.
2. Locate the ASYNCHRONOUS RIPPLE COUNTER circuit block, and connect the circuit shown in
Figure 6-6. Place the toggle switch on the PULSE GENERATOR circuit block in its UP position.
Figure 6-6
3. Activate the BLOCK SELECT function with a two-post connector. Can you predict the initial count of
the counter when power is first applied?
4. How can you reset your ripple counter?
5. Reset your ripple counter. What are the states of the UP and DOWN LEDs?
6. To clock your counter toggle the switch on the PULSE GENERATOR circuit blocif. Because the LS76
is a negative-triggered device, the downward action of the switch will not clock the counter. The switch
action must be down, then up, to complete a count.
7. Reset the counter, and generate five clock cycles with the pulse generator switch.
NOTE: This requires five down-up movements of the switch
82
8. Based on the UP LEDs, what Is the count output in binary, decimal, and hex?
Binary count = _____________
Decimal count = _____________
Hex count = _____________
9. Based on the DOWN LEDs, what is the count output In binary, decimal, and hex?
Binary count = _____________
Decimal count = _____________
Hex count = _____________
10. Do your results in steps 8 and 9 indicate that the ripple counter generates two different counts for a
given number of CLOCK inputs?
11. Do all outputs of your counter change together?

NOTE: Repeat steps 5, 6, and 7 if you are not
certain of your answer.
12. If YQur counter is preset, what LED patterns should you expect to see?
13. Preset your ripple counter. Initiate one CLOCK cycle. What is the count sequence of your ripple
counter?
14.Basedon your answer to step 12,can you determine the maximum count indication of your ripple
counter?
15. Based on your data, what is the count indicating range of a 4-BIT ripple counter?
Count indicating range = _______________ to ______________
83
REVIEW QUESTIONS
1. The counter you used in this exercise is
a. a binary counter.
b. a ripple counter.
c. an asynchronous counter.
d. All of the above.
2. The ripple counter Q outputs count

a. up.
b. down.
c. up and down.
d. All of the above.
3. A five-stage ripple counter provides a frequency or count division of

a. 32.
b. 16.
c. 8.
4. With a ripple counter each stage divides its input frequency by

a. 4.
b. 2.
c. 10.
d. 16.
5. With respect to the UP indicators of your ripple counter, the CLEAR and SET (preset) functions
a. generate 1111 and 0000, respectively.
b. have no effect since one function cancels the other.
c. generate 0000 and 1111, respectively.
d. generate 0101 and 1010, respectively.
84
EXERCISE 6-2: Ripple Counter Waveforms
EXERCISE OBJECTIVE
When you have completed this unit, you will be able to interpret output waveforms of the ripple counter.
You will verify your results by observing the waveforms on your oscilloscope.
DISCUSSION
A 4-BIT ripple counter produces four output waveforms, one for each section of the counter.
If the counter has complementary outputs, then four additional waveforms are produced. The ripple
counter on your circuit board has complementary outputs and, therefore, produces eight output
waveforms.
One way to view the signal waveforms is to use the BIT4 output of the circuit as an oscilloscope trigger
{reference time frame). A typical waveform pattern, using this method of observation, is illustrated in
Figure 6-7.
Figure 6-7. Typical ripple counter waveforms
Each output waveform changes its state on the negative edge of the preceding waveform. On your ripple
counter, this occurs because the individual stages are configured from negative edge-triggered JK flip-
flops.
85
One complete cycle of BIT1 requires two complete CLOCK periods. Because period and frequency are
reciprocals, doubling the period reduces the frequency by haIf, Therefore, BIT1 output divides the
CLOCK input frequency by half.
Using the same process, BIT2 divides the CLOCK input frequency by four. BIT3 divides the CLOCK
input frequency by eight. BIT4, the MSB, divides the CLOCK input frequency by sixteen.
Table 6-2 shows the relationship between clock frequency, period, and clock division factors for your
ripple counter (CLOCK input exactly equal to 50 kHz).
Table 6-2
FREQUENCY (kHz) PERIOD (µs) CLOCK DIVISION FACTOR

CLOCK 50 20 --------
BIT1 25 40 2
BIT2 12.5 80 4
BIT3 6.25 160 8
BIT4 3.125 320 16
A specific complementary output, BIT3, for example, will be 180 degrees out of phase with the true BIT3
output. This phase difference can be observed on your oscilloscope.
At the 50 kHz clock frequency, you will not be able to discern the counting sequence on the circuit LEDs.
The LEDs will appear to be on, all simultaneously If you desire, disable the LED by removing BLOCK
SELECT from your circuit.
All other circuit control functions (CLEAR, SET, and MOD) remain active and are not affected by a free-
running CLOCK input.
The asynchronous nature of a ripple counter is verified by its waveforms. For a given stage of the
counter, an output can change only if the preceding stage generates (ripples) a clocking input.
86
PROCEDURE
1.Make sure the power supplies are off. Insert the DIGITAL CIRCUIT FUNDAMENTALS 1 circuit board
into the base unit. Turn on the +15Vdc and -15Vdc power sources.
2. Locate the ASYNCHRONOUS RIPPLE COUNTER circuit block, and connect the circuit shown in
Figure 6-8.
Figure 6-8
3. Connect channel 1 of your oscilloscope to the MSB, Q output test point of the ripple counter
Synchronize your oscilloscope on this channel 1 input.
4. Adjust the time base control of your oscilloscope to 20𝜇s . Use the fine or time base variable control
to display one cycle of the waveform over exactly ten boxes of the scale grid.
DO NOT CHANGE YOUR TIME BASE SETTINGS UNTIL TOLD TO DO SO.
NOTE: The horizontal time base is not calibrated due to the displacement of the time base variable control.
5. Connect channel 2 of your oscilloscope to the CLOCK input test point (the LSB input point of your
ripple counter). Adjust your oscilloscope to view both channel waveforms simultaneously.Refer to
Figure 6-9 for a typical oscilloscope presentation
87
Figure 6-9
6. How many clock cycles are required to generate one complete cycle of the BIT4 (MSB) counter
output?
Clock cycles =
7. Move channel 2 of the oscilloscope to the BIT3, Q output test point.
Does the output of the BIT4 flip-flop alter its state on the positive or negative edge of the BIT3
waveform?
edge of the waveform
8. Based on your oscilloscope display, what is the ratio between the BIT3 and BIT4 waveforms?
Ratio =
9. Alternate channel 2 of the oscilloscope between the Q and Q outputs of the BIT3 flip-flop. What is the
relationship between these two signal outputs?
10. Use channel 2 of the oscilloscope to monitor, in sequence, the Q output of BIT1, BIT2, and BIT3 flip-
flops. Based on your observations,how are these outputs related?
88
REVIEW QUESTIONS
1. The input frequency of a 4-BIT ripple counter is 100 kHz. What is the frequency at the output of the
MSB?
a. 100 kHz
b. 50 kHz
c. 12.5 kHz
d. 6.25 kHz
2. As the clock frequency of a ripple counter increases,

a. the CLEAR and SET inputs do not control all stages of the counter.
b. the functions of the CLEAR and SET inputs are not affected.
c. its maximum count capability increases.
d. its maximum count capability decreases.
3. A free-running input clock

a. allows a ripple counter to run in asynchronous mode.
b. determines the maximum number of counts of a ripple counter.
c. alternates the operating modes of a ripple counter.
d. converts a ripple counter into a serial counter.
4. If the counter is cleared and then the Q (BIT4) output of your ripple counter is connected to the CLEAR
input of your counter,
a. the counter will not operate.
b. the eighth count will reset the counter
c. the eighth count will preset the counter.
d. all the outputs of your counter will be in place.
̅
5. if the counter is cleared and then the Q̅̅̅̅̅̅ (̅BIT4̅̅̅̅̅̅̅)̅ output of your ripple counter is connected to the CLEAR
input of your counter,
a. the counter will not operate.
b. the eighth count will reset the counter.
c. the eighth count will preset the counter.
d. all the outputs of your counter will be in phase.
89
7. Unit 7 - 4-BIT COMPARATOR
UNIT OBJECTICE
At the completion of this unit, you will have a working knowledge of a 4-BIT comparator.
The 74LS85 integrated circuit (IC) used on your circuit board is a 4-BIT magnitude comparator. The IC
falls into the MSI category. This comparator has the capability to make decisions about two 4-BIT words.
Fully decoded decisions are available at three IC outputs.
Figure 7-1. 74LS85 pin-outs.
There are three output terminals. The individual outputs reflect the results of a comparison between the
A-BITs and B-BITs of each input word.
Two 4-BIT words comprise the input of the comparator. The A-word (A0 through A3) is labeled A through
D on the circuit block. The B-word {B0 through B3} is labeled QA through QD on the circuit block.
In the figure, the SELECT INPUTS program the comparator. This programming determines in which
state (high or low) the IC outputs will indicate conditions of between A- and B-words or BITs.
In Figure 7-1, the connections between any one comparator output and the modulus (MOD) point allow
a specific feedback to the SYNCHRONOUS COUNTER circuit block.
LEDs are used on your circuit block to show the status of each output.
The fundamental operation of the comparator is illustrated in Figure 7-2.
90
Figure 7-2
In the figure, each stage compares one BIT of each word. For example, the LSB stage compares BITs
A0 and B0. The decision about the BITs is passed to the DECODING stage. At the DECODING stage,
all stage outputs are combined and the results are on the comparator output terminals.
Information between stages flows over an internal pipeline. This data is not available the IC terminals.
The comparator uses its internal connections to generate comparisons between individual BIT pairs.
This means that the LS85 comparator can provide information between words without regard to the BIT
structure of the words.
In Figure 7-2, the LSB input corresponds to the A0/B0 input, and the MSB corresponds to the A3/B3
input. Based on a straight binary 8-4-2-1 code, the MSB has a weight of 8 (23) and the LSB has a weight
of 1 (20).
Figure 7-3 shows that the LS85 comparator has a set of greater than (>), equal to {=), and less than (<)
inputs and outputs, both with identical labels.
Figure 7-3
The inputs are used to select how a decision is represented at the comparator output. In addition, the
inputs and outputs are required in applications where word lengths greater than 4BITs must be
compared. Such an application is illustrated in Figure 7-4.
91
Figure 7-4. 4-BIT comparator
Figure 7-4 shows the cascade connection required to compare two 8-BIT words
Outputs A and B of the LSB stage (a complete comparator) are connected to inputs A and B of the next
higher stage. The A = B input of the LSB stage is pulled to Vcc. The result of the 8-BIT comparison is
taken from the A>B, A = B, and A<B outputs of the MSB stage of the circuit.
On your circuit board, the LS85 compares two 4-BIT words on a BIT-by-BIT basis The comparison is
with respect to the A-word. if A is greater in value than B, for example, then the A> B output is activated.
If A is less in value than B, then A B or A < B).
Table 7-1 provides examples of comparisons between various words and the result
Table 7-1
WORD B 1111 1010 0101 0100 0000

WORD A 1111 1011 0100 0101 0000
A>B 0 1 0 1 0
A=B 1 0 0 0 1
AB in the LSB and BIT2 positions, A<B in the BIT3 position, and A = B in the MSB position.
Yet the final comparison shows that A<B.
In effect, the LSB and BIT2 results are ignored. Since BIT3 has an active input (BIT3 of WORD B = 1),
it is the result of the BIT3 comparison that determines the final output of A < B.
Figure 7-6 illustrates the same effect, where BIT3 of the A-word is greater than BIT3 of the B-word.
Figure 7-6
In the figure, the comparison results for BITS 1 and 2 (A<B for each BIT position) are effectively ignored.
93
EXERCISE 7-1: Fundamental Binary Comparisons
EXERCISE OBJECTIVE
When you have completed this exercise, you wiil be able to perform comparisons of two 4-BIT binary
words. You will verify your comparisons on a 4-BIT comparator.
DISCUSSION
On the 4 BIT COMPARATOR circuit block, Inputs D through A are controlled by toggle switches D
through A on the INPUT SIGNALS circuit block.
The QD and QA inputs of the 4 BIT COMPARATOR circuit block are hardwired to the SYNCHRONOUS
COUNTER circuit block; therefore, these inputs require the operation of the counter.
Your 4-BIT comparator can make decisions about two 4-BIT words. The result of the comparison is
available at three outputs, called A > B, A = B, and A < B.
The state of these outputs is indicated by circuit LEDs: ON = 1 and OFF = 0.
There are two basic operating modes for your comparator. The first occurs when words A and B are
equal. The second mode occurs when words A and B are not equal.
Each mode generates a specific set of output codes. The generated output code pattern is determined
by the setting of the three input control lines: A>B, A=B, and A<B. Although both inputs and outputs
have identical labels, do not confuse the groups with one another.
Operating states and control codes for unequal inputs are governed by the given function Table 7-2.
Table 7-2
COMPARING INPUTS CASCADE INPUTS OUTPUTS

A3, B3 A2,B2 A1,B1 A0,B0 A>B A=B AB A=B A B3 X,X X,X X,X X X X H L L
A3 < B3 X,X X,X X,X X X X L L H
A3 = B3 A2 > B2 X,X X,X X X X H L L

A3 = B3 A2 < B2 X,X X,X X X X L L H
A3 = B3 A2 = B2 A1 > B1 X,X X X X H L L
A3 = B3 A2 = B2 A1 < B1 X,X X X X L L H
A3 = B3 A2 = B2 A1 = B1 A0 > B0 X X X H L L
A3 = B3 A2 = B2 A1 = B1 A0 < B0 X X X L L H
Table 7-2 shows that for unequal inputs, the CASCADE INPUTS do not affect the operation of the
comparator. The output codes are identical for each situation in which A>B and A<B.
Table 7-2 indicates that the comparison is biased toward the most significant BIT side of the words. As
the BIT comparison moves toward A3, B3, the lower BITs of the word are "don't care."
94
Operating states and control codes for equal inputs are governed by the information given in function
Table 7-3.
Table 7-3
COMPARING INPUTS CASCADE INPUTS OUTPUTS

A3, B3 A2,B2 A1,B1 A0,B0 A > B A = B A B A = B A < B
A3 = B3 A2 = B2 A1 = B1 A0 = B0 X H X L H L
A3 = B3 A2 = B2 A1 = B1 A0 = B0 H L H L L L
A3 = B3 A2 = B2 A1 = B1 A0 = B0 L L L H L H
Table 7-3 shows that if the Input words are equal, the CASCADE INPUTS control the levels at the
comparator output. The output codes can be configured for three distinct sets of levels.
Based on Table 7-3, the condition applies when words A and B are equal. The BIT structure of the words
does not matter, but the BITs of both words must be identical.
95
PROCEDURE
1. Make sure the power supplies are off. Connect the DIGITAL CIRCUIT FUNDAMENTALS 1 circuit
board into the base unit. Turn on the +15Vdc and -15Vdc power supplies.
2. Place the toggle switches on the INPUT SIGNALS circuit block in the DOWN position.
3. Place the toggle switch on the PULSE GENERATOR circuit block in the UP
4. Connect the SYNCHRONOUS COUNTER circuit shown by Figure 7-7. Use the CLEAR input of the
counter to reset the counter outputs.
Figure 7-7
5. Activate the BLOCK SELECT function on the 4 BIT COMPARATOR circuit block. Ensure that your
circuit is connected as shown by Figure 7-7.
6. Based on the output indicators of the 4-BIT comparator, what can you determine about the word A
and B inputs?
7. How can you verify that the two-word inputs are equal?
8. Based on the results obtained in step 6, are the BIT pairs of each word identical?
9. Set input A of your comparator high. Based on the comparator output indicators What is the
relationship between words A and B?
96
10. On your 4 BIT COMPARATOR circuit block, measure A (A0) and QA (B0). What is the relationship
between the two?
11. Based on your observations, can the comparator determine the relationship between two words if
only one of the BIT pairs is not equal?
12. Use the parallel load function of your counter to set word B of your comparator for $A (1010).
13. Set word A of your comparator for $A (1010). Since word A and word B are equal the A = B indicator
of the comparator should be on.
NOTE: The INPUT SIGNALS toggle switches control
word A. The output of your counter is hardwired to your
comparator comparator word B input.
14. Generate one clock pulse (PULSE GENERATOR circuit block) for your synchronous counter.
15. Based on the input indicators of your comparator, what are the BIT patterns for words A and B?
16. Make words A and B of the comparator equal to each other. Any equal values will do.
17. Use two-post connectors on the comparator control inputs to complete Table 8-4.
NOTE: Use patch leads if you do not have enough two-post connectors. Table 7-4.
Table 7-4
CONTROL INPUTS OUTPUT STATES

A > B A = B A B A = B A < B
L H L
H L H
L L L
18. Based on your table, what is the effect of the control inputs on the output of your comparator?
19. Remove all two-post connectors from the inputs of your comparator circuit.
20. Set word B to 1000 and word A to 1000 to initiate an A = B output indication.
21. Use the word A controls to generate words of 1100, 1010, and 1001.
Observe the comparator output for each word pattern.
NOTE: The individual word groups to compare are:
Word B = 1000 1000 1000
Word A = 1100 1010 1001
RESULT = A>B A>B A>B
97
22. Based on your observations, can the comparator ignore all equal BIT patterns and make a decision
based only on unequal BITs of a word pattern?
23. If you repeat the comparisons given In step 21 but alter word B in place of word A Would you expect
the exact same output results?
NOTE: Word A is fixed at 1000 and word B varies.
24. Set word B to 1000 and word A to 1000 to initiate an A = B output indication.
25. Use the word B counter to generate words of 1100, 1010, and 1001.
Observe the comparator output for each word pattern.
NOTE: The individual word groups to compare are:
Word B = 1100 1010 1001
Word A = 1000 1000 1000
RESULT = A<B A<B A<B
26. Does the result of step 25 verify your answer in step 23?
27. Do not disconnect your circuit. You may use it to help you answer the review questions.
98
REVIEW QUESTIONS
1. Word A= 1000 and word B= 0111. A comparison between the two words indicates that
a. A>B.
b. A=B.
c. A<B.
d. B>A.
2. Word A=0111 and word B = 1000. A comparison between the two words indicates that
a. A>B.
b. A=B.
c. A<B.
d. B<A.
3. If word A and word B are equal, then the output condition is determined by
a. the A = B Input,
b. whichever input is 1.
c. the AB Input.
4. Based on your comparator, as illustrated by Figure 7-8, the outputs
a. will not function without LEDs.
b. are 1, 1, and 1.
c. are 0, 0, and 0.
d. are 0, 1, and 0.
Figure 7-8
5. Word A = 1001 and word B = 1010. Your comparator decides that A< B
a. on the basis of the LSB pair (BIT pair 0).
b. on the basis of BIT pair 1.
c. because the two MSB pairs are equal.
d. because the two MSB pairs are not equal.
99
EXERCISE 7-2: Comparators And Counter Modulus Control
EXERCISE OBJECTIVE
When you have completed this exercise, you will be able to set the modulus of a counter with a
comparator. You will verify your results by using a comparator to drive the CLEAR input of a
synchronous counter.
DISCUSSION
A comparator can be used to set the maximum count value of a counter.
Figure 7-9 illustrates the output waveforms of a comparator when words A and B are equal for a part
of the total compare time.
Figure 7-9
In the figure, only one of the outputs is active (high) at a time; however, the combination of all three
active outputs accounts for the total count time.
Figure 7-10 Illustrates the relationship between the output waveforms when A = B at an input value of
1010 ($A).
Figure 7-10
If word A = 1010 and word B cycles between 0 and 1111, the A > B, A = B, and A B is active (high) while the word B value is between 0 and
1001. Since word A is fixed at 1010, A is greater than B as long as word B is between 0000 and 1001.
Figure 7-11
In the figure, the counter is reset by the CLEAR input generated by the A = B output of the comparator.
Notice that the CLEAR input requires a high active input and that the A = B output is also high, when
active.
In Figure 7-11, the counter output value will be one less than the A = B set value of the comparator. This
operation occurs because the A = B value immediately generates a CLEAR input. The CLEAR input
resets the counter output to zero.
Figure 7-12 shows the circuitwaveformsassoclated with a variable modulus counter application.
Figure 7-12
The CLEAR pulse occurs as the counter output is clocked from 6 to 7. On 7, the comparator generates
a 100 ns pulse, which resets the counter output to zero.
The total duration or pulse width of the CLEAR pulse is made up of the response time of the comparator
and the time required for the counter to reset.
101
PROCEDURE
into the base unit. Turn on the +15Vdc and -15Vdc power supplies.
2. Place the toggle switches of the INPUT SIGNALS circuit block in a 1010 (hex A, or $A) pattern. The
A-word of your comparator is now set for 1010.
3. Connect the circuit shown in Figure 7-13. Do not activate the MOD function on the SYNCHRONOUS
COUNTER circuit block.
Figure 7-13
4. Connect your oscilloscope to the QC output of your counter. Synchronize your oscilloscope on the
negative slope of this signal. Adjust your oscilloscope for a sweep frequency of 20 𝜇s/cm.
5. Set the A-word of your comparator for a 0111 value.
NOTE: insure that the MOD (counter circuit) and MOD/A=B {comparator circuit} two-post Connectors are in place.
6. Use channel 2 of your oscilloscope to observe the signals required for the following questions.
7. What is the output range of your counter?
8. Based on your circuit waveforms, what counter output value follows the circuit reset?
9. Based on your circuit waveforms, what counter output precedes the circuit reset point?
102
10. Based on your circuit waveforms, where is the A = B pulse located?
NOTE: This is a narrow pulse and difficult to see. For this step, turn the oscilloscope intensity control to its full
clockwise position.
11. Based on your circuit measurements and observations, can a modulus feedback be used to
determine the maximum count output of a counter?
103
REVIEW QUESTIONS
1. The modulus feedback generated by a comparator is used to
a. reset a counter.
b. determine the maximum count value of a counter.
c. All of the above.
2. On your circuit, the pulse width of the CLEAR (A = B) signal

a. equals the pulse width of the counter clock,
b. depends on how long you desire a reset condition to occur.
c. varies based on the circuit modulus.
d. depends on the response time of the comparator and counter ICs.
3. As you vary the modulus of your circuit,

a. there is no effect on the ratio of the active time of each comparator output.
b. the ratio between the active times of the comparator outputs is altered.
c. all comparator outputs are low if A = B.
d. all comparator outputs are high if A= B.
4. A variable modulus feedback can be used

a. only If the counter Is configured to count up.
b. only if the counter is configured to count down.
c. for both static and dynamic counter clock inputs.
d. for any of the stated operations.
5. Your circuit has a modulus of 10 ($A). it is properly configured to count up and is dynamically clocked.
Its proper counting sequence is
a. 1001, 0000, 0001, and so on.
b. 0000, 1001. 0000, fixed reset.
c. 0000, 1111, 1110, 1010, reset, and so on.
104

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TON DUC THANG UNIVERSITY

FACULTY OF ELECTRICAL-ELECTRONICS ENGINEERING

Figure 1-1. Operating levels of TTL circuits

Figure 1-2. Logic Concepts

Figure 1-3. Boolean form of notation

Figure 1-5. AND and NAND gates

Figure 1-6. 74LS00 NAND, SSI IC

Figure 1-7. AND gate operation

NOTE: Remember that a high

Figure 1-9. 8-input NAND gate.

2. What are the logic levels at the AND gate inputs?

AB = _________ AB = _________

6. Do the output LEDs confirm your answer to step 5?

Figure 1-11. AND and NAND truth tables.

2. The output of a NAND gate is low

3. In the circuit of Figure 1-14, output levels A through D are, respectively,

Figure 1-15. OR and NOR gates

Figure 1-16. Typical 74LS02

Figure 1-17. OR circuit operation

Figure 1-19. 3-input NOR gate

2. What are the logic levels at the OR gate inputs?

3. What are the logic levels at the NOR gate inputs?

4. Do the circuit input LEDs confirm your answers to steps 2 and 3?

5. What is the logic level at the output of each gate?

A+B = __________ A+B = __________

6. Do the circuit output LEDs confirm your answer to step 5?

Figure 1-21. OR and NOR truth tables

2. The output of a NOR gate is low

Figure 2-1. EXCLUSIVE OR/NOR schematic symbols.

Figure 2-2. EXCLUSIVE-OR operation

Figure 2-4. Using XOR gates to complement.

Figure 2-5. Typical 74LS136

Figure 2-6. Open collector pull-up

2. What are the logic levels at the XOR gate inputs?

3. Using a two-input XOR gate to generate a complement

TOGGLE SWITCH INPUT/ OUTPUT PHASE

5. In Figure 2-12, output E

The output action of a flip-flop circuit is illustrated in Figure 3-1.

Figure 3-1. Flip-Flop output action

Figure 3-2. Flip-flop clock symbols

Figure 3-3. Flip-flop signal relationships.

Figure 3-5. D-type flip-flop.

The two outputs, Q and Q are complements of each other.

Figure 3-6. Inverting-input OR gate.

Figure 3-7: NAND gate and inverting-input OR gate symbol functions

Figure 3-8. Gate configured flip-flop.

Figure 3-9. Set/reset flip-flop.

Figure 3-11. Set circuit states.

9. Can this flip-flop circuit be used to debounce a switch contact?

11. How can the circuit be reset (Q output to low state)?

18. Does the circuit exhibit reset memory?

2. In the reset state, the Q output is

3. The SET/RESET FLIP-FLOP circuit can debounce a mechanical switch because

Figure 3-13. D type flip-flop.

3. What should the effect of activating the PR input be?

5. What should the effect of activating the CLR input be?

11. Do the answers to step 9 and 10 agree?

2. The Q output of a D-type flip-flop

3. If the CLK input of the D-type flip-flop is at a low state,

Figure 4-1. JK flip-flop with preset and clear Inputs.

3. What should the effect of activating the PR input be?

20. Why doesn't operation (2) generate an output change?

21. Why doesn't operation (4) generate an output change?

AB = _ AB = _

A+B = A+B =