The six-step process

1. Calculate the base voltage using the voltage divider equation.

2. Subtract 0.7 V to get the emitter voltage.
3. Divide by emitter resistance to get the emitter current.
4. Determine the drop across the collector resistor.
5. Calculate the collector voltage by subtracting the voltage across the
collector resistor from VCC.
6. Calculate the collector-emitter voltage by subtracting the emitter
voltage from the collector voltage.
VDB analysis
1. The base current must be much smaller than current through the
divider.
2. With the base voltage constant, the circuit produces a stable Q point
under varying operational conditions .
Firm voltage divider
1. Used because divider resistors (e.g. R1 and R2) in a stiff design would
be too small
2. The collector current will be about 10% lower than the stiff value
VDB load line and Q point
1. VDB is derived from emitter bias
2. The Q point is immune to changes in current gain
3. The Q point is moved by varying the emitter resistor
 DC Biasing Circuits
The ac operation of an amplifier +VCC
depends on the initial dc
values of IB, IC, and VCE.
By varying IB around an initial dc RC
value, IC and VCE are made to RB
vary around their initial dc v out
values.
DC biasing is a static operation
since it deals with setting a v in vce
ib
fixed (steady) level of
current (through the device)
ic
with a desired fixed voltage
drop across the device.

Ref:080314HKN EE3110 DC and AC Load Line 14

Purpose of the DC biasing circuit
• To turn the device “ON”
• To place it in operation in the region of its characteristic where the
device operates most linearly, i.e. to set up the initial dc values of IB, IC,
and VCE

Ref:080314HKN EE3110 DC and AC Load Line 15

 Voltage-Divider Bias
• The voltage – divider (or +VCC
potentiometer) bias circuit is by
far the most commonly used.
• RB1, RB2 RC
R1
 voltage-divider to set the v out
value of VB , IB C1 C2

• C3 v in

 to short circuit ac signals to R2

ground, while not effect the DC
operating (or biasing) of a circuit RE C3

(RE  stabilizes the ac signals)

→ Bypass Capacitor

Ref:080314HKN EE3110 DC and AC Load Line 16

 Graphical DC Bias Analysis
+VCC
VCC − ICRC − VCE − IERE = 0
for I C  I E
−1 VCC
IC RC IC = VCE +
RC + RE RC + RE
R1
Point - slope form of straight line equation :
y = mx + c

IC(sat) = VCC/(RC+RE)

R2 DC Load Line
IE
IC
RE (mA)
VCE(off) = VCC

VCE

Ref:080314HKN EE3110 DC and AC Load Line 17

 DC Load Line
The straight line is know as the DC load line IC(sat) = VCC/(RC+RE)
Its significance is that regardless of the behavior
of the transistor, the collector current IC and the DC Load Line

collector-emitter voltage VCE must always lie on (mA)

I C

VCE(off) = VCC
the load line, depends ONLY on the VCC, RC and RE
(i.e. The dc load line is a graph that represents VCE

all the possible combinations of IC and VCE for a

given amplifier. For every possible value of IC,
and amplifier will have a corresponding value of
VCE.)
It must be true at the same time as the transistor
characteristic. Solve two condition using
simultaneous equation
→ graphically → Q-point !!

What is IC(sat) and VCE(off) ?

Ref:080314HKN EE3110 DC and AC Load Line 18

 Q-Point (Static Operation Point)
• When a transistor does not have an ac input, it will
have specific dc values of IC and VCE.
• These values correspond to a specific point on the
dc load line. This point is called the Q-point.
• The letter Q corresponds to the word (Latent)
quiescent, meaning at rest.
• A quiescent amplifier is one that has no ac signal
applied and therefore has constant dc values of IC
and VCE.

Ref:080314HKN EE3110 DC and AC Load Line 19

 Q-Point (Static Operation Point)
• The intersection of the dc bias
value of IB with the dc load line
determines the Q-point.
• It is desirable to have the Q-point
centered on the load line. Why?
• When a circuit is designed to
have a centered Q-point, the
amplifier is said to be midpoint
biased.
• Midpoint biasing allows optimum
ac operation of the amplifier.

Ref:080314HKN EE3110 DC and AC Load Line 20

 DC Biasing + AC signal
• When an ac signal is applied to the base of
the transistor, IC and VCE will both vary
around their Q-point values.
• When the Q-point is centered, IC and VCE
can both make the maximum possible
transitions above and below their initial dc
values.
• When the Q-point is above the center on
the load line, the input signal may cause the
transistor to saturate. When this happens,
a part of the output signal will be clipped
off.
• When the Q-point is below midpoint on the
load line, the input signal may cause the
transistor to cutoff. This can also cause a
portion of the output signal to be clipped.

Ref:080314HKN EE3110 DC and AC Load Line 21

 DC Biasing + AC signal

Ref:080314HKN EE3110 DC and AC Load Line 22

 DC and AC Equivalent Circuits
+VCC
+VCC

RC IC RC
R1 R1

RL rC
vin vce
vin

R2 R1//R2
R2
IE
RE
RE

rC = RC//RL

Bias Circuit DC equivalent AC equivalent

circuit circuit

Ref:080314HKN EE3110 DC and AC Load Line 23

 AC Load Line
IC(sat) = VCC/(RC+RE)
• The ac load line of a given
amplifier will not follow the
DC Load Line plot of the dc load line.
IC
(mA)
VCE(off) = VCC • This is due to the dc load of an
amplifier is different from the
VCE
ac load.

IC(sat) = ICQ + (VCEQ/rC)

ac load line

ac load line
IC IC Q - point

dc load line
VCE(off) = VCEQ + ICQrC

VCE

VCE

Ref:080314HKN EE3110 DC and AC Load Line 24

 AC Load Line
What does the ac load line tell you?
• The ac load line is used to tell you the maximum possible
output voltage swing for a given common-emitter
amplifier.
• In other words, the ac load line will tell you the maximum
possible peak-to-peak output voltage (Vpp ) from a given
amplifier.
• This maximum Vpp is referred to as the compliance of the
amplifier.
(AC Saturation Current Ic(sat) , AC Cutoff Voltage VCE(off) )

Ref:080314HKN EE3110 DC and AC Load Line 25

AC Saturation Current and AC Cutoff Voltage

IC(sat) = ICQ + (VCEQ/rC)

ac load line
rC IC
vin vce

R1//R2
VCE(off) = VCEQ + ICQrC

VCE
rC = RC//RL

Ref:080314HKN EE3110 DC and AC Load Line 26

 Amplifier Compliance
• The ac load line is used to tell the maximum
possible output voltage swing for a given
common-emitter amplifier. In another words, the
ac load line will tell the maximum possible peak-
to-peak output voltage (VPP) from a given amplifier.
This maximum VPP is referred to as the compliance
of the amplifier.
• The compliance of an amplifier is found by
determine the maximum possible of IC and VCE
from their respective values of ICQ and VCEQ.

Ref:080314HKN EE3110 DC and AC Load Line 27

 Maximum Possible Compliance

Ref:080314HKN EE3110 DC and AC Load Line 28

 Compliance
The maximum possible transition for VCE is equal to the
difference between VCE(off) and VCEQ. Since this transition is
equal to ICQrC, the maximum peak output voltage from the
amplifier is equal to ICQrC. Two times this value will give the
maximum peak-to-peak transition of the output voltage:

VPP = 2ICQrC (A)

VPP = the output compliance, in peak-to-peak voltage
ICQ = the quiescent value of IC
rC = the ac load resistance in the circuit

Ref:080314HKN EE3110 DC and AC Load Line 29

 Compliance
When IC = IC(sat), VCE is ideally equal to 0V. When IC = ICQ, VCE is at
VCEQ. Note that when IC makes its maximum possible transition
(from ICQ to IC(sat)), the output voltage changes by an amount
equal to VCEQ. Thus the maximum peak-to-peak transition would
be equal to twice this value:

VPP = 2VCEQ (B)

• Equation (A) sets the limit in terms of VCE(off). If the value

obtained by this equation is exceed, the output voltage will try to
exceed VCE(off), which is not possible. This is called cutoff clipping,
because the output voltage is clipped off at the value of VCE(off).
• Equation (B) sets of the limit in terms of IC(sat). If the value
obtained by this equation is exceed, the output will experience
saturation clipping.

Ref:080314HKN EE3110 DC and AC Load Line 30

 Cutoff and Saturation Clipping
• When determining the output compliance for a given
amplifier, solve both equation (A) and (B). The lower of the
two results is the compliance of the amplifier.

Ref:080314HKN EE3110 DC and AC Load Line 31

 Example
• For the voltage-divider bias amplifier shown in the
figure, what is the ac and dc load line. Determine
the maximum output compliance.

+12V

RC
R1 4.7k
33k
RL
10k
 = 200

R2
10k RE
2.2k

Ref:080314HKN EE3110 DC and AC Load Line 32

Two Supply Emitter Bias
PNP transistor
1. The base is n-type material
2. The collector and emitter are p-type material
3. The emitter arrow points in
4. Can be used with a negative power supply
Terima Kasih
Otsukaresamadeshita