1-3ADDRESSES

All memory locations and 1/O registers are. of course, conprised of bits, but
because single bits contain very little information they are grouped together
form bytes and words. Because characters are normally 7 or 8 bits long and becausa
computers work more naturally with powers of 2. bytes almost always consist of s
on the
bits.
Words may consist of 2. 3, or 4 bytes, depending
computer
have
and its
systembus structure. Since the 16-bit single-chip microprocessors 16 data
lines in their system buses, they use the term "*word" to mean 2 bytes (16 bits).
Each byte has an identifying address associated with it and when a byte is to
be accessed its address is transmitted to the appropriate interface via the addres
lines. Addresses are composed of bit combinations and the set of all possible
combinations for a given situation is called an address space. Some computers have
two address spaces while others use a single address space to access all memory
locations and I/O registers. If there are separate memory and 1/O address spaces,

then of the control lines must be used in conjunction with the address lines
some

to determine which space is being accessed. Because the memory

is divided into
select the
modules, some of the high-order bits in a memory address are used to
module and the remaining (low-order) bits are used to identify the byte (or word)
within the module. Similarly, an interface is identified by the high-order bits in an

I/O address and the register within the interface is selected by the 2 or 3 low-order
bits. The overall organization of memory and I/O registers and how they are
addressed is summarized in Fig. 1-7.
The number of possiblebits in an address determines the size of an
space. If an address is n bits wide, then there are 2" possible addresses (0 through
address
2"-1). The number of address lines in the system bus dictates the size of the

emory (or possibly the combined memory and I/0) space. A total of address
nes would imply a maximum memory (or overall memory and 1/O) capaciy oi
n

2" bytes. Twenty address lines would

imply a
capacity or

220=(210)2=(103)2 =
1 million bytes
nere are 2
uaress is to be used tobytes in a
identifv
word there is some
question
the word. Also. it is
as to
wnic
te
t about a specific bit in a sometimes necessa to
C manuals) the address of byte or word. the
a word is the address Throughout this book (ai
of its low-order, or Ss,
loW-adu
 Sec. 1-3 Addresses 15

Addresses
Memory module

Bytes in memory

|
Interface10
Bus control
CPU logic

High-order bits
determine module

I/0 interface I/0 device

1/0 registers
(or ports)

High-order bits determine

interface and low-order
2 or 3 bits select the

Control lines register

determine address
space

Figure 1-7 Memory and I/O register organization.

The bits are numbered with being

0 assigned to the least significant bit (LSB).
byte. bit (MSB) is numbered 7 and in a
word the MSB is
In a byte the most significant
conventions are summarized in Fig.
1-8.
numbered 15. These addresses that are divisible
require that words begin with
Some computers if this rule is
an alignment error
in a word and produce
by the number of bytes words to begin at any address:
as the 8086, permit
not followed. Others, such

conventions.
Address and bit numbering
Figure 1-8
Word address

AddressN
Address N+1 Low-order byte
High-order byto

Bit 7 1465 4 21 08 7 6 5
3 10
13 12 11 9
nos. 15
 Introduction
16
Chap. 1
words may require more than
one memory acce
however, accessing *nonaligned" cess
word that begins with an odd address require.
res
(e.g.. c n the 8086, referencing
a

two memory accesses).

1-4 GENERAL OPERATION OF

A COMPUTER

that CPU must facilitats

high-level languages it is seen a
From our experience with ate
working with:

1. Assignments and arithmetic expressions.

2. Unconditional branches.
3. Conditional branches and relational
and logical expressions.
4. Looping.
5. Arrays and other data structures.

6. Subroutines.
7. 1/O.

architecture that is to accommodate these features is given

designed
A typical CPU
and carrying out the instructions,
Fig. 1-9. It includes a control unit for decoding
and computational tasks,
a set working registers for helping with the addressing and
of
for executing the arithmetic logical operations,
an arithmetic/logic unit (ALU)
I/O.
and an I/O control section for handling
unless a branch instruction is
Just as with high-level language programs,
encountered a machine language program
is executed in sequence. A register,
used to hold the current instruction whileit
called the instruction register (IR), is counter (PC),
is being decoded and executed,
and a register, called the program
the next instruction. When the present instruction
is used to hold the address of address bus,
has completed its execution,
the address in the PC is placed on the
instruction on the data bus, and the CPU inputs the
the memory places the next
instruction is decoded its length in bytes is de
instruction to the IR. While this the
the length so that the PC will point to
termined and the PC is incremented by
execution of this instruction is completed,
the contents
next instruction. When the
address bus and the cycle is repeated.
of the PC are placed on the
Unconditional branch instructions permit
the normal sequencing to be altered
the contents of the PC, the address of
the next instruction, with an
by replacing Conditional branch instructions may
address determined by the branch instruction.
or may not replace the contents of
the PC depending on the results of the previous
determined by the previOus
instructions, i.e., the current state of the processor as the
a register called
instructions. The current state of the processor is stored in
as

processorstatus word The PSW contains bits which indicate such things
(PSW).
whether the previous arithmetic operations produced a positive, negative, or zei

Tesuit. If a *subtract"" instruction is followed by a "branch on zero instruco

resultea n
C n e branch will be taken if the PSW indicates that the subtraction
Sec. 1-4 General Operation of a Computer 17

CPU

Control unit Working registers

Address registers
Program counter (PC)

Instruction register (IR)

Processor status word (PSW)

Arithmetic registers
Stack pointer (SP)

1/0 control logic

ALU

architecture. Glenn A. Gibson, James R. Young. INTRODUCTION

Figure 1-9 Typical CPU 16. Reprinted by permission of
TO PROGRAMMING USING FORTRAN 77,© 1982, p.
Prentice-Hall, Inc., Englewood Cliffs, NJ.

a nonzero result, the branch

a zero. If the PSW shows that the subtraction produced
taken a new sequence of instructions begins
will not be taken. When a branch is
at the address to which the
branch is made. A flowchart illustrating the sequencing
in Fig. 1-10.
of instructions within a computer is given
Loopingis normally performed using conditional branch instructions, al-
have instructions that combine counting and/or test-
though some microprocessors
Most loops, such as a FORTRAN DO-loop.
ing with the conditional branching. and repeating the loop until the
involve incrementing or decrementing a counter
counter reaches a limit. Each time the counter is changed the result is compared
and the branch is taken or not taken
with the limit, the PSW is set accordingly,
PSW.
depending on the contents of the
The sequencing involved in a subroutine call is shown in Fig. 1-11 and requires
a special form of branching.
As with other branehing, a subroutine call also causes
address being branched to, but it
the contents of the PC to be replaced by the
must also save the current contents
of the PC, which is the return address. The
branch instruction nust be capable of restoring the return address to
the
return
 18 Introduction
Chap
Start

The CPU sends the address contained

in the PC to the memory

The memory gets the machine instructionin the

location being addressed and sends it back
to the CPU

The CPU puts the machine instruction

in the IR and decodes it

A
branch instruction

conditional branch Execute the

instruction
Examine PSW

Branch F
condition met

T
Set PC to address
of next sequential

Set PC to
instruction
branch address

Figure 1-10 Instruction sequencing.

PC so that the main

program
continue in sequence once the
can
complete. In addition to
saving
the return subroutine is
porarily store other address, it is usually
while the subroutine isinformation, such as the contents of necessary to ten
executing. This is so because the the working registers,
destroy the original contents sudroutine
return is made of these registers might otherws
and
to the main
program. Normally, this they
needed when nmay be
special area in
The address information
menmory called the stack. is
of the stack storea
location tha
 Sec. 1-4 General 19
Operation of a Computer

Subroutine

Entry point:

Return Call
address

Return

Figure 111 Subroutine call.

was last accessed (or, on some computers, that will be accessed next) is kept in
the stack pointer (SP) register. Stacks and subroutines are discussed in detail in
Chap. 4.
The working registers are for temporarily holding information that aids the
addressing and computational process. They tend to be divided into two groups.
an address group and an arithmetic group, although some registers may be such
that they can be used for both purposes.
The address group is used for making the addressing of data more flexible.
A datum being operated on by an instruction may be part
of the instruction, its
address may be part of the instruction, it may be in a register,
its address may be
of the instruction and the
in a register, or its address may be the sum of part
contents of one or more registers.
Sometimes when a register is used the instruction
contains the address, but other times the address
simply indicates the register that when accessing elements of an
determination is more complicated. For example,
an element is comprised of
two parts, a base address, which
array the address of
in the array, and an offset. Because one often
is the address of the first element
if the offset can be easily incremented.
needs to index through an array, it is helpful
element is frequently computed by adding two
Therefore, the address of an array
contains the base address and is called a base register
registers together, one which
and is called an index register. A two-dimensional
and one which contains the offset
more complex situation which requires
the addition of a base.
array offers a slightly
This normally involves the sum of part of the
a column offset, and a displacement.
instruction (the displacement), a base register, and an index register. Base registers
and blocks of data within memory, a topic that
are also used to relocate programs
and 4.
is explored further in Chaps. 2
Arithmetic registers are for temporarily holding the operands and results of
the arithmetic operations. Because transfers over the system bus are the primary
limiting factor with regard to speed, accessing a register is muchfaster than accessing
memory. Therefore, il several operations must be perlormed on a set of data, it
is better to input the data to the arithmetic registers, do the necessary calculations,
and return the result to memory than it is to work directly from memory. The
2 8086 Architecture

The Intel 8086, a 16-bit microprocessor, contains approximately 29,000 transistors

and is fabricated using the HMOS technology. Its throughput is a considerable
improvement over that of the Intel 8080, its 8-bit predecessor. Although some
attempt at compatibility with the 8080 CPU architecture was made, the designers
decided not to sacrifice sophistication in order to attain compatibility (Morse et
al. [1]). By increasing the number of address pins from 16 to 20, the memory
addressing capacity was increased from 64K bytes to 220 1 megabyte. The ex-
panded memory capability made multiprogramming feasible and several multipro
gramming features have been incorporated into the 8086's design. The 8086 also
includes a number of features which enhance its multiprocessing capabilities, thus
allowing it to be used with other processing elements such as the 8087 numeric
data processor.
A pin assignment diagram for the 8086 is given in Fig. 2-1. The 8086 has 20
address pins, 16 of which are also used as data pins. The use of pins for both
addresses and data means that both an address and datum cannot be sent to the
This multiplexing of addresses and data reduces the
system bus at the same time.
number of pins needed, but does slow down the transfer of data. However, because
of the timing on the bus, the transfer rate is not decreased as much as one might
lines for providing handshaking signals during bus
expect. There are 16 control
control of the CPU. The 8086
transfers and for permitting at least some external
requires only supply
one voltage, +5 V, and one clock phase whose frequency can
be up to 5 MHz. (There are actually two other versions of the 8086, the 8086-2,
clock frequency of up to 8 MHz, and the 8086-1, which can handle
permits a
ENGIMEERING
which
1
two grounds, pins

LIBRARY
up to 10 MHz.) Rounding out the 40-pin contiguration are

and 20.
25
 8086 Arcniet
Chap.2
Supply voltage, +5 v

a0Vcc Address/data
26 3 9 A D 1 5 -

GND
3 8 A 1 6 / $ 3

Ground
c14
Address/control
37A17/s4
AD13 3
36 A 18/S5
AD124
35 A 19/S6
AD11 5
AD10 6 34BHES7
AD97 33MN/MK

AD8 8 32RD
Address/data AD79 31ROGTO
(HOLD)
AD610 8086 3 0 R O / G T Í (HLDA)
CPU
AD511 29 LOCK (WR)
AD4 12
(M/O) Control
2852
AD3 13
27T (DT/A)
A02 14
(DEN)
26 S0
AD115 (ALE)
25 as0
ADO16
24 aS1 INTA)
NMI 17
Control INTR 18 23 TEST

Clock CLK 19 22READY

Ground GND20 21RESET

Figure 2-1 8086 pin assignments. (Reprinted by permission of Intel Corporation.

Copyright 1981.)

This chapter begins

with a description of the 8086's CPU
internal operation. The third section defines the architecture and
data and perform branches and ways in which the 8086 can address
discusses the 8086's machine
formats. Section 2-4 discusses the
amounts of time needed to
language instructio
instructions and Sec. 2-5 describes the execute the varu
8-bit version of the 8086. The Intel 8088, which is a
8088 software compatibi
configurations to be upgraded to an 8086designed
was
to allow 8080 and
8085 hardwarc
software environment.
CPUARCHITECTURE
Figure 2-2 shows the
internal
register, which is actually architecture of
described in Sec. 1-4 are a 6-byte queue, thethe 8086. Except
cept for the ins
instruc
There are the data divided into control unit and e king regis
sters

group, which three working

pointer group, which includes baseis and indexygroups
registers,
ne setaccording
ofbut:
arithmetic registr
functions
essentially the set of to their
irthe the
ndex arithmetic
etic regist
roB
registers, but
ters;

also contains the pro

the pro
Sec. 2-1 CPU Architectuie
27

Instruction
Data registers
queue
AX AH AL
BX 8H BL
Address/data
Control
CX CH CL logic (20 pins)

DX DH DL

Pointers Segment registers Control

SP CS (16 pins)
BP SS
SI DS
ALU
DI ES +5 V

PSW IP -Ground
Clock

For the 8086 tte program counter is called the

instruction pointer (IP).

Figure 2-2 8086's internal configuration.

gram counter and stack pointer; and the segment group, which is a set of special
purpose base registers. All of the registers are 16 bits wide.
The data group consists of the AX, BX, CX, and DX registers. These registers
can be used to store both operands and results and each of them can be accessed
as a whole, or the upper and lower bytes can be accessed separately. For example,
either the 2 bytes in AX can be used together, or the upper byte AH or the lower
byte AL can be used by itself by specifying AH or AL, respectively. For purposes
of converting 8080 software into 8086 software the following correspondences can
be drawn:
8086 8080
AL
BH H
L
H B
L C
DH
DL
D
In addition to serving as arithmetic registers, the BX, CX, and DX registers
play special addressing, counting, and I/O roles:
BX may be used as a base register in address calculations.
CX is used as an implied counter by certain instructions.
DX is used to hold the I/O address during certain 1/0 operations.
 28 8086 Architecture
Chap
The pointer and index IP, SP, BP, SI,
consists of the
group and DI
rogram.registe
he instruction pointer (IP) and SP registers are essentially the pro
and stack pointer registers, but the complete instruction and stack add Oun
formed by iding the contents of these
registers to the contents of the codeesa
(CS) and stack segment (SS) registers discussed below. BP is a base r"gme
ecessing the stack and may be used with other registers and/ora giste
a t is part of the instruction. The SI and DI registers are for indexing. A e displace
they may be used by themselves, they are often used with the BX or Bpou
andor a displacement. Except for the IP. a pointer can be used to hold
old an.
an
giste=
but must be accessed
as a
whole. operan
o provide flexible base addressing and indexing, a data address
may
tormed by adding together a combination of the BX or BP register contay
Or
DI register contents, displacement. The result of such an addrese
and a ents,
putation is called an effective address (EA) or offset. |lhe Intel CoE
use the term
manuals tend
"effective address" when discussing the machine
term "offset" when
language and
discussing the assembler language. The word
IS used to
indicate a quantity that is added to the contents of a "*displacema
an
EA.] The final data address, however, is determined by the EAregister(s) to f
or
propriate data segment (DS), extra segment (ES), or stack segment and the-
The segment group consists of the (SS) regist
CS, SS, DS, and ES registers. As indicata
above, the registers that can be used for
DI registers, are addressing, the BX, IP, SP, BP, SL
only 16 bits wide and, therefore, an effective address has
bits.On the other hand, the address only 1
put on the address bus, called the physic
address, must contain 20 bits. The extra 4 bits are obtained
address to the contents of one of the by adding the etfectiv
addition is carried out by
segment registers shown in Fig. 2-3. Th
as

appending four 0 bits to the right of the number in th

segment register before the addition is made; thus a 20-bit result is
an
example, if (CSs) 123A and produced.
fetched from
=
(IP) =341B, then the next instruction will b

341B Effective address

+123A0 Beginning segment address
157BB Physical address of instruction
It is standard notation for parentheses around an
e.g.. (IP) means the contents of IP. entity to mean "contents ot,
Also, all addresses are given in hexadecimal
Effective address
or offtet 16 bits Figure 2-3 Formation of a physical
address.
+ 4 bits
Segnent address 16 bits

Physical dress 20 bits

 Sec. 2-1 CPU Architecture 29

The utilization of the segment registers essentially divides the memory space
into overlapping segments, with each segment being 64K bytes long and beginning
at a 16-byte, or paragraph, boundary, i.e., beginning at an address that is divisible
by 16. We will hereafter refer to the contents of a segment register as the segment
address, and the segment address multiplied by 160 as the beginning physical
segment address, or simply, the beginning segment address. An illustration ot the
example above is given in Fig. 2-4(a) and the overall segmentation of memory iIs
shown in Fig. 2-4(b).
The advantages of using segment registers are that they:

1. Allow the memory capacity to be 1 megabyte even though the addresses

associated with the individual instructions are only 16 bits wide.
2. Allow the instruction, data, or stack portion of a program to be more than
64K bytes long by using more than one code, data, or stack segment.
3. Facilitate the use of separate memory areas for a program, its data, and the
stack.
4. Permit a program and/or its data to be put into different areas of memory
each time the program is executed.

Figure 2-5 shows how a program's code and its associated data and stack can
be separated in memory. The simpler and conventional approach is to let both the
code and the data reside in one contiguous area in memory and put the stack in
some fixed area which always begins at, say, address 08000. This is satisfactory if
there is only one program in memory at a time, but in a multiprogramming en-
vironment there may be several programs in memory simultaneously. For multi-

Figure 2-4 Address computations and memory segmentation.

Memory
Memory
00000
00000

-(CS) 00010
123A0 (
-First segment
Effective address
(341B) 00020
Second segment
157BB Range of
code segment
Third segment
Next instruction 10000

10010
2239F
223A0
10020

(a) Address within segnent (b) Overlapping segments

 Sec. 2-3 Machine Language Instructions
35

beginning with an even address, and Fig. 2-9(b) shows the same sequence but
assumes an odd beginning address. Note that in the latter case the last byte of the
third instruction will not be brought into the queue until an empty word in the
queue becomes available.

2-3 MACHINE LANGUAGE INSTRUCTIONS

An instruction is divided into groups of bits, or fields, with one field, called the

op code). indicating what the computer is to do,

and the other
operation code (or
tields. called the operands, indicating the information needed by the instruction in

carrying out its task. An operand may contain a datum, at least part of the address
of a datum, an indirect pointer to a datum, or other information pertaining to the
data to be acted on by the instruction. A general instruction format is shown in

Fig. 2-10.
Instructions may contain several operands, but the more operands and the

these operands are, the more memory space they will occupy and
the more
longer
order to minimize
time it will take to transfer each instruction into the CPU. In
those for
the total number of bits in an instruction, most instructions, particularly
16-bit computers, are limited to one or two operands
with at least one operand in
a register. Because the memory
and/or I/O
a two-operand instruction involving

are relatively large, memory and

I/O addresses require several bits, but
spaces
because the number of registers is small, it takes only a few bits to specify a register.
bits is to use registers as much as
Therefore, one means of conserving instruction
instruc-
limitation does reduce the flexibility of many
possible. The two-operand
is not really needed. For example, an
tions. but normally the extra flexibility
addition instruction, which involves
the two numbers being added and the result.
the sum into the location that contained the
is reduced to two operands by putting
is lost, but this is usually not important. If it
addend. This means that the addend before
could be duplicated (by also storing it elsewhere)
is important, the addend
the addition is executed.

2-3-1 Addressing Modes

is is called its addressing mode. The ad-

specified
The way in which an operand below. They
instructions are typical and are discussed
dressing modes for the 8086 addresses.
those for data and those for branch
are broken into two categories,
how the operandsare determined for the various
graphically
2-11 shows
Figure
data-related addressing modes. These modes are

l6 bits long and is part of the

Immediate-The datum is either 8 bits
or

instruction.

Figure 2-10 General instruction format

Operand
OOp code Operand
 36
8086 Architecture
Instruction
Datum
(a) Immediate

Instruction Memory

EA Datur
(b) Direct

Instruction Register
Register Datum

(c) Register

Instruction Register Memory

Register EA Datum
(d) Register indirect

Instruction
Register D1splacement

EA Memory
Register Datum
Address
(e) Register relative

Instruction Register
Base reg.index reg Index
Memory
Register Datum
Base addr.
(f) Based indexed

Instruction
Base reg. Index
reg.|Displacement
Register
Index Memory
Regisler Datum
Base addr.
(g) Relatve based
EA is
added to
1610 times indexed
the
contents ot the
aopropriate segrment Figure 2-11
reg ster.
modes.
Data-related a
 Sec 2-3 Machine Language Instructions 37

Direct-The 16-bit effective address of the datum is part of the instruction.

Register-The datum is in the register that is specified by the instruction. For
a l6-bit operand, a
register may be AX, BX, CX, DX, SI, DI, SP, or BP
and for an 8-bit operand a register may be AL, AH, BL, BH, CL. CH, DL,
or DH
Register Indirect-The effective address of the datum is in the base register
BX or an index register that is specified by the instruction, i.e.,

(BX)
EA = (DI)
(SI)
Register Relative-The effective address is the sum of an 8- or l6-bit dis-
placement and the contents of a base register or an index register, i...

( (BX)) 8-bit displacement

EA (BP) + (sign extended)
(SI) 16-bit displacementJ
(DI)
Based Indexed-The effective address is the sum of a base register and an
index register. both of which are specified by the instruction, i.e.,

EA (BX)
1BP) J(D»}
(SI) |
Relative Based Indexed-The effective address is the sum of an 8- or 16-bit
displacement and a based indexed address, i.e.,

(BX) (SI) 8-bit displacement

EA
EA = T (D) + (sign extended)
(BP) J [(D)J 16-bit displacement)
For example, if
(DI) = 10A5 Displacement = 1B57 (DS) = 2100
(BX) 0158
and DS is used as the segment register, then the etfective and physical addresses

produced by these quantities and the various addressing modes would be

Direct: EA = IB57

IB57 21000 22BS7

Physical address= +

Register: No effective adyress-datum is in specified register

Register indirect assuming register BX

EA = 0158

Physical address 0158 + 21000= 21158

Register relative issuming register BX:

EA 0158 B57 ICAF
Physical address =1CAF 21000 22CAF
 38
8086 Architecture
Based indexed assuming registers BX and DI:
EA = 0158 + 10A5 = 11FD

Physical address= 11FD *x 21000

Relative based indexed assuming BX and DI:
=
221FD
EA = 0158 + 10AS + 1BS7 = 2D54
Physical address =
2D54 + 21000 =
23D54
The addressing modes for indicating branch addresses
in Fig. 2-12 and are: idresses are graphical|
de
Intrasegment Direct-The effective branch address is the
bit displacement and the current contents of the sum of
IP. When the
bits long. it is referred to as a short e anan &c
what most computer books refer to as
jump. Intr
relative addressing trasegment directisplaaddre
cemen
dres1r
Instruction ause the
Dsolacement Figure 2-12
modes. Branch-related adde
EA
effective branch address

(a) Intrasegment direct

Register
Instruction
EA' computed Effective branch address
Addressing mode according to or
addressing mode Memory
Effective branch address
(b) Intrasegment indirect

Instruction CS
Ofset Segynent
IP

(c) Intersegment direct

instruc1on Two consecutive

EA computed words in memory
AddrrsSing mode 2ccording to
addr essing mode Branch address offset

Segrnent address
d) inter segnent
ndurect
EAIS odded to 101, tmes t e
contents of the
appropriate sug1nent
register
 Sec. 2-3 Machine Language Instructions 39

placement is computed "relative" to the IP. It may be used with either con-
ditional or unconditional branching, but a conditional branch instruction can
have only an 8-bit displacement.
Intrasegment Indírect-The effective branch address is the contents of a reg-
ister or memory location that is accessed using any of the above data-related
addressing modes except the immediate mode. The contents of IP are replaced
by the effective branch address. This addressing mode may be used only in
unconditional branch instructions.
Intersegment Direct-Replaces the contents of IP with part of the instruction
and the contents of CS with another part of the instruction. The purpose of
this addressing mode is to provide a means of branching from one code
segment to another.
Intersegment Indirect-Replaces the contents of IP and CS with the contents
of two consecutive words in memory that are referenced using any of the
above data-related addressing modes except the immediate and register modes.

Note that the physical branch address is the new contents of IP plus the contents
of CS multiplied by 1610. An intersegment branch must be unconditional.
To demonstrate how indirect branching works with some of the data-related
addressing modes, suppose that
(BX) = 1256 (SI) = 528F Displacement = 20A1

Then:
With direct addressing, the effective branch address is the contents of:

20A1 + (DS) x 16,10

assuming register BX, the effective branch

With register relative addressing
address is the contents of:
1256+20A1 + (DS) x 1610

registers BX and SI, the effective

With based indexed addressing assuming
branch address is the contents of:
1256+ 528F + (DS) x 1610

2-3-2 Instruction Formats

Several representative 8086 instruction formats are shown in Fig. 2-13. The in-
structions vary from 1 to 6 bytes in length and a complete summary of them is
given in Scc. 3-12. Displaceinents and immediate data may be either 8 bits or 16
bits long depending on the instruction. The op code and addressing mode desig-
nations are in the first 1 or 2 bytes of an instruction. The op code/addressing mode