Computer Organization

Fall 2021
Lecture 9
Introduction

MR Instructions

Register Instructions
 INSTRUCTION CYCLE

 In Basic Computer, a machine instruction is executed in the following cycle:

1. Fetch an instruction from memory
2. Decode the instruction and calculate effective address (EA)
3. Execute the instruction

 After an instruction is executed, the cycle starts

again at step 1, for the next instruction

 Note: Every different processor has its own

(different) instruction cycle
 THE TYPE OF INSTRUCTION
Start
SC  

T0
AR  PC
T1
IR  M[AR], PC  PC +1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference) =>opcode ≠ 111

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0

D'7IT3: AR  M[AR]
D'7I'T3: Nothing
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.
Introduction

MR Instructions

Register Instructions
 MR Instructions

Operation
Symbol Symbolic Description
Decoder

AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1

- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to complete in a CPU cycle
- The execution of MR instruction starts with T4
 MR Instructions
S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
BUN: Branch Unconditionally PC  AR Write Read
AR 1
D4T4: PC  AR, SC  0
LD INR CLR
PC 2

LD INR CLR

DR 3

LD INR CLR
E
ALU AC 4

LD INR CLR

INPR
IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus
 MR Instructions
S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
BSA: Branch and Save Return Address Write Read
AR 1
M[AR]  PC, PC  AR + 1
LD INR CLR
D5T4: M[AR]  PC, AR  AR + 1 PC 2

D5T5: PC  AR, SC  0
LD INR CLR

DR 3

LD INR CLR
E
ALU AC 4

LD INR CLR

INPR
IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus
 MR Instructions
BUN: Branch Unconditionally PC  AR
D4T4: PC  AR, SC  0

BSA: Branch and Save Return Address M[AR]  PC, PC  AR + 1

D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0
Memory, PC, AR at time T4 Memory, PC after execution
20 0 BSA 135 20 0 BSA 135
PC = 21 Next instruction 21 Next instruction

AR = 135 135 21
136 Subroutine PC = 136 Subroutine

1 BUN 135 1 BUN 135

Memory Memory
 Flowchart of MR Instructions

Memory-reference instruction

AND ADD LDA STA

D0 T 4 D1 T 4 D2 T 4 D 3T 4
DR  M[AR] DR  M[AR] DR  M[AR] M[AR]  AC
SC  0

D0 T 5 D1 T 5 D2 T 5
AC  AC  DR AC  AC + DR AC  DR
SC  0 E  Cout SC  0
SC  0

BUN BSA ISZ

D4 T 4 D5 T 4 D6 T 4
PC  AR M[AR]  PC DR  M[AR]
SC  0 AR  AR + 1

D5 T 5 D6 T 5

PC  AR DR  DR + 1
SC  0
D6 T 6
M[AR]  DR
If (DR = 0)
then (PC  PC + 1)
SC  0
Introduction

MR Instructions

Register Instructions
 Computer Instruction
It is desirable to engineer the computer to support a reasonable Hex Code
Symbol I= 0 I= Description
number of independent instructions AND 0xxx 8xxx And memory word to AC
ADD 1xxx 9xxx Add memory word to AC
 Instruction Code Formats : LDA 2xxx Axxx Load memory word to AC
STA 3xxx Bxxx Store content of AC in memory
 Memory-reference instruction
BUN 4xxx Cxxx Branch unconditionally
 Opcode = 000  110 BSA 5xxx Dxxx Branch and Save return address
ISZ 6xxx Exxx Increment and skip if zero
 I=0 : 0xxx ~ 6xxx, I=1: 8xxx ~Exxx
CLA 7800 Clear AC
CLE 7400 Clear E
I=0 : Direct, 15 14 12 11 0
CMS 7200 Complement AC
I=1 : Indirect I Opcode Address CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
 Register-reference instruction SPA 7010 Skip next instruction if AC pos
 7xxx (7800 ~ 7001) : CLA, CMA, …. SNA 7008 Skip next instruction if AC neg
SZA 7004 Skip next instruction if AC zer
15 14 12 11 0 SZE 7002 Skip next instruction if E is 0
0 1 1 1 Register Operation HLT 7001 Halt computer
INP F800 Input character to AC
OUT F400 Output character from AC
SKI F200 Skip on input flag
 Input-Output instruction SKO F100 Skip on output flag
ION F080 Interrupt On
 Fxxx(F800 ~ F040) : INP, OUT, ION, SKI, ….
IOF F040 Interrupt Off
15 14 12 11 0

1 1 1 1 I/O Operation
 REGISTER REFERENCE
15 14 12 11 0 INSTRUCTIONS
IR 0 1 1 1 Reg. operation control bits

Register Reference Instructions are identified when

- D7 = 1, I = 0
- Register Ref. Instr. is specified in b0 ~ b11 ofIR
- Execution starts with timing signal T3
r = D7 IT3 => Register Reference Instruction
Bi = IR(i) , i=0,1,2,...,11
r: SC  0 Clear SC
CLA rB11: AC  0 Clear AC
CLE rB10: E0 Clear E
CMA rB9: AC  AC’ Complement AC
CME rB8: E  E’ Complement E
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0) Circulate right
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15) Circulate left
INC rB5: AC  AC + 1 Increment AC
SPA rB4: if (AC(15) = 0) then (PC  PC+1) Skip if positive
SNA rB3: if (AC(15) = 1) then (PC  PC+1) Skip if negative
SZA rB2: if (AC = 0) then (PC  PC+1) Skip if AC=0
SZE rB1: if (E = 0) then (PC  PC+1) Skip if E=0
HLT rB0: S  0 (S is a start-stop flip-flop) Halt the computer
 Problems
 The content of PC in the basic computer is 3AF (all numbers are in hexadecimal). The

content of AC is 7EC3. The content of memory at address 3AF is 7020.

a. What is the instruction that will be fetched and executed next?

b. Show the binary operation that will be performed in theAC when the instruction is executed.
 MR Instructions
S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
List the sequence of microoperations for fetching, Write Read
AR 1

decoding and executing the following memory LD INR CLR

PC 2

LD INR CLR
reference instruction.
DR 3

LD INR CLR
Opcode Symbolic designation
E
D0 M[EA]  (AC’ ∧ M[EA]’)’ ALU AC 4

LD INR CLR

INPR
IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus
 Summary

 Mano’s instruction set consists of 25 instructions:

Instruction

OpCode (0-6) OpCode (7)

Direct (I=0) Indirect (I=1) Direct (I=0) Indirect (I=1)

4 bit code 4 bit code 16 bit code 16 bit code
7800 CLA F800 INP
0 AND 8 AND
7400 CLE F400 OUT
1 ADD 9 ADD
7200 CMA F200 SKI
2 LDA A LDA
7100 CME F100 SKO
3 STA B STA
7080 CIR F080 ION
4 BUN C BUN
5 BSA D BSA 7040 CIL F040 IOF
7020 INC
6 ISZ E ISZ
7010 SPA
7008 SNA
7004 SZA 6
7
7002 SZE
12
7001 HLT
Thank you