Computer Architecture

VHDL Basics
What is VHDL
▪ VHDL stands for VHSIC Hardware Description Language.

▪ VHSIC is an abbreviation for Very High Speed Integrated Circuits.

▪ It is a hardware description language describes the behavior of electronic circuits or systems, from which the
physical circuit or system can then be implemented.
VHDL Units
▪ A standalone piece of VHDL code is composed of at least three fundamental sections:
1. LIBRARY declarations: Contains a list of all libraries to be used in the design.
2. ENTITY: Specifies the design interface I/O pins of the circuit.
3. ARCHITECTURE: Contains the VHDL code to describe design, which describes how the circuit should
behave (function).
▪ The code may contain the following sections as well:
1. Configuration:
2. Package Declaration:
3. Package Body:
Library Declaration
▪ To declare a LIBRARY, two lines of code are needed:
▪ The name of the library.
▪ A use clause to declare packages within the library.
▪ Each package contains many functions.
Entity
• An ENTITY is a list with specifications of all input and output pins (PORTS) of the circuit.

• An entity may have more than one architecture.

• Used architecture are defined using the configuration section of the design.
Architecture
▪ The ARCHITECTURE is a description of how the circuit should behave (function).

▪ An architecture has two parts:

▪ A declarative part (optional): where signals and constants (among others) are declared.

▪ A code part (from BEGIN down).

VHDL Properties
• Case Sensitivity: VHDL is not case sensitive.

• White Space: VHDL is not sensitive to white space (Spaces and tabs).

• Comments in VHDL begin with “--” two consecutive dashes.

Switches and LEDs

Switch 0 LED 0

Circuit

Switch 1 LED 1
Switches and LEDs
library IEEE; architecture Behavioral of switches_LEDs is
use IEEE.STD_LOGIC_1164.ALL; begin

entity switches_LEDs is led1 <= switch1;

port ( led2 <= switch2;
switch1 : in std_logic; end Behavioral;

switch2 : in std_logic;
led1 : out std_logic;
led2 : out std_logic);
end switches_LEDs;
Switches and LEDs
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity my_and is
port( a : in std_logic; A
b : in std_logic; C
c : out std_logic); B
end my_and;
architecture Behavioral of my_and is
begin
c <= a and b;
end Behavioral;
Computer Architecture
Entities and Architecture Modes
Entity – Port Modes and Data Types
▪ There are four modes used for an entity port:
▪ IN.

▪ OUT.

▪ INOUT.

▪ BUFFER.

▪ There are Three Data Types:

▪ Boolean: Takes either TRUE or FALSE.

▪ BIT: Takes either 0 or 1.

▪ STD_LOGIC: takes one of 9 different values.

STD_LOGIC
▪ A STD_LOGIC values are:
▪ ‘U’: Uninitialized.
▪ ‘X’: Unknown.
▪ ‘0’: Logic 0.
▪ ‘1’: Logic 1.
▪ ‘Z’: High Impedance.
▪ ‘W’: Unknown.
▪ ‘L’: Low Logic 0.
▪ ‘H’: High Logic 1.
▪ ‘-’: Don’t care.
Architecture - Modeling
▪ Statement written in architecture are concurrent statements.

▪ Architecture modeling are:

▪ Data Flow
▪ Structure
▪ Behavior

▪ In an Architecture all modeling could be used to construct a complete design.

Data Flow Modeling
Behavioral Modeling
Structural Modeling
Half Adder – Main Entity and Architecture
Half Adder – XOR Entity and Architecture
Half Adder – AND Entity and Architecture
Computer Architecture
Signals and Concurrent Statements
Signals
▪ Signals are wires connecting devices inside a design (Circuit) or Entity.

a
X temp
c
Y d O
b
Z
Concurrent Statements
▪ Concurrent means in parallel or at the same time.

X = X+Y; X <= X+Y;

X Y

X Y

+
+
X

Software Hardware
When-Else Statement
C
2:1 MUX
B

Assign_B 2:1 MUX Z

A

Assign_A

Priority Logic
With-Select Statement

A
B
4:1 MUX Z
C
D

Control_0

Control_1

Parallel Logic
Computer Architecture
Process and Sequential Statements
Processes
▪ Processes execute concurrently while statements within it are executed sequentially.
▪ Processes are the only concurrent statements that is used to describe sequential circuit (Registers and
Latches).
Process
▪ Sensitivity list contain signals that affect the process.
▪ Either sensitivity list or wait statements could be used.
▪ Whenever a signal in the sensitive list changes the process is executed
Process
▪ Process Types:
▪ Combinatorial.
▪ Clocked.
▪ Combinatorial Process:
▪ Sequential Statements does not always produce sequential logic.

A
B X
C
Process
▪ Clocked Process:
▪ Clocked process is used to generate synchronous logic)

D FLIP Q
CLK FLOP

Y
Z FLIP FLIP X
FLOP FLOP
CLK CLK
If Statement
• If statement evaluate conditions in order.
• Nested if statements could be used.
• Avoid many levels of If statements to reduce the logical delay.
If Statement

D 2:1
C MUX

𝑺𝟎 2:1
B MUX

𝑺𝟏 2:1
A MUX

𝑺𝟐
Case Statement
▪ In Case-Select all options must be covered.
▪ Avoid Overlap by covering each choice only one time.
▪ Null Statement could be used.
▪ When are checked concurrently, while statements are executed sequentially.
Case Statement

A
B
4:1 MUX y
C
D

Select_0

Select_1

Parallel Logic