2a1

LIBRARY ieee;
USE ieee.std_logic_1164.all ;
Wo W1
ENTITY mux2to1 IS PORT ( w0, w1,S
: IN
: OUT STD_LOGIC ) ;
END mux2to1 ;
f
S
ARCHITECTURE Behavior OF mux2to1 IS BEGIN
;
WITH S SELECT
f<= w0 WHEN ‘0’,
w1 WHEN OTHERS;

END Behavior

Multiplexor de 4 a 1
library IEEE;
use IEEE.std_logic_1164.all;

entity mux4to1 is
port (
y : out std_logic;
sel1, sel0, x3, x2, x1, x0 : in std_logic
);
end entity;

architecture arch of mux4to1 is.

signal auxSelVect : std_logic_vector (1 downto 0);

begin

auxSelVect(1) <= sel1;

auxSelVect(0) <= sel0;

y <= x0 when auxSelVect = "00" else

x1 when auxSelVect = "01" else
x2 when auxSelVect = "10" else
x3 when auxSelVect = "11" else
'U';

end architecture;
Multiplexor 8 a 1
library IEEE;

use IEEE.std_logic_1164.all;

entity mux is

port (sel : in std_logic_vector(2 downto 0);

A,B,C,D,E,F,G,H, enable: in std_logic;

Y : out std_logic);

end mux;

architecture mux8 of mux is

begin

if (enable==0)

then

begin

process (sel, A,B,C,D,E,F,G,H)

begin

case sel is

when “000” => Y <=A;

when “001” => Y <=B;

when “010” => Y <=C;

when “011” => Y <=D;

when “100” => Y <=E;

when “101” => Y <=F;

when “110” => Y <=G;

when “111” => Y <=H;

when others => Y <=A;$

end case;

end process;

else

Y <=0;

end if;

end mux8;