Xavier University - Ateneo de Cagayan

College of Engineering
Electronics and Communications Department

In partial fulfillment of
ECE 18 Digital Electronics 1 Final Project
Technical Report

A Logic Circuit Design and Switching Theory Application

Automatic Start-Stop SmartPhone Timer-Charger

with an Integrated Alarm Reminder

RENIER JANE GAID

Engr. Mary Jane Apor

Digital Electronics 1 ECE 18D Professor

December 2022
 TABLE OF CONTENTS
Pages

I. Introduction 1 - 10
● Background/Motivation of the Design
● Real Scenario for the Application
● Problem/Need
● Technical Narratives of the Purpose
● Functionality of the Logic Circuit
● Presentation of Input and Output Variables
● Description of the Input Conditions
● Design Flowchart

II. Design Procedures 11 - 16

● Logic Circuit Truth Table
● Boolean Expressions of the Output Variables

III. Implementation 17 - 23
● Different Circuit Implementations
of the Logic Circuit
● Simulations of Different Circuit
Implementations
● Best and Appropriate Design for
for Implementation

IV. Algorithms and Codes of the Design 24 - 26

V. Analyses of the Constructed Circuit Design 27 - 30

● Components of the Logic Circuit Design
● Verilog Simulation Outputs
● FPGA Virtual Lab Simulation Results
VI. Conclusion and Recommendations 31 - 32
● Conclusion
● Recommendation
(Future Applications)

VII. List of References

 INTRODUCTION

1. Background/Motivation of the Design

Recently, there is a focus on the realm of smartphones that is

undeniably one of the most commonly used devices of today’s generation.
Current phone charging systems are one of the primary concerns of people
who use it on daily basis and this includes people leaving for work or school
without smartphone devices and having left it connected to chargers
unplugged at home. Moreover, even though mobile phones may not blast
while charging and using it simultaneously, it has some adverse effects on the
phone and the battery. Obstructing charging process, and overheating of the
battery which leads to fire hazard are just some of these unpleasant effects.

Today, together with the high demands on smartphones and smart

devices are the developments of phone chargers. Timer-chargers and smart
chargers already exist in the market but is limited with specific and separate
functions. For most timer-chargers today, its specific function is to
automatically charge a drained phone battery for approx. 5-6 hours daily only
and not more than that without overcharging the battery (Bhatt, 2022).
Consecutively, an “intelligent/smart charger” is a charger that can only
respond to the condition of a battery, and modify its charging actions
accordingly together with monitoring the battery’s voltage and temperature.
However, these existing chargers do not work as how the present generation
needs it. The need for chargers that are smarter as to how other smart
devices works, need for chargers with an integrated alarm reminder for better
person-device communication where it can generate a message regarding the
current status of charging while sensing activities during the process of
charging, and knows when to stop charging in accordance to battery power,
time and other conditions weren’t addressed by these present charger
systems. According to GenZ Statistics (2022), the present generation
(Generation Z) both considered the busiest generation and the future of
today’s industries compromise 45% of the total population in the country
(Philippines), and 26% of the total world population today – who were also the
people who mostly need Automatic Start-Stop SmartPhone Timer-Charger with
an Integrated Alarm Reminder to make their work and school lives easier.

The researcher designed Automatic Start-Stop SmartPhone

Timer-Charger with an Integrated Alarm Reminder to address simple scenarios
of missing to unplug charging phones before leaving home due to a
pre-occupied mind of work and school, ensure optimum life span of
smartphone batteries and user-safety which are both at heavy risk due to
charging and external usage of phone simultaneously, to develop a charger
that makes use of the time system and intelligence of chargers through
integrating message-generation (that is acted out by an electronic reminder)
with modified and specific input variables, and to design a flexible timer
system wherein users can charge smartphone batteries in a specific time
interval they wish to. The Automatic Start-Stop SmartPhone Timer-Charger
with an Integrated Alarm Reminder is a logic circuit and a switching theory
application where certain combinations of input conditions are essential to
generate the desired output that the researcher finds significant to attain
purpose of the design.
2. Real Scenario for the Application

Communication has become one of the basic needs of the people. One
of the typical ways to get in touch with other is through widely used
smartphones. Based on a lot of experiences, the battery life of a smartphone
is the primary concern when it comes to the limit on its usage. Thus,
oftentimes even simple scenarios where an essential communication device
(mobile phone) are left charging at home most especially when in rush.
Circumstances wherein charging phones are played by the young members of
the family while charging without the adults knowing. Such circumstance is
an example of an external activity done on the phone while charging which
was considered as a primary cause of overheating of smartphone batteries
that eventually will damage the battery itself, shortening its battery health and
capacity to function efficiently (Jabin, 2022). Worst-case scenarios causes
too much and continuous heating of a Li-ion smartphone batteries leads to
fire hazards which is harmful to young users of this generation. Li-ion
smartphone batteries have a tendency to overheat, and can be damaged at
high voltages which can lead to thermal runaway and combustion causing fire
hazards (Clean Energy Institute, 2020).

The Automatic Start-Stop Phone Timer-Charger with an Integrated Alarm

Reminder is the solution that the researcher proposed and studied in order to
address multiple concerns and limitations of existing charger system and
charging processes.
3. Problem/Need

Despite the existence of recent phone chargers, it failed to address the

need for developing current charger systems that is highly efficient and of
great help to the generation today, to prioritize the user’s safety (most likely
occur to minor phone users), and neglected the adverse effects of external
activities (e.g. playing, and watching videos) while charging that primarily
causes overheating phone batteries and eventually leads to battery damage
due to the nature of Li-ion batteries and other risks to the phone system and
to the user.

Existing charger systems need development in terms of its operation

and working principle through logic circuits and switching principles and
application in order to aid the limitations and lacking features necessary for
users in this generation.

4. Technical Narratives of the Purpose

A charger is an accessory that connects to widely used smartphone

devices when your battery is low on power. Devices powered by rechargeable
or internal batteries require a charger to operate that battery. Usability,
convenience, user-safety, smart function, and battery optimization are
interconnected concerns of current charging battery systems.

The primary purpose of the Automatic Start-Stop Phone Timer-Charger

with an Integrated Alarm Reminder is to show the interconnectedness of these
concerns through designing a one (1) charger that addresses all of it through
logic circuit and switching applications. Moreover, the design aims to benefit
many people who consider smart mobile phones as important aspects of
their lives especifically the increasing population of the present generation for
 convenience, safety, and more. With this proposed solution, users can
conveniently charge their phone’s battery whenever even when they only want
to charge it in a specific time interval (e.g. 10 mins, etc.) and still not miss it
out on their way out of their homes, offices, and elsewhere. Also, through its
start-stop charging feature, the charger will be able to determine when to stop
and start charging and detect simultaneous charging and external usage of
the charging phone and acts on it to prevent further identifies risks.

5. Functionality of Logic Circuit

The logic circuit design of an Automatic Start-Stop Phone

Timer-Charger with an Integrated Alarm Reminder consists of three (3) input
variable that causes the two (2) outputs to change logic state, turns ON/OFF,
and stops/starts its function.

The Automatic Start-Stop Phone Timer-Charger with an Integrated Alarm

Reminder works with the following conditions:

a. The alarm reminder generates message (ON) to the user when

either P(in) is greater than OR equal to P(peak) AND when an
external activity (playing games, watching videos) is detected
while the phone is charging OR when T(charging) is greater than
or equal to T(set) by the user.

b. The Automatic Start-Stop Phone Timer-Charger automatically

stops charging only when either P(in) is greater than OR equal to
P(peak) AND an external activity (playing games, watching
videos) is detected while the phone is charging OR P(in) is
greater than OR equal to P(peak) AND T(charging) is greater
than or equal to T(set) by the user.
6. Presentation of the Input and Output Variables of the Logic Circuit Design

Fig. 1.3. Logic Circuit Design Block Diagram

The Automatic Start-Stop Phone Timer-Charger with an Integrated Alarm

Reminder has the following Input and Output Variables:

Input Variables of the Logic Circuit Design

● Phone Battery Power Percentage Difference (A)

0 - Power Percentage below 80%
1 - Power Percentage above or equal to 80%

● Time Set on the Timer (B)

0 - t(set) < t (charged) | time set is less than the time phone
battery is charged
1 - t(set) ≥ t (charged) | time set is greater than or equal to time
phone battery is charged
● External Activity in simultaneous with Charging (C)
0 - phone at rest while charging
1 - phone in use while charging

Output Variables of the Logic Circuit Design

● Alarm Reminder Generates Message to User (Y)

0 - OFF means that the user does not need to do necessary
 action on the charging phone
1 - ON means that the user is notified that something needs to
be done on the charging phone

● Start-Stop Charging (Z)

0 - stops charging
1 - starts/ continues charging

7. Description of the Input Conditions

The following input variables are the necessary conditions to generate

the necessary output that is expected from the device designed by the
researcher. The outputs of the Automatic Start-Stop Phone Timer-Charger with
an Integrated Alarm Reminder depends on the combination of the input
conditions defined as follows:

Input Condition A

Input condition/variable A is defined as the power percentage

difference of the input power percentage (𝑃𝑖𝑛) of the smartphone during

𝑡𝑑𝑖𝑓𝑓𝑒𝑟𝑒𝑛𝑐𝑒 = 𝑡𝑠𝑒𝑡 (before the actual charging started) and the peak power

percentage (𝑃𝑝𝑒𝑎𝑘) which is 80% (considered battery percentage to maintain

an optimized battery).

Input variable A is logic low (0) when 𝑃𝑖𝑛 < 𝑃𝑝𝑒𝑎𝑘.

On the other hand, Input A is logic high (1) when 𝑃𝑖𝑛 ≥ 𝑃𝑝𝑒𝑎𝑘.

A single-bit comparator is a combinational comparator logic circuit

used to compare 2 inputs. Thus, the researcher used a 1-bit magnitude
comparator in order to achieve the desired function/working of Input A and be
able to compare 𝑃𝑖𝑛 and 𝑃𝑝𝑒𝑎𝑘. The truth table of Comparator of Input A is

shown in Fig. 1.4 below.

𝑃𝑖𝑛 𝑃𝑝𝑒𝑎𝑘 𝑃𝑖𝑛 < 𝑃𝑝𝑒𝑎𝑘 𝑃𝑖𝑛 = 𝑃𝑝𝑒𝑎𝑘 𝑃𝑖𝑛 > 𝑃𝑝𝑒𝑎𝑘

0 0 0 1 0

0 1 1 0 0

1 0 0 0 1

1 1 0 1 0
Fig. 1.4. 1-bit magnitude Comparator of Input A

Since, Input Condition A is logic high only when Pin = Ppeak OR Pin >
Ppeak, the Boolean Equation for Input Condition A is generated through
Sum-of-Products Method below:

A = (Pin)(Ppeak) + (Pin’)(Ppeak’) + (Pin)(Ppeak’) Unsimplified Equation

A = (Pin ⊙ Ppeak) + (Pin)(Ppeak’) Use of Exclusive NOR

Input Condition B

Input condition/variable B is defined as the time difference between the

time the phone is charging (𝑡𝑐ℎ𝑎𝑟𝑔𝑖𝑛𝑔) and the time set by the user (𝑡𝑠𝑒𝑡)

Input variable B is logic low (0) when 𝑡𝑐ℎ𝑎𝑟𝑔𝑖𝑛𝑔 < 𝑡𝑠𝑒𝑡.

On the other hand, Input B is logic high (1) when 𝑡𝑐ℎ𝑎𝑟𝑔𝑖𝑛𝑔 ≥ 𝑡𝑠𝑒𝑡.

A single-bit comparator is a combinational comparator logic circuit

used to compare 2 inputs. The same manner with Input Variable A, a 1-bit
magnitude comparator is necessary in order to achieve the desired
function/working of Input B and be able to compare 𝑡𝑐ℎ𝑎𝑟𝑔𝑖𝑛𝑔 and 𝑡𝑠𝑒𝑡. The truth

table of Comparator of Input B is shown in Fig. 1.5 below.

𝑡𝑐ℎ𝑎𝑟𝑔𝑖𝑛𝑔 𝑡𝑠𝑒𝑡 𝑡𝑐ℎ𝑎𝑟𝑔𝑖𝑛𝑔 < 𝑡𝑠𝑒𝑡 𝑡𝑐ℎ𝑎𝑟𝑔𝑖𝑛𝑔 = 𝑡𝑠𝑒𝑡 𝑡𝑐ℎ𝑎𝑟𝑔𝑖𝑛𝑔 > 𝑡𝑠𝑒𝑡

0 0 0 1 0

0 1 1 0 0

1 0 0 0 1

1 1 0 1 0
Fig. 1.5. 1-bit magnitude Comparator of Input B

Since, Input Condition B is logic high only when t charging = t set OR

t set > t charging, the Boolean Equation for Input Condition B is generated
through Sum-of-Products Method below:

B = (tcharging)(tset) + (tcharging’)(tset’) + (tcharging)(tset’)

Unsimplified Equation

B = (tcharging ⊙ tset) + (tcharging)(tset’)

Use of Exclusive NOR

Input Condition C

Input Condition C is defined as the detector/sensor of the external

activity done in simultaneous while the smartphone is charging.

Input variable C is logic low (0) when no external activity is sensed

while charging or the phone is at rest.
 On the other hand, Input C is logic high (1) when an external activity
(playing games, watching videos, etc.) is sensed while the
smartphone is charging.

8. Logic Circuit Design Flowchart

The figure below describes the flowchart of the design which is the
primary source of determining the logic state of the outputs in response to the
different combination of the three (3) input conditions.

Fig. 1.4. Flowchart of the Functionality and Working of the Design

 DESIGN PROCEDURES

1. Logic Circuit Function/Truth Table

This chapter consists of two (2) specific tables: a general

characteristic table of the Input and Output Variables, and a function table
generated by the primary inputs (Pin, Ppeak, t charging, and t set) together
with Input Variable C driving outputs Y and Z.

Table 2.1.1 is the characteristic table of the three (3) input variables
(power percentage difference, time difference, and external activity done in
simultaneous while charging) that generates the two (2) outputs (Alarm
Reminder Generates Message to User, and Start-Stop Charging) of the design.

Inputs Outputs

A B C Y Z

0 0 0 0 0

0 0 1 0 0

0 1 0 1 0

0 1 1 1 0

1 0 0 0 0

1 0 1 1 1

1 1 0 1 1

1 1 1 1 1

Table 2.1.1. A general characteristic table of the Input and Output Variables
 Table 2.1.2 is the design function table that considers the primary
inputs (Pin, Ppeak, t charging, and t set) that generate the function of Input
Conditions A and B together with Input Condition C. It also consists of two (2)
outputs: Alarm Reminder Generates Message to User (Y), and Start-Stop
Charging (Z).

Input Conditions/Variables Outputs

𝑃𝑖𝑛 𝑃𝑝𝑒𝑎𝑘 𝑡𝑐ℎ𝑎𝑟𝑔𝑖𝑛𝑔 𝑡𝑠𝑒𝑡 C Y Z

0 0 0 0 0 1 1

0 0 0 0 1 1 1

0 0 0 1 0 0 0

0 0 0 1 1 1 1

0 0 1 0 0 0 0

0 0 1 0 1 1 1

0 0 1 1 0 1 1

0 0 1 1 1 1 1

0 1 0 0 0 1 0

0 1 0 0 1 1 0

0 1 0 1 0 0 0

0 1 0 1 1 0 0

0 1 1 0 0 1 0

0 1 1 0 1 1 0

0 1 1 1 0 1 0

0 1 1 1 1 1 0

1 0 0 0 0 1 1

1 0 0 0 1 1 1

1 0 0 1 0 0 0
1 0 0 1 1 1 1

1 0 1 0 0 1 1

1 0 1 0 1 1 1

1 0 1 1 0 1 1

1 0 1 1 1 1 1

1 1 0 0 0 1 1

1 1 0 0 1 1 1

1 1 0 1 0 0 0

1 1 0 1 1 1 1

1 1 1 0 0 1 1

1 1 1 0 1 1 1

1 1 1 1 0 1 1

1 1 1 1 1 1 1

Table 2.1.2. A Function Table of the Logic Circuit Design

with Primary Inputs (Pin, Ppeak, t charging, and t set).
2. Boolean Expressions of the Output Variables

The researcher used Karnaugh Map to simplify the General Truth Table
of the Input and Output Variables (depicted in Table 2.1.1) and generate its
boolean expression.

Karnaugh Map Method of Simplification

Step 1: Input Combinations with Y=1 output is reflected into a
3
2 Karnaugh Map A. While Input Combinations with Z=1 output
is reflected into Karnaugh Map B.

Inputs Outputs

A B C Y Z

0 0 0 0 0

0 0 1 0 0

0 1 0 1 0

0 1 1 1 0

1 0 0 0 0

1 0 1 1 1

1 1 0 1 1

1 1 1 1 1
Step 2: Reflect the Primary Inputs (Pin, Ppeak, t charging, and t set)
which generates the Input Variables A and B in the Boolean
Expression from the K-Map.
For Output Variable Y:

Since, A = (Pin ⊙ Ppeak) + (Pin)(Ppeak’) and;

B = (tcharging ⊙ tset) + (tcharging)(tset’)

Y = AC + B
Y = ((Pin ⊙ Ppeak) + (Pin)(Ppeak’))C +
(tcharging ⊙ tset) + (tcharging)(tset’)

Z = AB + AC
Z = ((Pin ⊙ Ppeak) + (Pin)(Ppeak’))
((tcharging ⊙ tset) + (tcharging)(tset’)) +
((Pin ⊙ Ppeak) + (Pin)(Ppeak’))C
Step 3: Boolean Expressions of Table 2.1.1 and Table 2.1.2

For Table 2.1.1 Y = AC + B

Z = AB +AC

For Table 2.1.2 Y = ((Pin ⊙ Ppeak) + (Pin)(Ppeak’))C +

(tcharging ⊙ tset) + (tcharging)(tset’)

Z = ((Pin ⊙ Ppeak) + (Pin)(Ppeak’))

((tcharging ⊙ tset) + (tcharging)(tset’)) +
((Pin ⊙ Ppeak) + (Pin)(Ppeak’))C
 IMPLEMENTATIONS

1. Different Circuit Implementation of the Design

The researcher implemented the Function/Characteristic Table in three

(3) different implementations specifically, AND-OR-NOT Implementation, Use
of Exclusive-NOR Gate Implementation, and Implementation through
Equivalent NOR and NAND Gates.
The researcher used Quartus II 13.01sp to model the implementations
of the design.

1.1. Implementation using AND-OR-NOT Gates

Fig. 3.1.1 Implementation using AND-NOT-OR Gates

1.1.2 Implementation using Exclusive-NOR Gates

Fig. 3.1.2. Implementation using Exclusive-NOR Gates

1.1.3 Implementation using Equivalent NOR and NAND Gates

Fig. 3.1.3. Implementation using Equivalent NAND and NOR Gates

2. Simulation of the Different Circuit Implementations

The researcher used Quartus II and Modelsim Software to simulate the

Schematic Diagram Designs generated together with the design Verilog HDL
codes.

2.1.1. Simulation of Implementation using AND-NOT-OR Gates

Fig. 3.2.1. Successful Flow Summary and Compilation Report 1

Fig. 3.2.2 Verilog HDL of Implementation 1

2.1.2. Simulation of Implementation using Exclusive-NOR Gates

Fig. 3.2.3. Successful Flow Summary and Compilation Report 2

Fig. 3.2.4. Verilog HDL of Implementation 2

2.1.3. Simulation of Implementation using Equivalent NAND and NOR Gates

Fig. 3.2.5. Successful Flow Summary and Compilation Report 3

Fig. 3.2.6 Verilog HDL of Implementation 3

3. Best and Appropriate Design for Implementation

Fig. 3.3. Best and Appropriate Circuit Design for Implementation

The researcher implemented the Logic Circuit Design of the Automatic

Start-Stop SmartPhone Timer-Charger with an Integrated Alarm Reminder to
different circuit implementations to fundamentally use different logic gates
which is part of the application when designing a circuit.

In real-life scenarios, the availability of logic gates Integrated circuits

(IC’s) are not always available, which makes knowledge on equivalent gates
and exclusive logic gates important. Logic Circuit and Switching Theory
Application enable engineers implement a design in multiple ways depending
on its need.

The researcher designed the Automatic Start-Stop SmartPhone

Timer-Charger with an Integrated Alarm Reminder through using combination
of AND, OR, and NOT gates which are the basic fundamental gates of Logic
Circuits. Also, the researcher makes use of Exclusive-NOR gates to simplify
the design. Equivalent NAND and NOR gates are also implemented in the
design of the circuit to showcase how the design still doable with only to
equivalent gates. However, in the field of digital electronics, faster transfer of
information is important from one gate to the other to generate an output
faster than other unsimplified designs. Thus, the more gates are used, the
more complicated the internal logic circuit of a device, the slower it generates
the output. Thus, the researcher finds the simplified circuit design
implementation using Exclusive-NOR gate as the most efficient, fewer wirings,
and has the the least number of gates used to generate the output compare to
the other two (2) implementations which were elaborately depicted in Figures
3.1.1, 3.1.2, and 3.1.3.
 ALGORITHMS AND CODES OF THE LOGIC DESIGN

The following are the design’s verilog hdl codes and algorithms are generated
from Quartus II 13.01sp used to program FPGA Cyclone V devices.

// Copyright (C) 1991-2013 Altera Corporation

// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.

// PROGRAM "Quartus II 64-Bit"

// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web
Edition"
// CREATED "Sat Dec 10 17:03:35 2022"

module \00_rawfinal (
Pin1,
Ppeak2,
Tcharging3,
Tset4,
C5,
Y6,
Z7
);

input wire Pin1;

input wire Ppeak2;
input wire Tcharging3;
input wire Tset4;
input wire C5;
output wire Y6;
output wire Z7;

wire SYNTHESIZED_WIRE_14;
wire SYNTHESIZED_WIRE_15;
wire SYNTHESIZED_WIRE_5;
wire SYNTHESIZED_WIRE_6;
wire SYNTHESIZED_WIRE_7;
wire SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_9;
wire SYNTHESIZED_WIRE_10;
wire SYNTHESIZED_WIRE_11;
wire SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_13;

assignSYNTHESIZED_WIRE_11 = Pin1 ~^ Ppeak2;

assignSYNTHESIZED_WIRE_13 = Tcharging3 ~^ Tset4;

assignSYNTHESIZED_WIRE_5 = SYNTHESIZED_WIRE_14 & C5;

assignSYNTHESIZED_WIRE_7 = SYNTHESIZED_WIRE_14 & SYNTHESIZED_WIRE_15;

assignSYNTHESIZED_WIRE_6 = SYNTHESIZED_WIRE_14 & C5;

assignY6 = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_5;

assignZ7 = SYNTHESIZED_WIRE_6 | SYNTHESIZED_WIRE_7;

assignSYNTHESIZED_WIRE_8 = ~Ppeak2;

assignSYNTHESIZED_WIRE_9 = ~Tset4;

assignSYNTHESIZED_WIRE_10 = Pin1 & SYNTHESIZED_WIRE_8;

assignSYNTHESIZED_WIRE_12 = Tcharging3 & SYNTHESIZED_WIRE_9;

assignSYNTHESIZED_WIRE_14 = SYNTHESIZED_WIRE_10 | SYNTHESIZED_WIRE_11;

assignSYNTHESIZED_WIRE_15 = SYNTHESIZED_WIRE_12 | SYNTHESIZED_WIRE_13;

endmodule
 ANALYSES OF THE CONSTRUCTED LOGIC CIRCUIT DESIGN

1. Logic Circuit Components Introduction

The researcher designed the logic circuit of the Automatic Start-Stop

SmartPhone Timer-Charger with an Integrated Alarm Reminder with the use of
the generated Boolean Equation in design procedure of the device and
implementing Exclusive-NOR Gates to further simplify the logic circuit design
and reduce the number of gates used. The logic circuit design is composed of
two (2) Comparator Circuits for Input Variables A and B and the circuit
generated from the truth table.

COMPARATOR A

COMPARATOR B

Y and Z Logic Circuit

 The Automatic Start-Stop SmartPhone Timer-Charger with an Integrated
Alarm Reminder as a device works with external circuits wherein power
source, timer circuit, message generation circuit, voltage and current sensors
for the power difference circuit, charger circuit, external activity sensor circuit,
and converters from AC supply if designed as wall chargers further in the
future studies.

2. Verilog Simulation Outputs in ModelSim Software

The following figures depicts the verilog simulation outputs generated

by MultiSim software. Figures 4.2.1 depicts the output of the Automatic
Start-Stop Phone Timer-Charger with an Integrated Alarm Reminder Logic
Circuit designed by the researcher in Quartus II.

Fig. 4.2.1 Verilog Simulation Output

Fig. 4.2.2 Verilog Simulation Output Continuation
3. FPGA Virtual Lab Simulation Outputs

FPGA Virtual Lab of Labsland under Intel is one of the recent

innovation of Intel in order to be able to surpass the limit of learning FPGA’s
and Coding through the Virtual FPGA that functions the same like the physical
FPGA’s. Intel is confident about the performance of this Virtual Laboratory in
testing verilog and VHDL codes even without FPGA’s at hand.

The researcher maximizes the use of this virtual laboratory amidst the
limitation of not having enough time and an FPGA at hand. Compilation
results are documented below.

FPGA Virtual Lab by Labsland, Intel

 CONCLUSION AND RECOMMENDATIONS

Conclusion

The Automatic Start-Stop SmartPhone Timer-Charger with an Integrated Alarm

Reminder focuses on designing a charger system that integrates the need of
applying intelligence, efficient timer-circuitry, generation of message to the user
through and alarm reminder and starts-stop charging efficiently while taking into
account the risks and hazards to the user caused by one (1) input variable which is
the sensor of an external activity done while charging.

The researcher makes use of Logic Circuit and Switching Theory Applications
to generate the outputs of this design. Logic Circuit and Switching Theory
Applications of Digital Electronics are used sufficiently to give solution to the existing
problem/need for development of current charging systems today. The logic circuit
design process of Automatic Start-Stop SmartPhone Timer-Charger with an Integrated
Alarm Reminder is well-represented through the Design Flowchart that generates the
output of the three (3) input conditions of the device. The function/characteristic
Table 2.1.2 shows clear relationship of the input combinations towards the
generation of the outputs of the circuit. Furthermore, the analysis of the design from
the schematic formulated with the Boolean Expression through Karnaugh Map
Method, shows series of successful compilations and simulations through Quartus II
and ModelSim output results. The verilog hdl output of the design shows the
compatibility of the verilog hdl codes necessary to program the FPGA Cyclone V
device and the truth table in the first part of the design process which identifies the
successful generation of verilog file of the design.

The output of the design were represented through LED (ON/OFF) activation
and does the working/functionatlity expected from the design/device.
Recommendations

Amidst the efforts of the researcher into further developing and improving the
design in the process, the Automatic Start-Stop Phone Timer-Charger with an
Integrated Alarm Reminder design still has a lot to improve and develop in terms of
the fundamentals most especially in studyingthoroghly the different charging
processes of various charging systems, how each of it are designed and how they
best works in terms of providing good power, and fast current to the charging battery
while preserving the battery health and condition. Furthermore, the researcher
recommends the analyzation of the results both virtually in Virtual Laboratories and
also through programming the design in physical FPGA’s.

The logic circuit design of Automatic Start-Stop Phone Timer-Charger with an

Integrated Alarm Reminder is only part of the entire charging system design. Thus,
the researcher finds it essential to have great knowledge and further research about
the external circuits of the design in order to work and function for the
objective/purpose of it which is to prioritize user-safety, convenience and reliability
of charger systems.

Hence, whatever the researcher missed to include in this paper and all the
limitations experienced by the researcher from enough time of physical FPGA
programming of the design are recommended as an essential primary step in the
continuation and improvement of the design.

Future Application of the Automatic Start-Stop Phone Timer-Charger with an

Integrated Alarm Reminder Logic Circuit Design

The researcher also uses studies of current charging systems and how it is
focused by most of the researchers is a potential aspect for development for future
needs. Whereas, the working and functionality of the circuit is also potential
application for other digital electronics application in the future.
List of References

Charging while using phone - is it really bad? Tech News Today. (2022, October 11).
Retrieved December 7, 2022, from
https://www.technewstoday.com/is-charging-while-using-phone-bad/

Gen Z statistics 2022: How many people are in gen Z? EarthWeb. (2022, November
25). Retrieved December 9, 2022, from https://earthweb.com/gen-z-statistics/

Belov, Dmitry & Yang, Mo-Hua. (2008). Failure mechanism of Li-ion battery at
overcharge conditions. Journal of Solid State Electrochemistry. 12. 885-894.
10.1007/s10008-007-0449-3.

Lithium-Ion Battery. Clean Energy Institute. (2020, September 25). Retrieved

December 9, 2022, from http://www.cei.washington.edu/education/science-
of-solar/battery-technology/