Q.Consider a 32-bit microprocessor that has an on- chip 16-kB four-way set- associative cache.

Assume that the cache has a line size of four words.  The 2048-MB main memory is byte
addressable.

i. Show the format of main memory addresses. (2.5-Marks)

ii. Where in the cache is the word from memory location 66BB01A6 mapped, show the
Tag, set and word values in hexadecimal format using the format of part (i). (2.5-
Marks)

Solution:
Part(a)
Size of Cache=16KB  w=24*210
Set Size=4
Block size=Line Size=4words  w=22
Size of Main Memory= 2048MB => 211*220 Address length (s+w) =231
Total No. of Lines= Size of Cache/ Line Size  16KB/4 = 4KB
Total No. of Sets= Total No. of Lines/ Set Size  4K/4 = 1K  v= 210
Size of Tag(T)=Address length(s+w)-Total no. of Sets(v)-Block/Line Size(w)
T=(s+w)-v-w  31-10-2  19
19 10 2
Tag Set word
Main Memory Format

Part(b)
Given Address: 66BB01A6
Hex Address 6 6 B B 0 1 A 6
Equivalent Binary 110 0110 1011 1011 0000 0001 1010 0110
Address

According to given Format:0110010101110010000000110100110

MM Format Tag(19-bits) Set(10-bits) Word(2-

bits)
Binary Value 1100110101110110000 0001101001 10
Hex Value 66BB0 069 2

word=2H, Set=069H, Tag=66BB0H

Solution:
Part(a)
Size of Cache=16KB  w=24*210
Set Size=4
Block size=Line Size=4words  w=22
Size of Main Memory= 2048MB => 211*220 Address length (s+w) =231
Total No. of Lines= Size of Cache/ Line Size  16KB/4 = 4KB
Total No. of Sets= Total No. of Lines/ Set Size  4K/4 = 1K  v= 210
Size of Tag(T)=Address length(s+w)-Total no. of Sets(v)-Block/Line Size(w)
T=(s+w)-v-w  31-10-2  19
19 10 2
Tag Set word
Main Memory Format

Part(b)
Given Address: 66BB01A6
Hex Address 6 6 B B 0 1 A 6
Equivalent Binary 110 0110 1011 1011 0000 0001 1010 0110
Address

According to given Format:0110010101110010000000110100110

MM Format Tag(19-bits) Set(10-bits) Word(2-

bits)
Binary Value 1100110101110110000 0001101001 10
Hex Value 66BB0 069 2

word=2H, Set=069H, Tag=66BB0H