PHAROS UNIVERSITY IN ALEXANDRIA

FACULTY OF ENGINEERING
COMPUTER ENGINEERING DEPARTMENT

SEMESTER: FALL SEMESTER FINAL EXAM

COURSE TITLE: ARCHITECTURE LEVEL: FIFTH YEAR
COURSE CODE: EC 313
ACADEMIC YEAR: 2021 – 2022
DATE: 23-1-2022 TIME ALLOWED: 2 HOURS TOTAL MARKS: 50 MARKS
EXAM COMMITTEE: PROF. DR. MAGDY ABDELAZIM DR. HOSSAM ELDIN MOSTAFA
EXAM IS ON 2 (TWO) PAGES.
Problem 1: [14 marks]
a) State the different types of storage memories which are used in computer systems. For
each type state the typical capacity and access time. What is the main difference between
direct mapped cache and set associate cache? Give the analogy with internet browser
cache as discussed in the lectures.

b) Consider a cache with 64 blocks and a block size of 16 bytes. To what block number does
byte address 1700 map in cache? What other byte addresses are mapped to this block
number?

c) Suppose we have a processor with a base CPI of 1, and a clock rate of 4 GHz. Assume a
main memory access time of 100 ns, including all the miss handling. Suppose the
miss rate per instruction at the primary cache is 4%. How much faster will the processor
be if we add a secondary cache that has a 5 ns access time for either a hit or a miss and is
large enough to reduce the miss rate to main memory to 0.5%?

Problem 2: [14 marks]

a) What does MIPS stand for? State at least four reasons for the importance of studying this
processer architecture.

b) Write the MIPS assembly instructions that implements the following C statements
i) int a = 0xC456F90D ii) if (i = = j ) f = g + h; else f = f - 1;

c) Add comments to the following MIPS code and describe in one sentence what it computes.
Assume that $a0 is used for the input and initially contains n and $v0 is used for the output
begin: addi $t0, $zero, 0
addi $t1, $zero, 1
loop: slt $t2, $a0, $t1
bne $t2, $zero, finish
add $t0, $t0, $t1
addi $t1, $t1, 2
j loop
finish: add $v0, $t0, $zero
1
Problem 3: [11 marks]

a) Write a verilog program to implement a 2 to 1 multiplexer using

i) Behavioral approach
ii) Structural approach

b) State the main manufacturers of FPGAs/CPLDs and their IDE tools. State three differences
between FPGAs and CPLDs.

c) Write a Verilog code to implement the 7447 IC which is a BCD to common anode decoder.
The design has four input lines DCBA and seven output lines gfedcba. There is a control
input named Lamp Test “LT” when it has logic 1, all the segments will be ON.

Problem 4: [11 Marks]

a) In your hardware course project, you have implemented a mini system for Xilinx
XC9536XL CPLD chip. Answer the following

i) What are the number of pins and the package of the used CPLD?
iii) What are the names of the programming pins?
iv) What is the supply voltage?
v) How many gates and macrocells in the used CPLD?
vi) How did you design a programmer for this chip (software and hardware)?
vii) How do you generate the binary file that is supplied to the programmer?
viii) Assume a 10MHz clock is applied to the clock pin of the chip, write a Verilog program
to flash a LED connected to one of its pins every 1 second. Comment your program.

b) In your Python software project, you noticed that although the code does extremely
useful tasks, but it executes very slowly. Discuss briefly how computer architecture can be
used to speed up Python programs execution. Also state the ideas you worked on in your
Python course project.