Cellular Automata Based Synthesis of Easily And
Fully Testable FSMs
D. Roy Chowdhury S. Chakraborty
Dept. of Computer Science @ Engg.
Indian Institute of Technology
Kharagpur - 721 302
India
Abstract
This paper reports an application of a special class of
non-group Cellular Automata, referred to as Dl*CA,
as the test machine embeded in the FSM to be syn-
thesised. The state transition properties of Dl*CA are
exploited in designing an easy testing scheme for the
finite state machine. The scheme has been found to
incur a small area overhead while providing extremely
high coverages close to 100 per cent for all single stuck-
at faults in the circuit.
1 Introduction
Design For Testability (DFT) has been proposed as
a solution to reduce test complexity of sequential cir-
cuits by using scan path techniques. However, the
area requirements are prohibitive and with long scan
path chains, the testing time requirement is also quite
high [5]. Partial scan designs [6] have been proposed
as a better alternative , reducing the scan overheads.
A better approach , called Syntheszs For Testabality
(SFT) , for synthesizing self testable FSMs has been
reported in [4]. An SFT Fheme for implementing self
testable FSMs using group Cellular Automata (CA)
has been reported in [7].
The present paper proposes an SFT approach for
synthesizing easily and fully testable FSMs using
a particular class of non-group CA referred to as
Dl*CA. A simple testing strategy has been evolved
from the knowledge of the unique state transition be-
havior of Dl*CA. At the cost of a small area overhead,
our scheme has consistently provided extremely high
coverages of all single stuck-at faults for a whole range
of benchmark FSMs.
Preliminaries of Cellular Automata and of Dl*CA
are discussed in Section 2. The synthesis scheme and
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B. Vamsi P. Pal Chaudhuri
the testing strategy are in sections 3 and 4. The ex-
perimental results are reported in Section 5.
2 Characterization of Dl*CA
A Cellular Automata (CA) consists of a number ofin-
terconnected cells arranged spatially in a regular man-
ner. In essence, each cell is made up of a memory ele-
ment (usually a D p a p - p o p ) and a combznatzonal logzc
generating the next-state of this cell from the present
states of its neighbouring cells.
If we express the next state function in the form of a
truth table, then the decimal equivalent of the output
column in the truth table is called the rule number of
the CA. For example, rule 90 : q:+' = qi-l @ qi+l, t
where @ refers to an ex-or function. An addatzve CA
uses only Ex-or/Ex-nor as the next state logic.
For an n-cell 1-dimensional additive CA it has been
shown [l]that the linear operator is an n x n matrix
whose ith row specifies the neighbourhood dependency
of the ith cell. The next state of the CA is gener-
ated by applying this linear operator on the present
state represented as a column vector. The operation
is the simple matrix multiplication, but the addition
involved is modulo-2 sum. The matrix is termed as
the Characterislic Matrix of the CA, and is denoted
by T .
If ft represents the state of the automata at t t h
instant of time, then the next state of the automata,
i.e. the state at (t + l)th time is given by fi+l =
T x ft. It has been proved in [l]that if the T matrix
is nonsingular, then the CA is a group CA; otherwise
it is a non-group CA. CA preliminaries are detailed in
PI *
The present work deals with a particular class
of depth-1 non-group CA having rule configuration
< 90,102,.. . ,102 > with null boundary conditions,
 referred to as Dl*CA. We introduce the concept of
a dual CA, which has been extensively used in our
testing strategy.
The conversion of an XOR gate of a cell to an
XNOR gate can be done simply by providing an addi-
tional control input to the XOR gate - with this control
as 0, the gate behaves as an ordinary XOR gate, while
with this input as 1, the gate behaves as an XNOR
gate. In the present work, we have utilized the dual
CA obtained by converting the next state function of
only the leftmost cell of a Dl*CA to an XNOR func-
tion. We shall refer to this dual CA as D1* CAdua1-
its rule vector is < 165,102,.. . l o 2 >.
If T is the characteristic matrix of a Dl*CA and
vector F denotes the cell positions for which XNOR
function is employed to arrive at the dual CA, then
the present state St and next state St+l of the dual
CA are related by the relation St+l = T [St] F
The T matrix and the corresponding characteristic
polynomial p ( z ) of a 4-cell Dl*CA with rule vector
< 90,102,102,102 > are noted below.
10 o o i J
The following results provide the basis for selecting
the Dl*CA as the basic building block of our SFT
scheme. These are stated here without any proof.
0 A CA with rule < 90,102,102,. . . ,102 > will con-
stitute a depth 1 non-group CA.
0 Each cyclic state of a Dl*CA has exactly one
cyclic predecessor (of even weight) and one non-
reachable predecessor (of odd weight).
0The Dl*CA's having number of cells ranging from
(2m-'+2) to (2"+1) have maximum cycle length
equal to 2".
The following theorem establishes the relationship
betweeen state transitions of a Dl*CA and the corre-
sponding D1 * CAdual.
Theorem 1 Let S be any state of a D1 *CA, S" the
state reached from S after two clock cycles and S"'
the non-reachable predecessor state of S" in the state
transition diagram of the Dl*CA (refer Figure 1).
Then the successor state of S in D1*CAdualis S"'.
3 The synthesis scheme
The basic block diagram of the general CA based FSM
design is shown in Figure 2.
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Figure 1: Relationship of states in a Dl*CA and
its dual
I - I1
+
Figure 2: Block Diagram of a CA Based FSM
The synthesised circuiit has two components : (a)
the combinational logic block consisting of the Inter-
rupt Logic and the primary output logic; and (b) the
CA. The primary output logic essentially generates the
primary outputs from the present state and primary
input information. The output of the Interrupt Logic,
referred to as Interrupt Vector, is fed as the control
input to the XOR gates associated with the CA cells.
With the all-zero Interrupt Vector , the CA runs in its
autonomous m o d e performing the autonomous tran-
sition Si + Sj, say. However, with some bits of the
Interrupt Vector as 1, the corresponding XOR gates in
the CA are effectively converted to XNOR gates and
an interrupt transition from S i to a different state 5';
now occurs. The required state-transitions of a given
FSM can be realized using the autonomous and inter-
rupt mode state-transitioms of the CA .
3.1 Dl*CA based FSM synthesis
In order to implement an n-state FSM, we have chosen
to use a rZog2nl cell Dl*CA, having the rule configu-
ration < 90,102,102. 1012 >. The unique state tran-
sition properties of Dl*CA and those of D1 * CAdual
make this class of CA the most suitable candidate for
our design scheme.
The state encoding strategy is another key factor
in the successful implementation of an easily testable
FSM. We have designed an algorithm which uses cer-
tain heuristic cost functions in arriving at a desired
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 state encoding. These functions have been designed
in such a way that the algorithm attempts to embed
the chosen Dl*CA in the FSM to enhance testabil-
ity, while simultaneously attempting to minimize the
area requirements in a multilevel implementation of
the combinational logic block. Experimental results
have established that by suitably specifying certain in-
put parameters to this algorithm, a reasonably good
tradeoff between these two goals can be achieved.
3.2 State encoding strategy
It is well known that in a muitilevel implementation
of a combinational logic block, the number of literals
in the optimized set of equations significantly affects
the number of gates required to implement the circuit.
Consequently, an attempt to minimize the number of
literals in the optimized set of equations would lead to
lesser circuit area requirements. This fact has been ex-
ploited in existing state encoding strategies like MUS-
TANG.
In our scheme, we have given due consideration to
this factor and have also attempted to find matches be-
tween the FSM state transitions and the state transi-
tions of Dl*CA. The existence of such matches greatly
helps in efficiently embedding the Dl*CA in the syn-
thesized sequential machine. A suitable combination
of these two factors is used to guide the state encoding
scheme.
4 Enhancing the testability
Cl c
2 Interpretation
1 1 Normal transitions of synthesized FSM
0 0 D 1*CA autonomous transitions
1 0 Autonomous transitions in dual CA
The important relationship between state transi-
tions in the Dl*CA and those in D1* CAdual, as al-
ready stated in Theorem l, has been utilized in ar-
riving at the following result, which is crucial to the
testing scheme.
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Theorem 2 Let S be a state of an n-cell Dl*CA and
m be the maximum cycle length in the state transition
diagram of the CA.
Case 1: S is even weighted - has an even number
of 1’s :
With S as the initial state, if D 1 * CAdual runs
+
for (m 1) clock cyles followed by (m - 1) cycles
in Dl*CA, then after these 2m cycles, the test
machine returns back to the state S .
Case 2: S is odd weighted - has an odd number
of 1’s :
With S as the initial state, if Dl*CA runs for (m
+ 1) clock cycles followed by (m - 1) clock cycles
in D 1 * CAdual, then after these 2m cycles, the
test machine returns back to state S .
The testing procedure essentially consists of check-
ing whether each of the transitions in the’original FSM
has actually occured without any fault in the machine.
In order to do this, we start from a known machine
state Si, apply the primary inputs and then run the
machine for 1 cycle in the normal FSM mode. Let the
expected transition in a faultfree FSM be S, -+S,. In
order to verify the correctness of the transition that
has occured, we now run the machine for 2m cycles in
the test mode. This would involve (m +
1) cycles in
Dl*CAdual mode followed by (m - 1)cycles in Dl*CA
mode if the expected next state Sj is even-weighted.
Otherwise, the 2m test clock cyles would involve (m
+ 1)cycles in D I V A mode followed by (m - 1) cycles
in D1 * mode.
+
During these 2m 1 clock cycles, we observe the
primary outputs and the output of the leftmost CA
cell. If the observed bit sequences on these lines match
with the fault-fiee bit sequences, we assume that the
transition has occured flawlessly. The unique state
transition properties of Dl*CA and D 1 * CAdual en-
sure that under fault free conditions, we would return
to the same state Sj from where we started our 2m
test clock cycles. In case the fault is detected by a
mismatch in the observed and expected fault-fiee bit
sequences, we stop the testing procedure and conclude
that the synthesized FSM has a stuck-at fault. 0th-
erwise, we proceed to verify the next FSM state tran-
siition starting from state Sj.
Experimental results on benchmark FSMs have
shown that this testing scheme produces a very high (
nearly 100 %) coverage of all single stuck-at faults.
5 Experimental results
In the Dl*CA based FSM design procedure, the states
of the FSM have been encoded using the state encod-
 ing module encode, the algorithm of which was out-
lined in an earlier section.
After encoding, the combinational logic of the FSM
has been optimized using MISII and has been mapped
to the gate library mcnc.genlib. The total gate area
and delay of the synthesized combinational logic block
have also been computed using gate characteristic in-
formation obtained from mcnc.genlib. For compar-
ing the gate area and delay of the combinatiohal logic
block obtained using the proposed CA based design
scheme with that obtained using MUSTANG’S state
encoding scheme, the combinational logic of FSMs en-
coded by MUSTANG have also been optimized using
MISII and have been mapped to the same gate library.
The maximum testing time requirement with the
+
proposed testing scheme is (2m l ) . k , where m is the
maximum cycle length in the state transition diagram
of the Dl*CA and k is the total number of transitions
in the FSM to be designed. The results of simulation
studies are given in Table 1.
References
[l] A.K. Das and P. F’al Chaudhuri. Pseudo-
exhaustive test pattern generation using Cellular
Automata. IEEE lkans. on Computers, 42(3):340-
352, March 1993.
[2] S . Devadas, H.K.T. Ma, A.R. Newton, and A S .
Vincentelli. Mustang: State assignment of finite
state machines targeting multi-level logic imple-
mentations. IEEE Trains. on C A D , CAD-7:1290-
1300, December 1988.
[3] S. Devadas, H.K.T. Ma, A.R. Newton, and AS.
Vincentelli. Synthesis atnd optimization procedures
for fully and easily test<ablesequential machines. In
Proc. Intl. Test Conference, pages 621-630, 1988.
[4] B. Eshermann and H.J. Wunderlich. Optimised
synthesis of self-testable finite machines. In Proc.
FTCS-20, pages 390-397, June 1990.

6 Conclusion [5] H. Fujiwara. Logic Design and Design for Testa-

In this paper, an elegant scheme for synthesis of eas-
ily testable FSMs using the regular structure of CA
has been reported. Average area and delay overheads
are in the range of 10 to 15 % and of 10 to 20 % re-
spectively. However, 100 % fault coverage has been
achieved for all benchmark FSMs .
bility. The MIT Press, London, 1985.
[6] H.K.T Ma and S. Devadas et. al. An incomplete
scan design approach to test generation for sequen-
tial machines. In Proc. I d . Test Conference, 1988.
[7] S. Misra, B. Mitra, and P. Pal Chaudhuri.
Synthesis of self-testatble sequential logic using

.i/
Table 1: Performance Comparison w.r.t Area programmable cellulair automata. In Proc. of
and Delay VLSI’92, INDIA, pages 193-198, January 1992.

n c o v . of all 11 Overhead in %

II 11 over MIYSTANG
Circuits 1 tS gate
s-a-1 delay a rea delay
ex5 98.931 12.85 11.59
dk14 100.0 99.228 100.0 100.0 217 17.9 6.37 16.99
ex4 100.0 98.507 100.0 100.0 161 14.4 7.33 -24.6
bbtas 66.292 65.169 100.0 100.0 72 11.4 14.9 -10.0 -23.49
bbara 99.457 99.652 100.0 100.0 155 14.3 -8.28 -14.88
bbsse 100.0 100.0 100.0 100.0 308 28.33 26.14
dk15 100.0 100.0 100.0 100.0 131 10.7 13.91 27.10
opus1 100.0 99.59 100.0 100.0 199 20.8 21.8 15.70 -4.59
keyb 100.0 99.813 100.0 100.0 470 -5.54
ex3 98.522 95.074 100.0 100.0 169 -13.87
train11 100.0 99.06 100.0 100.0 179 19.4 19.02
dk512 100.0 100.0 100.0 100.0 141 15.1 20.80
beecount 100.0 99.46 100.0 100.0 154 16.0 37.93
Note : High fault coverage has been achieved by
observing bit sequence from CA bit 1 due to specific char-
acteristic of Dl*CA.

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