Decap Cells

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cells
are temporary capacitors added in the design between power and ground rails to
counter functional failures due to dynamic IR drop.Dynamic I.R.
drop happens at the
active edge of the clock at which a high percentage
of Sequential and Digital elements
switch.Due to this simultaneous switching a high current is drawn from the power grid for
a small duration.If the power source is far away from a flop the chances are that this flop
can go into a metastable state due to IR Drop.To overcome
this decaps are added. At an
active edge of clock when the current requirement is high , these decaps discharge and
provide boost to the power grid. One caveat in usage of decaps is that these add to leakage
current. De caps are placed as fillers. The closer they are to the flop’s sequential elements,
the better it is.

Decap
cells are typically poly gate transistors where source and drain are connected to the
ground rail, and the gate is connected to the power rail. when
there is an instantaneous
switching activity the charge required moves from intrinsic and extrinsic local charge
reservoirs as oppose to voltage sources. Extrinsic capacitances are decap cells placed in
the design. Intrinsic capacitances
are those present naturally in the circuit, such as the
grid capacitance, the variable capacitance inside nearby logic, and the neighborhood
loading capacitance exposed when the P or N channel are open.One
drawback of decap
cells is that they are very leaky, so the more decap cells the more leakage. Another
drawback, which many designers
ignore, is the interaction of the decap cells with the
package RLC network. Since the die is essentially a capacitor with very small R and L, and
the package is a hug RL network, the more decap cells placed the more chance of tuning
the circuit into its resonance frequency. That would be trouble, since both VDD and GND
will be oscillating. I have seen designs fail because of thisDesigners
typically place decap
cells near high activity clock buffers, but I recommend a decap optimization flow where
tools study charge requirements at every moment in time and figure out how much decap
to place at any node. This should be done while taking package models into account to
ensure resonance frequency is not hit.

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