Analog Integr Circ Sig Process (2015) 84:173–183
DOI 10.1007/s10470-015-0542-y
Improving power efficiency of a two-stage operational amplifier
for biomedical applications
Meysam Akbari1 • Masoud Nazari2 • Leila Sharifi2 • Omid Hashemipour3
Received: 4 December 2014 / Revised: 7 April 2015 / Accepted: 18 April 2015 / Published online: 24 April 2015
Ó Springer Science+Business Media New York 2015
Abstract By using compensation technique with feed-
forward path, an improved folded cascode operational
transconductance amplifier (OTA) that operates in weak
inversion region is designed. The proposed configuration
consists of composite transistors, recycling structure and
feed-forward compensation path. In comparison with the
typical folded cascode CMOS Miller amplifier, this design
has higher DC gain, unity gain frequency and slew rate
without adversely affecting the noise and offset perfor-
mance. The presented OTA is simulated in 0.18 lm CMOS
technology and the simulation results confirm the theore-
tical analyses. Finally, the proposed amplifier has a
104.5 dB open-loop DC gain and 69.4 kHz unity gain
frequency @ 0.6 V supply voltage while the power con-
sumption is 300 nW.
Keywords OTA  Weak inversion region  Recycling
folded cascode  Feed-forward path  Composite transistor
& Meysam Akbari
Mey.akbari@yahoo.com
Masoud Nazari
Msu.nazari@gmail.com
Leila Sharifi
L_sharifi@sbu.ac.ir
Omid Hashemipour
Hashemipour@sbu.ac.ir
1
Department of Electrical and Computer Engineering, Payame
Noor University, 19395-3697 Tehran,
Islamic Republic of Iran
2
Microelectronic Laboratory, Shahid Beheshti University,
G. C., Tehran, Islamic Republic of Iran
3
Department of Electrical and Computer Engineering, Shahid
Beheshti University, G. C., Tehran, Islamic Republic of Iran
1 Introduction
Operational transconductance amplifiers (OTAs) are ex-
tensively used in analog and mixed-signal integrated cir-
cuits such as Gm-C filters, regulators, data converters and
many other applications. Therefore, the OTAs are still one
of the most useable building blocks [1, 2]. Among many
OTA architectures, the single-stage OTA is faster and
have better frequency response than the multistage one.
Therefore, the folded cascode (FC) amplifier is one of the
most commonly OTA topologies that has high open-loop
DC gain and proper frequency response. The FC amplifier
with the PMOS input transistors has lower flicker noise
and input common mode level than the FC with the
NMOS input transistors [3, 4]. This advantage makes the
FC amplifier with the PMOS input transistors a main
choice for ultra-low-power and low frequency applications
[3]. However, more inventions are still required to im-
prove the FC amplifier configuration. The recycling
structure [4], feed-forward technique [5] and multipath
schemes [6, 7] have been utilized in recent works to en-
hance performance of the FC amplifier. Due to these re-
cent works, the recycling folded cascode (RFC) amplifier
is introduced. Transconductance and low frequency output
impedance boosting techniques in [7–9] have been utilized
to increase the power efficiency of the RFC without in-
creasing power consumption. But, the enhancement of
transconductance leads to decay in the phase-margin that
resolves in [10] with a high-speed current mirror. How-
ever, these configurations are not suitable for specific
applications that require better performance. Therefore,
two-stage amplifiers with the RFC input stage and fre-
quency compensation technique are presented in [11, 12]
to achieve high output voltage swing and large open-loop
DC gain.
123
174
When considering the market trends towards low-power
and low-voltage applications, the power consumption,
frequency response and power supply voltage become the
key design parameters particularly in the weak inversion
operation region [13]. The drain-source voltage swing in
weak inversion region is larger than this voltage in strong
and moderate inversion. Due to the extremely low drain-
source current, the speed and bandwidth will be reduced
[14, 15]. Hence, the weak inversion operation region is an
interesting choice for designing ultra-low-power and low
frequency circuits such as biomedical applications [16, 17].
The ultra-low-power and ultra-low-voltage two-stage
OTAs with the folded cascode input stage and frequency
compensation technique are presented in [17–19]. How-
ever, their achievable transconductance may not be suffi-
cient in some cases, so the RFC architecture in [1, 4] can be
used as the first-stage amplifier in weak inversion region.
By using compensation technique with feed-forward path
in the design of two-stage amplifiers, low-valued com-
pensation capacitor and higher bandwidth are achieved in
[20, 21]. The compensation technique with feed-forward
path in [22] can be utilized for the two-stage amplifier with
the RFC input stage.
According to [23, 24], the flicker noise and DC offset
voltage are the main problems for designing an OTA in
weak inversion region. A simple approach to reduce the
flicker noise is increasing the transistor dimension par-
ticularly the transistor length [23]. Also by using chopper
stabilization technique in [24], the flicker noise and DC
offset voltage in multipliers are reduced. However, this
technique leads to increase the power dissipation and sili-
con area. In addition, the input referred flicker noise and
DC offset voltage are reduced in [4, 7, 25] by improving
transconductance without enhancement in the power
consumption.
In this paper, an ultra-low-power two-stage OTA that
operates in weak inversion region with the enhanced RFC
input stage is presented. The recycling structure is em-
ployed to improve open-loop DC gain, unity-gain fre-
quency, slew rate and common mode rejection ratio
(CMRR). Moreover, the recycling structure and composite
transistors enhance the noise and DC offset voltage per-
formance. Also by using the recycling structure, a feed-
forward path for frequency compensation is utilized in
this design that leads to the stable frequency behavior.
Finally, the paper is organized as follows: Sect. 2 de-
scribes the MOSFET operation in weak inversion region.
In the next section, the theoretical analyses are given for
open-loop DC gain, phase margin, noise, slew rate,
CMRR and offset voltage. The simulation results of the
designed amplifiers are reported in Sect. 4 followed by a
conclusion in Sect. 5.
123
Analog Integr Circ Sig Process (2015) 84:173–183
2 Weak inversion operation
The drain-source current of a long channel MOS transistor
in weak inversion region can be given by [13]
W VGS VTH  VDS

IDS ¼ 2nUt2 Cox l eð nUt Þ 1  e Ut ð1Þ
L
where W and L are the transistor channel width and
length, respectively, Ut is the thermal voltage, VTH is the
threshold voltage, VGS is the gate-source voltage, VDS is
the drain-source voltage, Cox is the gate-oxide ca-
pacitance per unit area, l is the electron mobility, and n is
the slope factor in weak inversion region [13, 17]. Note
that the transistor will be saturated in weak inversion
region when VDS [ 3Ut. Also, the gate and bulk
transconductance can be given by
oID ID
gm ¼ ¼ ð2Þ
oVGS nUt
c
gmb ¼ ðn  1Þgm ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi gm ð3Þ
2 2/F  VBS
where VBS is the bulk-source voltage, c is the body effect
coefficient and /F is the Fermi potential. The gmb varies
from 20 to 30 % of gm for the same transistor in a CMOS
process. Therefore, the sizes of transistors can be obtained
to work in weak inversion region [13, 15].
3 Improved two-stage folded cascode OTA
The conventional two-stage folded cascode (TSFC) am-
plifier is shown in Fig. 1. In this figure, transistors M1 and
M2 are input drivers. Also, transistors M3 and M4 conduct
the most current and have the largest transconductance. In
the proposed two-stage recycling folded cascode (TSRFC)
amplifier that is shown in Fig. 2, the M3 and M4 are uti-
lized as driving transistors. Input drivers M1, M2 in Fig. 1
are divided into Ma1, Ma2 and Mb1, Mb2 in Fig. 2 which
now conduct current flow equal to I/2. Moreover, transis-
tors M3 and M4 in Fig. 1 are exchanged with the current
mirrors of Ma3:Mb3 and Ma4:Mb4 in Fig. 2. This work
ensures that the small signal current is amplified by a ratio
of m. In addition, transistors M9 and M10 have a large
current and are utilized as driving transistors. Therefore,
the input signal is injected into the gates of M9 and M10 by
transistors Mc3-Mc6. As a result, the cross-over connec-
tions of the Mc5 and Mc6 with current mirrors Mc9:M9
and Mc10:M10 ensure that the input small signal current is
amplified by a ratio of kp. Finally, transistors Mb5, Mb6,
Mc5 and Mc6 maintain equal drain potentials across
Ma3:Mb3:Mc3 and Ma4:Mb4:Mc4 to improve matching
[4–6].
Analog Integr Circ Sig Process (2015) 84:173–183 175

Fig. 1 Schematic of
conventional two-stage folded Vcmfb2 Vb1 Vcmfb2
cascode amplifier M13 M9 M10 M14

M0
Vcmfb1

M7 M8

2I I nI/2

Vout- Cc Rc Rc Cc Vout+
Vin+ Vin-
M1 M2
CL CL

Vb2
M5 M6

Vb3
M11 M3 M4 M12

Fig. 2 Schematic of the p : 1 1 : p

proposed two-stage recycling Vcmf1 Vcmf1
Mb9 M9 Mc9 Mc10 M10 Mb10
folded cascode amplifier
Vb1
M0

M13 M7 Mc7 Mc8 M8 M14

2I

kpI/2
nI/2
Vin+ Vin-
Vout- Cc Cc Vout+
Ma1 Mb1 Mb2 Ma2

CL Composite
CL
transistor
Mc5 Mc6

M5 Mb5 Mb6 M6
Gmf

Ma3 Mc3 Mc4 Ma4

Vcmf2 Vcmf2
Mb11 M11 Mb3 Mb4 M12 Mb12

n : m : k : 1 1 : k : m : n

The amplifier’s transconductance (Gm) is obtained by
finding the short-circuit current at the output with respect to
the input voltage. Therefore, the small signal transcon-
ductance (Gm) of the TSFC and TSRFC amplifiers can be
expressed as follows:
GmTSFC ¼ gm1 gm12
GmTSRFC ¼ ðm þ kp þ 1Þgma1 gm14
The value of current gain factors p, m and k in Eq. (5)
are chosen to be 3, 2.5 and 0.5, respectively. This se-
lection maintains the power budget unchanged for both
the TSFC and TSRFC amplifiers that are shown in Figs. 1
and 2. The M1 in Fig. 1 is twice the size of Ma1 in Fig. 2
so gm1 = 2gma1. Moreover, gm12 in Fig. 1 is equal to
gm14 in Fig. 2 (gm12 = gm14). By substituting for the
values of p, m and k in Eq. (5), the input stage of TSRFC
ð4Þ has 150 % improvement in transconductance and unity-
gain bandwidth compared to the TSFC with the same
ð5Þ power consumption. These modifications provide the
TSRFC with enhanced features over that of the TSFC
while all devices are assumed to operate in the weak
inversion region.

123
176 Analog Integr Circ Sig Process (2015) 84:173–183

3.1 DC gain Cc

The AC model of the proposed TSRFC amplifier is shown Gm1 Gm2

in Fig. 3. Where Cb1, Cb2, Cb3, Cb4 and Cb5 are respec- Vin Vout
+ _
tively the parasitic capacitances in the drain node of tran-
sistors Mb1/Mb2, Mc5/Mc6, Ma3/Ma4, M9/M10 and M7/ R1 C1 R2 CL
M8. In addition, gm and go are obtained from the DC Gmf
biasing conditions. _
The open loop DC gain can be obtained directly from
the circuit of Fig. 3 by eliminating the parasitic ca-
pacitances. It is given by: Fig. 4 Frequency compensation topology with feed-forward path
ðkp þ m þ 1Þgma1 gm14
Ao ’ h i
go6 ðgoa4 þgoa2 Þ go8 go10 (RHP) zero which is introduced by using the Miller com-
ðgo12 þ go14 Þ gm6 þgmb6 þgo6 þðgoa4 þgoa2 Þ þ gm8 þgmb8 þgo8 þgo10
pensation capacitance, Cc. The major benefit is that the
ð6Þ positions of the poles are not affected by the additional
circuitry compared to the other compensation techniques
The DC gain of transconductance amplifiers is usually
[21, 22]. The transfer function of the compensation tech-
described as the product of the small signal transconduc-
nique with feed-forward path can be given by [22]
tance, Gm, with the low frequency output impedance, Rout.  
It was demonstrated that GmTSRFC = 2.5GmTSFC, which ðGmf Gm1 ÞCc
Gm1 Gm2 R1 R2 1 þ S Gm1 Gm2
results in a 8 dB gain enhancement for the same output Vout
 h i ð7Þ
impedance. Moreover, it can be seen that go of transistors Vin CL
ð1 þ SGm2 R1 R2 CcÞ 1 þ S Gm 2
Ma4, M6, M8 and M10 in cascode architecture are reduced
in the TSRFC amplifier compared to the TSFC amplifier, as where the symbols have their usual meanings [22]. With
these transistors conduct less current. Therefore, enhance- reference to (7), there are two left-hand plane (LHP) poles
ment of 12–14 dB in open loop DC gain can be obtained in and one zero as follows
the proposed TSRFC amplifier compared to the TSFC
1
amplifier. xp1  ð8Þ
Gm2 R1 R2 Cc
3.2 Phase margin Gm2
xp2  ð9Þ
CL
According to the added recycling structure in Fig. 2, fre- Gm1 Gm2
quency compensation technique with feed-forward path xz1    ð10Þ
Gmf  Gm1 Cc
(Fig. 4) can be utilized to keep the proposed amplifier
stable. The small-signal model of this technique is shown where Gm1 = (kp ? m?1)gma1, Gm2 = gm13 ? gm14 and
in Fig. 4. In this figure, the feed-forward transconductance Gmf = gm11 ? gm12. From (10), it can be seen that the
is an efficient technique to eliminate the right-hand plane zero can be counteracted by adjusting Gm1 and Gmf. For

Fig. 3 The proposed TSRFC amplifier AC model

123
Analog Integr Circ Sig Process (2015) 84:173–183 177

cancelling pole–zero (Z1 = P2) with each other, the value 8KB Tc hh i
of Gmf can be obtained by: V2 iT ¼ 1 þ ðm þ kpÞ2
TSRFC ðkp þ m þ 1Þ2 gma1

#
CL m þ ðkp þ mÞ2 þkp2 gma3 gm9
Gmf ¼ 1 þ Gm1 ð11Þ þ þ ð 1 þ pÞ
Cc m gma1 gma1
This leads to one dominant LHP pole in the transfer ð16Þ
function of (7). From (11), it can be considered that com-
pensation technique with feed-forward path is very power By substituting gm1 in terms of gma1, gm3 in terms of
effective at small or medium load capacitance or large gma3 and gm9,TSFC in terms of gm9,TSRFC the input referred
compensation capacitance [20]. thermal noise of the TSRFC amplifier is derived in (17).
 
The phase margin is determined by the poles and zeros 2 8KB Tc 34 23 gm3 12 gm9
V iT ¼ þ þ ð17Þ
of the amplifier transfer function and the transient response TSRFC gm1 25 25 gm1 25 gm1
of an amplifier can be evaluated by the phase margin [4].
By applying the Laplace transform, considering pole As mentioned before, it was assumed that all devices
separation and ignoring the parasitic capacitances at the operate in weak inversion region. So by using equations in
other nodes, the circuit of Fig. 3 presents poles and zero this region, the flicker noise expressions of the amplifiers
that are described in Eqs. (8), (9) and (10). Moreover, the can be expressed by (18) and (19).
 
Laplace transform shows that the TSRFC amplifier has two 2 Kfp 1 Kfn n21 1 n21 1
V if ¼ 2 þ4 þ
other poles, xP3 and xP4, associated with the current Cox f ðWLÞ1 Kfp n23 ðWLÞ3 n29 ðWLÞ9
TSFC
mirrors Ma4:Mb4:Mc4:M12 and M10:Mc10. The xP3 and
ð18Þ
xP4 can be described as
gmb4 Kfp
x p3 ¼  ð12Þ V2 if ¼2
ð 1 þ k þ m þ nÞCGB;b4 TSRFC ðkp þ m þ 1Þ2 Cox f
TSRFC
2  
2 2
gmc10 1 þ ðkp þ mÞ 2 2
Kfn na1 m þ ð kp þ m Þ þkp M
x p4 ¼  ð13Þ 4 þ
TSRFC ð 1 þ pÞCGB;c10 ðWLÞa1 2
Kfp na3 ðWLÞa3
where gmb4, gmc10, CGB,b4 and CGB,c10 are the transcon- #
ductance and gate-bulk capacitance of transistors Mb4 and n2 ð1 þ pÞðkpÞ2
þ a1
Mc10, respectively. As mentioned before, xP2 is n29 ðWLÞ9
eliminated by feed-forward technique. By choosing large ð19Þ
value for the current gain of transistors Ma4 and M10
(m and p), the input stage transconductance will be in- Since the channel length of devices has not been chan-
creased and the phase-margin will be degraded in the ged in order to improve the TSFC features, only Wa1, Wa3
TSRFC amplifier. By selecting m and p equal to 2.5 and 3, and W9,TSRFC are replaced with W1, W3 and W9,TSFC re-
the phase-margin of the TSRFC amplifier is degraded by spectively and input referred flicker noise of the TSRFC
4–6° in comparison with the TSFC amplifier. amplifier is concluded in (20).
 
Kfp 34 1 92 Kfn n2a1 1 12 n2a1 1
V2 if ¼2 þ þ
Cox f 25 ðWLÞ1 25 Kfp n2a3 ðWLÞ3 25 n29 ðWLÞ9
3.3 Noise TSRFC
ð20Þ
The maximum noise current power seen at the output of a Two terms in (17) and (20) have smaller value than their
MOSFET is given by (14) which comprises the thermal counterparts in (15) and (18). So, initial conclusion shows
and flicker noise [23, 24]. that the noise of the proposed TSRFC amplifier has been
  reduced or in worst case, it becomes equal to the noise of
Kf gm2
i2o ¼ 4KB Tcgm þ ð14Þ the TSFC.
Cox LWf
Both noises are expressed individually for comparison 3.4 Slew rate
purpose. The input referred thermal noise of the TSFC and
TSRFC amplifiers are expressed in (15) and (16). The slew rate (SR) is a critical design parameter as it di-
  rectly adds to the settling time of an amplifier. The SR for
2 8KB Tc gm3 gm9
V iT ¼ 1þ þ ð15Þ the RFC amplifier has been carefully analyzed in [4, 6], so
TSFC gm1 gm1 gm1
just a brief study about internal and external slew rate of

123
178
the TSRFC amplifier is presented here. Assuming a large
signal applied into Vin-, the Ma2 and Mb2 will be turned
off which forces Ma3 and Mc3 to turn off. As a result, the
drain voltage of Ma3 and Mc3 rises and Ma1 is driven into
deep triode of weak inversion region. Therefore, M5, Mc5,
Mc8, M8, Mc10 and M10 will be turned off which force
Mb10 to deep triode. The tail current 2I flows into Mb1 and
it is mirrored by a factor of k and m into Mc4 and Ma4,
respectively. Thus, the compensation capacitor, Cc, at
positive output is discharged by Ma4 and the compensation
capacitor at negative output is charged by M9. Therefore,
for the internal SR we have:
2I
SR in ¼ ð21Þ
TSFC Cc
A cm 
2IðkpÞ 2IðmÞ
SR in ¼ þ ð22Þ
ð26Þ
TSRFC Cc Cc
Based on the previous analysis, when a large signal is
applied into Vin-, the M11 is turned off and the tail current
2I is mirrored by a factor of n into M12. In this condition,
the drain voltage of M6 falls and drain voltage of M7 rises
that lead to increase the gate-source voltage and current of
M14 (ID14,max) and decrease the gate-source voltage and
current of M13 (ID13,min), respectively. IDb11 and IDb12 are
usually very smaller than ID11 and ID12. Therefore, the
external SR can be achieved by
proximation. However, these equations can show the better
2Ið1 þ n4Þ  ID12;max
SR ex ¼ CMRR performance of the TSRFC over TSFC structure.
TSFC
CL
2Ið1  n4Þ þ ID12;min
þ ð23Þ
CL
2Iðk þ nÞ  ID14;max 2IðkpÞ þ ID12;min
SR ex ¼ þ
TSRFC CL CL
ð24Þ
By assuming that (ID14,max) and (ID12,min) of the TSRFC
amplifier are equal to (ID12,max) and (ID12,min) of the TSFC
amplifier, respectively, the external SR of the TSRFC is
improved over the TSFC. Also by substituting values of p,
m and k in (22), the internal SR of the TSRFC is improved
4 times over the TSFC for the same power consumption
and silicon area. During negative slewing a similar im-
provement in the value of slew rate is also obtained.
3.5 CMRR
CMRR defines the ability of an amplifier to reject common
mode disturbances. Ideally CMRR for a differential am-
plifier should be infinite. However, in practical situations,
non-idealities such as mismatch, finite output impedance of
current sources and etc. cause CMRR to have finite value
[7]. The added drivers M9 and M10 are used to create a
123
Analog Integr Circ Sig Process (2015) 84:173–183
new common mode path to improve CMRR of the TSRFC
structure. By injecting the input common mode voltage to
the gate of transistors M9 and M10, a new common mode
path with negative gain is generated beside the conven-
tional paths. Therefore, the input common mode signal
passes from the input node to the output node by using the
current mirror Mc10:M10 with a ratio of kp. This modifi-
cation leads to the lower common mode gain (CMG) and
better CMRR is achieved compared to the TSFC. The
CMG for the TSFC and TSRFC amplifiers can be ex-
pressed approximately by (25) and (26), respectively.
4gm1 gm12 go0 Rout1
A cm  ð25Þ
TSFC ðgo0 þ 2gm1 Þðgo12 þ go14 Þ
4gma1 gm14 go0 Rout1
TSRFC ðgo0 þ 4gma1 Þðgo12 þ go14 Þ
n
þ kp þ 1  m
2gm14 Rout1
where Rout1 is the first stage output impedance of ampli-
fiers. From the above equations, it can be seen that the
CMG of the TSRFC is reduced over the TSFC with the
same power consumption. By substituting the values of p,
m and k in (26) and ignoring of (n/2gm14Rout1), the CMG
of the TSRFC can be equal to zero. But the value of zero
for the CMG is not achieved in simulation results because
the Eqs. (25) and (26) are obtained by using a lot of ap-
3.6 Offset
The composite MOS transistor is a significant structure for
operating in weak inversion region. The configuration of an
NMOS composite transistor is shown in Fig. 2. According
to [13, 17], the drain-source voltage for saturation of
transistors Ma3 and Ma4 can be given by:
ðW=LÞ5
VDSa3 ¼ Ut Ln 1 þ ð27Þ
ðW=LÞa3
It can be seen that Eq. (27) is a logarithmic function of
the transistor sizes and thermal voltage (Ut), and VDsa3 does
not depend on the transistor gate-source voltage [13].
Hence, a variation in drain-source voltage of M5 and M6
(VDS5 and VDS6) does not affect VDsa3 and VDsa4. Therefore,
VDsa1 and VDsa2 are become constant and equal that lead to
better matching for differential pair (Ma1 and Ma2). Fi-
nally, the differential input offset voltage is reduced by
using ten composite transistors in Fig. 2. According to the
similar analysis in [4, 7], the input offset variance can be
expressed as the sum of all device drain-current variances
seen at the output, and then referred to the input using the
amplifier’s transconductance (Gm). Therefore, the TSRFC
Analog Integr Circ Sig Process (2015) 84:173–183 179

with enhanced transconductance has less input offset of 15 pF (C1 = 1 pF, C2 = 7.5 pF). For calculating the
voltage in comparison with the TSFC configuration. slew rate, a large step of 0.6VPP at 3.33 kHz was applied to
the amplifiers to simulate the slew rate. The results of it are
given in Fig. 8. The TSRFC shows a clear improved slew
4 Simulation results
TSRFC
The two designed amplifiers (TSRFC and TSFC) are 2
TSFC
10
simulated in 0.18 lm BSIM3v3 level 49 mixed-signal

Spectral density, pV2/Hz

CMOS technology and they are biased with a 0.6 V power
supply to ensure operating in weak inversion region. These
OTAs are compensated with 2.5 pF compensation ca- 10
0

pacitor, Cc, and 50 kX compensation resistor, Rc. Open-

loop AC response of the TSRFC and TSFC are shown in
Fig. 5. The unity gain frequency (UGF) of the TSFC and
-2
TSRFC amplifiers is 34.9 and 69.4 kHz, respectively. It 10
obviously demonstrates that transconductance of the
TSRFC is boosted in comparison with the TSFC. The
phase margin of TSRFC and TSFC is equal to 58.1° and 0
10
2
10 10
4

62.2° at their respective UGFs. Thus, the phase margin of Frequency, Hz

TSRFC compared to the TSFC shows 4.1° degradation.
Since the TSRFC and TSFC amplifiers have not the same Fig. 6 Spectral power density of input referred noise for the two
UGF, the phase margin of the TSFC drops to 43.7° at designed amplifiers
69.4 kHz, so the TSRFC shows 14.4° advancement.
Moreover, DC gain of the TSFC and TSRFC is 90.1 and
104.5 dB respectively, thus it shows a significant advan- C1 CL
tage of the TSRFC over the TSFC amplifier. C1
The noise was characterized through simulations and the _ Vout+
Vin- +
spectral density of the input referred noise is given in
Fig. 6. The input referred noise of the TSFC and TSRFC _
Vin+ +
Vout-
amplifiers is 25.64 and 14.35 pV2/Hz @ 1 Hz, respectively. C1
Therefore, the TSRFC has better noise performance than C1 CL
the TSFC as described by Eqs. (17) and (20).
According to Fig. 7, three amplifiers were used as a
unity gain capacitive buffer to drive a total capacitive load Fig. 7 Unity gain buffer configuration

Fig. 5 Open loop frequency TSRFC

response of the two designed 100
TSFC
amplifiers
Gain,dB

50

0
Phase,deg

-50

-100

-150
-1 0 1 2 3 4 5
10 10 10 10 10 10 10
Frequency, Hz

123
180 Analog Integr Circ Sig Process (2015) 84:173–183

TSRFC 100 SS
0.3
TSFC FF
FS

Gain,dB
0.2
SF
Output voltage, V

50
0.1

0
0

-0.1

Phase,deg
-0.2 -50

-0.3

4.5 5 5.5 6 6.5 7 7.5 -100

Time, ms

Fig. 8 Step response of the two designed amplifiers 0 2 4

10 10 10
Frequency, Hz
80 TSRFC
Fig. 11 Corner analysis of open loop AC response
TSFC

70
CMRR, dB

0.2 SS
60
FF
0.15 FS
50 SF
0.1
Output voltage, V

40 0.05

0
30
-0.05
0 2 4
10 10 10
-0.1
Frequency, Hz
-0.15
Fig. 9 Simulated CMRR for the two designed amplifiers
-0.2
1.55 1.6 1.65 1.7 1.75 1.8 1.85
Time, s

Fig. 12 Corner analysis of output transient response

Fig. 10 Power supply variation of open loop AC response
rate over the TSFC despite the same bias current. The
average slew rate of the TSFC and TSRFC is 7.5 and
37.4 V/ms respectively i.e. the slew rate of the TSRFC is
enhanced 5 times over the TSFC with the same power
consumption.
Figure 9 shows the CMRR curves of the amplifiers. The
TSRFC shows a clear improvement of CMRR over the
TSFC. At the low frequency range, the CMRR of the TSFC
and TSRFC is 37 and 78.5 dB, respectively. The CMRR of
the TSRFC is enhanced 41.5 dB over the TSFC with the
same power consumption.
Corner analysis, power supply variation and temperature
dependent simulation are reported to demonstrate the

123
Analog Integr Circ Sig Process (2015) 84:173–183 181

Table 1 Important
Corner analysis Temperature variation Power supply variation
specifications of TSRFC in the
corner analysis, temperature Parameter SS FF -50 °C ?95 °C Vdd ? 15 % Vdd - 15 %
effects and power supply
variations Unity gain bandwidth (kHz) 64 71 69.2 63 71.2 58.4
Phase margin (°) 57.6 57.7 57.5 59.5 58 57.7
DC gain (dB) 103 103.5 100.2 99.3 106 100
0.2 % settling time (ls) 46.3 32.5 39.5 39.9 33.9 47.9

Table 2 Specifications of
Parameter TSFC [13] [18] [19] TSRFC
TSRFC in comparison with
TSFC and other works Power supply (mV) 600 600 400 500 600
Technology (lm) 0.18 0.35 0.18 0.18 0.18
Power consumption (nW) 300 550 386 1020 300
Capacitive load (pF) 2 9 7.5 15 15 15 2 9 7.5
Unity gain frequency (kHz) 34.9 13.02 111.4 83.88 69.4
Phase margin (°) 62.2 54.1 66 66.3 58.1
Open loop DC gain (dB) 90.1 73.5 91 88.5 104.5
Average slew-rate (V/ms) 7.5 14.7 22 52 37.4
0.2 % settling time (ls) 108.2 – – – 33.6
CMRR @ 100 Hz (dB) 37 67.4 106 133.85 78.5
PSRR @ 100 Hz (dB) 30.7 58.1 – – 52.2
Maximum output signal swing (mV) 1200 600 400 500 1200
Linear output signal swing range (mV) 100–1100 40–560 – – 100–1100
Input voltage noise @ 1 kHz (nV/HHz) 115.1 290 – – 93.3
Input referred noise (1–100 kHz) (lVrms) 116.2 – – – 93.1
Estimated area (lm2) 30,000 60,000 – – 30,000
FOM (dB kHz (V/ms)/nW) 78.6 25.6 577.7 378.4 904.1

global process variations and temperature effects on main 5 Conclusion

specifications of the proposed OTA. The open loop AC
response of the proposed OTA with ± 15 % power supply
variations is shown in Fig. 10. In addition, the open loop
AC response and output transient response of the proposed
OTA in the four process corners (SS, FF, SF and FS) are
shown in Figs. 11 and 12. Furthermore, for a 0.6 VPP input
step voltage in the closed loop unity gain configuration, the
SS, FS, FF and SF corners do not have a significant change
in the results compared to the TT corner at room
temperature.
Table 1 summarizes the important specifications of the
TSRFC amplifier in the corner analysis, temperature var-
iation and power supply variation. To assist comparing this
work with other works, a figure of merit (FOM) can be
defined by
ðDC gainÞðGain bandwidthÞðSlew rateÞ
FOM ¼ ð28Þ
Power dissipation
Finally, the designed amplifiers are configured such that
the output is set at VDD/2 to maximize swing. Table 2
summarizes the specifications of the TSFC and TSRFC
amplifiers.
In this paper, a two-stage enhanced RFC amplifier has been
proposed. Compared to the conventional two-stage FC am-
plifier, the designed OTA shows better open loop DC gain,
unity gain frequency and slew rate without adversely af-
fecting input referred noise. By keeping same power con-
sumption for the designed amplifiers and reducing phase
margin for the proposed amplifier, better FOM has been
achieved. The designed OTAs were simulated in 0.18 lm
CMOS technology. Simulation results show 14.4 dB,
34.5 kHz and 29.9 V/ms improvement in open loop DC
gain, unity gain frequency, and slew rate, respectively.
References
1. Assaad, R., & Silva-Martinez, J. (2007). Enhancing general
performance of folded cascode amplifier by recycling current.
Electronics Letters, 43, 1243–1244.
2. Akbari, M., Biabanifard, S., Asadi, S., & Yagoub, M. C. E.
(2014). Design and analysis of DC gain and transconductance

123
182 Analog Integr Circ Sig Process (2015) 84:173–183

boosted recycling folded cascode OTA. AEU—International International Conference on Microelectronics (ICM) 2008 (pp.
Journal of Electronics and Communications, 68, 1047–1052. 39–42).
3. Akbari, M, Hashemipour, O., & Javid, A., (2014). An ultra-low 20. Hoi, L., & Mok, P. K. T. (2004). Advances in active-feedback
voltage, ultra-low power fully recycling folded cascode amplifier. frequency compensation with power optimization and transient
In The 22nd Iranian Conference on Electrical Engineering (ICEE improvement. IEEE Transactions on Circuits and Systems—I:
2014) (pp. 514–518). Regular Papers, 51, 1690–1696.
4. Assaad, R. S., & Silva-Martinez, J. (2009). The recycling folded 21. Akbari, M., & Hashemipour, O. (2015). High gain and high
cascode: a general enhancement of the folded cascode amplifier. CMRR two-stage folded cascode OTA with Nested Miller com-
IEEE Journal of Solid-State Circuits, 44, 2535–2542. pensation. Journal of Circuits, Systems, and Computers, 24,
5. Thandri, B. K., & Silva-Martinez, J. (2006). An overview of feed- 1550057.
forward design techniques for high-gain wideband operational 22. Chan, P. K., & Chen, Y. C. (2003). Gain-enhanced feedforward
transconductance amplifiers. Microelectronics Journal, 37, path compensation technique for pole-zero cancellation at heavy
1018–1029. capacitive loads. IEEE Transactions on Circuits and Systems II:
6. Yavari, M., & Moosazadeh, T. (2014). A single-stage operational Analog and Digital Signal Processing, 50, 933–941.
amplifier with enhanced transconductance and slew rate for 23. Akbari, M., & Hashemipour, O. (2015). Design and analysis of
switched-capacitor circuits. Analog Integrated Circuits and Sig- folded cascode OTAs using Gm/Id methodology based on flicker
nal Processing, 79, 589–598. noise reduction. Analog Integrated Circuits and Signal Process-
7. Akbari, M., Biabanifard, S., Asadi, S., & Yagoub, M. E. (2015). ing. doi:10.1007/s10470-015-0535-x.
High performance folded cascode OTA using positive feedback 24. Agnes, A., Cabrini, A., Maloberti, F., & Martini, G. (2007).
and recycling structure. Analog Integrated Circuits and Signal Cancellation of amplifier offset and 1/f noise: An improved
Processing, 82, 217–227. chopper stabilized technique. IEEE Transactions on Circuits and
8. Zhao, X., Fang, H., & Xu, J. (2012). A transconductance en- Systems—II: Express Briefs, 54, 469–473.
hanced recycling structure for folded cascode amplifier. Analog 25. Liang, Z., & Islam, S. K. (2013). Low-voltage bulk-driven op-
Integrated Circuits and Signal Processing, 72, 259–263. erational amplifier with improved transconductance. IEEE
9. Yan, Z., Mak, P.-I., & Martins, R. P. (2012). Double recycling Transactions on Circuits and Systems—I: Regular Papers, 60,
technique for folded-cascode OTA. Analog Integrated Circuits 2084–2091.
and Signal Processing, 71, 137–141.
10. Akbari, M., Javid, A., & Hashemipour, O. (2014). A high input
dynamic range, low voltage cascode current mirror and enhanced Meysam Akbari was born in
phase-margin folded cascode amplifier. In The 22nd Iranian Kermanshah, Iran in 1988. He
Conference on Electrical Engineering (ICEE 2014) (pp. 77–81). received the B.S. and M.S. de-
11. Fahmy, G. A., Pokharel, R. K., Kanaya, H., & Yoshida, K. (2010). grees in Electrical Engineering
Indirect compensation technique based two-stage recycling folded from Kermanshah Islamic Azad
cascode amplifier for reconfigurable multi-mode sigma-delta ADC. University in 2010 and Shahid
In 2010 IEEE International Conference of Electron Devices and Beheshti University in 2013,
Solid-State Circuits (EDSSC 2010) (pp. 1–4). respectively. His research inter-
12. Zhou, Q., Li, H., Duan, X., & Yang, C. (2011). A two-stage am- ests include low power and high
plifier with the recycling folded cascode input-stage and feedfor- speed data converter, low volt-
ward stage. Cross Strait Quad-Regional Radio Science and age analogue circuits and RF
Wireless Technology Conference (CSQRWC), 2011, 1557–1560. integrated circuits design. He is
13. Ferreira, L. H. C., Pimenta, T. C., & Moreno, R. L. (2007). An currently with Department of
ultra-low-voltage ultra-low-power CMOS Miller OTA with rail- Electrical and Computer Engi-
to-rail input/output swing. Circuits and Systems II: Express neering in Payame Noor
Briefs, IEEE Transactions on, 54, 843–847. University, I.R. of Iran.
14. Alioto, M. (2010). Understanding DC behavior of subthreshold
CMOS logic through closed-form analysis. IEEE Transactions on
Circuits and Systems I: Regular Papers, 57, 1597–1607. Masoud Nazari received B.S
15. Valero Bernal, M. R., Celma, S., Medrano, N., & Calvo, B. degree in 2011 at K.N.Toosi
(2012). An ultralow-power low-voltage class-AB fully differen- University of Technology and
tial OpAmp for long-life autonomous portable equipment. IEEE M.S degree in 2013 at Shahid
Transactions on Circuits and Systems II, 59, 643–647. Beheshti University both in
16. Harrison, R. R., & Charles, C. (2003). A low-power low-noise Electronics Engineering. He is
CMOS amplifier for neural recording applications. IEEE Journal currently with the Microelec-
of Solid-State Circuits, 38, 958–965. tronic Research Laboratory in
17. Ferreira, L. H. C., & Sonkusale, S. R. (2014). A 60-dB gain OTA Shahid Beheshti University,
operating at 0.25-V power supply in 130-nm digital CMOS process. Tehran, Iran. His research in-
IEEE Transactions on. Circuits and Systems I, 61, 1609–1617. terests include low power and
18. Kargaran, E., Sawan, M., Mafinezhad, K., & Nabovati, H. (2012). high speed data converter, low
Design of 0.4 V, 386 nW OTA using DTMOS technique for voltage analog circuits and RF
biomedical applications. In 2012 IEEE 55th International Mid- integrated circuits design.
west Symposium on Circuits and Systems (MWSCAS 2012) (pp.
270–273).
19. Razzaghpour, M., & Golmakani, A. (2008). An ultra-low-voltage
ultra-low-power OTA with improved gain-bandwidth product. In

123
Analog Integr Circ Sig Process (2015) 84:173–183
Leila Sharifi received her B.S
and M.S degrees in Electronics
Engineering from Shahid Be-
heshti University, Tehran, Iran,
in 2011 and 2014, respectively.
She is also working towards her
PhD at the Microelectronic Re-
search Laboratory of this uni-
versity. Her research interests
include low power and high
speed digital to analog convert-
ers, sigma-delta analog to digi-
tal converters and CMOS
current mode logic.
183
Omid Hashemipour (BS’85,
MS’87, Phd’91) in Electrical
Engineering all received from
university of Arkansas at
Fayetteville USA. From 1991,
he is with the Electrical and
Computer Engineering Faculty
at Shahid Beheshti University,
G.C., Tehran, Iran as an asso-
ciate professor. His research in-
terests include low-power, low-
voltage, and current mode ana-
log integrated circuits.
123