Professional Documents
Culture Documents
Datasheet
Datasheet
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
SEG7 65 40 P20
SEG6 66 39 P21
SEG5 67 38 P22
SEG4 68 37 P23
SEG3 69 36 P24
SEG2 70 35 P25
SEG1 71 34 P26
SEG0 72 33 P27
VCC 73 M38224M6HXXXFP 32 VSS
VREF 74 31 XOUT
AVSS 75 30 XIN
COM3 76 29
P70/XCOUT
COM2 77 28 P71/XCIN
COM1 78 27 RESET
COM0 79 26 P40
VL3 80 25 P41/φ
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
P57/ADT
P51/INT3
P50/INT2
P44/RXD
P43/INT1
P42/INT0
VL2
VL1
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
P56/TOUT
P55/CNTR1
P54/CNTR0
P53/RTP1
P52/RTP0
P47/SRDY
P46/SCLK
P45/TXD
3822 Group
P34/SEG12
P35/SEG13
P36/SEG14
P37/SEG15
P00/SEG16
P01/SEG17
P02/SEG18
P03/SEG19
P04/SEG20
P05/SEG21
P06/SEG22
P07/SEG23
P10/SEG24
P11/SEG25
P12/SEG26
P13/SEG27
P14/SEG28
P15/SEG29
SEG10
SEG11
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG9 61 40 P16/SEG30
SEG8 62 39 P17/SEG31
SEG7 63 38 P20
SEG6 64 37 P21
SEG5 65 36 P22
SEG4 66 35 P23
SEG3 67 34 P24
SEG2 68 33 P25
SEG1
SEG0
69
70
M38223M4MXXXGP 32
31
P26
P27
VCC
VREF
71
72
M38224M6HXXXHP 30
29
VSS
XOUT
AVSS 73 28 XIN
COM3 74 27 P70/XCOUT
COM2 75 26 P71/XCIN
COM1 76 25 RESET
COM0 77 24 P40
VL3 78 23 P41/φ
VL2 79 22 P42/INT0
VL1 80 21 P43/INT1
20
10
11
12
13
14
15
16
17
18
19
4
1
2
3
5
6
7
8
9
P55/CNTR1
P61/AN1
P53/RTP1
P51/INT3
P50/INT2
P44/RXD
P45/TXD
P63/AN3
P62/AN2
P56/TOUT
P54/CNTR0
P57/ADT
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P60/AN0
P52/RTP0
P47/SRDY
P46/SCLK
2
FUNCTIONAL BLOCK DIAGRAM (Package type : 80P6Q-A)
Clock generating C P U 80
circuit VL 1
A ROM RAM 79 VL 2
78 VL 3
X
LCD display 77
LCD COM0
XCIN XCOUT φ Y RAM 76
drive control COM1
Sub-Clock Sub-Clock (16 bytes) 75
circuit COM2
Input Output S 74
COM3
PCH PCL 70 SEG0
Timer X(16)
69 SEG1
PS Timer Y(16) 68 SEG2
Timer 1(8) Timer 2(8) 67 SEG3
66 SEG4
Timer 3(8) 65 SEG5
64 SEG6
63 SEG7
62 SEG8
61 SEG9
60 SEG10
59 SEG11
A-D
converter(8) SI/O(8)
TOUT
CNTR0,CNTR1
Real time port function
XCOUT RTP0,RTP1
XCIN
φ
P7(2) P6(8) P3(4)
INT0,INT1
ADT
INT2,INT3
Key on wake up
26 27 1 2 3 4 5 6 7 8 72 73 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 55 56 57 58 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
I/O Port P7 I/O Port P6 VREF I/O Port P5 I/O Port P4 Input Port P3 I/O Port P2 I/O Port P1 I/O Port P0
AVSS
(0V)
3
MITSUBISHI MICROCOMPUTERS
3822 Group
PIN DESCRIPTION
Table 1 Pin description (1)
4
MITSUBISHI MICROCOMPUTERS
3822 Group
P70 /XCOUT, I/O port P7 •2-bit I/O port. •Sub-clock generating circuit I/O pins.
P71 /XCIN •CMOS compatible input level. (Connect a resonator. External clock
•CMOS 3-state output structure. cannot be used.)
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
5
MITSUBISHI MICROCOMPUTERS
3822 Group
PART NUMBERING
Package type
FP : 80P6N-A package
GP : 80P6S-A package
HP : 80P6Q-A package
FS : 80D0 package
ROM number
Omitted in One Time PROM version shipped in blank and EPROM version.
ROM/PROM size
1 : 4096 bytes 9: 36864 bytes
2 : 8192 bytes A: 40960 bytes
3 : 12288 bytes B: 45056 bytes
4 : 16384 bytes C: 49152 bytes
5 : 20480 bytes
6 : 24576 bytes
7 : 28672 bytes
8 : 32768 bytes
The first 128 bites and the last 2 bytes of ROM are
reserved areas ; they cannot be used.
Memory type
M : Mask ROM version
E : EPROM or One Time PROM version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
6
MITSUBISHI MICROCOMPUTERS
3822 Group
48K M38227EC
32K
28K
24K
20K
Mass product
16K M38223M4/E4
12K
Mass product
8K M38222M2
4K
Note: Products under development or planning: the development schedule and specifications
may be revised without notice.
7
MITSUBISHI MICROCOMPUTERS
3822 Group
Memory Type
Support for Mask ROM version.
Memory Size
ROM size ........................................................................ 48 K bytes
RAM size ....................................................................... 1024 bytes
32K
28K
24K
20K
16K
12K
8K
4K
Table 4 List of products for extended operating temperature version As of August 2000
ROM size (bytes)
Product RAM size (bytes) Package Remarks
ROM size for User in ( )
M38227MCDXXXFP 49152(49022) 1024 80P6N-A Mask ROM version
8
MITSUBISHI MICROCOMPUTERS
3822 Group
Memory Size
ROM size ........................................................... 16 K to 24 K bytes
RAM size .............................................................. 512 to 640 bytes
48K
32K
28K
Mass product
24K M38224M6M
20K
Mass product
16K M38223M4M
12K
8K
4K
9
MITSUBISHI MICROCOMPUTERS
3822 Group
Memory Size
ROM size ........................................................... 16 K to 48 K bytes
RAM size ............................................................ 512 to 1024 bytes
Mass product
32K M38227M8H
28K
Mass product
24K M38224M6H
20K
Mass product
16K M38223M4H
12K
8K
4K
10
MITSUBISHI MICROCOMPUTERS
3822 Group
b7 b0
A Accumulator
b7 b0
X Index register X
b7 b0
Y Index register Y
b7 b0
S Stack pointer
b15 b7 b0
PCH PCL Program counter
b7 b0
N V T B D I Z C Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
11
MITSUBISHI MICROCOMPUTERS
3822 Group
On-going Routine
Interrupt request
(Note) M (S) (PCH)
(S) (S)– 1
(S) (S) – 1
Subroutine Interrupt
Service Routine I Flag is set from “0” to “1”
Execute RTS Fetch the jump vector
Execute RTI
(S) (S) + 1
POP return (S) (S) + 1
address from stack POP contents of
(PCL) M (S) processor status
(PS) M (S) register from stack
(S) (S) + 1
(S) (S) + 1
(PCH) M (S)
(PCL) M (S)
POP return
address
(S) (S) + 1 from stack
(PCH) M (S)
Fig. 10 Register push and pop at interrupt generation and subroutine call
12
MITSUBISHI MICROCOMPUTERS
3822 Group
Table 8 Set and clear instructions of each bit of processor status register
C flag Z flag I flag D flag B flag T flag V flag N flag
Set instruction SEC – SEI SED – SET – –
Clear instruction CLC – CLI CLD – CLT CLV –
13
MITSUBISHI MICROCOMPUTERS
3822 Group
b7 b0
CPU mode register
(CPUM (CM) : address 003B 16)
14
MITSUBISHI MICROCOMPUTERS
3822 Group
RAM area
000016
RAM size Address
(bytes) XXXX16 SFR area
084016
Not used
ROM area
15
MITSUBISHI MICROCOMPUTERS
3822 Group
16
MITSUBISHI MICROCOMPUTERS
3822 Group
I/O PORTS
Direction Registers (ports P2, P4 1-P47, and b7 b0
PULL register A
P5-P7) (PULLA: address 001616 )
The 3822 group has 49 programmable I/O pins arranged in seven P00–P07 pull-down
I/O ports (ports P0–P2, P4 1–P4 7 and P5-P7). The I/O ports P2, P10–P17 pull-down
P41–P4 7 and P5-P7 have direction registers which determine the P20–P27 pull-up
P34–P37 pull-down
input/output direction of each individual pin. Each bit in a direction P70, P71 pull-up
register corresponds to one pin, and each pin can be set to be in- Not used (return “0” when read)
put port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin be-
comes an output pin. b7 b0
PULL register B
If data is read from a pin set to output, the value of the port output (PULLB : address 001716)
latch is read, not the value of the pin itself. Pins set to input are P41–P43 pull-up
floating. If a pin set to input is written to, only the port output latch P44–P47 pull-up
P50–P53 pull-up
is written to and the pin remains floating.
P54–P57 pull-up
P60–P63 pull-up
Direction Registers (ports P0 and P1) P64–P67 pull-up
Ports P0 and P1 have direction registers which determine the in- Not used (return “0” when read)
Pull-up/Pull-down Control
By setting the PULL register A (address 001616) or the PULL reg-
ister B (address 001716), ports except for port P4 0 can control
either pull-down or pull-up (pins that are shared with the segment
output pins for LCD are pull-down; all other pins are pull-up) with
a program.
However, the contents of PULL register A and PULL register B do
not affect ports programmed as the output ports.
17
MITSUBISHI MICROCOMPUTERS
3822 Group
P20 –P27 Port P2 Input/output, CMOS compatible Key input (key-on PULL register A (2)
individual bits input level wake-up) interrupt Interrupt control register 2
CMOS 3-state output input
P34 /SEG12 – Port P3 Input CMOS compatible LCD segment output PULL register A (3)
P37 /SEG15 input level Segment output enable
register
Notes1: How to use double-function ports as function I/O ports, refer to the applicable sections.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate po-
tential, a current will flow VCC to V SS through the input-stage gate.
18
MITSUBISHI MICROCOMPUTERS
3822 Group
(1) Ports P0, P1 (2) Ports P2, P42, P43, P50, P51
VL2/VL3
Pull-up control
VL1/VSS
Segment output enable bit
(Note) Direction register
Direction register
Data bus
VL1/VSS
Data bus
Pull-down control
Direction register
Direction register
19
MITSUBISHI MICROCOMPUTERS
3822 Group
Pull-up control
Pull-up control
Direction register
Direction register
20
MITSUBISHI MICROCOMPUTERS
3822 Group
Pul-up control
Pull-up control
Direction register
Direction register
Port XC switch bit + Pull-up control Port XC switch bit + Pull-up control
Oscillation circuit
Port P71 Sub-clock generating circuit input
VL2/VL3
VL3
21
MITSUBISHI MICROCOMPUTERS
3822 Group
22
MITSUBISHI MICROCOMPUTERS
3822 Group
b7 b0
Interrupt edge selection register
(INTEDGE : address 003A 16)
b7 b0 b7 b0
Interrupt request register 1 Interrupt request register 2
(IREQ1 : address 003C 16) (IREQ2 : address 003D 16)
b7 b0 b7 b0
Interrupt control register 1 Interrupt control register 2
(ICON1 : address 003E 16) (ICON2 : address 003F 16 )
23
MITSUBISHI MICROCOMPUTERS
3822 Group
Key Input Interrupt (Key-on wake-up) “1” to “0”. An example of using a key input interrupt is shown in
A Key-on wake-up interrupt request is generated by applying a Figure 20, where an interrupt request is generated by pressing
falling edge to any pin of port P2 that have been set to input mode. one of the keys consisted as an active-low key matrix which inputs
In other words, it is generated when AND of input level goes from to ports P20–P23.
Port PXX
“L” level output
PULL register A bit 2 = “1” Port P27 Key input interrupt request
direction register = “1”
✽ ✽✽ Port P27
latch
P27 output
Port P26
direction register = “1”
✽ ✽✽ Port P26
latch
P26 output
Port P25
direction register = “1”
✽ ✽✽ Port P25
latch
P25 output
Port P24
direction register = “1”
✽ ✽✽ Port P24
latch
P24 output
Port P23
direction register = “0” Port P2
✽ ✽✽ Port P23 Input reading circuit
P23 input latch
Port P22
direction register = “0”
✽ ✽✽ Port P22
latch
P22 input
Port P21
direction register = “0”
✽ ✽✽ Port P21
latch
P21 input
Port P20
direction register = “0”
✽ ✽ Port P20
latch
P20 input
Fig. 20 Connection example when using key input interrupt and port P2 block diagram
24
MITSUBISHI MICROCOMPUTERS
3822 Group
25
MITSUBISHI MICROCOMPUTERS
3822 Group
26
MITSUBISHI MICROCOMPUTERS
3822 Group
Timer Y
Timer Y is a 16-bit timer that can be selected in one of four modes.
b7 b0
(1) Timer Mode Timer Y mode register
(TYM : address 002816)
The timer counts f(XIN)/16 (or f(X CIN)/16 in low-speed mode).
Not used (return “0” when read)
Timer Y operating mode bits
(2) Period Measurement Mode b5 b4
0 0 : Timer mode
CNTR 1 interrupt request is generated at rising/falling edge of 0 1 : Period measurement mode
CNTR1 pin input signal. Simultaneously, the value in timer Y latch 1 0 : Event counter mode
1 1 : Pulse width HL continuously measurement
is reloaded in timer Y and timer Y continues counting down. Ex- mode
cept for the above-mentioned, the operation in period CNT R1 active edge switch bit
0 : Count at rising edge in event counter mode
measurement mode is the same as in timer mode. Measure the falling edge to falling edge
period in period measurement mode
The timer value just before the reloading at rising/falling of CNTR1 Falling edge active for CNTR1 interrupt
pin input signal is retained until the timer Y is read once after the 1 : Count at falling edge in event counter mode
Measure the rising edge period in period
reload. measurement mode
The rising/falling timing of CNTR1 pin input signal is found by Rising edge active for CNT R1 interrupt
Timer Y stop control bit
CNTR 1 interrupt. When using a timer in this mode, set the corre- 0 : Count start
1 : Count stop
sponding port P55 direction register to input mode.
27
MITSUBISHI MICROCOMPUTERS
3822 Group
28
MITSUBISHI MICROCOMPUTERS
3822 Group
Data bus
Shift clock
Clock control circuit
P46/SCLK
Serial I/O
clock selection bit
BRG count source selection bit Frequency division ratio 1/(n+1)
f(XIN) Baud rate generator 1/4
(f(XCIN) in low-speed mode) Address 001C16
1/4
TBE = 0 RBF = 1
TBE = 1 TSC = 1
TSC = 0 Overrun error (OE)
detection
Notes 1 : T he transmit interrupt (TI) can be generated either when the transmit buffer register has emptied (TBE=1) or after the transmit
shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is
output continuously from the TXD pin.
3 : T he receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
29
MITSUBISHI MICROCOMPUTERS
3822 Group
(2) Asynchronous Serial I/O (UART) Mode ter, but the two buffers have the same address in memory. Since
Clock asynchronous serial I/O mode (UART) can be selected by the shift register cannot be written to or read from directly, transmit
clearing the serial I/O mode selection bit of the serial I/O control data is written to the transmit buffer, and receive data is read from
register to “0”. the receive buffer.
Eight serial data transfer formats can be selected, and the transfer The transmit buffer can also hold the next data to be transmitted,
formats used by a transmitter and receiver must be identical. and the receive buffer register can hold a character while the next
The transmit and receive shift registers each have a buffer regis- character is being received.
Data bus
Address 001816
Serial I/O control register Address 001A16
OE Receive buffer register Receive buffer full flag (RBF)
Character length selection bit Receive interrupt request (RI)
P44/RXD STdetector 7 bits Receive shift register
8 bits 1/16
PE FE SP detector UART control register
Clock control circuit Address 001B16
Data bus
TBE=0 TBE=0
TSC=0
TBE=1 TBE=1 TSC=1✽
RBF=0
RBF=1 RBF=1
Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1” by the setting of the transmit interrupt source
selection bit (TIC) of the serial I/O control register.
3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.
4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
30
MITSUBISHI MICROCOMPUTERS
3822 Group
31
MITSUBISHI MICROCOMPUTERS
3822 Group
b7 b0 b7 b0
Serial I/O status register Serial I/O control register
(SIOSTS : address 001916) (SIOCON : address 001A16)
Transmit buffer empty flag (TBE) BRG count source selection bit (CSS)
0: Buffer full 0: f(XIN) (f(XCIN) in low-speed mode)
1: Buffer empty 1: f(XIN)/4 (f(XCIN)/4 in low-speed mode)
Receive buffer full flag (RBF) Serial I/O synchronization clock selection bit (SCS)
0: Buffer empty 0: BRG output divided by 4 when clock synchronized serial
1: Buffer full I/O is selected.
BRG output divided by 16 when UART is selected.
Transmit shift register shift completion flag (TSC) 1: External clock input when clock synchronized serial I/O is
0: Transmit shift in progress selected.
1: Transmit shift completed External clock input divided by 16 when UART is selected.
Parity error flag (PE) Transmit interrupt source selection bit (TIC)
0: No error 0: Interrupt when transmit buffer has emptied
1: Parity error 1: Interrupt when transmit shift operation is completed
Not used (returns “1” when read) Serial I/O mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
32
MITSUBISHI MICROCOMPUTERS
3822 Group
A-D CONVERTER
[A-D Conversion Register (AD)] 003516
The A-D conversion register is a read-only register that contains b7 b0
A-D control register
the result of an A-D conversion. When reading this register during (ADCON : address 003416)
an A-D conversion, the previous conversion result is read. Analog input pin selection bits
0 0 0 : P60/AN0
0 0 1 : P61/AN1
[A-D Control Register (ADCON)] 003416 0 1 0 : P62/AN2
The A-D control register controls the A-D conversion process. Bits 0 1 1 : P63/AN3
0 to 2 of this register select specific analog input pins. Bit 3 signals 1 0 0 : P64/AN4
the completion of an A-D conversion. The value of this bit remains 1 0 1 : P65/AN5
1 1 0 : P66/AN6
at “0” during an A-D conversion, then changes to “1” when the A- 1 1 1 : P67/AN7
D conversion is completed. Writing “0” to this bit starts the A-D AD conversion completion bit
conversion. Bit 4 controls the transistor which breaks the through 0 : Conversion in progress
1 : Conversion completed
current of the resistor ladder. When bit 5, which is the AD external VREF input switch bit
trigger valid bit, is set to “1”, this bit enables A-D conversion even 0 : OFF
by a falling edge of an ADT input. Set ports which share with ADT 1 : ON
pins to input when using an A-D external trigger. AD external trigger valid bit
0 : A-D external trigger invalid
1 : A-D external trigger valid
[Comparison Voltage Generator] Interrupt source selection bit
The comparison voltage generator divides the voltage between 0 : Interrupt request at A-D
conversion completed
AVSS and VREF by 256, and outputs the divided voltages. 1 : Interrupt request at ADT
input falling
[Channel Selector] Not used (returns “0” when read)
Data bus
b7 b0
A-D control register
P57/ADT
AVSS VREF
Fig. 31 A-D converter block diagram
33
MITSUBISHI MICROCOMPUTERS
3822 Group
LCD DRIVE CONTROL CIRCUIT enable bit is set to “1” after data is set in the LCD mode register,
The 3822 group has the built-in Liquid Crystal Display (LCD) drive the segment output enable register and the LCD display RAM, the
control circuit consisting of the following. LCD drive control circuit starts reading the display data automati-
●LCD display RAM cally, performs the bias control and the duty ratio control, and
●Segment output enable register displays the data on the LCD panel.
●LCD mode register
●Selector Table 11 Maximum number of display pixels at each duty ratio
●Timing controller
Duty ratio Maximum number of display pixel
●Common driver
64 dots
●Segment driver 2
or 8 segment LCD 8 digits
●Bias control circuit
96 dots
A maximum of 32 segment output pins and 4 common output pins 3
or 8 segment LCD 12 digits
can be used.
Up to 128 pixels can be controlled for LCD display. When the LCD 128 dots
4
or 8 segment LCD 16 digits
b7 b0
Segment output enable register
(SEG : address 003816)
b7 b0
LCD mode register
(LM : address 003916)
Fig. 32 Structure of segment output enable register and LCD mode register
34
Data bus
Segment Segment Segment Segment Segment Segment Common Common Common Common
driver driver driver Bias control driver driver driver driver
driver driver driver
SEG0 SEG1 SEG2 SEG3 P34/SEG12 P16/SEG30 P17/SEG31 VSS VL1 VL2 VL3 COM0 COM1 COM2 COM3
35
MITSUBISHI MICROCOMPUTERS
3822 Group
Bias Control and Applied Voltage to LCD Table 12 Bias control and applied voltage to VL1–VL3
Power Input Pins Bias value Voltage value
To the LCD power input pins (VL1 –VL3 ), apply the voltage shown VL3 =VLCD
in Table 12 according to the bias value. 1/3 bias VL2 =2/3 VLCD
Select a bias value by the bias control bit (bit 2 of the LCD mode VL1 =1/3 VLCD
register).
VL3 =VLCD
1/2 bias
VL2 =VL1=1/2 V LCD
Common Pin and Duty Ratio Control
Note 1: V LCD is the maximum value of supplied voltage for the
The common pins (COM 0–COM 3) to be used are determined by
LCD panel.
duty ratio.
Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the
Table 13 Duty ratio control and common pins used
LCD mode register).
Duty Duty ratio selection bit
Common pins used
ratio Bit 1 Bit 0
2 0 1 COM0 , COM1 (Note 1)
3 1 0 COM0–COM2 (Note 2)
4 1 1 COM0–COM3
Notes1: COM2 and COM 3 are open.
2: COM3 is open.
VL3 VL3
R1 R4
VL2 VL2
R2
VL1 VL1
R3 R5
R1 = R2 = R3 R4 = R5
1/3 bias 1/2 bias
Fig. 34 Example of circuit at each bias
36
MITSUBISHI MICROCOMPUTERS
3822 Group
f(LCDCK)
Frame frequency =
(duty ratio)
B it
7 6 5 4 3 2 1 0
Address
004016 SEG1 SEG0
004116 SEG3 SEG2
004216 SEG5 SEG4
004316 SEG7 SEG6
004416 SEG9 SEG8
004516 SEG11 SEG10
004616 SEG13 SEG12
004716 SEG15 SEG14
004816 SEG17 SEG16
004916 SEG19 SEG18
004A16 SEG21 SEG20
004B16 SEG23 SEG22
004C16 SEG25 SEG24
004D16 SEG27 SEG26
004E16 SEG29 SEG28
004F16 SEG31 SEG30
COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
37
MITSUBISHI MICROCOMPUTERS
3822 Group
Internal logic
LCDCK timing
VL3
COM0 VL2=VL1
VSS
COM1
COM2
COM3
SEG0 VL3
VSS
OFF ON OFF ON
1/3 duty
VL3
COM0 VL2=VL1
VSS
COM1
COM2
SEG0 VL3
VSS
1/2 duty
VL3
COM0 VL2=VL1
VSS
COM1
SEG0 VL3
VSS
38
MITSUBISHI MICROCOMPUTERS
3822 Group
Internal logic
LCDCK timing
1/4 duty
Voltage level
VL3
COM0 VL2
VL1
VSS
COM1
COM2
COM3
VL3
SEG0
VSS
OFF ON OFF ON
1/3 duty
VL3
COM0 VL2
VL1
VSS
COM1
COM2
VL3
SEG0
VSS
1/2 duty
VL3
VL2
COM0 VL1
VSS
COM1
VL3
SEG0
VSS
39
MITSUBISHI MICROCOMPUTERS
3822 Group
b7 b0
φ output control register
(CKOUT : address 002A16)
40
MITSUBISHI MICROCOMPUTERS
3822 Group
RESET CIRCUIT
Power on
To reset the microcomputer, RESET pin should be held at an “L”
level for 2 µs or more. Then the RESET pin is returned to an “H” Power
source
level (the power source voltage should be between VCC(min.) and RESET VCC voltage
5.5 V, and the quartz-crystal oscillator should be stable), reset is 0V
released. After the reset is completed, the program starts from the Reset input
voltage VIL spec.
address contained in address FFFD 16 (high-order byte) and ad-
0V
dress FFFC 16 (low-order byte). Make sure that the reset input
voltage meets V IL spec. when a power source voltage passes
VCC(min.).
RESET VCC
XIN
RESET
Address
? ? ? ? FFFC FFFD ADH, ADL
Data ADH
ADL
SYNC
XIN : about 8000 cycles
41
MITSUBISHI MICROCOMPUTERS
3822 Group
42
MITSUBISHI MICROCOMPUTERS
3822 Group
Rf Rd Open
VCC
VSS
43
MITSUBISHI MICROCOMPUTERS
3822 Group
XCIN XCOUT
“1” “0”
Port XC switch bit
Timing φ
“0” (Internal system clock)
High-speed mode
or Low-speed mode
Main clock stop bit
Q S S Q Q S
Reset
Interrupt disable flag I
Interrupt request
Note : When using the low-speed mode, set the port XC switch bit to “1” .
44
MITSUBISHI MICROCOMPUTERS
3822 Group
Reset
CM6
Middle-spe ed mode (f(φ) = 1 MHz) High-speed mode (f(φ) = 4 MHz)
“1” “0”
CM7 = 0 (8 MHz selected) CM7 = 0 (8 MHz selected)
CM6 = 1 (Middle-speed) CM6 = 0 (High-speed)
CM5 = 0 (8 MHz oscillating) CM5 = 0 (8 MHz oscillating)
CM4 = 0 (32 kHz sto pped) CM4 = 0 (32 kHz sto pped)
C
“0”
“0
” “0 M4 “0”
4 CM”
“1
CM “0
” ” 6
“1
” 6
CM4
CM4
“1 M ”
“1”
“1”
C “0
” ”
“1
CM6
Middle-spe ed mode (f(φ) = 1 MHz) High-speed mode (f(φ) = 4 MHz)
CM7 = 0 (8 MHz selected) “1” “0”
CM7 = 0 (8 MHz selected)
CM6 = 1 (Middle-speed) CM6 = 0 (High-speed)
CM5 = 0 (8 MHz oscillating) CM5 = 0 (8 MHz oscillating)
CM4 = 1 (32 kHz oscillatin g) CM4 = 1 (32 kHz oscillating)
“0”
“0”
CM7
CM7
“1”
“1”
CM6
Low-spee d mode (f(φ) = 16 kHz) L ow-speed mode (f(φ) =16 kHz)
“1” “0” CM7 = 1 (32 kHz selected)
CM7 = 1 (32 kHz sele cted)
CM6 = 1 (Middle-speed) CM6 = 0 (High-speed) b7 b4
CM5 = 0 (8 MHz oscillating) CM5 = 0 (8 MHz oscillating)
CM4 = 1 (32 kHz oscillatin g) CM4 = 1 (32 kHz oscillating) CPU mode register
(CPUM : address 003B16)
C
“0 M5
“0”
“0”
CM5
“1”
” “0 0: Oscillating
“1 ”
1: Stopped
CM6 : Main clock division ratio selection bit
CM6 L ow-speed mode (f(φ) =16 kHz)
0: f(XIN)/2 (high-speed mode)
Low-speed mode (f(φ) = 1 6 kHz)
CM7 = 1 (32 kHz sele cted) “1” “0” 1: f(XIN)/8 (middle-speed mode)
CM7=1(3 2 kHz selected)
CM6 = 1 (Middle-speed) CM6=0(High -spe ed) CM7 : Internal system clock selection bit
CM5 = 1 (8 MHz stopped ) CM5=1(8 MHz stop ped) 0: XIN–XOUT selected
CM4 = 1 (32 kHz oscillatin g) CM4=1(3 2 kHz oscillating) (middle-/high-speed mode)
1: XCIN–XCOUT selected
(low-speed mode)
Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2 : T he all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is
ended.
3 : T imer and LCD operate in the wait mode.
4 : When the stop mode is ended, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2 in middle-/high-speed mode.
5 : When the stop mode is ended, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2 in low-speed mode.
6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle-/high-speed mode.
7 : T he example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
45
MITSUBISHI MICROCOMPUTERS
3822 Group
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n + 1).
Ports
The contents of the port direction registers cannot be read.
The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis-
ter as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a
direction register
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an ex-
ternal clock and it is to output the S RDY signal, set the transmit
enable bit, the receive enable bit, and the SRDY output enable bit
to “1”.
Serial I/O continues to output the final bit from the TXD pin after
transmission is completed.
46
MITSUBISHI MICROCOMPUTERS
3822 Group
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 46 is recommended to verify programming.
Screening (Caution)
(150°C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
47
MITSUBISHI MICROCOMPUTERS
3822 Group
48
MITSUBISHI MICROCOMPUTERS
3822 Group
49
MITSUBISHI MICROCOMPUTERS
3822 Group
50
MITSUBISHI MICROCOMPUTERS
3822 Group
51
MITSUBISHI MICROCOMPUTERS
3822 Group
52
MITSUBISHI MICROCOMPUTERS
3822 Group
53
MITSUBISHI MICROCOMPUTERS
3822 Group
54
MITSUBISHI MICROCOMPUTERS
3822 Group
55
MITSUBISHI MICROCOMPUTERS
3822 Group
56
MITSUBISHI MICROCOMPUTERS
3822 Group
57
MITSUBISHI MICROCOMPUTERS
3822 Group
58
MITSUBISHI MICROCOMPUTERS
3822 Group
59
MITSUBISHI MICROCOMPUTERS
3822 Group
60
MITSUBISHI MICROCOMPUTERS
3822 Group
61
MITSUBISHI MICROCOMPUTERS
3822 Group
62
MITSUBISHI MICROCOMPUTERS
3822 Group
63
MITSUBISHI MICROCOMPUTERS
3822 Group
64
MITSUBISHI MICROCOMPUTERS
3822 Group
65
MITSUBISHI MICROCOMPUTERS
3822 Group
66
MITSUBISHI MICROCOMPUTERS
3822 Group
67
MITSUBISHI MICROCOMPUTERS
3822 Group
68
MITSUBISHI MICROCOMPUTERS
3822 Group
69
MITSUBISHI MICROCOMPUTERS
3822 Group
70
MITSUBISHI MICROCOMPUTERS
3822 Group
71
MITSUBISHI MICROCOMPUTERS
3822 Group
100 pF 1 kΩ
100 pF
CMOS output
72
MITSUBISHI MICROCOMPUTERS
3822 Group
tC(CNTR)
tWH(CNTR) tWL(CNTR)
CNTR0, CNTR1
0.8VCC 0.2VCC
tWH(INT) tWL(INT)
INT0–INT3 0.8VCC 0.2VCC
tW(RESET)
RESET 0.8VCC
0.2VCC
tC(XIN)
tWH(XIN) tWL(XIN)
XIN 0.8VCC
0.2VCC
tC(SCLK)
tf tWL(SCLK) tr tWH(SCLK)
SCLK
0.2VCC 0.8VCC
tsu(RXD-SCLK) th(SCLK-RXD)
RX D 0.8VCC
0.2VCC
td(SCLK-TXD) tv(SCLK-TXD)
T XD
73
MITSUBISHI MICROCOMPUTERS
3822 Group
PACKAGE OUTLINE
80P6N-A MMP Plastic 80pin 14✕20mm body QFP
EIAJ Package Code JEDEC Code Weight(g) Lead Material
QFP80-P-1420-0.80 – 1.58 Alloy 42 MD
e
HD
D
ME
80 65
b2
1 64
I2
A – – 3.05
A1 0 0.1 0.2
A2 – 2.8 –
b 0.3 0.35 0.45
c 0.13 0.15 0.2
24 41 D 13.8 14.0 14.2
E 19.8 20.0 20.2
e – 0.8 –
25 40 A
HD 16.5 16.8 17.1
L1 HE 22.5 22.8 23.1
L 0.4 0.6 0.8
L1 – 1.4 –
A2
x – – 0.2
y – – 0.1
c
F 0° – 10°
e
A1
b x M L b2 – 0.5 –
y Detail F I2 1.3 – –
MD – 14.6 –
ME – 20.6 –
HD
D
ME
80 61
b2
1 60
I2
A – – 3.05
A1 0 0.1 0.2
A2 – 2.8 –
b 0.25 0.3 0.4
20 41
c 0.13 0.15 0.2
D 13.8 14.0 14.2
E 13.8 14.0 14.2
21 40 A e – 0.65 –
L1 HD 16.5 16.8 17.1
HE 16.5 16.8 17.1
L 0.4 0.6 0.8
L1 – 1.4 –
A2
F x – – 0.13
y – – 0.1
c
e b x M 0° – 10°
y b2 – 0.35 –
A1
L
Detail F I2 1.3 – –
MD – 14.6 –
ME – 14.6 –
74
MITSUBISHI MICROCOMPUTERS
3822 Group
e
HD
ME
D
b2
80 61
l2
1 60 Recommended Mount Pad
Dimension in Millimeters
Symbol
Min Nom Max
A – – 1.7
HE
E
A1 0 0.1 0.2
A2 – 1.4 –
b 0.13 0.18 0.28
c 0.105 0.125 0.175
20 41
D 11.9 12.0 12.1
E 11.9 12.0 12.1
21 40 e – 0.5 –
HD 13.8 14.0 14.2
A
HE 13.8 14.0 14.2
L1 L 0.3 0.5 0.7
F L1 – 1.0 –
e
Lp 0.45 0.6 0.75
A3 – 0.25 –
A2
A3
x – – 0.08
y – – 0.1
b 0° – 10°
A1
x M y L
c
b2 – 0.225 –
Detail F Lp I2 0.9 – –
MD – 12.4 –
ME – 12.4 –
75
HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN
(1/2)
REVISION HISTORY 3822 GROUP DATA SHEET
(2/2)