EASWARI ENGINEERING COLLEGE Format No : LP-01

Department of Electronics and Communication Engineering

Issue No : 01
LESSON PLAN
Issue Date : 05.05.06

Subject code : VL7101 Degree / Branch: M.E / VLSI Design

Subject Name : VLSI Signal Processing
Year : I Year / I Semester
Faculty : Dr. G.R.Suresh
Total No. of hrs given in syllabus
Tutorial : 0
Lecture : 45
Grand Total : 45 Periods

COURSE OBJECTIVES:
 To understand the various VLSI architectures for digital signal processing.
 To know the techniques of critical path and algorithmic strength reduction in the filter
structures.
 To study the performance parameters, viz. area, speed and power.

COURSE OUTCOMES:
 To be able to design architectures for DSP algorithms.
 To be able to optimize design in terms of area, speed and power.
 To be able to incorporate pipeline based architectures in the design.
 To be able to carry out HDL simulation of various DSP algorithms.

Session
Topics to be covered No. of Periods Ref Page no.
No
UNIT I – INTRODUCTION
Objective: To understand the basic concepts of signal processing in VLSI architecture
1 Overview of DSP 1 R2 1
2 FPGA Technology 1 R2 3
3 DSP Technology requirements 1 R2 10
4 Design Implementation 1 R2 13
5 FPGA structure 1 R2 18
Case study: frequency synthesizer,
6 1 R2 35
Design with intellectual property cores

UNIT II METHODS OF CRITICAL PATH REDUCTION

Objective: To understand different methods in critical path reduction
7 Binary Adders, Binary Multipliers 1 R2 74, 82
Multiply-Accumulator (MAC) and sum of product
8, 9 (SOP)
2 R2 114
10,11,12 Pipelining and parallel processing 3 R1 (Ch.3) 63
 13, 14 retiming 2 R1(Ch.4) 91
15, 16 unfolding 2 R1(Ch.5) 119
17,18 systolic architecture design 2 R1(Ch.7) 189

UNIT III ALGORITHMIC STRENGTH REDUCTION METHODS AND RECURSIVE FILTER

DESIGN
Objective: To understand the concepts on algorithmic strength reduction methods and recursive
filter design.
Fast convolution: Introduction 227,
19 Cook-toom algorithm, Winograd algorithm,
1 R1(Ch.8)
228,237
20 Iterated convolution, Cyclic convolution 1 R1 244,246
design of fast convolution algorithm by
21 inspection
1 R1 250
pipelined and parallel processing of
22 recursive and adaptive filters: 1 R1(Ch.10) 313,314
Introduction, Pipeline interleaving in digital filters
Pipelining in 1st order and higher order IIR digital
23 filters
1 R1 320, 325
24 Parallel processing for IIR filters 1 R1 339
Combined pipelining and parallel processing for
25 IIR filters
1 R1 345
fast IIR filters design:
26 Low power IIR filter design using pipelining and 1 R1 348
parallel processing
27 Pipelined adaptive digital filters 1 R1 351

UNIT-IV DESIGN OF PIPELINED DIGITAL FILTERS

Objective: To understand the procedures involved in the design of pipelined digital filters
Designing FIR filters, Digital lattice filter
structures:
28 Introduction, Schur algorithm, digital basic lattice
1 R1(Ch.12) 421
filters
Derivation of one-multiplier, normalized ,scaled-
29 normalized lattice filters
1 R1 437
bit level arithmetic architecture:
30 Introduction, parallel multipliers, Interleaved floor 1 R1(Ch.13) 477
plan and bit plane based digital filters
Bit serial multipliers
31 Bit serial filter design and implementation
1 R1 490
redundant arithmetic:
redundant number representation, carry free
32 radix-2 addition and subtraction, hybrid radix-4
1 R1(Ch.14) 529
addition
Radix-2 hybrid redundant multiplication
33 architecture, Data format conversion, Redundant 1 R1 540
to non redundant converter
 scaling and round-off noise:
34 state variable description of digital filters, scaling 1 R1(Ch.11) 377
and round off noise computation
35 Round off noise in pipelined IIR filters, 1 R1 391
Round off noise computation using state
36 1 R1 403
variable description.

UNIT –V SYNCHRONOUS ASYNCHRONOUS PIPELINING AND PROGRAMMABLE DSP

Objective: To understand the basic concepts on synchronous and asynchronous pipelining and
programmable DSP
Numeric strength reduction:
37 Sub expression elimination, Multiple constant 1 R1(Ch.15) 559
multiplication
Sub expression sharing in digital filters
38 Adaptive and multiplicative number splitting
1 R1 566
synchronous – wave and asynchronous
pipelines
39 clock skew and clock distribution in bit level
1 R1(Ch.16) 591
pipelined VLSI design,
Wave pipelining, constraint space diagram and
40 degree of wave pipelining
R1 606
asynchronous pipelining, signal transition graph,
41 implementation of computational units
1 R1 619
low power design
42 Scaling vs power consumption, power analysis,
1 R1(Ch.17) 645
power reduction techniques, power estimation
43 approaches
1 R1 662
programmable DSPs
44 Introduction, evolution of DSP processors
R1(Ch.18) 695
DSP architectural features/alternatives for
45 high performance and low power
1 R1 697

REFERENCES:

1. Keshab K.Parhi, “VLSI Digital Signal Processing Systems, Design and

Implementation”, John Wiley, Indian Reprint, 2007.
2. U. Meyer – Baese, "Digital Signal Processing with Field Programmable
Arrays", Springer, Second Edition, Indian Reprint, 2007.
3. S.Y.Kuang, H.J. White house, T. Kailath, “VLSI and Modern Signal
Processing”, Prentice Hall, 1995.

Prepared by Approved by
(G.R.Suresh) HOD/ECE