‫أﺳﺋﻠﺔ اﻟـ‬

Assignment
 Assignment

1. Illustrate the bus interconnection schema and also illustrate the operation
of the bus.
 The bus interconnection schema:

 The operation of the bus:

I. Data Bus:
 Consist of set of lines (data bus width).
 If data = 64 bit & bus width = 32 bit, you need 2 cycles.

II. Address Bus:

 Width represents max accessible memory address.
 Can hold memory or I/O device address.

Higher order bits for module to connect with (memory, I/O)

The remaining part is the address.

Module Address

X1010011
X=0 memory
X= 1 I/O
III. Control Bus
 Used to control the access and the use of the data and address lines.
 Because the data and address lines are shared by all components there must be a means of controlling their use.
2. Discuss with drawing the difference between interrupts: (short I/O wait,
long I/O wait)
 Short I/O wait:

1. User program is running in (1).

2. The write command interrupted the normal execution of the program.
 Processor execute program called Interrupt-Service-Routine (Interrupt Handler).
3. I/O operation prepares the command and sends command to device in (4).
4. Return execution in the user program in (2a) until the device be ready.
5. When the device is ready, interrupt sign is send.
6. Start the I/O operation in (5) =< (I/O operation Concurrent with processor executing).
7. Return execution in the user program in (2b).
8. Another write command interrupted the normal execution of the program.
9. I/O operation prepares the command and sends command to device in (4).
10. Return execution in the user program in (3a) until the device be ready.
11. When the device is ready, interrupt sign is send.
12. Start the I/O operation in (5) =< (I/O operation Concurrent with processor executing).
13. Return execution in the user program in (3b).
14. And so on…
 Instruction is executed one by one.
 The current system state is saved in memory before serving interrupt request.
 When Interrupt -Service-Routine completed, the state is restored from memory by processor and the
interrupt program continues.
  long I/O wait:
1. User program is running in (1).
2. The write command interrupted the normal execution of the program.
 Processor execute program called Interrupt-Service-Routine (Interrupt Handler).
3. I/O operation prepares the command and sends command to device in (4).
4. Return execution in the user program in (2) until the device be ready. =< (I/O operation Concurrent with
processor executing then processor waits).
5. When the device is ready, interrupt sign is send.
6. In the same time, another write command arrived.
 Instruction is executed one by one.
7. Start the I/O operation in (5).
8. When the I/O operation ends ,Go to the next Instruction (write command -2)
9. Write command interrupted the normal execution of the program.
10. I/O operation prepares the command and sends command to device in (4).
11. Return execution in the user program in (3) until the device be ready. =< (I/O operation Concurrent with
processor executing then processor waits).
12. When the device is ready, interrupt sign is send
13. In the same time, another write command arrived.
 Instruction is executed one by one.
14. Start the I/O operation in (5).
15. When the I/O operation ends ,Go to the next Instruction (write command -3)
16. And so on…
 Instruction is executed one by one.
 The current system state is saved in memory before serving interrupt request.
 When Interrupt -Service-Routine completed, the state is restored from memory by processor and the
interrupt program continues.
3. Illustrate and draw the flowchart for the read operation in cache system

The cashe contains a copy of portions of main memory

• When the processor attempts to read a word of memory, a check is made
to determine if the word is in the cashe. If so, the word is delivered to the
processor.
• If not, a block of main memory, consisting of some fixed number of words,
is read into the cashe and then the word is delivered to the processor.