Computer Organization

Lab 15
Logic Distinction
Combination Logic
Compute output based on input only 𝑋
𝑆
Output is function of input
𝑌
Clock is not required in such logic blocks Combinational Logic
Sequential Logic 𝐶𝑜𝑢𝑡
Storing data 𝐶𝑖𝑛
Contains memory element
Registers 𝑖𝑛1 𝑂1
Clock is an essential element 𝑖𝑛2
Combinational Logic
𝑂2

𝐹𝑏
Memory
Sequential Elements
Register: stores data in a circuit
Uses a clock signal to determine when to update the stored value
Edge-triggered: update when 𝑪𝒍𝒌 changes from 0 to 1

Clk
D Q
D

Clk
Q
Template for inferring Physical Register
always@(posedge clk or posedge rst)
begin RegA
if (rst == 1)
data_in
begin
RegA <= 0;
end
else rst_n
begin
RegA <= data_in;
end
end
Behavioral Modeling - Assignment
A statement within a procedural block is called a procedural statement

An assignment within a procedural block is called a procedural assignment

Procedural assignment can either be:

Blocking ( = operator)
▪ Acts in a similar fashion to MIPS or C
Non-blocking (<= operator)
▪ Evaluates all the LHS for current time unit and assign the values at the end of that time unit
 Assume 𝒂 = 𝟏𝟎 and 𝒃 = 𝟏𝟓
Example
a=?
always@(*) begin b=?
a = 5;
b = a;
end

a=?
always@(posedge clk) begin b=?
a <= 5;
b <= a;
end
Task 1 (Counter)
A counter is a circuit that can
count from some between
two numbers with a pre-
defined increment.
Write Verilog code for the
circuit shown in the figure
that counts in increments of 𝟏
starting at 𝟎.
Extend this code such that another input by the
name of Start controls if counting starts or not
Task-1
Extend on the previous code such
that you have a ROM (8 × 19) where
depth is 8 and each location is 19 bit
wide. ROM
Here the counter acts as an address Counter (Program
of ROM fetching each value from it. Start Data
Memory)
Clock
Module Calling
 IN OUT
My_Design_1

Module Instantiating module My_Design_1(IN, OUT);

Let us consider that module (topmodule) wants to use another input IN;
module (My_Design_1) by calling it inside main logic ouput OUT;
.
Top-most Module (Calling Module) .
endmodule
Output port is of type
Input “wire” by default; it
module topmodule(…..);
port is of can be redefined as reg in; //can be wire or reg
type
“wire”
“reg” wire out; //can be wire only

My_Design_1 //ModuleName OBJNAME (Ports In

Input port is Output port is defined
defined as as wire only
order);
either reg or My_Design_1 uut (a, b);
wire
endmodule
 module Calling_Module(input a, output c);
reg b;

Module Instantiating wire c_t, d_t;

My_Design_1 uut (a, c_t);
Top-most Module (Calling Module) My_Design_1 uut2 (b, d_t);
My_Design_2 uut3 (c_t, d_t, c);
𝒂 c_t
My_Design_1 .
𝒄
My_Design_2 .
endmodule
b d_t
My_Design_1
uut, uut2 and uut3
User defined Object
names for modules
Task 3:
Using the code of half adder we
intend to implement a full adder
(by use of module calling)
 clk
ROM
Task 4:

ALU
rst

PC
Instr.
We intend to use the previously Memory Control out
build code and design a simple ALU Signals
based process which takes input Datapath
directly from instruction. Control Unit
ROM: 8𝑥19
PC: 3-bit Control Signals:
In this example control signals are as follows:
ALU: Based on previous week
• Opcode
• A
• B