HP 250 g7 Compal La-G07fp Epw50 Rev 1.0 (v0.3)

A B C D E
https://vinafix.com
1 1
Compal LA-G07FP
2
Intel M/B Schematics Document 2
Kabylake-U(2+2)-DDR4 SODIMMx2
nVidia N16 gDDR5-2GB
(N16S-GTR : GM108-670/770: GeForce MX130)
(N16V-GMR1 : GM108-626/726:GeForce MX110)
3 3
Project :2018OPP_Harry Potter(15.6")

EPW50 :LA-G07FP
Date : 2018-01-08
Version : 1.0
4 4
(Modified&Ref from:
01."NFLC_KBLR_LAE802PR10_MV_FINAL") Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/10/22 DecipheredDate 2017/10/22 Title
(02."Canadiens_LA-F035P-R10_KBL-UR_2017-06-23_CPU) Cover Page
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENSTiIzAeL Document Number
(02."CNL-U ORB_DDX02_LA-F152PR01_0822B") AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EPW50_LA- G07FP v0.3
Date: 1 of 59
A B C D E
Monday, January 08, 2018 Sheet
A B C D E
UV6 UV7 ChA:JDIIIIMM1(REV)

UV8 UV9(for 4GB) UV1 UC1 ChB:JDIIIIMM2(STD) https://vinafix.com
VRAM nVidia PCIex4
gDDR5x4pcs N16S-GTR (MX130)
DDR4-SO-DIMM X 2
Port #1~#4 Dual Channel Interleaved
N16V-GMR1 (MX110) P.17~18
256Mbx32 PCIe 3.0:8Gb/s
(8Gb) DDR4 2133MHz 1.2V
P.25 P.19~26
1 1
JHDD
SATA 3.0 Port 0
P.30 2.5" SATA HDD *sub board
(sub board) LS-G072P
DA4002LZ000
JEDP
eDPx2Lane JODD
eDP CONN SATA 3.0 Port 1 M.2 SATA SSD *sub board
P.27 SATA ODD P.30 (sub board) LS-G074P

DA6001WR00S
Kaby Lake-RU42 *sub board
JHDMI eMMC
(sub board) LS-G075P
JSSD DA6001WS00S
HDMI CONN DDI x4Lane Port 1
PCIe 3.0: 8Gb/s PCIe x2 M.2 SSD(Key M)NVMe
P.28 P.19
Port #11~#12 *need supported Intel Optane (3D Xpoint)
SATA 3.0 Port 2

JLAN UL1
RJ45 CONN LAN PCIex1 Port#5
P.29 RTL8111HSH-CG P.29 PCIe Gen1 Only:2.5Gb/s
2 JWLAN USB3.0 2
NGFF WLAN+BT PCIex1 Port#6 5Gb/s

(Key E) P.30 PCIe Gen1 Only:2.5Gb/s
JUSB1
USB2.0 Port 1 USB3.0 port Port 1
1356P BGA 480Mb/s P.30
JUSB2
Port 2 Port 2
USB3.0 port P.31
JIO
Port 3
USB2.0 Port P.31
*sub board
PUB1 PJPB1 LS-G071PR01
Port 4 Card Reader DA6001WJ000
Charger Battery AK6485RB63-GLF-GR P.29
(sub board)
P.47 P.46
UK1
JEDP
SMBus1
EC ENE LPC Port 5 Camera P.27
3
KB9022QD 33MHz 3
SMBus2
P.33 JWLAN
Port 6
UV1 UC3 Bluetooth
PS2 P.30
dGPU Thermal sensor JKB JTP
G753T11U P.10 Int.KBD TouchPad JEDP
P.22 SMBus Port 7
P.34 P.34 Touch Screen P.27
*sub board
JFAN JKBL LS-G073PR01
DA4002M0000
Fan KB light
75x70 P.38 P.34 SPI UA1 JSPK
50MHz
UC2 HDA 24MHz HDA Aduio codec Internal SPK P.32
SPI ROM ALC3247-CG
8MBytes P.07 P.32 JHP
Combo Jack
P.32
UT1
TPM
SLB9670VQ2.0
4 P.35 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/08/24 Deciphered Date 2018/08/24 Title
TH IS S H E E T O F E N G I N E E R I N G D R A W I N G IS T H E P R O P R IE TA R Y P R O P E R T Y O F C O M P A L E L E C TR O N IC S , IN C . A N D C O N TA IN S CONFIDENT I A L
Block Diagrams
S iii ze Document Number Rev
A N D T R A D E S E C R E T IN F O R M A T I O N . TH IS S H E E T M A Y N O T B E T R A N S F E R E D F R O M T H E C U S T O D Y O F T H E C O M P E T E N T D IV IS IO N O F R & D
D E P A R TM E N T E X C E P T A S A U TH O R I Z E D B Y C O M P A L E L E C TR O N IC S , IN C . N E ITH E R TH IS S H E E T N O R T H E I N F O R M A T I O N IT C O N TA IN S Custom v0.3
M A Y B E U S E D B Y O R D IS C L O S E D T O A N Y TH IR D P A R T Y W I T H O U T P R I O R W R I T T E N C O N S E N T O F C O M P A L E L E C TR O N IC S , IN C . LA-G07FP(KBL-U_UMA_6L)
Date: Monday, January 08, 2018 Sheet 2 of 59
A B C D E
5 4 3 2 1
+5VALW/+3VALW
AC
Adapter 19.5V
(SY8288C/SY8286B) https://vinafix.com
P.45 Vout +3VALW +3VALW

Vout +1.8V_PRIM
Vin G5719
EC_ON Vout +5VALW PCH_PWR_EN PGOOD +1.8V_PG
D
EN EN D
P.51
Charge Charger +19.5VB

BQ24725 Vin
+3VALW
Vout +2.5V
Vin G5719
P.47
PM_SLP_S4# PGOOD +2.5V_PG
EN
P.49
PGOOD SPOK
DC Discharge P.48
Battery
P.46
+1.2V/+0.6VS
Vin(G5616B)
Vout +0.6V_0.6VS
+2.5V_PG Vout +1.2V_VDDQ
EN S5
C C
SM_PG_CTRL
EN S3
P.49
+1.0V_PRIM Vout +1.0V_PRIM

Vin (SY8286R)
+1.8V_PG PGOOD
EN +1.0V_VS_PG_PWR
P.50
CPU_CORE Vout +VCC_CORE

Vin (RT3602AE) Vout +VCC_GT
VR_ON Vout +VCC_SA
EN
B PGOOD VR_PWRGD B
P.52,53
+VGA_CORE
Vin (RT8812A) Vout +VGA_CORE
VRAM_PG
EN PGOOD GPU_PGD
P.56
+1.35VS_VGA Vout +1.35VS_VGA

Vin (SY8286R)
A A
DGPU_PWR_EN PGOOD VRAM_PG

EN
P.55

Power Block Diagram Vinafix.com
THIS S H E E T O F ENGINEERING D R AW IN G IS TH E P R O P R IE TA R Y P R O P E R TY O F C O M P A L ELECTRONICS,,, INC. A N D CONTAINS CONFIDENT II A L
S i z e Document Number
A N D TR A D E S E C R ET IN F O R M A TIO N . THIS S H E E T M A Y N O T B E TR A N S F E RE D F R O M TH E C U S TO D Y O F TH E C O M P E TE N T DIVISION O F R & D Rev
D E P A RTM E NT E X C EP T A S A U TH O R IZ E D B Y C O M P A L E L E C TR O NIC S , INC. NEIIITHER THIS S H E E T N O R TH E IN F O R M A TIO N IIIT CONTAINS LA-G07FP(KBL-U_UMA_6L) v0.3
M A Y B E U S E D B Y O R D IS C L O S ED TO A N Y TH IR D P A R TY W ITH O U T P R IO R W R ITTE N C O N S E NT O F C O M P A L E L E CTR O N IC S, IIINC...
Dattte: Friday,,, January 05,,, 2018 Sheett 58 of 59
5 4 3 2 1
A B C D E
Power rail Control (EC) Source (CPU)

EC SMBUS Address Table (TBC)
+RTCVCC X X SOC SMBUS Address Table
VIN X X Address (8bit) EC_SMBUS Port Power Rail Device Address (7 bit)
BATT+ X X
SOC_SMBUS Net Name Power Rail Device Address (7 bit)
Write Read https://vinafix.com
B+ X X BAT 0x16
DIMM1 0x50 0xA0 0xA1
+VL X X SMBCLK SMBUS Port 1 +3VL_EC
+3VL X X SMBDATA +3V_PRIM DIMM2 0x52 0xA4 0xA5 CHGR 0x12
+5VALW EC_ON X
Touch PAD 0x2C 0x58 0x59
+3VALW EC_ON X dGPU
1
+3VALW _EC EC_ON X 1
+3V_PCH PCH_PWR_EN X Thermal

SMBUS Port 2 +3VS 0x90
+1.2V_VDDQ SYSON PM_SLP_S5#/PM_SLP_S4# i3_7100U_R1@ i3_7100U_R3@ MX110@ MX130@
Sensor
+5VS SUSP# PM_SLP_S3#
UC1 UC1 UV1 UV1
PCH
+3VS SUSP# PM_SLP_S3#
+1.5VS SUSP# PM_SLP_S3# i3_7100U i3_7100U N16V-GMR1-S-A2 N16S-GTR-S-A2
SA0000A38H0 SA0000A38J0 SA00009IT00 SA00009FP00
+1.05VS SUSP# PM_SLP_S3# S IC FJ8067702739738 SR343 H0 2.4GBGA S IC FJ8067702739738 SR343 H0 2.4G A32! S IC N16V-GMR1-S-A2 BGA 595P S IC N16S-GTR-S-A2 BGA 595PGPU
+0.6V_0.6VS SUSP#
+VCC_CORE X VR12.5_VR_ON U_i5_7200U_SR342@ i5_7200U_R3@ ZZZ ZZZ ZZZ ZZZ Power State
STATE SIGNAL
UC1 UC1 2G Micron 2G Micron 4G Micron 4G Micron
SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
S0 (Full ON) HIGH HIGH HIGH ON ON ON ON
BOM Structure Table (1/2) U_SI_i5-7200U_SR342 H0 2.5G
SA0000A37H0
i5_7200U
SA0000A37J0
M2G_R1@
X7674032L01
M2G_R3@
X7674032L06
M4G_R1@
X7674032L26
M4G_R3@
X7674032L29
S IC FJ8067702739739 SR342 H0 2.5GBGA S IC FJ8067702739739 SR342 H0 2.5GA32! S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
Function Stuff Un-Stuff
S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
DGPU SKU PX@ U_i7_7500U_SR341@ i7_7500U_R3@ ZZZ ZZZ ZZZ ZZZ
UMA SKU UMA@ S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
UC1 UC1 2G Hynix 2G Hynix 4G Hynix 4G Hynix
TPM TPM@
U_SI_i7-7500U_SR341 H0 2.7G i7_7500U H2G_R1@ H2G_R3@ H4G_R1@ H4G_R3@
SA0000A34F0 SA0000A34H0 X7674032L04 X7674032L07 X7674032L25 X7674032L28
S IC FJ8067702739740 SR341 H0 2.7GBGA S IC FJ8067702739740 SR341 H0 2.7G A32! <USB2.0 port>
45@ ROYALTY HDMI W/LOGO
ZZZ ZZZ ZZZ ZZZ

Part Number Description USB2.0 port DESTINATION
R_i5_8250U_QNEF@ i5_8250U_R3@ RO0000002HM HDMI W/Logo:RO0000002HM
2
2G Samsung 2G Samsung 4G Samsung 4G Samsung RO0000003HM
1 USB3.0 Type-C 2
UC1 UC1 2 USB2.0/USB3.0

R_i3_7020U_QN96@ R_i3_8130U_QP8K@
R_SI_i5_8250U_QNEF Y0 1.6G i5_8250U
S2G_R1@
X7674032L05
S2G_R3@
X7674032L08
S4G_R1@
X7674032L27
S4G_R3@
X7674032L30
3 USB2.0/USB3.0
UC1 UC1
SA0000AWB10 SA0000AWB30
S IC FJ8067703282221 SR3LA Y0 1.6G FCBGA S IC FJ8067703282221 SR3LA Y0 1.6GA32!
4 BT
5 HD/IR_1/IR_2 Camera
R_SI_i3_7020U_QN96 Y0 2.3G
SA0000BLD00
R_SI_i3-8130U_QP8K Y0 2.2G
SA0000BKN10 R_i7_8550U_SR3LC@ i7_8550U_R3@
6 IR_2 Camera
S IC A32 FJ8067703282620 QN96 Y0 2S.3GIC A32 FJ8067703282227 QP8K Y0 2.2G
7 Card Reader
R_i7_8550U_QNBF@ U_i3_7020U_QNZU@ UC1 UC1 DAX DAX DAX DAX ZZZ
8 X
R_SI_i7-8550U_SR3LC Y0 1.8G i7_8550U KBLU-2G KBLR-2G KBLU-4G KBLR-4G EMC for EE
9 X
UC1 UC1
SA0000AWC20 SA0000AWC30
S IC FJ8067703281816 SR3LC Y0 1.8G FCBGA S IC FJ8067703281816 SR3LC Y0 1.8G A32!
10 X
R_SI_i7_8550U_QNBF Y0 1.8G U_SI_i3-7020U_QNZU H0 2.3G KBLU_2G@ KBLR_2G@ KBLU_4G@ KBLR_4G@ X4E@
SA0000AWC10 SA0000BLH00 DA6001WM000 DA6001WI000 DA8001EH000 DA8001EI000 X4EABB32L01
S IC A32 FJ8067703281816 QNBF Y0 1S.8IGCA32 FJ8067702739769 QNZU H02.3G PCB 29M LA-G07AP REV0 MB 3 PCB 29L LA-G07CP REV0 MB 3
SMT EMC FOR EE AG07C EPW50
<PCI-E,SATA,USB3.0/CLK>
ZZZ ZZZ ZZZ ZZZ
Lane# PCI-E SATA USB3.0 DESTINATION CLK
DAZ_U2G DAZ_R2G DAZ_U4G DAZ_R4G
+3V_PRIM 1 1 USB3.0 Type-C X
UC1
+3VS
SO-DIMM A DAZ_U2G@ DAZ_R2G@ DAZ_U4G@ DAZ_R4G@
2 2 USB3.0 Type-C X
R=1K
+3V_PRIM R=10K
DAZ23T00600 DAZ23T00500 DAZ23T00600 DAZ23T00500
3 3 USB2.0/USB3.0 X
SMBCLK PCH_SMBCLK DAX DAX
R7 SMBDATA 2N7002 PCH_SMBDATA 4 4 USB2.0/USB3.0 X
R8 SO-DIMM B
KBLU-UMA KBLR-UMA
5 1 5 GPU(DIS only) CLK0
+3V_PRIM
+3VALW 6 2 6 GPU(DIS only)
CPU
KBLU_UMA@ KBLR_UMA@
3 R=499
+3V_PRIM R=10K DA6001YA000 DA6001YB000 7 3 GPU(DIS only) 3
SML0CLK TP_SMBCLK PCB 29M LA-G07FP REV0 M/B 3 PCB 29L LA-G07EP REV0 M/B 3
R9 8 4 GPU(DIS only)
SML0DATA 2N7002 TP_SMBDAT
W2 Touch Pad 9 5 LAN CLK1
10 6 WLAN CLK2
11 7 0 HDD X
+3V_PRIM+3VS +3VS +3VS_DGPU_AON
12 8 1a ODD CLK3
R=1K R=2.2K
13 9 X X
SML1CLK
+3VS_DGPU_AON
@ 14 10 X X
W3 SML1DATA
V3 2N7002 15 11 1b* X CLK4
EC_SMB_CK2 NVMe x2
EC_SMB_DA2 R=2.2K
16 12 2 SATA SSD X
PX@
U6 2N7002 DGPU
U7 I2CS_SCL
I2CS_SDA
U9 Thermal Sensor :G753T11U

U8 Address : 0x48
UK1:+3VALW_EC (+3VL)
EC_SMB_CK2
79 EC_SMB_DA2
4 4
80
EC +3V_SMBUS
R=2.2K
R=0
GSEN_I2DAT
GSEN_I2CLK G-Sensor
HP2DC
EC_SMB_CK1
77
EC_SMB_DA1 R=100
78 BAT
Issued Date 2016/12/15 2019/12/15 Title
Deciphered Date
Charger T HI S S HE E T O F ENGI I NEERI I NG D R AW I NG I S T HE P R O P R I E T AR Y P R O P E R T Y O F C O M P AL E L E C T R O NI C S , I NC . AND C O NT AI NS CONFIDENTSSIAizLe Document Number
Notes List
AND T R AD E S E C R E T I NF O R M AT I O N. T HI S S HE E T M AY NO T B E T R ANS F E R E D F R O M T HE C US T O D Y O F T HE C O M P E T E NT DI VI SI ON O F R & D Rev
D E P AR T M E NT E X C E P T AS AUT HO R I Z E D B Y C O M P AL E L E C T R O NI C S , I NC . NE I T HE R T HI S S HE E T NO R T HE I NF O R M AT I O N I T C O NT AI NS Custom
M AY B E US E D B Y O R D I S CL O S ED T O ANY T HI R D P AR T Y W I T HO UT P R I O R W R I T T E N C O NS E NT O F C O M P AL E L E C T R O NI C S , I NC . LA-G07FP(KBL-U_UMA_v60.L
3
)
Date: Friday, January 05,2018 Sheet 3 of 59
A B C D E
5 4 3 2 1
[Diner-PWR Sequence_SKL-U22_DDR3L_Volume_NON CS]
G3->S0 S0->S3/DS3 S0/DS3->S0 S0->S5 https://vinafix.com

+3VL_RTC +3VL_RTC
tPCH01_Min : 9 ms
SOC_RTCRST# SOC_RTCRST#
+19VB +19VB
+3VLP/+5VLP +3VLP/+5VLP
D D
EC_ON EC_ON
tPCH04_Min : 9 ms
+5VALW /+3VALW /+3VALW_DSW +5VALW /+3VALW /+3VALW_DSW
Pull-up to DSW well if not implemented.
PM_BATLOW # PM_BATLOW #
PCH_PWR_EN (SLP_SUS#) PCH_PWR_EN (SLP_SUS#)
+3V_PRIM +3V_PRIM
+1.8V_PRIM +1.8V_PRIM
EXT_PW R_GATE# If EXT_PW R_GATE# T offmin is too small, Pwr EXT_PWR_GATE#

gate may choose to completely ignore it
+1.0V_MPHYPLL +1.0V_MPHYPLL
+1.0V_PRIM_CORE +1.0V_PRIM_CORE
tPCH34_Max : 20 ms
+1.0V_PRIM tPCH06_Min : 200 us +1.0V_PRIM
SUSACK# SUSACK#
tPCH02_Min : 10 ms
PCH_DPW ROK PCH_DPW ROK
tPCH03_Min : 10 ms
EC_RSMRST# EC_RSMRST#
tPLT02_Min : 0 ms Max : 90 ms
AC_PRESENT AC_PRESENT
C C
ON/OFF ON/OFF
PBTN_OUT# PBTN_OUT#
Minimum duration of PW RBTN# assertion = 16mS. PW RBTN# can assert before or after RSMRST#
PM_SLP_S5# PM_SLP_S5#
tPCH18_Min : 90 us
ESPI_RST# ESPI_RST#
SYSON SYSON
+1.0V_VCCST/+1.0V_VCCSFR +1.0V_VCCST/+1.0V_VCCSFR
+1.35V_VDDQ/+1.35V_VCCSFR_OC +1.35V_VDDQ/+1.35V_VCCSFR_OC
SUSP# SUSP#
tCPU04 Min : 100 ns
+1.0VS_VCCSTG +1.0VS_VCCSTG
tCPU10 Min : 1 ms
+1.0VS_VCCIO +1.0VS_VCCIO
+5VS/+3VS/+1.5VS/+1.05VS
B +5VS/+3VS/+1.5VS/+1.05VS B
T4 = Min : 20ms Max : 3 0ms(EC Control)

EC_VCCST_PG EC_VCCST_PG
VR_ON VR_ON
tCPU19 Max : 100 ns
SM_PG_CTRL SM_PG_CTRL
tCPU18 Max : 35 us
+0.675VS_VTT +0.675VS_VTT
tCPU09 Min : 1 ms
+VCC_SA +VCC_SA
+VCC_CORE +VCC_CORE
+VCC_GT +VCC_GT
VR_PW RGD VR_PW RGD

tCPU16 Min : 0 ns
PCH_PW ROK PCH_PW ROK
H_CPUPWRGD H_CPUPWRGD
SYS_PW ROK SYS_PW ROK
SUS_STAT# SUS_STAT#
A SOC_PLTRST# A
SOC_PLTRST#

Issued Date Deciphered Date Title
HW Reserve
TH I S S H E E T O F E N G I N E E R I N G D R A W I N G I S TH E P R O P R I E TA R Y P R O P E R TY O F C O M P A L E L E C TR O N I C S , I NC . A N D C ONTAI N S C O N F I D E N TSSIAizLe
A N D TR A D E S E C R E T I N F O R M A TI O N . TH I S S H E E T M A Y N O T B E TR A N S F E R E D F R O M TH E C U S TO D Y O F TH E C O M P E TE N T D I VI SI ON O F R & D Document Number Rev
Custo m v0.3
D E P A R TM E N T E X C E P T A S A U TH O R I ZE D B Y C O M P A L E L E C TR O N I C S , I NC . NEI THE R TH I S S H E E T N O R TH E I N F O R M A TI O N I T C O N TA I N S
M A Y B E U S E D B Y O R D I SC LOSED TO A N Y TH I R D P A R TY W I TH O U T P R I O R W R I TTE N C O N S E N T O F C O M P A L E L E C TR O N I C S , I NC .
LA-G07FP(KBL-U_UMA_6L)
Date: Friday, January 05, 2018 Sheet 4 of 59
5 4 3 2 1
A B C D E
UC1A SKL-U
Rev_0.53
<28>
<28>
HOST_DP1_N0
HOST_DP1_P0
E55
F55
DDI1_TXN[0]
DDI1_TXP[0]
EDP_TXN[0]
EDP_TXP[0]
C47
C46
EDP_TXN0
EDP_TXP0
https://vinafix.com
<27>
<27>
E58 D46 <eDP>
<28> HOST_DP1_N1 DDI1_TXN[1] EDP_TXN[1] EDP_TXN1 <27>
<HDMI> F58 C45
<28> HOST_DP1_P1 DDI1_TXP[1] EDP_TXP[1] EDP_TXP1 <27>
SOC_DP1_CTRL_DATA(Internal Pull Down): F53 A45
<28> HOST_DP1_N2 DDI1_TXN[2] EDP_TXN[2]
G53 B45
<28> HOST_DP1_P2 DDI1_TXP[2] EDP_TXP[2]
F56 A47
DDI1_TXN[3] EDP_TXN[3]
Display Port B Detected <28> HOST_DP1_N3 G56
DDI1_TXP[3] EDP_TXP[3]
B47
<28> HOST_DP1_P3
C50 E45 EDP_AUXN <27>
0 = Port B is not detected. D50
DDI2_TXN[0] DDI EDP EDP_AUXN
F45
1 DDI2_TXP[0] EDP_AUXP EDP_AUXP <27> 1
C52
DDI2_TXN[1]
1 = Port B is detected. D52 B52
DDI2_TXP[1] EDP_DISP_UTIL
A50
DDI2_TXN[2]
B50 G50
DDI2_TXP[2] DDI1_AUXN
D51 F50
DDI2_TXN[3] DDI1_AUXP
SOC_DP2_CTRL_DATA(Internal Pull Down): C51 E48
DDI2_TXP[3] DDI2_AUXN
F48
DDI2_AUXP
G46
Display Port C Detected DISPLAY SIDEBANDS DDI3_AUXN
F46
HOST_DP1_CTRL_CLK L13 DDI3_AUXP
<28> HOST_DP1_CTRL_CLK GPP_E18/DDPB_CTRLCLK
HDMI DDC (Port B) HOST_DP1_CTRL_DATA L12 L9 HOST_DP1_HPD HOST_DP1_HPD <28>From HDMI
0 = Port C is not detected. <28> HOST_DP1_CTRL_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0
L7 DDI2_HPD
GPP_E14/DDPC_HPD1 TP@ T408
N7 L6 NMI_DBG#_CPU NMI_DBG#_CPU <10,33>
GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2
1 = Port C is detected. N8 N9 EC_SCI# EC_SCI# <33>
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 From eDP
L10 EDP_HPD EDP_HPD <27>
GPP_E17/EDP_HPD
N11
GPP_E22/DDPD_CTRLCLK
N12 R12 ENBKL ENBKL <33>
GPP_E23/DDPD_CTRLDATA EDP_BKLTEN
R11
EDP_COMP E52 1 OF 20 EDP_BKLTCTL ENVDD_CPU BKL_PWM_CPU <27>
U13
EDP_RCOMP EDP_VDDEN ENVDD_CPU <27>
SKL-U_BGA1356
+1.0V_VCCST
+1.0V_PRIM RC123 1 @ 2 100K_0402_5% ENVDD_CPU
1
1 2 H_THERMTRIP#
RC2 1K_0402_5% RC3 UC1D SKL-U RC124 1 2 100K_0402_5% ENBKL
1K_0402_5% Rev_0.53
CATERR# D63
T248 TP@ H_PECI CATERR#
2 A54 2
<33> H_PECI
H_PROCHOT#_R C65 PECI
2
<33> PROCHOT# 1 2 JTAG
PROCHOT#
COMPENSATION PU FOR eDP RC4 499_0402_1% H_THERMTRIP# C63
THERMTRIP#
A65 B61 CPU_XDP_TCK0
+1.0V_PRIM SKTOCC# PROC_TCK SOC_XDP_TDI
CPU MISC D60
PROC_TDI
1
C55 A61 SOC_XDP_TDO
DS11 D55 BPM#[0] PROC_TDO
C60 SOC_XDP_TMS
PROC_TMS
RC1 1 2 EDP_COMP CK0402101V05_0402-2 B54 BPM#[1] B59 SOC_XDP_TRST#
24.9_0402_1% C56 BPM#[2] PROC_TRST#
ESD@ BPM#[3]
CAD note: B56 PCH_JTAG_TCK1
SCV00001K00 A6 PCH_JTAG_TCK D59 SOC_XDP_TDI
Trace width=20 mils,Spacing=25mil,Maxlength=100mils A7 GPP_E3/CPU_GP0
2
PCH_JTAG_TDI A56 SOC_XDP_TDO

BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDO C59 SOC_XDP_TMS
AY5 GPP_B3/CPU_GP2 PCH_JTAG_TMS C61 SOC_XDP_TRST#
GPP_B4/CPU_GP3 PCH_TRST# A59 CPU_XDP_TCK0
RC5 2 1 49.9_0402_1% CPU_POPIRCOMP AT16 JTAGX
RC6 2 1 49.9_0402_1% PCH_OPIRCOMP AU16 PROC_POPIRCOMP
RC7 2 1 49.9_0402_1% EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
RC8 2 1 49.9_0402_1% EOPIO_RCOMP H65 OPCE_RCOMP
OPC_RCOMP
4 OF 20
SKL-U_BGA1356
XDP CONN
3 3
+1.0V_PRIM
RC11 2 @ 1 51_0402_5% SOC_XDP_TMS
RC13 2 @ 1 51_0402_5% SOC_XDP_TDI
RC15 2 1 51 +-1% 0402 SOC_XDP_TDO SD000008H80
RC364 2 @ 1 51_0402_5% CPU_XDP_TCK0
+1.0V_PRIM
RC14 2 @ 1 51_0402_5% XDP_PREQ# XDP_PREQ# <11>
RC31 1 @ 2 1K_0402_5% XDP_ITP_PMODE XDP_ITP_PMODE <16>
4 RC365 2 @ 1 51_0402_1% SOC_XDP_TRST# 4
RC35 2 1 51_0402_1% CPU_XDP_TCK0 SD000008H80
RC37 2 @ 1 51_0402_5% PCH_JTAG_TCK1
Compal Electronics, Inc.

RC366 1 @ 2 0_0402_5% CFG3 CFG3 <16> Security Classification Compal Secret Data
SKL-U(1/12)DDI,MSIC,XDP,EDP
T HIS SH EET O F EN G IN EER IN G D R AW IN G IS T H E PR O PR IET AR Y PR O PER T Y O F C O MPAL ELEC T R O N IC S, INC. AN D CONT AINS CONFIDENTSSIAizLe Document Number
AN D T R AD E SEC R ET IN F O R MAT IO N . T HIS SH EET MAY N O T BE T R AN SF ER ED F R O M T H E C U ST O D Y O F T H E C O MPET EN T DIVISION O F R &D Rev
D EPAR T MEN T EXC EPT AS AU T H O R IZ ED BY C O MPAL ELEC T R O N IC S, INC. NEIT HER T HIS SH EET N O R T H E IN F O R MAT IO N IT CONT AINS Custom
MAY BE U SED BY O R DISCLO S ED T O AN Y T H IR D PAR T Y W IT H O UT PR IO R W R IT T EN C O N SEN T O F C O MPAL ELEC T R O N IC S, INC. LA-G07FP(KBL-U_UMA_6L) v0.3

A B C D E
5 4 3 2 1
Interleaved Memory https://vinafix.com
D
<Cocoa_1020> D
PDG#543016, ODT: CPU side no connect, DRAM side connect to VDDQ(Memory down); FET+R(SO-DIMM)
SKL-U
UC1B SKL-U UC1C
Rev_0.53 Rev_0.53
AU53 DDR_M0_CLK#0 DDR_M0_CLK#0 <17>
<17> DDR_M0_D[0..15] DDR0_CKN[0] <18> DDR_M1_D[0..15]
DDR_M0_D0 AL71 AT53 DDR_M0_CLK0 DDR_M0_CLK0 <17> DDR_M1_D0 AF65 AN45 DDR_M1_CLK#0 DDR_M1_CLK#0 <18>
DDR_M0_D1 AL68 DDR0_DQ[0] DDR0_CKP[0] DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0]
AU55 DDR_M0_CLK#1 DDR_M0_CLK#1 <17> DDR_M1_D1 AF64 AN46 DDR_M1_CLK#1 DDR_M1_CLK#1 <18>
DDR_M0_D2 AN68 DDR0_DQ[1] DDR0_CKN[1] DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1]
AT55 DDR_M0_CLK1 DDR_M0_CLK1 <17> DDR_M1_D2 AK65 AP45 DDR_M1_CLK0 DDR_M1_CLK0 <18>
DDR_M0_D3 AN69 DDR0_DQ[2] DDR0_CKP[1] DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0]
DDR_M1_D3 AK64 AP46 DDR_M1_CLK1 DDR_M1_CLK1 <18>
DDR_M0_D4 AL70 DDR0_DQ[3] DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1]
BA56 DDR_M0_CKE0 DDR_M1_D4 AF66
DDR_M0_D5 AL69 DDR0_DQ[4] DDR0_CKE[0] DDR_M0_CKE0 <17> DDR1_DQ[4]/DDR0_DQ[20]
DDR0_DQ[5] BB56 DDR_M0_CKE1 DDR_M0_CKE1 <17> DDR_M1_D5 AF67 AN56 DDR_M1_CKE0 <18>
DDR_M0_D6 AN70 DDR0_CKE[1] DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0]
AW 56 DDR_M1_D6 AK67 C
0
KE
R_
MD
_DAP55
1 DDR_M1_CKE1 <18>
DDR_M0_D7 AN71 DDR0_DQ[6] DDR0_CKE[2] DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1]
AY56 DDR_M1_D7 AK66 DDR_M1_CKE1 AN55
DDR_M0_D8 AR70 DDR0_DQ[7] DDR0_CKE[3] DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2]
DDR_M1_D8 AF70 AP53
DDR_M0_D9 AR68 DDR0_DQ[8] DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
AU45 DDR_M0_CS#0 DDR_M0_CS#0 <17> DDR_M1_D9 AF68
DDR_M0_D10AU71 DDR0_DQ[9] DDR0_CS#[0] AU43 DDR_M0_CS#1 DDR_M0_CS#1 <17> DDR_M1_D10AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42 DDR_M1_CS#0 DDR_M1_CS#0 <18>
DDR0_DQ[10] DDR0_CS#[1] DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0]
DDR_M0_D11AU68 AT45 DDR_M0_ODT0 DDR_M0_ODT0 <17> DDR_M1_D11AH68 AY42 DDR_M1_CS#1 DDR_M1_CS#1 <18>
DDR0_DQ[11] DDR0_ODT[0] DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42 DDR_M1_ODT0
DDR_M0_D12AR71 AT43 DDR_M0_ODT1 DDR_M0_ODT1 <17> DDR_M1_D12AF71 DDR_M1_ODT0 <18>
DDR0_DQ[12] DDR0_ODT[1] DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW 42 DDR_M1_ODT1
DDR_M0_D13AR69 DDR_M1_D13AF69 DDR_M1_ODT1 <18>
DDR0_DQ[13] DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1]
DDR_M0_D14AU70 BA51 DDR_M0_MA5 DDR_M0_MA5 <17> DDR_M1_D14AH70
DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR_M0_D15AU69 BB54 DDR_M0_MA9 DDR_M0_MA9 <17> DDR_M1_D15AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48 DDR_M1_MA5
<17> DDR_M0_D[16..31] DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] <18> DDR_M1_D[16..31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR_M1_MA5 <18>
DDR_M0_D16BB65 BA52 DDR_M0_MA6 DDR_M0_MA6 <17> DDR_M1_D16AT66 DDR1_DQ[15]/DDR0_DQ[31] AP50 DDR_M1_MA9 DDR_M1_MA9 <18>
DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDR_M1_MA6
DDR_M0_D17AW65 AY52 DDR_M0_MA8 DDR_M0_MA8 <17> DDR_M1_D17AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR_M1_MA6 <18>
DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48 DDR_M1_MA8
DDR_M0_D18AW63 AW 52 DDR_M0_MA7 DDR_M0_MA7 <17> DDR_M1_D18AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR_M1_MA8 <18>
DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR_M1_D19AN65 DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDR_M1_MA7
DDR_M0_D19AY63 AY55 DDR_M0_BG0 DDR_M0_BG0 <17> DDR1_DQ[18]/DDR0_DQ[50] DDR_M1_MA7 <18>
DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR_M1_D20AN66 DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52 DDR_M1_BG0
DDR_M0_D20BA65 AW 54 DDR_M0_MA12 DDR_M0_MA12 <17> DDR1_DQ[19]/DDR0_DQ[51] DDR_M1_BG0 <18>
DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR_M1_D21AP66 DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 DDR_M1_MA12
DDR_M0_D21AY65 BA54 DDR_M0_MA11 DDR_M0_MA11 <17> DDR1_DQ[20]/DDR0_DQ[52] DDR_M1_MA12 <18>
DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR_M1_D22AT65 DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 DDR_M1_MA11
DDR_M0_D22BA63 BA55 DDR_M0_ACT# DDR_M0_ACT# <17> DDR1_DQ[21]/DDR0_DQ[53] DDR_M1_MA11 <18>
DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR_M1_D23AU65 DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 DDR_M1_ACT#
DDR_M0_D23BB63 AY54 DDR_M0_BG1 DDR_M0_BG1 <17> DDR1_DQ[22]/DDR0_DQ[54] DDR_M1_ACT# <18>
DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_M1_D24AT61 DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52 DDR_M1_BG1
DDR_M0_D24BA61 DDR1_DQ[23]/DDR0_DQ[55] DDR_M1_BG1 <18>
DDR0_DQ[24]/DDR0_DQ[40] DDR_M1_D25AU61 DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR_M0_D25AW61 AU46 DDR_M0_MA13 DDR_M0_MA13 <17> DDR1_DQ[24]/DDR0_DQ[56]
C DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR_M1_D26AP60 BA43 DDR_M1_MA13 C
DDR_M0_D26BB59 AU48 DDR_M0_MA15_CAS# DDR_M0_MA15_CAS# <17> DDR1_DQ[25]/DDR0_DQ[57] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDR_M1_MA13 <18>
DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR_M1_D27AN60 AY43 DDR_M1_MA15_CAS#
DDR_M0_D27AW59 AT46 DDR_M0_MA14_WE# DDR_M0_MA14_W E# <17> DDR1_DQ[26]/DDR0_DQ[58] DDR_M1_MA15_CAS# <18>
DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR_M0_D28BB61 AU50 DDR_M0_MA16_RAS# DDR_M0_MA16_RAS# <17> DDR_M1_D28AN61 DDR1_DQ[27]/DDR0_DQ[59] AY44 DDR_M1_MA14_W E# DDR_M1_MA14_W E# <18>
DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR1_W E#/DDR1_CAB[2]/DDR1_MA[14]
DDR_M0_D29AY61 AU52 DDR_M0_BA0 DDR_M0_BA0 <17> DDR_M1_D29AP61 DDR1_DQ[28]/DDR0_DQ[60] AW 44 DDR_M1_MA16_RAS# DDR_M1_MA16_RAS# <18>
DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR_M0_D30BA59 AY51 DDR_M0_MA2 DDR_M0_MA2 <17> DDR_M1_D30AT60 DDR1_DQ[29]/DDR0_DQ[61] BB44 DDR_M1_BA0 DDR_M1_BA0 <18>
DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDR_M1_D31AU60 DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR_M0_D31AY59 AT48 DDR_M0_BA1 DDR_M0_BA1 <17> DDR1_DQ[30]/DDR0_DQ[62] AY47 DDR_M1_MA2 DDR_M1_MA2 <18>
<17> DDR_M0_D[32..47] DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] <18> DDR_M1_D[32..47] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR_M0_D32AY39 AT50 DDR_M0_MA10 DDR_M0_MA10 <17> DDR_M1_D32AU40 DDR1_DQ[31]/DDR0_DQ[63] BA44 DDR_M1_BA1 DDR_M1_BA1 <18>
DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR_M1_D33AT40 DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW 46 DDR_M1_MA10
DDR_M0_D33AW39 BB50 DDR_M0_MA1 DDR_M0_MA1 <17> DDR1_DQ[32]/DDR1_DQ[16] DDR_M1_MA10 <18>
DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR_M1_D34AT37 DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46 DDR_M1_MA1
DDR_M0_D34AY37 AY50 DDR_M0_MA0 DDR_M0_MA0 <17> DDR1_DQ[33]/DDR1_DQ[17] DDR_M1_MA1 <18>
DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 DDR_M0_MA3 DDR_M1_D35AU37 DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46 DDR_M1_MA0 DDR_M1_MA0 <18>
DDR_M0_D35AW37 DDR0_MA[3] DDR_M0_MA3 <17> DDR1_DQ[34]/DDR1_DQ[18]
DDR0_DQ[35]/DDR1_DQ[3] BB52 DDR_M0_MA4 DDR_M1_D36AR40 DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BB46 DDR_M1_MA3 DDR_M1_MA3 <18>
DDR_M0_D36BB39 DDR0_MA[4] DDR_M0_MA4 <17> DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[3]
DDR0_DQ[36]/DDR1_DQ[4] DDR_M1_D37AP40 BA47 DDR_M1_MA4 DDR_M1_MA4 <18>
DDR_M0_D37BA39 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[4]
DDR0_DQ[37]/DDR1_DQ[5] AM70 DDR_M0_DQS#0 DDR_M1_D38AP37
DDR_M0_D38BA37 DDR0_DQSN[0] DDR_M0_DQS#0 <17> DDR1_DQ[37]/DDR1_DQ[21]
DDR0_DQ[38]/DDR1_DQ[6] AM69 DDR_M0_DQS0 DDR_M1_D39AR37 AH66 DDR_M1_DQS#0
DDR_M0_D39BB37 DDR0_DQSP[0] DDR_M0_DQS0 <17> DDR1_DQ[38]/DDR1_DQ[22] DDR_M1_DQS#0 <18>
DDR0_DQ[39]/DDR1_DQ[7] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDR_M1_DQS0
DDR_M0_D40AY35 AT69 DDR_M0_DQS#1 DDR_M0_DQS#1 <17> DDR_M1_D40AT33 DDR_M1_DQS0 <18>
DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 DDR_M1_DQS#1
DDR_M0_D41AW35 AT70 DDR_M0_DQS1 DDR_M0_DQS1 <17> DDR_M1_D41AU33 DDR_M1_DQS#1 <18>
DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 DDR_M1_DQS1
DDR_M0_D42AY33 BA64 DDR_M0_DQS#2 DDR_M0_DQS#2 <17> DDR_M1_D42AU30 DDR_M1_DQS1 <18>
DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDR_M1_DQS#2
DDR_M0_D43AW33 AY64 DDR_M0_DQS2 DDR_M0_DQS2 <17> DDR_M1_D43AT30 DDR_M1_DQS#2 <18>
DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] DDR_M1_D44AR33 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDR_M1_DQS2
DDR_M0_D44BB35 AY60 DDR_M0_DQS#3 DDR_M0_DQS#3 <17> DDR_M1_DQS2 <18>
DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] DDR_M1_D45AP33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDR_M1_DQS#3
DDR_M0_D45BA35 BA60 DDR_M0_DQS3 DDR_M0_DQS3 <17> DDR_M1_DQS#3 <18>
DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] DDR_M1_D46AR30 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSN[3]/DDR0_DQSN[7] AR60 DDR_M1_DQS3
DDR_M0_D46BA33 BA38 DDR_M0_DQS#4 DDR_M0_DQS#4 <17> DDR_M1_DQS3 <18>
DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] DDR_M1_D47AP30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDR_M1_DQS#4
DDR_M0_D47BB33 AY38 DDR_M0_DQS4 DDR_M0_DQS4 <17> DDR_M1_DQS#4 <18>
<17> DDR_M0_D[48..63] DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] <18> DDR_M1_D[48..63] DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSN[4]/DDR1_DQSN[2] AR38 DDR_M1_DQS4
DDR_M0_D48AY31 AY34 DDR_M0_DQS#5 DDR_M0_DQS#5 <17> DDR_M1_D48AU27 DDR_M1_DQS4 <18>
DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] DDR_M1_D49AT27 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDR_M1_DQS#5
DDR_M0_D49AW31 BA34 DDR_M0_DQS5 DDR_M0_DQS5 <17> DDR_M1_DQS#5 <18>
DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] DDR_M1_D50AT25 DDR1_DQ[48] DDR1_DQSN[5]/DDR1_DQSN[3] AR32 DDR_M1_DQS5
DDR_M0_D50AY29 BA30 DDR_M0_DQS#6 DDR_M0_DQS#6 <17> DDR1_DQ[49] DDR_M1_DQS5 <18>
DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] DDR_M1_D51AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25 DDR_M1_DQS#6
DDR_M0_D51AW29 AY30 DDR_M0_DQS6 DDR_M0_DQS6 <17> DDR_M1_DQS#6 <18>
DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] DDR1_DQ[51] DDR1_DQSN[6] AR27 DDR_M1_DQS6
DDR_M0_D52BB31 AY26 DDR_M0_DQS#7 DDR_M0_DQS#7 <17> DDR_M1_D52AP27 DDR_M1_DQS6 <18>
DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] DDR1_DQ[52] DDR1_DQSP[6] AR22 DDR_M1_DQS#7
DDR_M0_D53BA31 BA26 DDR_M0_DQS7 DDR_M0_DQS7 <17> DDR_M1_D53AN27 DDR_M1_DQS#7 <18>
DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5] DDR1_DQ[53] DDR1_DQSN[7] AR21 DDR_M1_DQS7
DDR_M0_D54BA29 DDR_M1_D54AN25 DDR_M1_DQS7 <18>
DDR0_DQ[54]/DDR1_DQ[38] DDR1_DQ[54] DDR1_DQSP[7]
DDR_M0_D55BB29 AW 50 DDR_M0_ALERT# DDR_M0_ALERT# <17> DDR_M1_D55AP25
DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# DDR1_DQ[55]
DDR_M0_D56AY27 AT52 DDR_M0_PAR DDR_M0_PAR <17> DDR_M1_D56AT22 AN43 DDR_M1_ALERT# AP43 DDR_M1_ALERT# <18>
DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR DDR1_DQ[56] DDR1_ALERT#
DDR_M0_D57AW27 DDR_M1_D57AU22 DDR_M1_PAR DDR_M1_PAR <18>
DDR0_DQ[57]/DDR1_DQ[41] AY67 +0.6V_VREFCA DDR_M1_D58AU21 DDR1_DQ[57] DDR1_PAR AT13 DDR_DRAMRST# AR18
DDR_M0_D58AY25 DDR_VREF_CA +0.6V_VREFCA
DDR0_DQ[58]/DDR1_DQ[42] DDR1_DQ[58] DRAM_RESET# 2 121_0402_1%
DDR_M0_D59AW25 AY68 DDR_M1_D59AT21 SM_RCOMP0 RC38 1
DDR0_DQ[59]/DDR1_DQ[43] DDR0_VREF_DQ BA67 +0.6V_B_VREFDQ DDR1_DQ[59] DDR_RCOMP[0] 2 80.6_0402_1%
DDR_M0_D60BB27 DDR CH - A
+0.6V_B_VREFDQ DDR_M1_D60AN22 AT18 SM_RCOMP1 RC39 1
DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ DDR1_DQ[60] DDR CH - B DDR_RCOMP[1]
B DDR_M0_D61BA27 DDR_M1_D61AP22 AU18 SM_RCOMP2 RC40 1 2 100_0402_1% B
DDR0_DQ[61]/DDR1_DQ[45] AW 67 DDR_PG_CTRL DDR_M1_D62AP21 DDR1_DQ[61] DDR_RCOMP[2]
DDR_M0_D62BA25 DDR_VTT_CNTL
DDR0_DQ[62]/DDR1_DQ[46] DDR_M1_D63AN21 DDR1_DQ[62]
DDR_M0_D63BB25
DDR0_DQ[63]/DDR1_DQ[47] 2 OF 20 DDR1_DQ[63] 3 OF 20
SKL-U_BGA1356 SKL-U_BGA1356
+1.2V_VDDQ
For VTT power control
+1.2V_VDDQ
1
+3VS
1
RC904 0.1U_0201_10V6K 2 1 CC57

1
RC905 @ 100K_0402_5%
100K_0402_5% @ UC7 RC394
1 5 100K_0402_5%
NC
2
VCC
2
DDR_PG_CTRL 2
A
2
1
4 SM_PG_CTRL <49>
Y
2
RC906 3 +1.2V_VDDQ
GND @ESD@
100K_0402_5% @
74AUP1G07SE-7_SOT353-5 DDR_PG_CTRL 1 2
@ SA00007W E00 CC70 100P_0402_50V8J
2
1
DDR_PG_CTRL 3 1 SM_PG_CTRL
RC32 From ESD Team Request
470_0402_5%
2
UC9 SB000008E10
MMBT3904W H NPN SOT323-3 DDR_DRAMRST# 1 Rshort@2 DDR_DRAMRST#_R RC33 DDR_DRAMRST#_R <17,18>
SB00000QJ00,S TR DRC5115E0L NPN 0_0402_5%
SOT323-3
A A
Security Classification
2017/04/10
Compal Secret Data
2019/12/15 Title
Issued Date Deciphered Date
SKL-U(2/12)DDRIII
D E P A R TM E N T E X C E P T A S A U TH O R I Z E D B Y C O M P A L E L E C TR O N IC S , IN C . N E ITH E R TH IS S H E E T N O R T H E I N F O R M A T I O N IT C O N TA IN S Custom
M A Y B E U S E D B Y O R D IS C L O S E D T O A N Y TH IR D P A R T Y W I T H O U T P R I O R W R I T T E N C O N S E N T O F C O M P A L E L E C TR O N IC S , IN C . LA-G07FP(KBL-U_UMA_6L) v0.3

5 4 3 2 1
5 4 3 2 1
SML0ALERT# (Internal Pull Down):

eSPI or LPC
SKL-U
UC1E 0 = LPC is selected f or EC --> For KB9022/9032 Use
https://vinafix.com
Rev_0.53
SPI - FLASH
1 = eSPI is selected f or EC --> For KB9032 Only.
SMBUS, SMLINK
HOST_SPI_0_CLK AV2
SPI0_CLK
<35> HOST_SPI_0_SO HOST_SPI_0_SO AW3 R7 SMBCLK SMB SML0ALERT#
SPI0_MISO GPP_C0/SMBCLK
HOST_SPI_0_SI AV3 R8 SMBDATA
<35> HOST_SPI_0_SI
HOST_SPI_0_SIO2 AW2 SPI0_MOSI GPP_C1/SMBDATA
R10 SMBALERT# TP@ T239
(Link to XDP, DDR, TP)
SPI0_IO2 GPP_C2/SMBALERT#
1
HOST_SPI_0_SIO3 AU4
SPI0_IO3 RC218
HOST_SPI_0_CS0# AU3 R9 SML0CLK
SPI0_CS0# GPP_C3/SML0CLK
AU2 W2 SML0DATA 1K_0402_1%
GPP_C4/SML0DATA
<35> HOST_SPI_0_CS2# HOST_SPI_0_CS2# AU1 SPI0_CS1# W1 SML0ALERT#
SPI0_CS2# GPP_C5/SML0ALERT#
2
D W3 SML1CLK D
SPI - TOUCH GPP_C6/SML1CLK SML1
V3 SML1DATA
GPP_C7/SML1DATA 2 SML1ALERT# (Link to EC,DGPU, LAN, Thermal Sensor)
M2 AM7 GPP_B23 1
GPP_D1/SPI1_CLK GPP_B23/SML1ALERT#/PCHHOT# RC902 @ +3V_PRIM
M3
GPP_D2/SPI1_MISO 0_0201_5%
J4
GPP_D3/SPI1_MOSI SML1ALERT# RC903 2 @ 1 150K_0402_1%
V1 TP@ T234
GPP_D21/SPI1_IO2
V2
GPP_D22/SPI1_IO3
M1 LPC
GPP_D0/SPI1_CS# AY13 LPC_AD0 SML0ALERT# RC360 2 @ 1 10K_0402_5%
GPP_A1/LAD0/ESPI_IO0 BA13 LPC_AD1 LPC_AD0 <33> +3VS
C LINK GPP_A2/LAD1/ESPI_IO1 BB13 LPC_AD2 LPC_AD1 <33>
G3 GPP_A3/LAD2/ESPI_IO2 AY12 LPC_AD2 <33> SMBALERT# 8 1
LPC_AD3
G2 CL_CLK GPP_A4/LAD3/ESPI_IO3 BA12 LPC_FRAME#
LPC_AD3 <33> 7 2
G1 CL_DATA GPP_A5/LFRAME#/ESPI_CS# BA11 SUS_STAT# LPC_FRAME# <33> EC_KBRST# 6 3
CL_RST# GPP_A14/SUS_STAT#/ESPI_RESET# TP@ T2402 5 4
EC_KBRST# AW13 AW9 CLK_PCI0 RC387 1 2 22_0402_5% RPC19 10K_0804_8P4R_5%

<33> EC_KBRST# GPP_A0/RCIN# GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_PCI_LPC <33>
GPP_A10/CLKOUT_LPC1
AY9 To EC
To TPM <33,35> SERIRQ SERIRQ AY11 AW11 PM_CLKRUN#
PM_CLKRUN# <33>
GPP_A6/SERIRQ 5 OF 20 GPP_A8/CLKRUN#
LPC Mode 1
CC182
SKL-U_BGA1356
22P 50V J NPO 0402
EMI@
2
+3VS +3VS
to SPI ROM UC2 Source From +3V_PRIM
2
RPH11
C HOST_SPI_0_CS0#_R 1 8 EC_SPI_CS0# RC216 RC215 C
EC_SPI_CS0# <33>
HOST_SPI_0_CS0#_R 2 7 HOST_SPI_0_CS0# 10K_0402_5% 10K_0402_5% SML0CLK RC49 1 2 499_0402_1%
HOST_SPI_0_SO_R 3 6 EC_SPI_SO EC_SPI_SO <33>
2
HOST_SPI_0_SO_R 4 5 HOST_SPI_0_SO QC1A SML0DATA RC50 1 2 499_0402_1%
1
15_0804_8P4R_5% SMBCLK 6 1
PCH_SMBCLK <17,18>
RPC7
RPH12 L2N7002SDW1T1G 2N SC88-6 SML1CLK 1 8
HOST_SPI_0_HOLD# 1 8 HOST_SPI_0_SIO3 SB00001FF00 SML1DATA 2 7
5
HOST_SPI_0_SI_R 2 7 HOST_SPI_0_SI SMBCLK 3 6
HOST_SPI_0_SI_R 3 6 EC_SPI_SI QC1B SMBDATA 4 5
EC_SPI_SI <33>
4 5 SMBDATA 3 4
PCH_SMBDATA <17,18>
1K_0804_8P4R_5%
15_0804_8P4R_5% L2N7002SDW1T1G 2N SC88-6
SB00001FF00
HOST_SPI_0_WP# 2 1 HOST_SPI_0_SIO2 +3VS +3V_SPI
RC388 15_0402_5%
HOST_SPI_0_SIO2 RC3901 @ 2 1K_0402_1%
+3V_SPI
SPI ROM ( 8MByte Only) CC8 HOST_SPI_0_SIO3 RC3911 @ 2 1K_0402_1%
UC2 1 2 0.1U_0201_10V6K
HOST_SPI_0_CS0#_R 1 8 <DB> Un-pop QC2 f or new 0x90 thermal sensor
CS# VCC
2
HOST_SPI_0_SO_R 2 7 HOST_SPI_0_HOLD#
DO(IO1) HOLD#(IO3) @
HOST_SPI_0_WP# 3 6 HOST_SPI_0_CLK_R
4 WP#(IO2) CLK SML1CLK 6 1
5 HOST_SPI_0_SI_R EC_SMB_CK2 <10,33>
GND DI(IO0) QC2A 5 HOST_SPI_0_CS0#_R 1 @ 2
XM25QH64AHIG SOP 8P L2N7002SDW1T1G 2N SC88-6 RC357 1K_0402_5%
SA0000B8300 SPI ROM Part: SB00001FF00 @
ACES_91960-0084L_8P-T Main:SA0000B8300, S IC FL 64M XM25QH64AHIG SOP 8P(XMC)
2nd: SA000039A40, S IC FL 64M W25Q64JVSSIQ SOIC 8P SPI ROM(Winbond) SML1DATA 3 4
EC_SMB_DA2 <10,33>
Use socket f ootprint 3th: SA00008SL00, S IC FL 64M MX25L6473FM2I-08G SOP 8P(MXIC) QC2B
4rd: SA00007LA10, S IC FL 64M GD25B64CSIGR SOP 8P SPI ROM(GigaDevice) L2N7002SDW1T1G 2N SC88-6
SB00001FF00
B B
+3V_PRIM +3VALW HOST_SPI_0_SIO3 RC51 1 ES@ 2 1K_0402_1%
From WW36 MOW f or SKL-U ES sample

2
RC81 RC82
10K_0402_5% 10K_0402_5%
2
SB00001FF00 +3VS_PGPPA
1
SMBCLK 1 6
TP_SMBCLK <34>
CLK Source CPU to SPI ROM UC2&EC QC7A PM_CLKRUN# 1 2
L2N7002SDW1T1G 2N SC88-6 RC107 8.2K_0402_5%
15_0402_5%
5
HOST_SPI_0_CLK 2 1 HOST_SPI_0_CLK_R
HOST_SPI_0_CLK_R <33,35>
RC368 EMI@ SERIRQ 1 2
SMBDATA 4 3 RC122 8.2K_0402_5%
TP_SMBDATA <34>
1 2
CC9 QC7B SB00001FF00
10P_0402_50V8J L2N7002SDW1T1G 2N SC88-6 Follow 543016_SKL_U_Y_PDG_0_9
@EMI@
EON SA000046400 S IC FL 64M EN25Q64-104HIP SOP 8P MXIC

SA00006N100 S IC FL 64M MX25L6473EM2I-10G SOP 8P
WINBOND SA000039A30 S IC FL 64M W25Q64FVSSIQ SOIC 8P SPI ROM
Micron SA00005L100 S IC FL 64M N25Q064A13ESEC0F SO8W 8P
A A
2017/04/10
Compal Secret Data
2019/12/15 Title
SKL-U(3/12)SPI,ESPI,SMB,LPC
AN D T R AD E SEC R ET IN F O R MAT IO N . T HIS SH EET MAY N O T BE T R AN SF ER ED F R O M T H E C U ST O D Y O F T H E C O MPET EN T DIVISION O F R &D Rev
D EPAR T MEN T EXC EPT AS AU T H O R IZ ED BY C O MPAL ELEC T R O N IC S, INC. NEIT HER T HIS SH EET N O R T H E IN F O R MAT IO N IT CONT AINS Custom
MAY BE U SED BY O R DISCLO S ED T O AN Y T H IR D PAR T Y W IT H O UT PR IO R W R IT T EN C O N SEN T O F C O MPAL ELEC T R O N IC S, INC.
LA-G07FP(KBL-U_UMA_6L) v0.3

5 4 3 2 1
5 4 3 2 1
https://vinafix.com
UC1G SKL-U
Rev_0.53 +3V_PRIM
D AUDIO UMA DIS D
1
HDA_SYNC BA22 PROJECT_ID
HDA_BIT_CLK AY22
HDA_SYNC/I2S0_SFRM 0 1
HDA_SDOUT HDA_BLK/I2S0_SCLK PX@ RC127
BB22 SDIO/SDXC
HDA_SDO/I2S0_TXD
<32> HDA_SDIN0 HDA_SDIN0 BA21
HDA_SDI0/I2S0_RXD
10K_0402_5% 2G VRAM 4G VRAM
AY21 AB11
HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD
2
HDA_RST# AW22 AB13 VRAMCLK_SEL VRAM Clock
J5
HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0
AB12 PROJECT_ID 0 1
GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 PLAT_SEL0
AY20 W12
I2S1_SFRM GPP_G3/SD_DATA2
1
AW20 W11 PLAT_SEL1
I2S1_TXD GPP_G4/SD_DATA3 RC128
W10
SOC_GPIOF1 AK7 GPP_G5/SD_CD# UMA@ 10K_0402_5% +3V_PRIM
T38 TP@ W8
SOC_GPIOF0 AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK
W7
T39 TP@
AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
2
AK10 GPP_F2/I2S2_TXD
2
BA9
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9 RC900
GPP_A16/SD_1P8_SEL X76@ 10K_0402_5%
H5 AB7 SD_RCOMP RC76 2 1 200_0402_1%
GPP_D19/DMIC_CLK0 SD_RCOMP
D7
GPP_D20/DMIC_DATA0
1
D8 AF13 SOC_GPIOF17 T235 TP@ VRAMCLK_SEL
GPP_F23
C8 GPP_D17/DMIC_CLK1
GPP_D18/DMIC_DATA1
2
HDA_SPKR RC901
<10,32> HDA_SPKR AW5
GPP_B14/SPKR X76 BOM control RAM size X76@ 10K_0402_5%
7 OF 20
Net Name 4G 2G
1
C
SKL-U_BGA1356 VRAMCLK_SEL 1 0 C
HDA for AUDIO

RPC9 RC367 1 Rshort@20_0402_5%
1 8 <33> ME_FLASH_EN
<32> HDA_SYNC_R 2 7 HDA_SYNC

<32> HDA_RST#_R 3 6 HDA_RST#
2
4 5 HDA_SDOUT +3V_HDA
G
<32> HDA_SDOUT_R
@
33_0804_8P4R_5% 1 @ 2 RC380 1 3 HDA_SDOUT
1K_0402_1% QC380
S
MESS138W-G_SOT323-3
<32> HDA_BIT_CLK_R 2 EMI@ 1 HDA_BIT_CLK

+3V_PRIM
EMI@
RC383 33_0402_5%
HDA_SDOUT:
CC143 22P 50V J NPO 0402 ME Flash Descriptor Security Override
@RF@ Low : Disabled(Default)
2
CC183 22P 50V J NPO 0402
High : Enabled
SKL_ULT
EMI request UC1I
Rev_0.53
KBLR@ RC919 SKYL@ RC916
10K_0402_5% 10K_0402_5%
CSI-2
1
PLAT_SEL0
A36 C37 PLAT_SEL1
CSI2_DN0 CSI2_CLKN0
B36 D37
CSI2_DP0 CSI2_CLKP0
2
B B
C38 C32
CSI2_DN1 CSI2_CLKN1
D38 D32
CSI2_DP1 CSI2_CLKP1 KBLU@ RC918 KBLU@ RC917
C36 C29
CSI2_DN2 CSI2_CLKN2 10K_0402_5% 10K_0402_5%
D36 D29
CSI2_DP2 CSI2_CLKP2
A38
CSI2_DN3 CSI2_CLKN3
B26 PLAT_SEL1
1
B38 A26
CSI2_DP3 CSI2_CLKP3
C31 E13 CSI2_COMP RC80 2 1 100_0402_1% 0 1 SKYL@ KBLR@
CSI2_DN4 CSI2_COMP
D31 B7 RC918 RC917
CSI2_DP4 GPP_D4/FLASHTRIG 0 KBL-U KBL-R
C33
CSI2_DN5 PLAT_SEL0
D33 10K_0402_5% 10K_0402_5%
A31
CSI2_DP5 EMMC 1 SKL-U NA SD028100280 SD028100280
CSI2_DN6
B31 AP2
CSI2_DP6 GPP_F13/EMMC_DATA0
A33 AP1
CSI2_DN7 GPP_F14/EMMC_DATA1
B33 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2
AN3
A29 GPP_F16/EMMC_DATA3
AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4
AN2
C28CSI2_DP8 GPP_F18/EMMC_DATA5
AM4
D28CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
9 OF 20 AT1 EMMC_RCOMP 2 1
EMMC_RCOMP 200_0402_1%
RC89
SKL-U_BGA1356
A A
2017/04/10
Compal Secret Data
2019/12/15 Title
SKL-U(4/12)HDA,EMMC,SDIO,CSI2
THIS SHEET O F ENG INEERING DRAW ING IS T HE PRO PRIET ARY PRO PERT Y O F COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENSSTiIzAeLDocumentNumber
AND T RADE SECRET INFORMAT ION. THIS SHEET MAY NO T BE T RANSFERED FRO M T HE CUST ODY O F T HE COMPET ENT DIVISION O F R&D
Rev
DEPARTMENT EXCEPT AS AUT HO RIZED BY CO MPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMAT ION IT CONTAINS Custom
MAY BE USED BY O R DISCLOSED T O ANY THIRD PART Y W IT HO UT PRIO R W RIT T EN CONSENT O F COMPAL ELECTRONICS, INC. LA-G07FP(KBL-U_UMA_6L) v0.3

5 4 3 2 1
5 4 3 2 1
+RTCVCC
RC91 1 2 20K_0402_5% PCH_SRTCRST#
CC10 1 2 1U_0402_6.3V6K
https://vinafix.com
CLRP1 1 2 SHORT PADS CLR ME UC1J SKL_ULT
Rev_0.53
RC93 1 2 20K_0402_5% PCH_RTCRST# CLOCKSIGNALS
CC11 1 2 1U_0402_6.3V6K D42

CLKOUT_PCIE_N0
C42
CLKREQ_PEG#0 CLKOUT_PCIE_P0
AR10
CLRP2 1 2 SHORT PADS CLR CMOS GPP_B5/SRCCLKREQ0#
CLK_PCIE_N1 B42
<29> CLK_PCIE_N1 CLKOUT_PCIE_N1
LAN CLK_PCIE_P1 A42 F43
D <29> CLK_PCIE_P1 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N D
RC941 2 1M_0402_5% SM_INTRUDER# CLKREQ_PCIE#1 AT7 E43
<29> CLKREQ_PCIE#1 GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
CLK_PCIE_N2 D41 BA17 SUSCLK
<30> CLK_PCIE_N2 CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK <30>
PCH_RTCRST# 2 1 CLR_CMOS# <33> W LAN CLK_PCIE_P2 C41
<30> CLK_PCIE_P2 CLKOUT_PCIE_P2
0_0402_5% R1088 CLKREQ_PCIE#2 AT8 E37 PCH_KBLU24_IN
<30> CLKREQ_PCIE#2 GPP_B7/SRCCLKREQ2# XTAL24_IN
1
PCH_SRTCRST# 2 1 E35 PCH_KBLU24_OUT
XTAL24_OUT
0_0402_5% R1089 Clear CMOS close to RAM door D40
@ CLKOUT_PCIE_N3 E42 XCLK_BIASREF RC96 1 2 2.7K_0402_1%
C40 +1.0V_CLK5_F24NS
JCMOS1 CLKREQ_PCIE#3 CLKOUT_PCIE_P3 XCLK_BIASREF
AT10
0_0603_5% GPP_B8/SRCCLKREQ3# AM18 PCH_RTCX1
2
CLK_PCIE_N4 B40 RTCX1 AM20 PCH_RTCX2

<31> CLK_PCIE_N4 A40 CLKOUT_PCIE_N4 RTCX2
PCIe SSD <31> CLK_PCIE_P4
CLK_PCIE_P4
CLKREQ_PCIE#4 AU8 CLKOUT_PCIE_P4 AN18 PCH_SRTCRST#
+3VS <31> CLKREQ_PCIE#4 GPP_B9/SRCCLKREQ4# SRTCRST# AM16 PCH_RTCRST#
E40 RTCRST#
E38 CLKOUT_PCIE_N5
1 2 CLKREQ_PCIE#4 CLKREQ_PCIE#5 AU7 CLKOUT_PCIE_P5 XCLK_BIASREF RC97 1 @ 2 60.4_0402_1%
RC165 10K_0402_5% From 545659_SKL_PCH_U_Y_EDS_R0_7 GPP_B10/SRCCLKREQ5#
1 2 CLKREQ_PCIE#5
RC105 10K_0402_5% <Cocoa_1027> 10 OF 20
<DB> Add RX1~4 for KBL U/R Colay
RPC10 check un-use GPIO for termination guidance
8 1 CLKREQ_PCIE#1
SKL-U_BGA1356 Change XTAL(YC1) to 2016 Type
7 2 CLKREQ_PCIE#2 KBLU@
6 3 CLKREQ_PEG#0 PCH_KBLU24_IN RX1 2 1 33_0402_1% PCH_XTAL24U_IN PCH_RTCX2
5 4 CLKREQ_PCIE#3
10K_0804_8P4R_5%
PCH KBLU@ KBLU@
PLTRST RC99 1 2 0_0402_5% PCH_KBLU24_OUT RX2 2 1 33_0402_1% PCH_XTAL24U_OUT 1
RC92
2
1M_0402_5%
PCH_RTCX1 1 2
RC98 10M_0402_5%
+3VALW _DSW
Buffer +3VS @
1 2 PCH_PW ROK CC145 YC1 KBLU@ YC2
RC925 10K_0402_5% 1 2 24MHZ 18PF XRCGB24M000F2P51R0 32.768KHZ 9PF 10PPM 9H03200055
C 1 2 LAN_WAKE# 1 2 C
5
RC926 10K_0402_5% @ UC8 0.1U_0201_10V6K 3 1
+3V_PRIM 3 1
1 2 PCH_RSMRST# PLT_RST#_PCH 1 SJ10000Q800
DS12 IN1 NC NC
RC927 10K_0402_5% 4 PLT_RST# KBLU@ KBLU@
O PLT_RST# <29,30,31,33,35>
G P
1 2 SYS_RESET# 2 1 PCH_PW ROK 2 CC12 SJ10000UJ00 CC13
CC15
6.8P 50V C NPO 0402
6.8P 50V C NPO 0402

CC16
IN2 1 1
RC928 10K_0402_5% 4 2 SE07168AC80
J
27P_0402_50V8
J
27P_0402_50V8
SN74AHC1G08DCKR_SC70-5
CK0402101V05_0402-2
3
SE07168AC80
ESD@ 2 2
SCV00001K00
2 1 SYS_RESET# 24MHz Parrrrttt: <SI> CC15/CC16 SI change 3.9p=>6.8p

Maiiiiiin::::::SJ10000X700,,,,,, S CRYSTAL 24MHZ 18PF
CLRP3 SHORT PADS +--20PPM 8Y24000033((((((TXC))))))::::::2......0x1......6mm
1 @ 2 SUSCLK 2nd:::::SJ10000TK00,,,,,, S CRYSTAL 24MHZ 18PF
+--20PPM 7M24000027((((((TXC))))))::::::3......2x2......5mm
RC100 1K_0402_5%
2 1 PCH_DPW ROK
RC101 100K_0402_5%
TP@T254
TP@T255
TP@T256
TP@T257
TP@T258
+3VALW _DSW UC1K SKL-U
Rev_0.53
SYSTEM POWERMANAGEMENT
1 2 PM_BATLOW # AT11 PM_SLP_S0#
RC103 8.2K_0402_5% GPP_B12/SLP_S0# AP15 PM_SLP_S3#
GPD4/SLP_S3# PM_SLP_S3# <12,33,40>
1 2 W AKE# PLT_RST#_PCH AN10 BA16 PM_SLP_S4#
GPP_B13/PLTRST# GPD5/SLP_S4# PM_SLP_S4# <12,33,40,49>
RC104 1K_0402_5% SYS_RESET# B5 AY16 PM_SLP_S5#
T296 TP@ SYS_RESET# GPD10/SLP_S5# PM_SLP_S5# <33>
1 @ 2 AC_PRESENT_R PCH_RSMRST# AY17
<33> PCH_RSMRST# RSMRST#
RC106 10K_0402_5% AN15 PM_SLP_SUS#
SLP_SUS# AW 15 PM_SLP_SUS# <33>
RC102 1 @ 2 1K_0402_5% H_CPUPW RGD A68
B EC_VCCST_PG B65 PROCPW RGD SLP_LAN# BB17 B
VCCST_PW RGD GPD9/SLP_W LAN# AN16 PM_SLP_A#
Only For Power Sequence Debug GPD6/SLP_A#
+3V_PRIM SYS_PW ROK B6
<33> SYS_PW ROK SYS_PW ROK
<33> PCH_PW ROK PCH_PW ROK BA20 BA15 PBTN_OUT# PBTN_OUT# <33>
GPD3/PW RBTN#
PCH_DPW ROK_R BB20 PCH_PW ROK AY15 AC_PRESENT_R 2 1
DSW _PWROK GPD1/ACPRESENT ACIN <33>
AU13 PM_BATLOW # RC108 0_0402_5%
GPD0/BATLOW #
RC1151 @ 2 10K_0402_5% SOC_VRALERT# PCH_SUSW ARN# AR13
<33> PCH_SUSW ARN# GPP_A13/SUSW ARN#/SUSPW RDNACK
<33> SUSACK# 2 Rshort@ 1 SUSACK#_R AP11
RC110 0_0402_5% GPP_A15/SUSACK# AU11 EC_PCIE_W AKE#_CPU 2@ 1
GPP_A11/PME# AP16 SM_INTRUDER# EC_PCIE_W AKE# <30,33>
W AKE# BB15 RC922 0_0402_5%
+3VALW _DSW <30> W AKE# AM15 W AKE# INTRUDER#
LAN_WAKE#
AW 17 GPD2/LAN_W AKE# AM10 EXT_PW R_GATE# TP@T298
AT15 GPD11/LANPHYPC GPP_B11/EXT_PW R_GATE# AM11 SOC_VRALERT#
T94 TP@ GPD7/RSVD GPP_B2/VRALERT#
11 OF 20
DS13 ESD@
RC111 2 @ 1 100K_0402_5% PBTN_OUT# SCV00001K00
SKL-U_BGA1356
1 2 H_CPUPW RGD
CK0402101V05_0402-2
DS14 @ESD@
SCV00001K00
1 2 SUSACK#
CK0402101V05_0402-2 DC3 SCS00000Z00

RB751V-40 SOD-323
PCH_RSMRST# 1 2 PCH_PW ROK
ESD@
C5229 1 2 SYS_PW ROK
2 1
SPOK <48>
0.1U_0402_25V6 DC4 SCS00000Z00
RB751V-40 SOD-323
A Vinafix.com <33> PCH_DPW ROK

RC112
2 Rshort@
1
0_0402_5%
PCH_DPW ROK_R
A
From EC(open-drain) +1.0V_VCCST

1
RC113

1K_0402_5%
Security Classification Compal Secret Data
2
RC1161 2 60.4_0402_1% EC_VCCST_PG

<33,40> EC_VCCST_PG_R
SKL-U(5/12)CLK,GPIO
D E P A R TM E N T E X C E P T A S A U TH O R I Z E D B Y C O M P A L E L E C TR O N IC S , IN C . N E ITH E R TH IS S H E E T N O R T H E I N F O R M A T I O N IT C O N TA IN S
M A Y B E U S E D B Y O R D IS C L O S E D T O A N Y TH IR D P A R T Y W I T H O U T P R I O R W R I T T E N C O N S E N T O F C O M P A L E L E C TR O N IC S , IN C .
Custom

5 4 3 2 1
5 4 3 2 1
UC1F SKL-U https://vinafix.com +3VS

Rev_0.53
LPSS ISH
AN8
GPP_B15/GSPI0_CS# P2 DGPU_PW R_EN RC382 1 2 10K_0402_5%
AP7
GPP_B16/GSPI0_CLK GPP_D9 TS_GPIO_CPU <27>
AP8 P3
GSPI0_MOSI GPP_B17/GSPI0_MISO GPP_D10
AR7 P4
GPP_B18/GSPI0_MOSI GPP_D11 +3V_PRIM
P1
AM5 GPP_D12
AN7 GPP_B19/GSPI1_CS# M4
D GPP_D5/ISH_I2C0_SDA N3 D
SOC_GPIOB21 AP5 GPP_B20/GSPI1_CLK RPC14
GSPI1_MOSI AN5 GPP_B21/GSPI1_MISO GPP_D6/ISH_I2C0_SCL 1 8
GPP_B22/GSPI1_MOSI N1 W L_OFF# 2 7
TP@T129 UART_0_CRXD_DTXD AB1 GPP_D7/ISH_I2C1_SDA N2 SOC_GPIOB21 3 6
TP@T128 UART_0_CTXD_DRXD AB2 GPP_C8/UART0_RXD GPP_D8/ISH_I2C1_SCL NMI_DBG#_CPU 4 5
W 4 GPP_C9/UART0_TXD AD11 <5,33> NMI_DBG#_CPU
W L_OFF# AB3 GPP_C10/UART0_RTS# GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12 10K_0804_8P4R_5%
<30> W L_OFF# GPP_C11/UART0_CTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
TP@T133 UART_2_CRXD_DTXD AD1
UART_2_CTXD_DRXD GPP_C20/UART2_RXD
TP@T132 AD2 U1
GPP_C21/UART2_TXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
AD3 U2
GPP_C22/UART2_RTS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
AD4 U3
GPP_C23/UART2_CTS# GPP_D15/ISH_UART0_RTS#
U4
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
U7 AC1
GPP_C16/I2C0_SDA GPP_C12/UART1_RXD/ISH_UART1_RXD DGPU_PW R_EN <33>
U6 AC2 DGPU_HOLD_RST#
GPP_C17/I2C0_SCL GPP_C13/UART1_TXD/ISH_UART1_TXD
AC3
U8 GPP_C14/UART1_RTS#/ISH_UART1_RTS#
AB4
U9 GPP_C18/I2C1_SDA GPP_C15/UART1_CTS#/ISH_UART1_CTS#
GPP_C19/I2C1_SCL AY8
AH9 GPP_A18/ISH_GP0 BA8
AH10 GPP_F4/I2C2_SDA GPP_A19/ISH_GP1 BB7
GPP_F5/I2C2_SCL GPP_A20/ISH_GP2 BA7 +3VS
GPP_A21/ISH_GP3 AY7 ODD_PW R <37>
AH11 ODD_DA# <37>
AH12 GPP_F6/I2C3_SDA GPP_A22/ISH_GP4 AW 7
UART_2_CTXD_DRXD GPP_F7/I2C3_SCL GPP_A23/ISH_GP5 AP13 SOC_GPIOA12
GPP_A12/BM_BUSY#/ISH_GP6 T122 TP@
1
AF11 DGPU_HOLD_RST# RC923 1 @ 2 10K_0402_5%

R5194 AF12 GPP_F8/I2C4_SDA
@ 0_0402_5% GPP_F9/I2C4_SCL 6 OF 20
ODD_PW R RC929 1 2 10K_0402_5%
UART_2_CRXD_DTXD
SKL-U_BGA1356
2
ODD_DA# RC930 1 2 10K_0402_5%
C C
CPU THERMAL SENSOR
Functional Strap Definitions Strap Pin Address : 0x48
+3VS UC3
1 5
<7,33> EC_SMB_CK2 SMBCLK SMBDATA EC_SMB_DA2 <7,33>
SPKR (Internal Pull Down): 2 +3VS
RC117 1 @ 2 100K_0402_5% HDA_SPKR GND
HDA_SPKR <8,32>
TOP Swap Override 3
ALERT# +Vs
4
1
0 = Disable TOP Swap mode.---> AAX05 Use RC118 1 @ 2 4.7K_0402_5% GSPI0_MOSI CC127
G753T11U_SOT23-5 0.1U_0201_10V6K
SA00008CH00
1 = Enable TOP Swap Mode. 2
RC201 1 @ 2 150K_0402_1% GSPI1_MOSI
<DB> Change Thermal Sensor IC

GSPI0_MOSI (Internal Pull Down):
No Reboot
0 = Disable No Reboot mode. --> AAX05 Use
1 = Enable No Reboot Mode. (PCH will disable the TCO

Timer system reboot feature). This f unction is usef ul
when running ITP/XDP.
B B
GSPI1_MOSI (Internal Pull Down):
Boot BIOS Strap Bit
0 = SPI Mode --> AAX05 Use
1 = LPC Mode
A A
2017/04/10
Compal Secret Data
2019/12/15 Title
TH IS S H E E T O F E N G I N E E R I N G D R A W IN G IS T H E P R O P R I E T A R Y P R O P E R T Y O F C O M P A L E L E C TR O N IC S , IN C . A N D C O N TA IN S CONFIDENT I A L
SKL-U(6/12)GPIO
S ii ze Document Number Rev
D E P A R TM E N T E X C E P T A S A U T H O R I Z E D B Y C O M P A L E L E C TR O N IC S , IN C . N E ITH E R TH IS S H E E T N O R T H E I N F O R M A T I O N IT C O N TA IN S
Custom v0.3

5 4 3 2 1
5 4 3 2 1
UC1H SKL-U
Rev_0.53
SSIC / USB3
https://vinafix.com
PCIE/USB3/SATA
H8 USB3_CRX_DTX_N1 <38>
USB3_1_RXN
G8 USB3_CRX_DTX_P1 <38>
H13 USB3_1_RXP
C13 USB3_CTX_DRX_N1 <38> USB2.0/USB3.0
G13 PCIE1_RXN/USB3_5_RXN USB3_1_TXN
D13 USB3_CTX_DRX_P1 <38>
B17 PCIE1_RXP/USB3_5_RXP USB3_1_TXP
A17 PCIE1_TXN/USB3_5_TXN J6 USB3_CRX_DTX_N2 <38>
PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN H6
USB3_2_RXP/SSIC_1_RXP USB3_CRX_DTX_P2 <38>
G11 B13 USB3_CTX_DRX_N2 <38>
D
PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13
USB2.0/USB3.0 D
F11 USB3_CTX_DRX_P2 <38>
D16 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP
C16 PCIE2_TXN/USB3_6_TXN J10
PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN H10
H16 USB3_3_RXP/SSIC_2_RXP B15
G16 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN A15
D17 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP
C17 PCIE3_TXN E10
PCIE3_TXP USB3_4_RXN F10
G15 USB3_4_RXP C15
F15 PCIE4_RXN USB3_4_TXN D15
B19 PCIE4_RXP USB3_4_TXP
A19 PCIE4_TXN AB9
PCIE4_TXP USB2N_1 USB20_N1 <38>
AB10 USB20_P1 <38> USB2.0/USB3.0
PCIE_CRX_DTX_N5 F16 USB2P_1
<29> PCIE_CRX_DTX_N5 PCIE5_RXN
LAN <29> PCIE_CRX_DTX_P5 PCIE_CRX_DTX_P5 E16 AD6 USB20_N2 <38>
PCIE5_RXP USB2N_2
*PCIe for Device Down
CC177 2 1 0.1U_0402_16V7K PCIE_CTX_DRX_N5 C19 AD7
Place AC coupling capacitors very close to either
the transmitter or the receiver.
<29> PCIE_CTX_C_DRX_N5
CC176 2 1 0.1U_0402_16V7K PCIE_CTX_DRX_P5 D19
PCIE5_TXN USB2P_2 USB20_P2 <38> USB2.0/USB3.0
*TX/RX with Cap <29> PCIE_CTX_C_DRX_P5 PCIE5_TXP
AH3 USB20_N3 <39>
PCIE_CRX_DTX_N6 G18 USB2N_3
<30> PCIE_CRX_DTX_N6 AJ3 USB20_P3 <39> USB2.0
PCIE_CRX_DTX_P6 F18 PCIE6_RXN USB2P_3
WLAN <30> PCIE_CRX_DTX_P6
*PCI Express* Connector
Place AC caps closer to the PCIe* connector. <30> PCIE_CTX_C_DRX_N6 CC175 2 1 0.1U_0402_16V7K PCIE_CTX_DRX_N6 D20 PCIE6_RXP AD9 USB20_N4 <39>
*Only TX with Cap, RX Cap on Add in Card CC174 2 1 0.1U_0402_16V7K PCIE_CTX_DRX_P6 C20 PCIE6_TXN USB2N_4 AD10
<30> PCIE_CTX_C_DRX_P6 USB20_P4 <39> Card Reader
PCIE6_TXP USB2P_4
<37> SATA_CRX_DTX_N0 F20 AJ1 USB20_N5 <27>
PCIE7_RXN/SATA0_RXN USB2N_5
<37> SATA_CRX_DTX_P0 E20 AJ2 USB20_P5 <27> Camera
PCIE7_RXP/SATA0_RXP USB2P_5
HDD <37> SATA_CTX_DRX_N0 B21 USB2
PCIE7_TXN/SATA0_TXN
<37> SATA_CTX_DRX_P0 A21 AF6 USB20_N6 <30>
PCIE7_TXP/SATA0_TXP USB2N_6
C AF7 USB20_P6 <30> BT C
USB2P_6
<37> SATA_CRX_DTX_N1 G21
PCIE8_RXN/SATA1A_RXN
<37> SATA_CRX_DTX_P1 F21 AH1 USB20_N7 <27>
PCIE8_RXP/SATA1A_RXP USB2N_7
ODD <37> SATA_CTX_DRX_N1 D21 AH2 USB20_P7 <27> TS
PCIE8_TXN/SATA1A_TXN USB2P_7
<37> SATA_CTX_DRX_P1 C21
PCIE8_TXP/SATA1A_TXP AF8
E22 USB2N_8 AF9
E23 PCIE9_RXN USB2P_8
B23 PCIE9_RXP AG1
A23 PCIE9_TXN USB2N_9 AG2
PCIE9_TXP USB2P_9
F25 AH7
PCIE10_RXN USB2N_10
E25 AH8
PCIE10_RXP USB2P_10
D23
PCIE10_TXN AB6 USB2_COMP RC119 1 2 113_0402_1%
C23
PCIE10_TXP USB2_COMP AG3 USB2_ID
RC120 1 2 100_0402_1% PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE
PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE
PCIE_RCOMPP A9 USB_OC0#
D56 GPP_E9/USB2_OC0# C9 USB_OC1#
XDP_PREQ# D61 PROC_PRDY# GPP_E10/USB2_OC1# D9 USB_OC2#
<5> XDP_PREQ# BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9 USB_OC3#
SOC_GPIOA7 USB2_ID RC20 1 Rshort@20_0402_5%
GPP_A7/PIRQA# GPP_E12/USB2_OC3#
<31> PCIE_CRX_DTX_N11 PCIE_CRX_DTX_N11 E28 J1 DEVSLP0 T241 TP@
PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 USB2_VBUSSENSE1 Rshort@
2
M.2 SSD <31> PCIE_CRX_DTX_P11 PCIE_CRX_DTX_P11 E27 J2 DEVSLP1
CC178 0.22U 6.3V K X5R 0402 2 1 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 RC21 0_0402_5%
<31> PCIE_CTX_C_DRX_N11 PCIE_CTX_DRX_N11 D24 J3 DEVSLP2 <31>
*For PCIe* Gen 3/ SATA multiplexed configuration, CC179 0.22U 6.3V K X5R 0402 2 1 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
<31> PCIE_CTX_C_DRX_P11 PCIE_CTX_DRX_P11 C24
motherboard Tx requires a 220 nF
PCIE11_TXP/SATA1B_TXP
AC capacitor and NO AC capacitor is required for
<31> PCIE_CRX_DTX_N12 PCIE_CRX_DTX_N12 E30 H2 SATA_GP0
motherboard Rx channel. This option DOES NOT PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0
supportAC
*Place DCcaps
coupled ODDs
closer to/the
Devices.
M.2 connector. <31> PCIE_CRX_DTX_P12 PCIE_CRX_DTX_P12 F30 H3 ODD_PLUG# ODD_PLUG# <37>
B *Only TX with Cap, RX Cap on Add in Card
CC180 0.22U 6.3V K X5R 0402 2 1 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 B
<31> PCIE_CTX_C_DRX_N12 PCIE_CTX_DRX_N12 A25 G4 SSD1_IF SSD1_IF <31>
CC181 0.22U 6.3V K X5R 0402 2 1 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2
<31> PCIE_CTX_C_DRX_P12 PCIE_CTX_DRX_P12 B25
PCIE12_TXP/SATA2_TXP
H1 SATA_LED# <39>
GPP_E8/SATALED#
8 OF 20 +3VS
SKL-U_BGA1356 2
DEVSLP1 1
SOC_GPIOA7 RC3621 2 10K_0402_5%
GPIO DEVICE CONTROL RC361 10K_0402_5%
When PCIE8/SATA1A is used USB_OC0# USB2 Port 1 and Port 2 SATA_LED# 1

RPC13
8
as SATA Port 1 (ODD), then SATA_GP0 2 7
PCIE11/SATA1B (M.2 SSD) USB_OC1# USB2 Port 3 SSD1_IF 3 6
ODD_PLUG# 4 5
cannot be used as SATA
Port 1. USB_OC2# N/A
10K_0804_8P4R_5%
USB_OC3# N/A +3V_PRIM
DEVSLP0 N/A
RPC20
N/A USB_OC1# 1 8
DEVSLP1 USB_OC3# 2 7
USB_OC0# 3 6
DEVSLP2 NGFF SSD KEY- M USB_OC2# 4 5
10K_0804_8P4R_5%
SATA_GP0 N/A
A A
SATA_GP1 ODD_PLUG#
SATA_GP2 PCIE/SATA
2017/04/10
Compal Secret Data
2019/12/15 Title
THIS SHEET O F ENG INEERING DRAW ING IS T HE PRO PRIET ARY PRO PERT Y O F COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENSSTiIzzAeL
SKL-U(7/12)PCIE,USB,SATA
Document Number Rev

5 4 3 2 1
5 4 3 2 1
+1.0V_PRIM TO +1.0V_VCCSTU
+1.2V_VDDQ +1.0V_PRIM https://vinafix.com
UC1N SKL-U
Rev_0.53
CPU POWER 3 OF 4
+5VALW +1.0V_PRIM +1.0V_PRIM +1.0V_VCCSTU
AU23 AK28
VDDQ_AU23 VCCIO
I (Max) : 4.5 A AU28
VDDQ_AU28 VCCIO
AK30
R5188 1 @ 2 0_0603_5% AU35
VDDQ_AU35 VCCIO
AL30 I (Max) : 3.4 A
AU42 AL42
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 VDDQ_AU42 VCCIO
I (Max) : 0.04 A(+1.0V_VCCSTU) BB23 AM28
CC98
CC97
1 VDDQ_BB23 VCCIO
1@ CC96 BB32 AM30
0.1U_0402_25V6
D
@ RON(Max) : 25 mohm 0.1U_0201_10V6K VDDQ_BB32 VCCIO D
BB41 AM42
CC151
2 2 V drop : 0.001 V BB47
VDDQ_BB41 VCCIO
2 VDDQ_BB47
BB51 AK23 +VCC_SA
2 VDDQ_BB51 VCCSA
AK25
UC5 VCCSA
G23
1 14 AM40 VCCSA
+1.2V_VDDQ G25
RC142 1 2 0_0402_5% 2 VIN1 VOUT1 13 VDDQC VCCSA
G27
<33,40,49> SYSON VIN1 VOUT1 A18 VCCSA
+1.0V_VCCST G28
RC144 1 @ 2 0_0402_5% EN_1.0V_VCCSTU 3 12 1.0V_VCCSTU_CT1 1 2 VCCST VCCSA
J22
<9,33,40,49> PM_SLP_S4# ON1 CT1 VCCSA
CC95
+1.0V_PRIM A22
VCCSTG_A22 VCCSA
J23 I (Max) : 5 A
RC168 1 2 0_0402_5% 4 11 10P_0402_50V8J J27
<33,40,49> SUSP# VBIAS GND AL23 VCCSA
+1.2V_VCCSFR_OC K23
RC194 1 @ 2 0_0402_5% EN_1.8VS 1 2 VCCPLL_OC VCCSA
5 10 1.8VS_CT2 K25
<9,33,40> PM_SLP_S3# ON2 CT2 @CC94 VCCSA
+1.0V_VCCSFR K20 K27
6 9 1000P_0402_50V7K VCCPLL_K20 VCCSA
K21 K28
+1.8V_PRIM 7 VIN2 VOUT2 8 VCCPLL_K21 VCCSA
K30
VIN2 VOUT2 +1.8VS VCCSA
15 AM23 VCCIO_SENSE T124 TP@
GPAD VCCIO_SENSE
AM22 VSSIO_SENSE T125 TP@
VSSIO_SENSE
EM5209VF_DFN14_2X3 <Cocoa_1113>
SA00007PM00 1 H21 VSSSA_SENSE
Per
1U_0402_6.3V6K
1 VSSSA_SENSE VSSSA_SENSE <52>
CC99 CC100 H20 VCCSA_SENSE
0.1U_0201_10V6K 543977_SKL_PDDG_Rev0_91,
VCCSA_SENSE <52>
I (Max) : 0.536 A(+1.8VS) 14 OF 20VCCSA_SENSE
@
2 RON(Max) : 25 mohm 2
change CC95 value from
V drop : 0.013 V 1000pf to 10pf for meet SKL-U_BGA1356
<= 65us timing for
+1.0V_VCCSTU power rail.
C C
+1.0V_VCCSTU +1.0V_VCCST Vinafix.com

RC140 1 2 0_0402_5%
PSC Side
+1.0V_PRIM TO +1.0VS_VCCSTG / +1.0VS_VCCIO
1U_0402_6.3V6K
1
CC48
+5VALW +1.0V_PRIM I (Max) : 3 A(+1.0VS_VCCIO) +1.0V_PRIM
2
RON(Max) : 6.2 mohm near pin A22
V drop : 0.019 V @
Imax : 2.77 A CC89 1 2 0.1U_0201_10V6K
0.1U_0201_10V6K
1U_0402_6.3V6K
1 1
@
CC88
CC117
UC6 @ RC208 Follow 544669_SKL_U DDR3L_RVP7_Schematic_Rev1.0

1 +1.0V_PRIM
2@ 2 2 VIN1
VIN2 RC189 +1.0V_VCCSFR +1.0V_PRIM
7 6 +1.0VS_VCCSTG_IO 1@2 CC90 1 2 0.1U_0201_10V6K
VIN thermal VOUT SD002000080 PSC Side BSC Side
3 0_0805_5% RC143 1 2 0_0402_5%
VBIAS Imax : 3 A
SUSP# RC186 1 2 0_0402_5% 4 5
1U_0402_6.3V6K
ON GND 1
1U_0402_6.3V6K
B
1 B
RC187 1 2 0_0402_5%
CC56
<33> EC_S0IX_EN @ TPS22961DNYR_WSON8
CC55
Part Number = SA00007XR00 2
2
For Verify S0IX <Cocoa_1027>
connect to EC, check /w EC
RC208 Follow 544669_SKL_U DDR3L_RVP7_Schematic_Rev0_53
+1.0V_PRIM +1.2V_VDDQ +1.2V_VDDQ

BSC Side PSC Side PSC Side BSC Side
BSC Side
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CC47 Follow 543016_SKL_U_Y_PDG_0_9
CC27
CC28
CC29
CC30
CC31
CC32
CC33
CC34
CC35
CC36
CC47
CC37
CC38
CC39
CC40
CC41
CC42
CC43
CC44
CC45
CC46
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
+1.35V_VDDQ_CPU : 10UF/6.3V/0603 *6
A 1UF/6.3V/0402 * 4 A
2017/04/10
Compal Secret Data
2019/12/15 Title
THIS SHEET O F ENGINEERING DRAW ING IS T HE PRO PRIET ARY PRO PERT Y O F COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENSTiIzAeL
SKL-U(8/12)Power
Document Number Rev
DEPART MENT EXCEPT AS AUT HO RIZED BY CO MPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMAT ION IT CONTAINS Custom
MAY BE USED BY O R DISCLO SED T O ANY THIRD PART Y W IT HO UT PRIO R W RIT T EN CONSENT O F COMPAL ELECTRONICS, INC. LA-G07FP(KBL-U_UMA_6L) v0.3

5 4 3 2 1
5 4 3 2 1
+1.0V_PRIM
+1.0V_PRIM
+1.0V_PRIM +1.0V_APLL +3V_PRIM +3V_HDA
1U_0201_6.3V6K
https://vinafix.com
1
UC1O SKL-U
0.69A Rev_0.53
1209_follow G group GPIO
22U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K
CC91
CPU POWER 4 OF 4
RC148 1 Rshort@2 0_0603_5% RC150 1 Rshort@2 0_0402_5% 1 1 1 powe rail to +3V_PRIM
@ @ 2 AB19
22U_0603_6.3V6M
22U_0603_6.3V6M
CC147
CC148
CC61
VCCPRIM_1P0
1 1 AB20 AK15 +3V_PGPPA
VCCPRIM_1P0 VCCPGPPA
near pin K15,L15 AG15
1U_0402_6.3V6K
CC142
CC134
@ @ 1 1 P18 +3V_PGPPB
CC63 2 2 2 VCCPRIM_1P0 VCCPGPPB Y16
VCCPGPPC +3V_PGPPC
AF18 Y15
CC72
1U_0201_6.3V6K +1.0V_PRIM VCCPRIM_CORE +3V_1.8V_PGPPD
2 2 2.574A AF19 VCCPGPPD T16
VCCPRIM_CORE +3V_PGPPE
2 2 +1.0VO_DSW V20 VCCPGPPE AF16
VCCPRIM_CORE +1.8V_PRIM
V21 VCCPGPPF AD15
VCCPRIM_CORE +3V_PRIM For SD CARD
VCCPGPPG
D D
+1.0V_PRIM AL1 V19 +3V_PRIM
DCPDSW_1P0 VCCPRIM_3P3_V19
Follow 543016_SKL_U_Y_PDG_1_0 K17 T1
1U_0201_6.3V6K
1 +1.0V_MPHYAON VCCMPHYAON_1P0 VCCPRIM_1P0_T1 +1.0V_DTS
L1
CC85
+1.0V_CLK5_F24NS +3V_PGPPA VCCMPHYAON_1P0 AA1
1U_0402_6.3V6K
VCCATS_1P8 +1.8V_PRIM
+3V_PRIM +1.0V_PRIM N15
VCCMPHYGT_1P0_N15
2 1.87A N16 AK17
CC68
1 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3 +3V_PRIM_RTC
RC152 1 Rshort@2 0_0603_5% N17
VCCMPHYGT_1P0_N17
near pin N18 P15
VCCMPHYGT_1P0_P15 VCCRTC_AK19
AK19
+RTCVCC
P16 BB14
2 VCCMPHYGT_1P0_P16 VCCRTC_BB14
10U_0402_6.3V6M
10U_0402_6.3V6M
1 1
@ @ +1.0V_PRIM K15 BB10 +DCPRTC 1 2
RC197 1 Rshort@2 0_0402_5% L15 VCCAMPHYPLL_1P0 DCPRTC CC71 0.1U_0201_10V6K
CC135
CC130
VCCAMPHYPLL_1P0 A14
2 2 VCCCLK1 +1.0V_CLK6_24TBT
+3V_SPI +1.0V_APLL V15
VCCAPLL_1P0 K19
AB17 VCCCLK2
1U_0402_6.3V6K
1 +1.0V_PRIM VCCPRIM_1P0_AB17
@ Y18 L21 +1.0V_APLL
CC67 RC154 1 Rshort@2 0_0402_5% VCCPRIM_1P0_Y18 VCCCLK3
+1.0V_PRIM +3VALW _DSW AD17 VCCCLK4 N20 +1.0V_CLK4_F100OC
2 VCCDSW _3P3_AD17
AD18
VCCDSW _3P3_AD18
AJ17 VCCCLK5 L19 +1.0V_CLK5_F24NS
VCCDSW _3P3_AJ17
+1.0V_CLK4_F100OC +3V_PGPPB
AJ19 A10
+3V_HDA VCCHDA VCCCLK6 +1.0V_CLK6_24TBT
1U_0201_6.3V6K
1
RC190 1 Rshort@2 0_0603_5% near pin AF20, +3V_SPI AJ16
VCCSPI GPP_B0/CORE_VID0
AN11 PRIMCORE_VID0 T130 TP@
RC161 1 Rshort@2 0_0402_5% AF21,T19, T20 AN13 PRIMCORE_VID1
CC141
GPP_B1/CORE_VID1 T131 TP@
AF20
22U_0603_6.3V6M
22U_0603_6.3V6M
+1.0V_PRIM VCCSRAM_1P0
2 0.64A AF21
1U_0402_6.3V6K
1 1 1 VCCSRAM_1P0
@ @ T19
CC136
CC137
VCCSRAM_1P0
CC102
T20
VCCSRAM_1P0
2 2 2 AJ21
+3V_PRIM VCCPRIM_3P3_AJ21
+1.0V_PRIM +1.0V_PRIM AK20
C VCCPRIM_1P0_AK20 C
N18
+1.0V_PRIM VCCAPLLEBB
+3V_PGPPC 15 OF 20
+1.0V_PRIM
SKL-U_BGA1356
Imax : 2.57A RC163 1 Rshort@2 0_0402_5% near pin N15, N16,
N17,P15,P16
1U_0402_6.3V6K
22U_0603_6.3V6M
22U_0603_6.3V6M
1 1 1
1U_0402_6.3V6K @
1
1U_0402_6.3V6K
CC80
CC81
CC82
near pin AF18,
1
RTC Battery
CC73
2 2 2
AF19,V20,V21
CC76
2 MAX. 8000mil
2
Per 543016_SKL_U_Y_PDG_0_9
VCCRTC does not exceed 3.2 V From PDG From Battery

+3V_1.8V_PGPPD +1.8V_PRIM CC7 Close UC1.AK19.
Power Rail Voltage +RTCBATT_R +3V_LID
+1.0V_MPHYAON +RTCVCC
1K_0402_5%
RC1721 Rshort@2 0_0402_5% RC2061 @ 2 0_0402_5% +CHGRTC 3.383V(MAX) RC19
DC1 15mils 15mils
RC175 1 Rshort@2 0_0402_5% 2 2 1
1U_0402_6.3V6K
1
BAT54C(VF) 240 mV
15mils 1
@
3
CC103
1 +3VL
CC7
1U_0402_6.3V6K
1 2 +3VL_RTC 3.143V 1U_0201_6.3V6K BAV70W 3P C/C_SOT-323

CC87
SC600000B00
2
2 Result : Pass
+3V_PGPPE
B B
NEED TOCHECK Kabylake No Support Deep S3.

+1.0V_CLK6_24TBT RC167 1 Rshort@2 0_0402_5%
1U_0402_6.3V6K
BOM
1
RC169 1 Rshort@2 0_0603_5%
CC74
2
+3VALW TO +3V_PRIM
1U_0402_6.3V6K
1U_0402_6.3V6K
22U_0603_6.3V6M
10U_0402_6.3V6M
1 1 1 1 I (Max) : 0.46 A(+3V_PRIM)

@ @ @ @
I (Max) : 0.1 A RDS(Typ) : 65 mohm
CC86
CC75
CC138
CC139
2 2 2 2 V drop : 0.03 V
+3V_PRIM_RTC
RC171 1 Rshort@2 0_0402_5%

+1.0V_DTS
0.1U_0201_10V6K
1U_0402_6.3V6K
1 1
CC78
CC77
RC162 1 Rshort@2 0_0402_5%

2 2
+1.2V_VCCSFR_OC +3V_PRIM
+1.2V_VDDQ +3VALW
0.1U_0201_10V6K
0.1U_0201_10V6K
Follow 543016_SKL_U_Y_PDG_0_9 1 1 1 1
@
1U_0402_6.3V6K
CC150
CC49
CC51
CC50
1U_0402_6.3V6K
+1.0V_PRIM +3V_PRIM +1.8V_PRIM
2 2 2 2
A
+3VS +3VS_PGPPA 1 2 2 1 A
RC141 0_0402_5% RC393 0_0805_5%
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0402_6.3V6M
22U_0402_6.3V6M
1 1 1 1 1 1
@ @ @ @ @ @
CC111
CC112
CC113
CC114
CC116
CC115
RC178 1 Rshort@2 0_0402_5%
2 2 2 2 2 2
+3VALW +3VALW _DSW
RC173 1 Rshort@2 0_0603_5%

2017/04/10
Compal Secret Data
2019/12/15 Title
SKL-U(9/12)Power
Follow 543016_SKL_U_Y_PDG_0_9 S ii ze Document Number
A N D T R A D E S E C R E T IN F O R M A T I O N . TH IS S H E E T M A Y N O T B E T R A N S F E R E D F R O M T H E C U S T O D Y O F T H E C O M P E T E N T D IV IS IO N O F R & D Rev
D E P A R TM E N T E X C E P T A S A U T H O R I Z E D B Y C O M P A L E L E C TR O N IC S , IN C . N E ITH E R TH IS S H E E T N O R T H E I N F O R M A T I O N IT C O N TA IN S Custom
M A Y B E U S E D B Y O R D IS C L O S E D T O A N Y TH IR D P A R T Y W I T H O U T P R I O R W R I T T E N C O N S E N T O F C O M P A L E L E C TR O N IC S , IN C . LA-G07FP(KBL-U_UMA_6L) v0.3

5 4 3 2 1
5 4 3 2 1
+VCC_GT_VR +VCC_GT
https://vinafix.com
JU42A
+VCC_CORE +VCC_CORE 1 2 +VCC_GT
+VCC_CORE 1 2
JUMP@ UC1M SKL-U
UC1L SKL-U JUMP_43X39_0805 Rev_0.53
Rev_0.53 CPU POW ER 2 OF 4
CPU POW ER 1 OF 4
JU22 N70
A30 G32 1 2 A48 VCCGT
+VCC_GT N71
VCC_A30 VCC_G32 1 2
A34 G33 JUMP@ A53 VCCGT VCCGT
R63
A39 VCC_A34 VCC_G33 G35 A58 VCCGT VCCGT
R64
A44 VCC_A39 VCC_G35 G37 JUMP_43X39_0805 A62 VCCGT VCCGT
R65
AK33 VCC_A44 VCC_G37 G38 A66 VCCGT VCCGT
R66
AK35 VCC_AK33 VCC_G38 G40 AA63 VCCGT VCCGT
R67
VCC_AK35 VCC_G40
D
AK37
AK38 VCC_AK37 VCC_G42
G42
J 30
JU42A/JU42B for KBLR AA64 VCCGT
AA66 VCCGT
VCCGT
VCCGT
R68
R69 D
AK40 VCC_AK38
VCC_AK40
VCC_J30
VCC_J33
J33 JU221 for KBLU AA67 VCCGT
VCCGT
VCCGT
VCCGT
R70
AL33 J37 AA69 R71
VCC_AL33 VCC_J37 VCCGT VCCGT
AL37 J40 AA70 T62
VCC_AL37 VCC_J40 VCCGT VCCGT
AL40 K33 AA71 U65
VCC_AL40 VCC_K33 VCCGT VCCGT
AM32 K35 AC64 U68
VCC_AM32 VCC_K35 VCCGT VCCGT
AM33 K37 AC65 U71
AM35 K38 AC66 W 63
AM37 K40 AC67 W 64
AM38 K42 AC68 W 65
G30 K43 Trace Length < 25 mils AC69 W 66
VCC_G30 VCC_K43 VCCGT VCCGT
AC70 W 67
K32 E32 VCCGT VCCGT
AC71 W 68
RSVD_K32 VCC_SENSE VCCCORE_SENSE <52> VCCGT VCCGT
E33 J43 W 69
VSS_SENSE VSSCORE_SENSE <52> VCCGT VCCGT
AK32 J45 W 70
RSVD_AK32 B63 SOC_SVID_ALERT# VCCGT VCCGT
J46 W 71 +VCC_GTX_VR
AB62 VIDALERT# A63 VCCGT VCCGT
J48 Y62
VR_SVID_CLK <52>
P62 VCCOPC_AB62 VIDSCK D64 VR_SVID_DATA J50
VCCGT VCCGT
V62 VCCOPC_P62 VIDSOUT
J52
VCCGT
JU42B
VCCOPC_V62 VCCGT
For CPU2+3e SKU G20 +1.0V_PRIM J53 AK42 1
1 2
2
+VCC_CORE
H63 VCCSTG_G20 VCCGT VCCGTX_AK42
J55 AK43 JUMP@
VCC_OPC_1P8_H63 VCCGT VCCGTX_AK43
J56 AK45
G61 VCCGT VCCGTX_AK45 JUMP_43X39_0805
J58 AK46
VCC_OPC_1P8_G61 VCCGT VCCGTX_AK46
J60 AK48
AC63 VCCGT VCCGTX_AK48
K48 AK50
AE63 VCCOPC_SENSE K50
VCCGT VCCGTX_AK50
AK52
VSSOPC_SENSE VCCGT VCCGTX_AK52
1 @ 2 K52 AK53
AE62 VCCGT VCCGTX_AK53
RC920 0_0402_5% K53 AK55
AG62 VCCEOPIO K55
VCCGT VCCGTX_AK55
AK56
VCCEOPIO VCCGT VCCGTX_AK56
K56 AK58
VCCGT VCCGTX_AK58
AL63 K58 AK60 For CPU2+3e SKU
AJ62 VCCEOPIO_SENSE K60
VCCGT VCCGTX_AK60
AK70
VSSEOPIO_SENSE VCCGT VCCGTX_AK70
12 OF 20 L62 AL43
VCCGT VCCGTX_AL43
L63 AL46
VCCGT VCCGTX_AL46
SKL-U_BGA1356
SOC PINS K52 AND AK52 L64 AL50
VCCGT VCCGTX_AL50
SHOULD BE LEFT UNCONNECTED L65
VCCGT VCCGTX_AL53
AL53
FOR KBL R U42 DESIGNS L66
VCCGT VCCGTX_AL56
AL56
L67 AL60
L68 VCCGT VCCGTX_AL60 AM48
C L69 VCCGT VCCG TX_AM 48 AM50 C
L70 VCCGT VCCG TX_AM 50 AM52
L71 VCCGT VCCG TX_AM 52 AM53
M62 VCCGT VCCG TX_AM 53 AM56
N63 VCCGT VCCG TX_AM 56 AM58
N64 VCCGT VCCG TX_AM 58 AU58
N66 VCCGT VCCG TX_AU58 AU63
N67 VCCGT VCCGTX_AU63 BB57
N69 VCCGT VCCGTX_BB57
SVID ALERT VCCGT VCCGTX_BB66
BB66
+1.0V_VCCST
Place the PU <52> VCCGT_SENSE
VCCGT_SENSE J70
VCCGT_SENSE VCCGTX_SENSE
AK62 VCCGTX_SENSE T155 TP@
VSSGT_SENSE J69 AL61 VSSGTX_SENSE
resistors close to CPU <52> VSSGT_SENSE VSSGT_SENSE VSSGTX_SENSE T219 TP@
13 OF 20
Trace Length < 25 mils
1
SKL-U_BGA1356
RC179
56_0402_5%
2
SOC_SVID_ALERT# 1 2
VR_ALERT# <52>
(To VR)
RC180 220_0402_5%
+1.0V_VCCST
SVID DATA Place the PU

resistors close to CPU
1
RC181
100_0402_1%
2
B B
VR_SVID_DATA <52> (To VR)
A A

SKL-U(10/12)Power,SVID
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN TSiIAzeeL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom v0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2 1
5 4 3 2 1
https://vinafix.com
D D
UC1P SKL-U UC1Q SKL-U
Rev_0.53 Rev_0.53 UC1R SKL-U
GND 1 OF 3 GND 2 OF 3
GND 3 OF 3
Rev_0.53
A5 AL65 AT63 BA49 F8 L18
VSS VSS VSS VSS VSS VSS
A67 AL66 AT68 BA53 G10 L2
A70 AM13 AT71 BA57 G22 L20
AA2 AM21 AU10 BA6 G43 L4
AA4 AM25 AU15 BA62 G45 L8
AA65 AM27 AU20 BA66 G48 N10
AA68 AM43 AU32 BA71 G5 N13
AB15 AM45 AU38 BB18 G52 N19
AB16 AM46 AV1 BB26 G55 N21
AB18 AM55 AV68 BB30 G58 N6
AB21 AM60 AV69 BB34 G6 N65
AB8 AM61 AV70 BB38 G60 N68
AD13 AM68 AV71 BB43 G63 P17
AD16 AM71 AW10 BB55 G66 P19
AD19 AM8 AW12 BB6 H15 P20
AD20 AN20 AW14 BB60 H18 P21
AD21 AN23 AW16 BB64 H71 R13
AD62 AN28 AW18 BB67 J11 R6
AD8 AN30 AW21 BB70 J13 T15
AE64 AN32 AW23 C1 J25 T17
AE65 AN33 AW26 C25 J28 T18
AE66 AN35 AW28 C5 J32 T2
AE67 AN37 AW30 D10 J35 T21
AE68 AN38 AW32 D11 J38 T4
C AE69 AN40 AW34 D14 J42 U10 C
AF1 AN42 AW36 D18 J8 U63
AF10 AN58 AW38 D22 K16 U64
AF15 AN63 AW41 D25 K18 U66
AF17 AP10 AW43 D26 K22 U67
AF2 AP18 AW45 D30 K61 U69
AF4 AP20 AW47 D34 K63 U70
AF63 AP23 AW49 D39 K64 V16
AG16 AP28 AW51 D44 K65 V17
AG17 AP32 AW53 D45 K66 V18
AG18 AP35 AW55 D47 K67 W13
AG19 AP38 AW57 D48 K68 W6
AG20 AP42 AW6 D53 K70 W9
AG21 AP58 AW60 D58 K71 Y17
AG71 AP63 AW62 D6 L11 Y19
AH13 AP68 AW64 D62 L16 Y20
AH6 AP70 AW66 D66 L17 Y21
AH63 AR11 AW8 D69
VSS VSS VSS VSS
AH64 AR15 AY66 E11
VSS VSS VSS VSS
AH67 AR16 B10 E15 18 OF 20
VSS VSS VSS VSS
AJ15 AR20 B14 E18
VSS VSS VSS VSS
AJ18 AR23 B18 E21
VSS VSS VSS VSS SKL-U_BGA1356
AJ20 AR28 B22 E46
VSS VSS VSS VSS
AJ4 AR35 B30 E50
VSS VSS VSS VSS
AK11 AR42 B34 E53
VSS VSS VSS VSS
AK16 AR43 B39 E56
VSS VSS VSS VSS
AK18 AR45 B44 E6
VSS VSS VSS VSS
AK21 AR46 B48 E65
VSS VSS VSS VSS
AK22 AR48 B53 E71
B VSS VSS VSS VSS B
AK27 AR5 B58 F1
VSS VSS VSS VSS
AK63 AR50 B62 F13
VSS VSS VSS VSS
AK68 AR52 B66 F2
VSS VSS VSS VSS
AK69 AR53 B71 F22
VSS VSS VSS VSS
AK8 AR55 BA1 F23
VSS VSS VSS VSS
AL2 AR58 BA10 F27
VSS VSS VSS VSS
AL28 AR63 BA14 F28
VSS VSS VSS VSS
AL32 AR8 BA18 F32
VSS VSS VSS VSS
AL35 AT2 BA2 F33
VSS VSS VSS VSS
AL38 AT20 BA23 F35
VSS VSS VSS VSS
AL4 AT23 BA28 F37
VSS VSS VSS VSS
AL45 AT28 BA32 F38
VSS VSS VSS VSS
AL48 AT35 BA36 F4
VSS VSS VSS VSS
AL52 AT4 F68 F40
VSS VSS VSS VSS
AL55 AT42 BA45 F42
VSS VSS VSS VSS
AL58 AT56 BA41
VSS VSS VSS
AL64 AT58
VSS VSS
16 OF 20 17 OF 20
SKL-U_BGA1356 SKL-U_BGA1356
A A
2017/04/10
Compal Secret Data
2019/12/15 Title
SKL-U(11/12)GND
AND T RADE SECRET INFORMAT ION. THIS SHEET MAY NO T BE T RANSFERED FRO M T HE CUST ODY O F T HE COMPET ENT DIVISION O F R&D Rev

5 4 3 2 1
5 4 3 2 1
Vinafix.com https://vinafix.com
D D
UC1S SKL-U
Rev_0.53
RESERVED SIGNALS-1
E68 BB68
CFG[0] RSVD_TP_BB68
B67 BB69
CFG[1] RSVD_TP_BB69
D65
CFG[2]
<5> CFG3 D67 AK13 T158 TP@
CFG4 E70 CFG[3] RSVD_TP_AK13
AK12 T159 TP@
CFG[4] RSVD_TP_AK12
C68
CFG[5]
D68 BB2
CFG[6] RSVD_BB2
C67 BA3
CFG[7] RSVD_BA3
F71
CFG[8]
G69
CFG[9] AU5
F70 TP5 T162 TP@
CFG[10] AT5
G68 TP6 T163 TP@
CFG[11]
H70
CFG[12]
G71
H69
CFG[13]
D5 <DB> Add ball E3/C7 for KBL U/R Colay
CFG[14] RSVD_D5
G70 D4
CFG[15] RSVD_D4 UC1T SKL-U
B2
RSVD_B2 C2 Remove T166 / T167 for 24MHz GND shielding
E63 RSVD_C2 Rev_0.53
CFG[16]
F63 SPARE
CFG[17] B3
RSVD_B3 A3 AW69 F6
E66 T252 TP@
F66 CFG[18] RSVD_A3 AW68 RSVD_AW69 RSVD_F6 E3 PCH_KBLR24_IN
C
CFG[19] AW1 AU56 RSVD_AW68 RSVD_E3 C11 C
CFG_RCOMP E60 RSVD_AW1 AW48 RSVD_AU56 RSVD_C11 B11
CFG_RCOMP E1 PCH_KBLR24_OUT C7 RSVD_AW48 RSVD_B11 A11
XDP_ITP_PMODE E8 RSVD_E1 E2 U12 RSVD_C7 RSVD_A11 D12
<5> XDP_ITP_PMODE ITP_PMODE RSVD_E2 RSVD_U12 RSVD_D12 C12
U11
AY2 BA4 H11 RSVD_U11 RSVD_C12 F52
AY1 RSVD_AY2 RSVD_BA4 BB4 RSVD_H11 RSVD_F52
RSVD_AY1 RSVD_BB4 20 OF 20
D1 A4
RSVD_D1 RSVD_A4 SKL-U_BGA1356
D3 C4
RSVD_D3 RSVD_C4
K46 BB5
RSVD_K46 TP4
K45
RSVD_K45 A69
RSVD_A69 B69
Eletro-XTechnical16 AL25
AL27 RSVD_AL25
RSVD_AL27
RSVD_B69
AY3 RC182 1 2 0_0402_5%
PCH_KBLR24_IN RX3 2 KBLR@ 1 33_0402_1%PCH_XTAL24R_IN
C71 RSVD_AY3
B70 RSVD_C71 D71
RSVD_B70 RSVD_D71 C70
F60 RSVD_C70
RSVD_F60 C54 PCH_KBLR24_OUT RX4 2 KBLR@ 1 33_0402_1% PCH_XTAL24R_OUT 1 KBLR@ 2
A52 RSVD_C54 D54 RC915 1M_0402_5%
RSVD_A52 RSVD_D54
BA70 AY4 KBLR@
RSVD_TP_BA70 TP1
BA68 BB3 YC3 SJ10000UJ00
RSVD_TP_BA68 TP2 24MHZ 18PF XRCGB24M000F2P51R0
J71 AY71 1 RC183 2 0_0402_5%
RSVD_J71 VSS_AY71
J68 AR56 PM_ZVM# T225 TP@ 3 1
RSVD_J68 ZVM# 3 1
B
For 2+3e Solution NC NC
B
F65 AW71
27P_0402_50V8J
27P_0402_50V8J
KBLR@ KBLR@
G65 VSS_F65 RSVD_TP_AW71 AW70 PM_ZVM# CC168 CC169
VSS_G65 RSVD_TP_AW70 PM_MSM# 4 2
SI 1/15 F61 AP56 PM_MSM# T230 TP@ +1.0V_VCCST
RSVD_F61 MSM#
E61 C64 SKL_CNL#
RSVD_E61 PROC_SELECT#
19 OF 20 1@ 2
RC184 100K_0402_5%
SKL-U_BGA1356
Follow 544669_SKL_U_DDR3L_RVP7_schematic_rev1.0 24MHzParrrttt::
Maiiiiiin::::::SJ10000X700,,,,,,S CRYSTAL 24MHZ 18PF +-20PPM
8Y24000033(((TXC)))
2nd::::::SJ10000TK00,,,,,,S CRYSTAL 24MHZ 18PF +-20PPM
7M24000027(((TXC)))
CFG_RCOMP 1 2
RC185 49.9_0402_1%
CFG4 1 2
RC193 1K_0402_1%
A A
Display Port Presence Strap
1 : Disabled; No Physical Display Port

CFG4 attached to Embedded Display Port Security Classification
2017/04/10
Compal Secret Data
2019/12/15 Title
0 : Enabled; An external Display Port device is SKL-U(12/12)RSVD
connected to the Embedded Display Port THIS SHEET O F ENGINEERING DRAW ING IS T HE PRO PRIET ARY PRO PERT Y O F COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENSTiIzAeL DocumentNumber
AND T RADE SECRET INFORMAT ION. THIS SHEET MAY NO T BE T RANSFERED FRO M T HE CUST ODY O F T HE COMPET ENT DIVISION O F R&D Rev

5 4 3 2 1
5 4 3 2 1
CHANNEL-A REVERSE TYPE

JDIMM1A https://vinafix.com
DDR_M0_CLK0 137 STD 8 DDR_M0_D0
<6> DDR_M0_CLK0
Interleaved Memory
CK0(T) DQ0
DDR_M0_CLK#0 139 7 DDR_M0_D4
<6> DDR_M0_CLK#0 CK0#(C) DQ1 20
DDR_M0_CLK1 138 DDR_M0_D3
<6> DDR_M0_CLK1 CK1(T) DQ2
<6> DDR_M0_CLK#1 DDR_M0_CLK#1 140 21 DDR_M0_D7
CK1#(C) DQ3
4 DDR_M0_D1
TOP: JDIMM1 CONN Non-ECC DIMM DDR_M0_CKE0 DQ4 DDR_M0_D5

<6> DDR_M0_CKE0 109 3
DDR_M0_CKE1 CKE0 DQ5 16 DDR_M0_D2
<6> DDR_M0_CKE1 110 DQ6
<6> DDR_M0_D[0..15] CKE1 17 DDR_M0_D6
DQ7
DDR_M0_CS#0 149 13 DDR_M0_DQS0
<6> DDR_M0_D[16..31] <6> DDR_M0_CS#0 S0# DQS0(T) DDR_M0_DQS0 <6>
DDR_M0_CS#1 157 11 DDR_M0_DQS#0
D +3VS +3VS +3VS <6> DDR_M0_CS#1 S1# DQS0#(C) DDR_M0_DQS#0 <6> D
162
<6> DDR_M0_D[32..47] S2#/C0
165 28 DDR_M0_D8
S3#/C1 DQ8 29 DDR_M0_D12
<6> DDR_M0_D[48..63] DQ9
1
1
DDR_M0_ODT0 155 41 DDR_M0_D14
<6> DDR_M0_ODT0 161 ODT0 DQ10 42 DDR_M0_D10
RD1 RD4 RD2 DDR_M0_ODT1
<6> DDR_M0_ODT1 ODT1 DQ11 24 DDR_M0_D9
@ 0_0402_5% @ 0_0402_5% @ 0_0402_5% JDIMM1B
STD DQ12 25 DDR_M0_D13
DDR_M0_BG0 115
<6> DDR_M0_BG0 BG0 DQ13 38 DDR_M0_D11
111 141 DDR_M0_BG1 113
+1.2V_VDDQ +1.2V_VDDQ <6> DDR_M0_BG1 BG1 DQ14
2
2
SA0_CHA_DIM1 SA1_CHA_DIM1 SA2_CHA_DIM1 VDD1 VDD11 DDR_M0_BA0 150 37 DDR_M0_D15
112 142 BA0 DQ15 34 DDR_M0_DQS1
VDD2 VDD12 <6> DDR_M0_BA0
117 147 DDR_M0_BA1 145
VDD3 VDD13 <6> DDR_M0_BA1 BA1 DQS1(T) 32 DDR_M0_DQS#1 DDR_M0_DQS1 <6>
118 148 DDR_M0_DQS#1 <6>
VDD4 VDD14 DQS1#(C)
1
1
123 153 DDR_M0_MA0 144
VDD5 VDD15 <6> DDR_M0_MA0 A0
RD3 RD5 RD6 124 154 DDR_M0_MA1 133 50 DDR_M0_D21
VDD6 VDD16 <6> DDR_M0_MA1 A1 DQ16
0_0402_5% 0_0402_5% 0_0402_5% 129 159 DDR_M0_MA2 132 49 DDR_M0_D17
130 160 DDR_M0_MA3 131 62 DDR_M0_D23
135 163 <6> DDR_M0_MA4 DDR_M0_MA4 128 63 DDR_M0_D18
VDD9 VDD19 A4 DQ19
2
2 +3V_PRIM_DA 136 DDR_M0_MA5 126 46 DDR_M0_D16

VDD10 <6> DDR_M0_MA5 A5 DQ20
<6> DDR_M0_MA6 DDR_M0_MA6 127 45 DDR_M0_D20
A6 DQ21
255 258 <6> DDR_M0_MA7 DDR_M0_MA7 122 58 DDR_M0_D19
VDDSPD VTT +0.6V_0.6VS DDR_M0_MA8 125
A7 DQ22
59 DDR_M0_D22
<6> DDR_M0_MA8 A8 DQ23
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM DDR_M0_MA9 121 55 DDR_M0_DQS2
0.1U_0201_10V6K
164 257 <6> DDR_M0_MA9
+2.5V
2.2U_0402_6.3V6M
+0.6V_DDR_VREFCA VREFCA VPP1 A9 DQS2(T) DDR_M0_DQS2 <6>
DDR_M0_MA10 53 DDR_M0_DQS#2
CD1
2 2 259 <6> DDR_M0_MA10 146 DQS2#(C) DDR_M0_DQS#2 <6>
VPP2 DDR_M0_MA11 120 A10_AP
<6> DDR_M0_MA11 A11
DDR_M0_MA12 119 70 DDR_M0_D25
CD2
1 99 <6> DDR_M0_MA12 A12 DQ24
VSS VSS 102 DDR_M0_MA13 158 71 DDR_M0_D28
2 VSS <6> DDR_M0_MA13 A13 DQ25
1 1 VSS
SPD ADDRESS FOR CHANNEL A : 5
6
VSS
VSS
VSS
VSS
103
106 9/8 Modify <6> DDR_M0_MA14_WE#
<6> DDR_M0_MA15_CAS#
DDR_M0_MA14_WE# 151
DDR_M0_MA15_CAS# 156
A14_W E#
A15_CAS#
DQ26
DQ27
83
84
DDR_M0_D30
DDR_M0_D31
WRITE ADDRESS: 0XA0 9 107 DDR_M0_MA16_RAS# 152 66 DDR_M0_D24

VSS VSS <6> DDR_M0_MA16_RAS# A16_RAS# DQ28
10 167 67 DDR_M0_D29
PLACE NEAR TO PIN VSS VSS
DDR_M0_ACT#
DQ29
READ ADDRESS: 0XA1 14 168 114 79 DDR_M0_D27
VSS VSS <6> DDR_M0_ACT# ACT# DQ30
15 171 80 DDR_M0_D26
VSS VSS DQ31
18 172 DDR_M0_PAR 143 76 DDR_M0_DQS3
SA0 = 0; SA1 = 0; SA2 = 0. 19
22
VSS
VSS
VSS
VSS
175
176 RD7 2
<6> DDR_M0_PAR
<6> DDR_M0_ALERT#
1
DDR_M0_ALERT# 116
DIMM1_CHA_EVENT# 134
PARITY
ALERT#
DQS3(T)
DQS3#(C)
74 DDR_M0_DQS#3
DDR_M0_DQS3
DDR_M0_DQS#3
<6>
<6>
VSS +1.2V_VDDQ EVENT#
DDR4 POR OPERATING SPEED: 1867 MT/S
VSS 180 DDR_DRAMRST#_R 108 174 DDR_M0_D32
23 VSS 240_0402_<16,18> DDR_DRAMRST#_R RESET# DQ32
C VSS 181 173 DDR_M0_D37 C
26 VSS DQ33
VSS
STRETCH GOAL IS 2133 MT/S 27
30
VSS
VSS
VSS
VSS
184
185
<7,18> PCH_SMBDATA
PCH_SMBDATA 254
SDA
DQ34
DQ35
187
186
DDR_M0_D34
DDR_M0_D39
31 188 PCH_SMBCLK 253 170 DDR_M0_D36
VSS VSS <7,18> PCH_SMBCLK SCL DQ36
35 189 169 DDR_M0_D33
VSS VSS DQ37
Layout Note: Layout Note: 36
VSS VSS
192 SA2_CHA_DIM1 166
SA2 DQ38
183 DDR_M0_D35
39 193 SA1_CHA_DIM1 260 182 DDR_M0_D38
Place near JDIMM1.257,259 Place near JDIMM1.258 40
VSS VSS
196 SA0_CHA_DIM1 256 SA1 DQ39
179 DDR_M0_DQS4
VSS VSS SA0 DQS4(T) DDR_M0_DQS4 <6>
43 197 177 DDR_M0_DQS#4
VSS VSS DQS4#(C) DDR_M0_DQS#4 <6>
44 201
VSS VSS
47 202 92 195 DDR_M0_D44
VSS VSS 91 CB0_NC DQ40
48 205 194 DDR_M0_D45
+2.5V +0.6V_0.6VS VSS VSS CB1_NC DQ41
10uF*2 10uF*2 51
VSS VSS
206 101
CB2_NC DQ42
207 DDR_M0_D42
52 209 105 208 DDR_M0_D43
1uF*2 1uF*1 VSS VSS CB3_NC DQ43
@ESD@
56
57
VSS VSS
210
213
For ECC DIMM 88
87 CB4_NC DQ44
191
190
DDR_M0_D41
DDR_M0_D40
VSS VSS 100 CB5_NC DQ45 203 DDR_M0_D46
214
10U_0603_6.3V6M
10U 6.3V M X5R 0603 H0.8
0.1U_0201_10V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
60
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 VSS VSS CB6_NC DQ46

217 104 204 DDR_M0_D47
CC159
61 VSS
VSS 218 97 CB7_NC DQ47 200 DDR_M0_DQS5
CD3
CD4
CD7
CD8
64
CD5
CD6
CD9
VSS VSS DQS8(T) DQS5(T) DDR_M0_DQS5 <6>

65 222 95 198 DDR_M0_DQS#5
2 2 2 2 2 2 2 2 VSS VSS DQS8#(C) DQS5#(C) DDR_M0_DQS#5 <6>
68 223
VSS VSS +1.2V_VDDQ
69 226 216 DDR_M0_D53
VSS VSS DQ48
72 227 12 215 DDR_M0_D48
VSS VSS 33 DM0#/DBI0# DQ49
73 230 228 DDR_M0_D54
VSS VSS 54 DM1#/DBI1# DQ50 229 DDR_M0_D50
77 231
78 234
81 235
82 238
85 239
VSS VSS 241 DM6#/DBI6# DQ55 221 DDR_M0_DQS6
86 243 DDR_DRAMRST#_R
VSS VSS DM7#/DBI7# DQS6(T) DDR_M0_DQS6 <6>
89 244 96 219 DDR_M0_DQS#6
VSS VSS DM8#/DBI8# DQS6#(C) DDR_M0_DQS#6 <6>
Layout Note: 90
VSS VSS
247
93 248 @ESD@
PLACE THE CAP near JDIMM1. 164 94
VSS VSS
251 CD10
VSS VSS
+3V_PRIM +3V_PRIM_DA 98
VSS VSS
252 PLACE NEAR TO SODIMM 0.1U_0402_25V6 237 DDR_M0_D60
DQ56 236 DDR_M0_D57
2 1
B B
DQ57
1 2 262 261 249 DDR_M0_D59
GND GND DQ58
RD32 0_0402_5% 250 DDR_M0_D62
DQ59
232 DDR_M0_D56
DQ60
+0.6V_DDR_VREFCA 2.2uF*1 FOX_AS0A827-H2RB-7H
DQ61
233 DDR_M0_D61
245 DDR_M0_D58
0.1uF*1 DQ62
246 DDR_M0_D63
CONN@ DQ63
2 2 242 DDR_M0_DQS7
DQS7(T) DDR_M0_DQS7 <6>
240 DDR_M0_DQS#7
DQS7#(C) DDR_M0_DQS#7 <6>
CD11 CD12
1 0.1U_0201_10V6K 1 2.2U_0402_6.3V6M Part Number:LTCX0069GA0
Part Value:S SOCKET FOX AS0A827-H2RB-7H 260P DDR4 FOX_AS0A827-H2RB-7H
+1.2V_VDDQ CONN@
DIMM Side CPU Side
2
Layout Note: RD8 +0.6V_DDR_VREFCA +0.6V_VREFCA
Place near JDIMM1 @ 2 1K_0402_1%
CD13
1
1 0.1U_0402_10V6K
1 RD9 2
VREF traces should be at least 20 mils
10uF*6 2_0402_1% wide with 20 mils spacing to other
+1.2V_VDDQ 1uF*8 +1.2V_VDDQ 1
signals
2
330uF*1
2
CD15
+1.2V_VDDQ RD10 CD14
2 0.022U_0402_25V7K
1K_0402_1%
1 0.1U_0402_10V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
RD11
CD93
CD16
CD17
CD18
CD19
CD20
CD21
CD22
CD23
CD95
A 1 A
24.9_0402_1%
CD96
CD24
CD25
CD26
CD27
CD28
CD29
CD30
CD31
CD94
C174 +
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Part Number = SF000006S00
1
330U_2.5V_M
2
@

P18-DDRIV_CHA: DIMM0
S i ze Document Number Rev
D E P A R TM E N T E X C E P T A S A U T H O R I Z E D B Y C O M P A L E L E C TR O N IC S , IN C . N E ITH E R TH IS S H E E T N O R T H E I N F O R M A T I O N IT C O N TA IN S v0.3
5 4 3 2 1
5 4 3 2 1
STD (5.2 mm)

CHANNEL-B Interleaved Memory <6> DDR_M1_CLK0
DDR_M1_CLK0 137
JDIMM2A
STD
https://vinafix.com
8 DDR_M1_D15
CK0(T) DQ0
DDR_M1_CLK#0 DDR_M1_D10
TOP: JDIMM2 CONN Non-ECC DIMM

139 7
<6> DDR_M1_CLK#0 CK0#(C) DQ1
DDR_M1_CLK1 138 20 DDR_M1_D11
<6> DDR_M1_D[0..15] <6> DDR_M1_CLK1 CK1(T) DQ2 21
DDR_M1_CLK#1 140 DDR_M1_D12
<6> DDR_M1_CLK#1 CK1#(C) DQ3
4 DDR_M1_D14
+3VS +3VS +3VS <6> DDR_M1_D[16..31] DQ4 DDR_M1_D9
DDR_M1_CKE0 109 3
<6> DDR_M1_CKE0 CKE0 DQ5 16
DDR_M1_CKE1 110 DDR_M1_D8
<6> DDR_M1_D[32..47] <6> DDR_M1_CKE1 CKE1 DQ6
17 DDR_M1_D13
DQ7
1
1
1
DDR_M1_CS#0 149 13 DDR_M1_DQS1
D <6> DDR_M1_D[48..63] <6> DDR_M1_CS#0 S0# DQS0(T) DDR_M1_DQS1 <6> D
RD19 RD20 RD21 DDR_M1_CS#1 157 11 DDR_M1_DQS#1
<6> DDR_M1_CS#1 S1# DQS0#(C) DDR_M1_DQS#1 <6>
@ 0_0402_5% 0_0402_5% @ 0_0402_5% JDIMM2B 162
STD S2#/C0 28 DDR_M1_D0
165 DQ8
S3#/C1 29 DDR_M1_D5
111 141
+1.2V_VDDQ +1.2V_VDDQ DQ9
2
2
SA0_CHB_DIM2 2 SA1_CHB_DIM2 SA2_CHB_DIM2 VDD1 VDD11 DDR_M1_ODT0 41 DDR_M1_D7

112 142 <6> DDR_M1_ODT0 155 DQ10
VDD2 VDD12 DDR_M1_ODT1 ODT0 42 DDR_M1_D6
117 147 <6> DDR_M1_ODT1 161 DQ11
VDD3 VDD13 ODT1 24 DDR_M1_D4
118 148 DQ12
VDD4 VDD14
1
1
1
123 153 DDR_M1_BG0 115 25 DDR_M1_D1
VDD5 VDD15 <6> DDR_M1_BG0 BG0 DQ13
RD22 RD23 RD24 124 154 DDR_M1_BG1 113 38 DDR_M1_D3
VDD6 VDD16 <6> DDR_M1_BG1 BG1 DQ14
0_0402_5% @ 0_0402_5% 0_0402_5% 129 159 DDR_M1_BA0 150 37 DDR_M1_D2
VDD7 VDD17 <6> DDR_M1_BA0 BA0 DQ15
130 160 <6> DDR_M1_BA1 DDR_M1_BA1 145 34 DDR_M1_DQS0
VDD8 VDD18 BA1 DQS1(T) DDR_M1_DQS0 <6>
135 163 32 DDR_M1_DQS#0
DQS1#(C) DDR_M1_DQS#0 <6>
2
VDD9 VDD19
2
2
+3V_PRIM_DB 136 DDR_M1_MA0 144
VDD10 <6> DDR_M1_MA0 A0
DDR_M1_MA1 133 50 DDR_M1_D20
255 258 DDR_M1_MA2 132 49 DDR_M1_D17
VDDSPD VTT +0.6V_0.6VS <6> DDR_M1_MA2
DDR_M1_MA3 131
A2 DQ17 62 DDR_M1_D19
164 257 DDR_M1_MA4 128 63 DDR_M1_D22
+2.5V
2.2U_0402_6.3V6M
+0.6V_DDRB_VREFCA VREFCA VPP1 259 <6> DDR_M1_MA4 A4 DQ19
1 2 DDR_M1_MA5 126 46 DDR_M1_D21
VPP2 <6> DDR_M1_MA5 A5 DQ20
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM CD60
1 99
<6> DDR_M1_MA6 DDR_M1_MA6
DDR_M1_MA7
127
122
A6 DQ21
45
58
DDR_M1_D16
DDR_M1_D18
CD61
VSS VSS <6> DDR_M1_MA7 A7 DQ22
0.1U_0201_10V6K 2 102 DDR_M1_MA8 125 59 DDR_M1_D23
VSS VSS <6> DDR_M1_MA8 A8 DQ23 55 DDR_M1_DQS2
2 1 5 103 DDR_M1_MA9 121
<6> DDR_M1_MA9
SPD ADDRESS FOR CHANNEL B : 6
9
VSS
VSS
VSS
VSS
106
107
<6>
<6>
DDR_M1_MA10
DDR_M1_MA11
DDR_M1_MA10
DDR_M1_MA11
146
A9
120 A10_AP
DQS2(T) 53 DDR_M1_DQS#2
DQS2#(C)
DDR_M1_DQS2
DDR_M1_DQS#2
<6>
<6>
WRITE ADDRESS: 0XA4 10 VSS VSS 167 A11

DDR_M1_MA12 119 70 DDR_M1_D25
PLACE NEAR TO PIN 14 VSS VSS 168
<6>
<6>
DDR_M1_MA12
DDR_M1_MA13 DDR_M1_MA13 158
A12 DQ24 71 DDR_M1_D24
READ ADDRESS: 0XA3 15
18
VSS
VSS
VSS
VSS
VSS
VSS
171
172 9/8 Modify <6> DDR_M1_MA14_W E#
<6> DDR_M1_MA15_CAS#
DDR_M1_MA14_W E#
DDR_M1_MA15_CAS#
151 A13
156 A14_W E#
A15_CAS#
DQ25
DQ26
DQ27
83
84
DDR_M1_D31
DDR_M1_D27
SA0 = 0; SA1 = 1; SA2 = 0. 19

22 VSS
VSS
VSS
VSS
175
176
<6> DDR_M1_MA16_RAS#
DDR_M1_MA16_RAS# 152
A16_RAS# DQ28
DQ29
66
67
DDR_M1_D28
DDR_M1_D29
23 180 DDR_M1_ACT# 114 79 DDR_M1_D30
DDR4 POR OPERATING SPEED: 1867 MT/S 26
27
VSS
VSS
VSS
VSS
181
184
<6> DDR_M1_ACT#
DDR_M1_PAR 143
ACT# DQ30 80 DDR_M1_D26
DQ31 76 DDR_M1_DQS3
STRETCH GOAL IS 2133 MT/S 30
31
VSS
VSS
VSS
VSS
185
188 RD25 2
<6> DDR_M1_PAR
<6> DDR_M1_ALERT#
1
DDR_M1_ALERT# 116 PARITY
DIMM2_CHB_EVENT# 134 ALERT#
DQS3(T) 74 DDR_M1_DQS#3
DQS3#(C)
DDR_M1_DQS3
DDR_M1_DQS#3
<6>
<6>
C 35 VSS VSS 189 +1.2V_VDDQ DDR_DRAMRST#_R 108 EVENT# 174 DDR_M1_D37 C
240<_064,1072>_1%DDR_DRAMRST#_R
VSS VSS RESET# DQ32
Layout Note: Layout Note: 36
VSS VSS
192
DQ33
173 DDR_M1_D33
39 193 187 DDR_M1_D35
Place near JDIMM2.257,259 Place near JDIMM2.258 40 VSS VSS 196 PCH_SMBDATA 254 DQ34 186 DDR_M1_D38
43 VSS VSS 197 <7,17> PCH_SMBDATA 253 SDA DQ35 170 DDR_M1_D32
PCH_SMBCLK
VSS VSS <7,17> PCH_SMBCLK SCL DQ36 169 DDR_M1_D36
44 201
47 VSS VSS 202 DQ37 183 DDR_M1_D34
SA2_CHB_DIM2 166
48 VSS VSS 205 260 SA2 DQ38 182 DDR_M1_D39
SA1_CHB_DIM2
+2.5V +0.6V_0.6VS VSS VSS 256 SA1 DQ39 179 DDR_M1_DQS4
10uF*2 10uF*2 51
VSS VSS
206 SA0_CHB_DIM2
SA0 DQS4(T) 177 DDR_M1_DQS#4 DDR_M1_DQS4 <6>
52 209
1uF*2 1uF*1 56 VSS VSS 210 DQS4#(C) DDR_M1_DQS#4 <6>
57 VSS VSS 213 92 195 DDR_M1_D44
60 VSS VSS 214 91 CB0_NC DQ40 194 DDR_M1_D45
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1
CD62
CD63
CD66
CD67
CD64
CD65
CD68

VSS VSS 87 CB4_NC DQ44
2 2 2 2 2 2 2 68
69 VSS VSS
223
226
For ECC DIMM 100 CB5_NC DQ45
190
203
DDR_M1_D41
DDR_M1_D43
73 VSS VSS 230 97 CB7_NC DQ47 200 DDR_M1_DQS5
77 VSS VSS 231 95 DQS8(T) DQS5(T) 198 DDR_M1_DQS#5 DDR_M1_DQS5 <6>
VSS VSS DQS8#(C) DQS5#(C) DDR_M1_DQS#5 <6>
78 234
81 VSS VSS 235 216 DDR_M1_D48
82 VSS VSS 238 12 DQ48 215 DDR_M1_D53
85 VSS VSS 239 +1.2V_VDDQ 33 DM0#/DBI0# DQ49 228 DDR_M1_D54
86 VSS VSS 243 54 DM1#/DBI1# DQ50 229 DDR_M1_D51
DDR_DRAMRST#_R
VSS VSS DM5#/DBI5# DQ54
Layout Note: 94
VSS VSS
251 220
DM6#/DBI6#
225 DDR_M1_D50
DQ55 221 DDR_M1_DQS6
98 252 241
PLACE THE CAP WITHIN 200 MILS VSS VSS 96 DM7#/DBI7# DQS6(T) 219 DDR_M1_DQS#6 DDR_M1_DQS6 <6>
FROM THE JDIMM2 262 261 @ESD@ DM8#/DBI8# DQS6#(C) DDR_M1_DQS#6 <6>
GND GND CD92
2 1
0.1U_0402_25V6
B FOX_AS0A827-H2SB-7H 237 DDR_M1_D60 B
DQ56
236 DDR_M1_D57
DQ57
+0.6V_DDRB_VREFCA 2.2uF*1 CONN@ DQ58
249 DDR_M1_D58
250 DDR_M1_D62
0.1uF*1 DQ59
232 DDR_M1_D56
Part Number:LTCX0069FA0 DQ60
233 DDR_M1_D61
2 2
Part Value:S SOCKET FOX AS0A827-H2SB-7H 260P DDR4 PLACE NEAR TO SODIMM DQ61
DQ62
245 DDR_M1_D59
CD69 CD70 246 DDR_M1_D63
DQ63
242 DDR_M1_DQS7
1 0.1U_0201_10V6K 1 2.2U_0402_6.3V6M +1.2V_VDDQ DQS7(T)
240 DDR_M1_DQS#7
DDR_M1_DQS7 <6>
+3V_PRIM +3V_PRIM_DB DQS7#(C) DDR_M1_DQS#7 <6>
1 2
RD33 0_0402_5% FOX_AS0A827-H2SB-7H
CONN@
Layout Note:
2
DIMM Side CPU Side
Vinafix.com
2
Place near JDIMM2 CD71
@ RD26
1 0.1U_0402_10V6K
1K_0402_1%
+0.6V_DDRB_VREFCA +0.6V_B_VREFDQ
1
10uF*6
1 RD27 2
+1.2V_VDDQ 1uF*8 +1.2V_VDDQ
330uF*1
2_0402_1%
VREF traces should be at least 20 mils
2 wide with 20 mils spacing to other
2
2
RD28 CD72
1
signals
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD81 1K_0402_1% CD82

1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0.1U_0402_10V6K
CD73
CD74
CD75
CD76
CD77
CD78
CD79
CD80
1 0.1U_0402_10V6K 2 0.022U_0402_25V7K
CD83
CD84
CD85
CD86
CD87
CD88
CD89
CD90
A A
2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
RD29
24.9_0402_1%
@ @
1
Issued Date 2017/04/10 Deciphered Date 2019/12/15 Tiiitlle
P19-DDRIV_CHB: DIMM0
D E P A R TM E N T E X C E P T A S A U TH O R I Z E D B Y C O M P A L E L E C TR O N IC S , IN C . N E ITH E R TH IS S H E E T N O R T H E I N F O R M A T I O N IT C O N TA IN S v0.3
5 4 3 2 1
5 4 3 2 1
eDP Power <6,7,9,10,11,13,17,18,28,29,30,31,32,33,36,39,40,52> +3VS +3VS

W =60mils
<46,47,48,49,50,53> +19VB +19VB
INVPW R_B+ +19VB
+LCDVDD SM010014520 3000ma W =60mils
https://vinafix.com
220ohm@100mhz <7,13,29,30,33,34,35,40,48,49,50,51> +3VALW +3VALW
DCR 0.04
L1 1 @ 2 0_0805_5%
4.7U_0402_6.3V6M
0.1U_0201_10V6K
1 1 SD002000080
CG3
CG2 @ L2 1 @ 2 0_0805_5%
SD002000080
2 2 1 2 DISPOFF#
@EMI@ C117
1 1
C118 1 2 <EC> <33> EC_BKOFF# R166 33_0402_5%
1
*UG1 +LCDVDD Current Limit : 0.8A 680P_0402_50V7K 68P_0402_50V8J FU1 0.75A_24V_MF-MSMF075/24
SP040009I00 R5176
2 2
10K_0402_5%
D D
2
UG2
9
GND
Rshort@
<5> ENVDD_CPU
R6 1 2 ENVDD_CPU_R 1
0_0402_5%
EN1 IN1
8 +3VS <CPU> <5> BKL_PW M_CPU
R259
1 Rshort@2
0_0402_5%
INVTPW M
1
+3VS R5198 1 @ 2 UG2_FLAG1 2 7 +LCDVDD
FLAG1 OUT1
100K_0402_5%
ENVDD_CPU R5200 1 @ 2 UG2_EN2 3 6 @ R163
EN2 IN2 +3VS
0_0402_5% 100K_0402_5%
R5201 1 2
0.1U_0402_16V7K
+3VS 4 5 +3VS_CAMERA
FLAG2 OUT2
2
100K_0402_5%
1U_0402_6.3V4Z
0.1U_0201_10V6K
1U_0402_6.3V4Z
0.1U_0402_16V7K
1U_0402_6.3V4Z
1 1 1 1 1 1
R5199 1 @ 2 UG2_FLAG2 G510F51U_MSOP8
CG75
C5232
CG76
C5231
+3VS
100K_0402_5% @
CG1
CG4
SA0000BEY00
2 2 2 2 2 2 RT34 1 Rshort@2 0_0201_5% EDP_HPD_R
<CPU> <5> EDP_HPD
Camera
1
RT11
100K_0402_5%
R170 EMI@ 1
2
2
SM070005U00 MURATA DLM0NSN900HY2D @ESD@
4 0_0201_5% 3 USB20_N5_R D7 SCA00000U10
<11> USB20_N5 4 3
@EMI@ USB20_P5_R 2
L12 1 2 USB20_P5_R 1
<11> USB20_P5 1 2 2 .1U_0402_16V7K EDP_AUXP_C
USB20_N5_R 3 CT102 1
<5> EDP_AUXP
EMI@ CT101 1 2 .1U_0402_16V7K EDP_AUXN_C
PESD5V0U2BT_SOT23 -3 <5> EDP_AUXN
1 2
R171 0_0201_5%
CT98 1 2 .1U_0402_16V7K EDP_TXP0_C
<5> EDP_TXP0
1 @ 2
R5196 0_0603_5% <CPU> CT97 1 2 .1U_0402_16V7K EDP_TXN0_C
C <5> EDP_TXN0 C
SD013000080
D_MIC_CLK
<32> D_MIC_CLK CT103 1 2 .1U_0402_16V7K EDP_TXP1_C
+3VS_CAMERA <5> EDP_TXP1
D_MIC_DATA 1 Rshort@2 D_MIC_L_DATA CT100 1 2 .1U_0402_16V7K EDP_TXN1_C
<32> D_MIC_DATA <5> EDP_TXN1
R175 0_0402_5%
1 1
@
+3VS
C5221 C5222
.1U_0402_16V7K 4.7U_0402_6.3V6M
2 2 SE00000SO00
C593 2 1 220P_0402_50V7K INVTPW M

*FG3 Camera Current Limit : 0.4A
1st:SA000080300, S IC G5250Q1T73U SOT-23 3P POWER SWITCH_0.4A C594 2 1 220P_0402_50V7K DISPOFF#
2nd:SA00004ZA00, S IC AP2330W-7 SC59 3P PWR SW_0.4A
eDP
Touch Screen R5175 EMI@
1 2
0_0201_5%
CONN@
JEDP
L13 EDP_TXP1_C 1
1 @EMI@ 2 USB20_P7_R TS_GPIO EDP_TXN1_C 2 1
1 2 1 @ 2
@ESD@ <11> USB20_P7 <10> TS_GPIO_CPU 2
R260 0_0402_5% 3
EDP_TXP0_C 3
D6 4
4
4 3 USB20_N7_R 1 2 EDP_TXN0_C 5
<11> USB20_N7 4 3 <33> TS_GPIO_EC 5
USB20_P7_R 2 SM070005U00 R5187 0_0402_5% 6
6
1 MURATA DLM0NSN900HY2D EDP_AUXP_C 7 7
USB20_N7_R 3 EMI@ EDP_AUXN_C 8 8
1 2 9 9
+LCDVDD
R173 0_0201_5% 10 10
PESD5V0U2BT_SOT23-3
B EDP_HPD_R 11 11 B
SCA00000U10 12 12
Touch screen USB20_P7_R 13 13
USB20_N7_R 14 14
DISPOFF# 15 15
+3VS_TOUCH
Touch Screen Power Selection: INVTPW M
TS_GPIO
16
17
16
17
18 18
19 19
INVPW R_B+
RTS7 1 @ 2 0_0402_5% 20 20
21 21
22 22
+5VS_TOUCH 23
+3VS_TOUCH 23
24 24
@ 25 GND
FG4 +3VS_TOUCH only for FHD with TS 25 36
+3VS_CAMERA 26 GND
USB20_N5_R 26 35
3 +3VS USB20_P5_R 27 27 GND 34
OUT Camera 28 GND 33
1 28
D_MIC_CLK 29 GND 32
@ 1 29
IN 30 GND 31
CTS3 D_MIC_L_DATA 30
4.7U_0402_6.3V6M
20mil
2
2 GND ACES_50203-03001-002
1
@ CTS7 SP010023710
SA00004ZA00 0.1U_0402_16V4Z
G5250Q1T73U SOT-23 3P POWER SWITCH
2
+5VS_TOUCH
RTS8 1 @ 2 0_0402_5%
TS@
FG2 +5VS_TOUCH only for HD with TS
3 +5VS
A OUT A
1
TS@ 1 20mil
IN
CTS6
4.7U_0402_6.3V6M 2
2 GND TS@ 1
CTS1
SA00004ZA00 0.1U_0402_16V4Z
G5250Q1T73U SOT-23 3P POWER SWITCH
2

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT I A L
eDP CONN/Camera/TS
Sii zee Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS v0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G07FP(KBL-U_UMA_6L)
5 4 3 2 1
5 4 3 2 1
<6,7,9,10,11,13,17,18,27,29,30,31,32,33,36,39,40,52> +3VS +3VS

+3VS
<27,32,33,34,36,37,40> +5VS +5VS
HOST_DP1_P0 0.1U_0402_16V7K 1 2 CG8 HDMI_TX_P2
<5> HOST_DP1_P0
<5> HOST_DP1_N0
HOST_DP1_N0 0.1U_0402_16V7K 1 2 CG9 HDMI_TX_N2 https://vinafix.com
<5> HOST_DP1_P1 HOST_DP1_P1 0.1U_0402_16V7K 1 2 CG10 HDMI_TX_P1
HOST_DP1_N1 0.1U_0402_16V7K 1 2 CG11 HDMI_TX_N1
<CPU> <5> HOST_DP1_N1
1
RG47
HOST_DP1_P2 0.1U_0402_16V7K 1 2 CG12 HDMI_TX_P0
<5> HOST_DP1_P2
HOST_DP1_N2 0.1U_0402_16V7K 1 2 CG13 HDMI_TX_N0 1M_0402_5%
<5> HOST_DP1_N2
2
HOST_DP1_P3 0.1U_0402_16V7K 1 2 CG14 HDMI_CLKP
<5> HOST_DP1_P3 RG108
2
D
HOST_DP1_N3 0.1U_0402_16V7K 1 2 CG15 HDMI_CLKN D
<5> HOST_DP1_N3
1 6 HDMI_HPD 1 2 HP_DETECT
<5> HOST_DP1_HPD
QG1A
20K_0402_5%
10K_0402_5%
5
6
7
8
5
6
7
8
L2N7002SDW1T1G 2N SC88-6
1
SB00001FF00 1
5V Level RG56 @
QG1B SB00001FF00 CM17
L2N7002SDW1T1G 2N SC88-6 220P_0402_50V7K
4
3
2
1
4
3
2
1
3 4 2
2
RP1 RP2
470_0804_8P4R_5% 470_0804_8P4R_5%
5
+3VS
+3VS
*DDA30_LA-F292PR02: RS_8.2ohm_RP_360ohm @ESD@

D21
HDMI_R_TX_N0 1 1 10 9 HDMI_R_TX_N0
HDMI_CLKP RG59 1 EMI@ 2 15 +-1% 0402 HDMI_R_CLKP
HDMI_R_TX_P0 2 2 9 8 HDMI_R_TX_P0
2
C CG71 EMI@ HDMI_R_CLKN 4 4 7 7 HDMI_R_CLKN C
2
360 +-5%0402
SD028360080 HDMI_R_CLKP 5 5 6 6 HDMI_R_CLKP
HOST_DP1_CTRL_CLK 1 6 HDMI_CTRL_CLK
<5> HOST_DP1_CTRL_CLK
1
HDMI_CLKN RG60 1 EMI@ 2 15 +-1% 0402 HDMI_R_CLKN 33

QG2A SB00001FF00
8 L2N7002SDW1T1G 2N SC88-6
+3VS
HDMI_TX_N2 RG63 1 EMI@ 2 15 +-1% 0402 HDMI_R_TX_N2
AZ1045-04F.R7G DFN2510P10E ESD
2
SC300001Y00
CG72 EMI@
5
360 +-5%0402
SD028360080
HOST_DP1_CTRL_DATA 4 3 HDMI_CTRL_DAT
<5> HOST_DP1_CTRL_DATA
1
HDMI_TX_P2 RG61 1 EMI@ 2 15 +-1% 0402 HDMI_R_TX_P2 @ESD@

D22 QG2B SB00001FF00
HDMI_R_TX_N1 1 1 10 9 HDMI_R_TX_N1 L2N7002SDW1T1G 2N SC88-6
HDMI_TX_P1 RG65 1 EMI@ 2 15 +-1% 0402 HDMI_R_TX_P1
HDMI_R_TX_P1 2 2 9 8 HDMI_R_TX_P1
2
CG73 EMI@ HDMI_R_TX_N2 4 4 7 7 HDMI_R_TX_N2 +HDMI_CRT_5V

360 +-5%0402
SD028360080 HDMI_R_TX_P2 5 5 6 6 HDMI_R_TX_P2
+3VS
1
HDMI_TX_N1 RG10 1 EMI@ 2 15 +-1% 0402 HDMI_R_TX_N1 33 RG105

1 8 HDMI_CTRL_CLK
8 2 7 HDMI_CTRL_DAT
HDMI_TX_P0 RG12 1 EMI@ 2 15 +-1% 0402 HDMI_R_TX_P0 3 6 HOST_DP1_CTRL_CLK
B AZ1045-04F.R7G DFN2510P10E ESD 4 5 HOST_DP1_CTRL_DATA B
2
SC300001Y00
CG74 EMI@ 2.2K_0804_8P4R_5%
360 +-5%0402 HDMI Conn.
SD028360080
1
HDMI_TX_N0 RG13 1 EMI@ 2 15 +-1% 0402 HDMI_R_TX_N0 @ESD@

DG1 JHDMI CONN@
HP_DETECT 1 1 10 9 HP_DETECT HP_DETECT 19
HP_DET
+HDMI_CRT_5V 18
+5V
HDMI_CTRL_DAT 2 2 9 8 HDMI_CTRL_DAT 17
DDC/CEC_GND
HDMI_CTRL_DAT 16
SDA
HDMI_CTRL_CLK 4 4 7 7 HDMI_CTRL_CLK HDMI_CTRL_CLK 15
SCL
14
5 5 Utility
6 6 13
CEC
HDMI_R_CLKN 12
3 3 @ @ CK-
11
HDMI_R_CLKP CK_shield
10P_0402_50V8J
10P_0402_50V8J
W=40mils 1 1 10
8 CM26 CM27 HDMI_R_TX_N0 CK+
FG1 9
+HDMI_CRT_5V D0-
8
AZ1045-04F.R7G DFN2510P10E ESD HDMI_R_TX_P0 D0_shield
7
3 SC300001Y00 2 2 HDMI_R_TX_N1 D0+
6
OUT D1-
5
1 HDMI_R_TX_P1 D1_shield 23
+5VS 4
IN HDMI_R_TX_N2 D1+ GND1 22
1 1 3
2 D2- GND2
2 21
GND HDMI_R_TX_P2 D2_shield GND3
1 20
CG46 CG47 D2+ GND4
0.1U_0402_16V7K 2 4.7U_0402_6.3V6M 2 ACON_HMRBL-AK120H
A AP2330W-7_SC59-3 A
DC231709273
SA00004ZA00

HDMI Conn/Level shift
Rev
v0.3
DEPARTMENT EXCEPT AS AUT HO RIZED BY CO MPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMAT ION IT CONTAINS
MAY BE USED BY O R DISCLOSED T O ANY THIRD PART Y W IT HO UT PRIO R W RIT T EN CONSENT O F COMPAL ELECTRONICS, INC. LA-G07FP(KBL-U_UMA_6L)
5 4 3 2 1
5 4 3 2 1
JL33
+LAN_VDD_3V3 Rising
1
12
2
JUMP@
time
+3VALW @
JUMP_43X79
need>0.5mS and https://vinafix.com
UL2
1
<100mS+LAN_VDD_3V3 CL8, CL23 closeLL2.
5 VOUT CL26 close UL1 Pin 3.
VIN
1 CL12 close UL1 Pin 8.
@ 2 +LAN_VDD_1V0
CL28 4 GND CL13 ~ CL15 close UL1 Pin 22.
<33> LAN_PWR_EN EN
1500P_0402_50V7K
2
LL2 CL11, CL27 close UL1 Pin 30.
3 +LAN_REGOUT 1 2
/OC
1U_0402_6.3V6K
2.2UH +-20% 1239AS-H-2R2M=P22A
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
4.7U_0402_6.3V6M
4.7U_0603_6.3V6K
G524B1T11U_SOT23-5 SH000014700 1 1 1 1 1 1 1 1 1 1
CL8
@
CL29
CL23
SA00006Y800 @
CL11 CL12 CL13 CL14 CL15 CL26 CL27
D @ D
2 2 2 2 2 2 2 2 2 2
EC_LAN_ISOLATEB#_R 2 1 +3VS
1K_0402_5% RM6
RTL8107ESH-CG/RTL8111HSH-CG Co-Lay
2
+LAN_VDD_3V3 +LAN_VDD_3V3
RM11
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
UL1 +LAN_VDD_3V3=40mil 15K_0402_5%

0.1U_0402_16V7K
0.1U_0402_16V7K
1 1 1 1 1 RTL8111HSH-CG
0.1U_0402_16V7K
1
1
L
CL16
@ +LAN_VDD_1V0
CL20 CL9 CL5 CL10
SA000084T00 +VDDREG=40mil
CL19
@
2 2 2 2 2 2 LAN_MDIP0 1 3 +LAN_REGOUT=60mil
LAN_MDIN0 2 MDIP0 AVDD10 8
LAN_MDIP1 4 MDIN0 AVDD10 30 +LAN_VDD_3V3 XTLI
LAN_MDIN1 5 MDIP1 AVDD10 22 +LAN_VDD_3V3
LAN_MDIP2 6 MDIN1 DVDD10 2 1 XTLO
LAN_MDIN2 7 MDIP2 11 1M_0402_5% RL7
LAN_MDIP3 9 MDIN2 AVDD33 32 +LAN_VDD_3V3
1
LAN_MDIN3 10 MDIP3 AVDD33
RL15
MDIN3
CL9, CL20 close to UL1 Pin 11 CL10& CL16 close to UL1: Pin 23 23
VDDREG(VDD33) 24 +LAN_REGOUT 10K_0402_5% YL1
REGOUT
CL5 & CL19 close to UL1: Pin 32 <9> CLKREQ_PCIE#1 CLKREQ_PCIE#1 2 Rshort@1 CLKREQ_PCIE#1_R 12 1
1 3
3
2
CLKREQB 21
PLT_RST# RL6 0_0201_5% 19 EC_PME# EC_PME# <33>
<9,30,31,33,35> PLT_RST# PERSTB LANWAKEB 20 NC NC
ISOLATEB EC_LAN_ISOLATEB#_R
15 +LAN_VDD_3V3
<9> CLK_PCIE_P1 CLK_PCIE_P1 REFCLK_P 2 2 4 2
16 27 LAN_ACT#
10P_0402_50V8J
CL25
CL24
10P_0402_50V8J
<9> CLK_PCIE_N1 CLK_PCIE_N1 REFCLK_N LED0
26 LED1/GPO 1@ 2
13 LED1/GPO 25 LAN_LINK#
PCIE_CTX_C_DRX_P5 LED2(LED1) RL56 4.7K_0402_5%
<11> PCIE_CTX_C_DRX_P5
PCIE_CTX_C_DRX_N5 14 HSIP 1 SJ10000UP00 1
<11> PCIE_CTX_C_DRX_N5
<11> PCIE_CRX_DTX_P5 PCIE_CRX_DTX_P5 CR11 1 2 0.1U_0402_10V7K PCIE_CRX_C_DTX_P5 17 HSIN HSOP CKXTAL1 29
28 25MHZ 10PF XRCGB25M000F2P34R0
<11> PCIE_CRX_DTX_N5 PCIE_CRX_DTX_N5 CR13 1 2 0.1U_0402_10V7K PCIE_CRX_C_DTX_N5 18 XTLO
XTLI
HSON CKXTAL2
RSET 31 33
RSET GND
2
C
RL11 C
TSL1 2.49K_0402_1%
25 XGND RL55 1 @ 2 0_0805_5% (SA0000ALR00) RTL8107ESH-CG 10/100
+V_DAC 1 LANGND 24
TCT1 MCT1
1
LAN_MDIP0 2 23 RJ45_MDIP0 RP5 (SA000084T00) RTL8111HSH-CGGiga
TD1+ MX1+
LAN_MDIN0 3 22 RJ45_MDIN0 MCT1 1 8
TD1- MX1-
MCT2 2 7
4 21 MCT3 3 6
LAN_MDIP1 TCT2 MCT2 20 RJ45_MDIP1 5
5 TD2+ MX2+ MCT4 4
LAN_MDIN1 6 19 RJ45_MDIN1
TD2- MX2- 75_0804_8P4R_1%
7 18 SD300002E80 2
LAN_MDIP2 TCT3 MCT3 17 RJ45_MDIP2
8 CL2 +LAN_VDD_3V3
LAN_MDIN2 9 TD3+ MX3+
16 RJ45_MDIN2 SE167100J80
TD3- MX3- JLAN
10 15 1 10P_1808_3KV A1
LAN_MDIP3 11 TCT4 MCT4 14 RJ45_MDIP3 White_LED+
TD4+ MX4+ 1
LAN_MDIN3 12 13 RJ45_MDIN3 CL3 LAN_LINK# 2 1 LAN_LINK#_R LAN_ACT#_R A2
TD4- MX4- 120P_0402_50V8J White_LED-
RL30 1K +-5% 0402
LANGND EMI@ RJ45_MDIN3 8
DI_D4-
3
2
2 1 LAN-8100G1G DL1 RJ45_MDIP3 7
DI_D4+
3
@EMI@ SP050008Y00 PESD5V0U2BT 3P CC SOT23 ESD

CL1 CL4 ESD@ RJ45_MDIN1 6
RX_D2-
SCA00000T00
1
1 0.01U_0402_16V7K 2 0.1U_0402_16V7K
RJ45_MDIN2 5
BI_D3-
1
RJ45_MDIP2 4
BI_D3+
RJ45_MDIP1 3
RX_D2+
RJ45_MDIN0 2 9
TX_D1- GND1
10
RJ45_MDIP0 1 GND2
11
TX_D1+ GND3
12
B1 GND4
Amber_LED+
LAN_ACT# 2 1 LAN_ACT#_R LAN_LINK#_R B2
Amber_LED-
RL31 510_0402_5%
SINGA_2RJ3081-1A8211F LANGND
DC231710035
@ESD@ @ESD@
B B
DM12 DM13
LAN_MDIP0 4 3 LAN_MDIN0 LAN_MDIP2 4 3 LAN_MDIN2
4 3 4 3
powe rail need to check powe rail need to check

+LAN_VDD_3V3 5 2 +LAN_VDD_3V3 5 2
Vbus GND Vbus GND
LAN_MDIN1 6 1 LAN_MDIP1 LAN_MDIN3 6 1 LAN_MDIP3

6 1 6 1
YSUSB2.0-5_SOT-23-6-6 YSUSB2.0-5_SOT-23-6-6
SC300001G00 SC300001G00
A A

Deciphered Date
T HI S S HE E T O F E NG I NE E R I NG D R AW I NG I S T HE P R O P R I E T AR Y P R O P E R T Y O F C O M P AL E L E C T R O NI C S , I NC . AND C O NT AI NS CONFIDENTSSIAizLe Document Number
LAN 8111
D E P AR T M E NT E X C E P T AS AUT HO R I Z E D B Y C O M P AL E L E C T R O NI C S , I NC . NE I T HE R T HI S S HE E T NO R T HE I NF O R M AT I O N I T C O NT AI NS
M AY B E US E D B Y O R D I S C L O SED T O ANY T HI R D P AR T Y W I T HO UT P R I O R W R I T T E N C O NS E NT O F C O M P AL E L E C T R O NI C S , I NC .

5 4 3 2 1
5 4 3 2 1
<6,7,9,10,11,13,17,18,27,28,29,31,32,33,36,39,40,52> +3VS +3VS

https://vinafix.com
<7,13,29,33,34,35,40,48,49,50,51> +3VALW +3VALW
D D
+3VS_W LAN
CONN@
2
JW LAN +3VS_W LAN
+3VS_W LAN
RN7
1 2 4.7K_0402_5%
3 1_GND 3.3V_2 4
<11> USB20_P6 3_USB_D+ 3.3V_4
1
5 6
<11> USB20_N6 5_USB_D- LED1#_6
7 8
7_GND N/C_8
9 10 @RF@ @RF@ @RF@ @RF@
0.1U_0402_25V6
100P_0402_50V8J
0.1U_0402_25V6
100P_0402_50V8J
9_N/C N/C_10
11 12 R5179 R5180 R5181 R5182 R5183 R5184
100P_0402_50V8J
0.1U_0402_25V6
11_N/C N/C_12
2 1
2 1
2 1
2 1
13 14 @RF@ @RF@
13_N/C N/C_14
2 1
2 1
15 16
15_N/C LED2#_16
17 18
17_N/C GND_18
19 20
19_N/C N/C_20
21 22
21_N/C N/C_22
23
23_N/C
+3VS_W LAN 25 24 +3VS_W LAN

33_GND N/C_32
27 26
<11> PCIE_CTX_C_DRX_P6 35_PERp0 N/C_34
29 28
<11> PCIE_CTX_C_DRX_N6 37_PERn0 N/C_36
1
31 30
39_GND CLink Reset_38 E51TXD_P80DATA <33>
1
33 32
<11> PCIE_CRX_DTX_P6 41_PETp0 CLink DATA_40 E51RXD_P80CLK <33>
35 34 RN15 @ R F @
<11> PCIE_CRX_DTX_N6 43_PETn0 CLink CLK_42
RN3 37 36 10K_0402_5%
45_GND COEX3_44
10K_0402_5% 39 38
<9> CLK_PCIE_P2 47_REFCLKP0 COEX2_46
2
41 40
<9> CLK_PCIE_N2 49_REFCLKN0 COEX1_48
2
43 42 RN14 1 Rshort@2 0_0201_5% BT_ON_EC +3VS_W LAN

51_GND SUSCLK_50 SUSCLK <9>
45 53_CLKREK0# 44 PLT_RST# <9,29,31,33,35>
<9> CLKREQ_PCIE#2 PERST0#_52
47 46 BT_ON_EC <33>
<9,33> EC_PCIE_WAKE# 55_PEWake0# W _DISABLE2#_54
49 48 W L_OFF# <10>
57_GND W _DISABLE1#_56
51 50
C 59_N/C N/C_58 C
53 52
0.1U_0402_16V7K
61_N/C N/C_60
55 54
CN3
63_GND N/C_62 1 1
57 56 CN2
65_N/C RESERVED_64 +3VS_W LAN
58
1
R5185
R5186
59
10P_0402_50V8J
10P_0402_50V8J
67_N/C N/C_66
@RF@ @RF@ 61 60 22U_0603_6.3V6K
69_GND N/C_68 2 2
63 62
71_N/C N/C_70
2
65 64
73_N/C 3.3V_72
67 75_GND 3.3V_74 66
GND 68
GND 69
NC_70 70
NC_71 71
LOTES_APCI0019-P003H
SP070010DA0
Active Low
W L_PWREN_EC# <33>
1
NGFF and W LAN RW L1
200K_0402_5%
Unpop QB8 and RL25 for not supportOBFF CW L1
2
1 2
+3VS_W LAN
2
+3VS +3VS_W LAN 0.1U_0402_16V4Z
QW L1
G
B B
1 3
+3VALW
2
S
1
RL25 @ CW L2 PJ2301 1P SOT23-3
100K_0402_5% 0.1U_0402_16V4Z SB00000T900
2
G
@ 2
1 3 EC_PCIE_WAKE# 1 @ 2
<9> W AKE#
RW L2 0_0603_5%
D
SB00000EN00
QB8
2N7002H_SOT23-3
A A

Issued Date 2017/08/24 Deciphered Date 2018/08/24 Tiitttlle
THIS SHEET OF ENGINEERING DRAW ING IIIS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC. AND CONTAINS CONFIDENT I A L
WLAN-BT
Siii zee Documenttt Number Rev
AND TRADE SECRET INFORMATION... THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIIION OF R&D
v0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IIINC... NEITHER THIIIS SHEET NOR THE IIINFORMATION IIIT CONTAIIINS
MAY BE USED BY OR DISCLOSED TO ANY THIIIRD PARTY W ITHOUT PRIOR WRIIITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G07FP(KBL-U_UMA_6L)
Date: Friday, January 05,,, 2018 Sheet 30 of 59
5 4 3 2 1
5 4 3 2 1
+3VS +3VS_SSD
JPHW9 <6,7,9,10,11,13,17,18,27,28,29,30,32,33,36,39,40,52> +3VS +3VS

1 1 2 2 https://vinafix.com
JUMP_43X79 CS27 CSS7 CS8 CS9 1 CSS6
1 CSS5 JUMP@ 1@ 1 1 1
47U_0603_6.3V6M
10U_0603_10V6M
0.1U_0201_10V6K
1U_0402_6.3V6K
RF@ CS10
18P_0201_50V NPO
10P_0201_50V
RF@
2 1
2 2 2 2 2 2 10P_0201_50V
RF@
D D
JSSD
1 2 +3VS_SSD
GND 3P3VAUX
3 4
GND 3P3VAUX
5 6
PETn3 NC
7 8
PETp3 NC TS123
9 10
GND DAS/DSS# TP@
11 12
PERn3 3P3VAUX
13 14
PERp3 3P3VAUX
15 16
GND 3P3VAUX
17 18
PETn2 3P3VAUX 20
19 NC
PETp2 22
21 NC
GND 24
23 NC
PERn2 26
25
<11> PCIE_CRX_DTX_N11 29
Key TYP. M
27 PERp2
GND
PETn1
NC
NC
NC
28
30
<SSD> 31 32
<11> PCIE_CRX_DTX_P11 PETp1 NC
33 34
GND NC
<11> PCIE_CTX_C_DRX_N11 35 36
PERn1 NC
<11> PCIE_CTX_C_DRX_P11 37 38 DEVSLP2 <11>
PERp1 DEVSLP 40
C 39 NC
C
GND 42 RS46 1 2 10K_0402_5%
41
<11> PCIE_CRX_DTX_P12 43
PETn0/SATA-B+ NC
44
<11> PCIE_CRX_DTX_N12 PETp0/SATA-B- NC
45 46
GND NC
<11> PCIE_CTX_C_DRX_N12 47 48
PERn0/SATA-A- NC
<11> PCIE_CTX_C_DRX_P12 49 50 PLT_RST#_SSD RT3 1 Rshort@ 2 0_0201_5% PLT_RST# <9,29,30,33,35>
PERp0/SATA-A+ PERST# CLKREQ_PCIE#4
51 52 CLKREQ_PCIE#4 <9>
GND CLKREQ#
<9> CLK_PCIE_N4 53 54
REFCLKN PEWake# 56
<9> CLK_PCIE_P4 55 NC
REFCLKP 58
57 NC
GND
1 2
+3VS @EMI@ CS16
VARIST_ CK0402101V05 0402 67 68
NC SUSCLK(32kHz)
SSD_PDET 69 70
PEDET 3P3VAUX
2
SSD1_IF PU on CPU side RPC13.3_10K 71 72

@ RS21 1 2 GND 3P3VAUX
+3VS 73 74
RS22 10K_0402_5% GND 3P3VAUX
100K_0402_5% 75
GND 76
GND1 77
GND2
<11> SSD1_IF
1 1
YPCI0016-P003A 67P A32

D
DC04000L9A0 CONN@
2
G
S QS1 SB000009Q80
3
2N7002KW_SOT323-3
B pre PV: change to 10K for redriver detect pin voltage level B
A A

Deciphered Date
M.2 SSD
Rev
DEPARTMENT EXCEPT AS AUT HO RIZED BY CO MPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMAT ION IT CONTAINS LA-G07FP(KBL-U_UMA_6L) v0.3
MAY BE USED BY O R DISCLOSED T O ANY THIRD PART Y W IT HO UT PRIO R W RIT T EN CONSENT O F COMPAL ELECTRONICS, INC.
5 4 3 2 1
5 4 3 2 1
https://vinafix.com
UA1 +3VS +DVDD +3VS +DVDD_IO
+5VS +5VS_PVDD1 RA1 RA2
RA8
<8> HDA_SYNC_R 9 1 +DVDD 1 2 1 2 1 2
BCLK SYNC DVDD
<8> HDA_BIT_CLK_R 5 8 +DVDD_IO
BCLK DVDD_IO 0_0402_5% 0_0402_5% 0_0402_5%
10U 6.3V M X5R 0603 CA19
4.7U_0402_6.3V6M CA32
0.1U 16V K X7R 0402 CA20
0.1U 16V K X7R 0402 CA33

1 2 1 2 20 +5VS_AVDD 1 1 11
4.7U_0402_6.3V6M CA36
0.1U 16V K X7R 0402 CA37

AVDD1
CA34 RA53 22_0402_5% 33 +1.8VS_AVDD 1 1
22P 50V J NPO 0402 EMI@ AVDD2
EMI@ INT_MIC 14 34
MIC2-R/SLEEVE PVDD1 +5VS_PVDD1 2 2 2 2
13 39
MIC2-L/RING2 PVDD2 +5VS_PVDD2 2 2
CA29
GNDA 1 2 MIC2_CAP 15 16 VD33STB1 RA23 2 +3VS
MIC2_CAP VD33STB
0_0402_5%
10U 6.3V M X5R 0603
D D
35 SPK_L+
SPK_OUT_L+
36 SPK_L-
SPK_OUT_L-
37 SPK_R-
PC_BEEP SPK_OUT_R-
11 38 SPK_R+
PCBEEP SPK_OUT_R+
26 HPOUT_R RA38 1 2 30_0402_1% HP_OUTR Headphone
HPOUT_R
25 HPOUT_L RA37 1 2 30_0402_1% HP_OUTL
HPOUT_L
100K_0402_5% 2.2K_0402_5%
RA24 1 2 INT_MIC RA40 1 2 MIC2-VREFO 23 +5VS +5VS_AVDD +1.8VS +1.8VS_AVDD
MIC2-VREFO 4 +5VS +5VS_PVDD2 RA5
SDATA_OUT RA39 RA4
7 HDA_SDIN0_R 1 2 HDA_SDOUT_R <8>
<33> MUTE_LED_IN 24 RA26 1 2 1 2 1 2
HDA_SDIN0 <8>
CA30 1 2 10U 6.3V M X5R 0603 LDO1_CAP 21 LINE1-VREFO-L SDATA_IN 22_0402_5%
GNDA
CA31 1 2 2.2U 6.3V M X5R 0402 VREF 22 LDO1-CAP 0_0402_5% 0_0402_5% 0_0402_5%
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
10U 6.3V M X5R 0603 CA21
VREF
0.1U 16V K X7R 0402 CA22

GNDA
1 1 1 1
10U 6.3V M X5R 0603
0.1U 16V K X7R 0402

CA15 1 2 1U_0402_6.3V6K CPVEE 27 1 1 DA6
CPVEE
CA8
CA39 1 2 10U 6.3V M X5R 0603 CPVDD 29 18 AZ5125-01H.R7G_SOD523-2 @
CBN 28 CPVDD LINE1_L
CA7
CA5
CA6
+1.8VS CBN 17 SC400005Q00
CA16 2 1 1U_0402_6.3V6K CBP 30 LINE1_R 2 2 2 2
CBP 2 2
2 1
D_MIC_DATA 2
<27> D_MIC_DATA
2 1 D_MIC_CLK_R 3 GPIO0/DMIC_DATA12 32 CA27 1 2 10U 6.3V M X5R 0603 GNDA
<27> D_MIC_CLK GPIO1/DMIC_CLK LDO2_CAP
BLM15PX221SN1DEMI@ LA6 6 CA28 1 2 10U 6.3V M X5R 0603
LDO3_CAP
GNDA
1 @EMI@ RA41 10
DCDET
GNDA
CA41 +DVDD 1 2 100K_0402_1% 12
PLUG_IN# 1 JD1 19
10P_0402_50V8J 2 200K_0402_1%
AVSS1 31 GNDA
RA42
2 PDB 40 AVSS2 41 GNDA
PDB THERMALPAD
ALC3247-CG_MQFN40_5X5
Internal SPK
CONN@
JSPK
SPK_R- RA36 1 EMI@ 2 0_0603_5% SPK_R-_CONN 1
+3VS +DVDD RA34 1 EMI@ 2 0_0603_5% SPK_R+_CONN 1
SPK_R+ 2
RA33 1 EMI@ 2 0_0603_5% SPK_L-_CONN 3 2
C
1 SPK_L- 3 C
SPK_L+ RA35 1 EMI@ 2 0_0603_5% SPK_L+_CONN 4
PC Beep 4
1
RA10 5 G1
10K_0402_0.5% RA9 6 G2
@ 100K_0402_5%
wide 40 MIL ACES_50278-00401-001
220P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
2
2 2
EC Beep <33> EC_BEEP# 1 2 PC_BEEP_R CA44 1 1 1 1

B
0.1U 16V K X7R 0402
@EMI@ C14
@ QA2
@EMI@ C11
@EMI@ C12
@EMI@ C13
RA16
HDA_RST#_R
E
3 1 PDB 47K_0402_5%
<8> HDA_RST#_R 2 2 2 2
C
SB Beep <8,10> HDA_SPKR 1 2 1 2 1 2 PC_BEEP CA42

MMBT3904WH_SOT323-3 1 CA43 0.1U 16V K X7R 0402
0.1U 16V K X7R 0402 CA23
1
SB000008E10 0.1U 16V K X7R0402
@
EC_MUTE# 1 2 RA17
<33> EC_MUTE# 2
DA2 SCS00000Z00 10K_0402_5%
RB751V-40 SOD-323
2
R5260 Close to Codec pin34
1 2
0_0201_5%
Reserve for ESD request.

INT_MIC_R GNDA HP_OUTR_R HP_OUTL_R
Place RA51/RA52/RA53 on moat of UA1 BOT side
3
RA51 1 2 0_0603_5%
DA4
Rshort@ L03ESDL5V0CC3-2_SOT23-3 DA5
RA52 1 2 0_0603_5% SCA00002900 L03ESDL5V0CC3-2_SOT23-3
ESD@ SCA00002900
Rshort@ @ESD@
RA54 1 2 0_0603_5%
Rshort@
1
1 2
RA6 0_0402_5%
1/20:Swap DA3
RA7 @
B 1 2 B
0_0402_5%
1 2
CA9 EMI@ JHP
0.1U 16V K X7R 0402 INT_MIC 1 RA13 2 0_0402_5% INT_MIC_R 3 3:M/G_EARTH
EMI@ HP_OUTL 1 RA14 2 0_0402_5% HP_OUTL_R 1 1:L/R_TIP SPRING
EMI@
1 2
CA10 PLUG_IN# 5 5:TRANSFER TERMINAL
0.1U 16V K X7R 0402
EMI@
6 6:MAKE TERMINAL
1 2 HP_OUTR 1 RA15 2 0_0402_5% HP_OUTR_R 2 2:R/L_RING A
CA11 @EMI@ EMI@
0.1U 16V K X7R0402 4 4:G/M_RING B
1 1 1 7 7:MS_SHELL
100P_0603_50V7 CA24
100P_0603_50V7 CA25
100P_0603_50V7 CA26
1 2
CA12 @EMI@ SINGA_2SJ3095-067111F
0.1U 16V K X7R0402
@EMI@
@EMI@
@EMI@
2 2 2 DC23000DY00
GNDA Pin6 and Pin5
1 2 Normal OPEN
CA13
0.1U 16V K X7R 0402
EMI@
GNDA
GNDA
A A

Deciphered Date
T HI S S HE E T O F E NG I NE E R I NG D R AW I NG I S T HE P R O P R I E T AR Y P R O P E R T Y O F C O M P AL E L E C T R O NI C S , I NC . AND C O NT AI NS CONFIDENTSSIAiizLe Document Number
AUDIO ALC3258-CG
D E P AR T M E NT E X C E P T AS AUT HO R I Z E D B Y C O M P AL E L E C T R O NI C S , I NC . NE I T HE R T HI S S HE E T NO R T HE I NF O R M AT I O N I T C O NT AI NS Custom v0.3
M AY B E US E D B Y O R DI I SCL OSED T O ANY T HI R D P AR T Y W I T HO UT P R I O R W R I T T E N C O NS E NT O F C O M P AL E L E C T R O NI C S , I NC . LA-G07FP(KBL-U_UMA_6L)
Date: Friday, January 05,2018 Sheet 32 of 59
5 4 3 2 1
5 4 3 2 1
+3VL +3VALW _EC
<6,7,9,10,11,13,17,18,19,22,23,24,27,28,29,30,31,32,36,39,40,52,55>
+3VS
+3VS LK1 SM01000Q 500
S SUPPRE_ T AI-T ECH HCB1005KF-221T15 0402
+3VALW _EC
EC Board ID (UMA, DIS, phase) control table
https://vinafix.com
1 2 +3VALW _EC 1 2 +EC_VCCA
0.1U_0201_10V6K
0.1U_0201_10V6K
+3VALW _EC
2
RK1 0_0603_5% 1 KBL-U KBL-R
CK1
CK2
<22,45> +3VALW _EC 1 1
<13,39,46,47,48> +3VL +3VL
RK2
RK4
CK3 100K_0402_1% DB SI PV MV DB SI PV MV
ECAGND
2 2 2 0.1U_0201_10V6K
UMA 15K 27K 43K 75K 130K 200K 270K 430K
1
(0x02) (0x04) (0x06) (0x08) (0x0A) (0x0C) (0x0E) (0x10)
BOARD_ID DIS 20K (0x03) 33K 56K
(0x05) (0x07) 100K (0x09) 160K (0x0B) 240K (0x0D) 330K (0x0F) 560K (0x11)
+3V_EC_VDD +3VL
2
+3V_LID U_PX@ U_UMA@
ESD@ 1 RK3 2 RK4 RK4
D
2 1 PLT _RST # 56K +-1% 0402 43K +-1% 0402 U_DB_UMA_15kohm:SD034150280, S RES 1/16W 15K+-1% 0402 Reserve EC_CLR_CMOS for clear CMOS D
CK4 0.1U_0402_25V6 0_0402_5% SD034560280 SD034430280 U_DB_ DIS_20kohm:SD034200280, S RES 1/16W 20K +-1% 0402 (2016-03-04 ::Confirm intelplatformnot support EC Clear CMOS function)
U_SI_UMA_27kohm:SD034270280, S RES 1/16W 27K +-1% 0402 (2017-10-05 : 2018OPP Add EC Clear CMOS function)
1
U_SI_ DIS_33kohm:SD034330280, S RES 1/16W 33K +-1% 0402
111
125
R_PX@ R_UMA@ U_PV_UMA_43kohm:SD034430280, S RES 116W 43K +-1% 0402 RK106 1 2 0_0402_5%
22
33
96
67
UK1 CLR_CMOS# <9>
9
RK4 RK4 U_PV_ DIS_56kohm:SD034560280, S RES 1/16W 56K +-1% 0402
330K +-1% 0402 270K +-1% 0402 U_MV_UMA_75kohm:SD034750280, S RES 1/16W 75K +-1% 0402
VCC0
VCC_LPC
VCC
VCC
VCC
VCC
AVCC
1
SD034330380 SD00000G280 U_MV_ DIS_100kohm:SD034100380, S RES 1/16W 100K+-1% 0402 @
@ D
RK7 2 1 330K_0402_5% EC_RST # EC_CLR_CMOS 2 Q51
+3VALW _EC Pin111:VCC0
T OUCH_ON 1 21 EC_VCCST _PG_R G 2N7002K_SOT23-3
T 2403 T P@ GAT EA20/GPIO00 EC_VCCST _PG/GPIO 0F EC_VCCST _PG_R <9,40>
2
@ 1 2 EC_KBRST # 2 23 R_DB_UMA_130kohm:SD034130380, S RES 116W 130K +-1%0402 S SB00000EN00
<7> EC_KBRST # KBRST #/GPIO01 BEEP#/GPIO10 EC_BEEP# <32> R_DB_ DIS_160kohm:SD034160380, S RES 116W 160K +-1%0402
CK5 0.1U_0402_16V7K SERIRQ 3 26 EC_FAN_PW M1 R483
<7,35> SERIRQ EC_FAN_PW M1 <36>
3
LPC_FRAME# SERIRQ EC_FAN_PW M/GPIO12 27 EC_CLR_CMOS
4 PWMOutput R_SI_UMA_200kohm:SD034200380, S RES 1/16W 200K +-1% 0402 @ 10K_0402_5%
<7> LPC_FRAME# LPC_FRAME# AC_OFF/GPIO13
LPC_AD3 5 R_SI_ DIS_240kohm:SD000001B80, S RES 116W 240K +-1%0402
<7> LPC_AD3 LPC_AD2 LPC_AD3
7 R_PV_UMA_270kohm:SD00000G280, S RES 1/16W 270K +-1% 0402
<7> LPC_AD2 LPC_AD2
1
LPC_AD1 8 63 B/I#
<7> LPC_AD1 LPC_AD1 VCIN1_BAT T _T EMP/AD0/GPIO38 B/I# <46> R_PV_ DIS_330kohm:SD034330380, S RES 1/16W 330K +-1%0402
LPC_AD0 10
LPC_ADL0 PC & MISC
<7> LPC_AD0 64
CLK_PCI_LPC VCIN1_BAT T _DROP/AD1/GPIO39 ADP_I
65 ADP_I <45,47>
CLK_PCI_LPC 12 ADP_I/AD2/GPIO3A BOARD_ID
<7> CLK_PCI_LPC CLK_PCI_EC AD Input AD_BID/AD3/GPIO3B
66
PLT _RST # 13 75 ADP_ID
<9,19,29,30,31,35> PLT _RST # PCIRST #/GPIO05 AD4/GPIO42 ADP_ID <45>
1 12 2 EC_RST # 37 76 EC_PME#_EC_R R5178 1 2
EC_RST # AD5/GPIO43 EC_PME# <29>
CK9 RK109 22_0402_5% EC_SCI# 20 0_0201_5% VR_HOT # 1 2 0_0402_5%
<5> EC_SCI# EC_SCI#/GPIO0E <52> VR_HOT # PROCHOT # <5>
22P 50V J NPO 0402 EMI@ 1 @ 2 PM_CLKRUN#_R 38 RK8
<7> PM_CLKRUN# CLKRUN#/GPIO1D
EMI@ RK10 1 @ 2 0_0402_5%
<9,30> EC_PCIE_W AKE#
RK6 0_0402_5% 68
DA0/GPIO3C 70 NMI_DBG# KBL_ON# <34>
<34> KSI[0..7] DA Output EN_DFAN1/DA1/G PIO3D D
1
KSI0 55 71 VR_PW RGD
56 KSI0/GPIO30 DA2/GPIO3E VR_PW RGD <52>
KSI1 72 EC_MUT E# H_PROCHOT#_EC 2
KSI1/GPIO31 DA3/GPIO3F EC_MUT E# <32>
KSI2 57 G
KSI3 58 KSI2/GPIO32 83 @ QK1 S
KSI3/GPIO33 EC_MUT E#/PSC LK1/G PIO 4A 84
3
KSI4 59 2N7002_SOT23-3
C KSI5 60 KSI4/GPIO34 USB_EN#/PSDAT 1/GPIO4B 85 VR_ON C
SB00000EN 00
61 KSI5/GPIO35 PSCLK2/GPIO4C 86 VR_ON <40,52>
1 @ 2 VCIN1_ACOK_R KSI6 PS2 Interface
<47> VCIN1_ACOK 62 KSI6/GPIO36 PSDAT 2/GPIO 4D 87 T P_CLK LAN_PW R_EN <29>
R4958 0_0402_5% KSI7
<34> KSO[0..17] KSI7/GPIO37 T P_CLK/GPIO4E 88 T P_CLK <34>
KSO0 39 T P_DAT A
KSO0/GPIO20 T P_DAT A/GPIO4F T P_DAT A <34>
KSO1 40 RK91 2 0_0402_5%
KSO2 41 KSO1/GPIO21
1 2 VCIN1_AC_IN_R KSO3 42 KSO2/GPIO22 97 ENBKL +3VALW
0_0402_5% KSO4 43 KSO3/GPIO23 ENKBL/GPXIO A00 98 ENBKL <5>
R5094
44 KSO4/GPIO24 W OL_EN/GPXIOA01 99 ME_FLASH_EN W L_PW REN_EC# <30>
KSO5
KSO5/GPIO25
Int. K/B ME_EN/GPXIO A02 ME_FLASH _EN <8>
T P_CLK RK12 1 2 4.7K_0402_5%
KSO6 45 109 VCIN0_PH
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH1/GPXIOD00 VCIN0_PH <45>
T P_DAT A RK13 1 2 4.7K_0402_5%
KSO8 47 KSO7/GPIO27
VCIN1_AC_IN 1 @ 2 VCIN1_AC_IN_R R4960 48 KSO8/GPIO28 SPI Device Interface
KSO9 119
49 KSO9/GPIO29 MISO/GPIO5B 120 EC_SPI_SO <7>
0_0402_5% KSO10
50 KSO10/GPIO 2A MOSI/GPIO5C EC_SPI_SI <7> +3VL
KSO11 SPI Flash ROM 126 EC_SPI_C LK
KSO12 51 KSO11/GPIO 2B SPICLK/GPIO58 128
For Solve tPCH04(Min 9ms) Sequenc e T i mi ng KSO12/GPIO 2C SPICS#/GPIO5A EC_SPI_C S0# <7>
KSO13 52
KSO14 53 KSO13/GPIO 2D RP12
KSO15 54 KSO14/GPIO 2E 73 8 1
KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 T S_GPIO_EC <27> PLT _RST # 7 2
KSO16 81 74 SYS_PW ROK
KSO16/GPIO48 SYS_PW ROK/AD7/GPIO 41 SYS_PW ROK <9> EC_ON 6 3
KSO17 82 89 EC_S0IX_EN
KSO17/GPIO49 GPIO50 EC_S0IX_EN <12> PCH_PW R_EN 5 4
90 BAT _CHG_LED
BAT T _CHG_LED#/GPIO52 91 CAP_LOCK# BAT _CHG_LED <45>
CAPS_LED#/GPIO53 92 PW R_LED# CAP_LOCK# <34>
77 GPIO 100K_0804_8P4R_5%
<46,47> EC_SMB_C K1 EC_SMB_C LK1/G PIO 44 PW R_LED#/GPIO54 93 PW R_LED# <39>
<46,47> EC_SMB_D A1 78 ACIN <9>
EC_SMB_C K2_R EC_SMB_D AT 1/G PIO 45 BAT T _LOW _LED#/GPIO55 95 SYSON
RK15 1 2 0_0402_5% 79 PBT N_OUT # R295 1 @ 2 1K_0402_5%
<7,10,22> EC_SMB_CK2 EC_SMB_C LK2/G PIO 46 SYSON/GPIO 56 121 BT _ON_EC SYSON <12,40,49>
RK16 1 2 0_0402_5% EC_SMB_D A2_R 80
<7,10,22> EC_SMB_DA2 EC_SMB_D AT 2/G PIO 47 VR_ON/GPIO57 BT _ON_EC <30>
127 PCH_DPW ROK EC_CLR_CMOS 1 @ 2 RK107
DPW ROK_EC/GPIO59 PCH_DPW ROK <9>
SM Bus 10K_0402_5%
+3VALW _EC
PM_SLP_S3# 6 100 PCH_RSMRST #
+5VS <9,12,40> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST #/GPXIO A03 PCH_RSMRST # <9>
PM_SLP_S5# 14 101 USB_ON# LID_SW # RK18 2 @ 1 47K_0402_5%
<9> PM_SLP_S5# GPIO07 GPXIOA04 USB_ON# <38,39>
B <9> SUSACK# SUSACK# 15 102 VCIN1_PH VCIN1_PH <45> B
PM_SLP_SU S# GPIO08 VCIN1_ADP_PROCHOT /GPXIO A05 +3V_SMBU S
<9> PM_SLP_SU S# 16 103 H_PROCHOT #_EC
PCH_SUSW ARN# GPIO0A VCOUT 1_PROCHOT #/GPXIO A06
17 104 MAINPW ON
<9> PCH_SUSW ARN# GPIO0B VCOUT 0_MAIN_PW R_ON/GPXIO A07 MAINPW ON <48> +3VS
18 105 EC_BKOFF# EC_SMB_C K1 8 1 RP11
RK28 GPIO0C BKOFF#/GPXIO A08 EC_BKOFF# <27>
19 GPIOGPO 106 RK25 1 2 0_0402_5% EC_SMB_D A1 7 2
AC_PRESENT /GPIO 0D GPXIOA09 DGPU_PW R_EN <10,24>
2 1 MUT E_LED_OUT MUT E_LED_IN 25 107 PCH_PW R_EN EC_SMB_C K2 6 3
<32> MUT E_LED_IN PW M2/GPIO11 PCH_PW R_EN/GPXIOA10 PCH_PW R_EN <40,51>
FAN_SPEED1 28 108 +1.0VS_PG EC_SMB_D A2 5 4
<36> FAN_SPEED 1 FAN_SPEED1/GPIO 14 PW R_VCCST _PG/GPXIOA11 +1.0VS_PG <50>
100K_0402_5% VCIN1_ACOK_R 29
E51T XD_P80D AT A FANFB1/GPIO15
30 2.2K_0804_8P4R_5%
<30> E51T XD_P80D AT A EC_T X/GPIO16
E51RXD_P80CLK 31 110 VCIN1_AC_IN_R
RK26 <30> E51RXD_P80C LK EC_RX/GPIO 17 VCIN1_AC_IN/GPXIOD01 112 EC_ON
PCH_PW ROK 32
<9> PCH_PW ROK PCH_PW ROK/GPIO18 ALW_PWE_EN EC_ON/GPXIOD 02 EC_ON <39,48>
2 1 E51T XD_P80D AT A AC_LED# 34 114 ON/OFF# EC_SCI# RK14 2 1 10K_0402_5%
<45> AC_LED# SUSP_LED #/G PIO19 ON/OFF#/GPXIOD03 ON/OFF# <39>
<34> MUT E_LED_OUT 36 GPI 115 LID_SW #
NUM_LED#/GPIO1A LID_SW #/GPXIOD04 LID_SW # <39>
100K_0402_5% 116 SUSP#
SUSP#/GPXIOD 05 117 VCIN1_AC_IN SUSP# <12,40,49>
GPXIOD06
118 EC_PECI RK17 1 2 43_0402_1%
PECI/GPXIOD07 H_PECI <5>
PBT N_OUT # 122 SYSON RK23 1 @ 2 100K_0402_5%
<9> PBT N_OUT # PBT N_OUT #/GPIO5D
PM_SLP_S4# 123 124 +V18R
<9,12,40,49> PM_SLP_S4# PM_SLP_S4#/G PIO 5E V18R/VCC_IO2 +3VALW _EC
1
AGND
CK8 SUSP# RK27 1 2 100K_0402_5%

GND
GND
GND
GND
GND
1 @ 2 PCH_PW ROK 4.7U_0402_6.3V6M

RK20 100K_0402_5% KB9022QD_LQF P128_14X14 2
11
24
35
94
69
113
1 2 MUT E_LED_IN 20mil

RK108 10K_0402_5%
EC_SPI_C LK RC369 1 2 HOST _SPI_0_CLK_R
SA000075S30 HOST _SPI_0_CLK_R <7,35>
LK2 SM01000Q 500 EMI@ 15_0402_5%
ECAGND 2 1
T AI-T ECH HCB1005KF-221T15 0402 CC144
CC128 RC369 place near ECSide 22P 50V J NPO 0402
@EMI@
+3VALW _EC
ECAGND <45>
A
EMI request A
1
RK21
10K_0402_5%
2
NMI_DBG# 1 2
NMI_DBG#_CPU <5,10>
DK2 SCS00000Z00
RB751V-40 SOD-323
T HIS SHEET OF ENGINEERING DRAW ING IS T HE PROPRIET ARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONT AINS CONFIDENT IAL
EC ENE-KB9022
AND T RADE SECRET INFORMAT ION. T HIS SHEET MAY NOT BE T RANSFERED FROM T HE CUST ODY OF T HE COMPET ENT DIVISION OF R&SDize Document Number Rev
DEPART MENT EXCEPT AS AUT HORIZED BY COMPAL ELECT RONICS, INC. NEIT HER T HIS SHEET NOR T HE INFORMAT ION IT CONT AINS Custom v0.3
MAY BE USED BY OR DISCLOSED T O ANY T HIRD PART Y W IT HOUT PRIOR W RIT TEN CONSENT OF COMPAL ELECT RONICS, INC. LA-G07FP(KBL-U_UMA_6L)
Date: T uesday, January 09, 2018 Sheet 33 of 59
5 4 3 2 1
<7,13,29,30,33,35,40,48,49,50,51> +3VALW +3VALW
<12,37,38,39,40,48,49,52,53> +5VALW
https://vinafix.com
+5VALW
TP Button BD Connector
+3VALW
CONN@
JTP
<33> KSI[0..7]
KSI7
KSI6
Keyboard conn
1 KSI5
2 1 KSI4
<33> TP_CLK 2
3 KSI3 CONN@
<33> TP_DATA 3 KSI2
4 JKB
4 KSI1 32
<7> TP_SMBCLK 5 7 KSI1 34
5 G1 KSI0 31 32 G2
<7> TP_SMBDATA 6 8 KSI7 33
6 G2 30 31 G1
KSI6
30
PS2+SMBus ACES_51524-0060N-001 KSO9 29
28 29
SP010014M10 KSI4
27 28
<33> KSO[0..17] KSI5
27
3
1 1 KSO17 KSO0 26
KSO16 25 26
DM5 @ @ JKB1 KB Spec KSI2
25
PESD5V0U2BT 3P CC SOT23 ESD C135 C136 KSO15 KSI3 24
KSO14 24
SCA00000T00 Pin1 KSI1 KSI1 KSO5 23
2 2 KSO13 23
ESD@ KSO1 22
KSO12 22
Pin32 5V 5V 21
470P_0402_50V8J
470P_0402_50V8J
KSI0 21
KSO11 KSO2 20
KSO10 20
KSO4 19
KSO9 19
KSO7 18
18
1
KSO8 KSO8 17
KSO7 17
KSO6 16
KSO6 16
KSO3 15
KSO5 15
KSO12 14 14
KSO4 KSO13 13
KSO3 13
KSO14 12 12
KSO2 KSO11 11
KSO1 11
KSO10 10 10
KSO0 KSO15 9 9
KSO16 8 8
R203 KSO17 7 7
1K_0402_5% 6 6
1 2 +5VS 5
<33> CAP_LOCK# CAP_LOCK# CAP_LOCK#_R 5
1 2 MUTE_LED_OUT_R 4 4
+5VALW +5VS <33> MUTE_LED_OUT
R207 3 3
549_0402_1% 2 2
1 1
+5VS
1
R23 ACES_50690-0320N-P01
100K_0402_5% CAP_LOCK# SP01001RG00
Q9 +5VS_KBL MUTE_LED_OUT
3
S
2
G
2
<33> KBL_ON# ESD@
ACES_51575-00401-001 KSI0 C193 2 1 100P_0402_50V8J
D 1 1
1
4 6
0.047U_0402_16V7K
4 G2 5
1 PJ2301 1P SOT23-3 3 CC122 CC123
3 G1
@ 2
SB00000T900 2 2 100P_0402_50V8J 2 100P_0402_50V8J
1
C68
1 ESD@ ESD@
2 JKBL
SP01002BY00

THIS SHEET O F ENG INEERING DRAW ING IS T HE PRO PRIET ARY PRO PERT Y O F CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENSSTiIzAeLDocumentNumber
KB/TP
Rev
DEPARTMENT EXCEPT AS AUT HO RIZED BY CO MPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMAT ION IT CONTAINS Custom v0.3
5 4 3 2 1
+3VALW +3VALW <7,13,29,30,33,34,40,48,49,50,51>
https://vinafix.com
D Screw Hole D
TPM2.0 UT1
+3VS_TPM +3VALW
H1 H2
H_2P4N H_3P0
H4
H_3P0
CPU
H8 H9 H10 H11 H_5P0
H_5P0 H_5P0H_5P0
TPM@
<9,29,30,31,33> PLT_RST# 1 TPM@ 2 PLT_RST#_TPM 17 1 RC9341 2 0_0402_5%
R28 0_0402_5% RST# VDD
8 @ @ @ @ @ @ @
VDD
1
1 TPM@ 2 TPM_SERIRQ 18 22 1 1 1 1
<7,33> SERIRQ PIRQ# VDD
R5202 0_0402_5% CT1 CT3 CT4 CT2
<7,33> HOST_SPI_0_CLK_R RT6 1 2 HOST_SPI_0_CLK_R_TPM 19 3
SCLK NC
TPM@ 33_0402_5%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0402_6.3V6K
4
RT7 1 2 HOST_SPI_0_CS2#_TPM 20 NC 2 2 2 2
<7> HOST_SPI_0_CS2# CS# 5
TPM@ 33_0402_5% NC 10
NC
RT8 1 2 HOST_SPI_0_SI_TPM 21 11
<7> HOST_SPI_0_SI MOSI NC
TPM@ 33_0402_5% 12 TPM@ TPM@ TPM@ TPM@ H13 H14 H16 H17 H18 H19
NC
RT9 1 2 HOST_SPI_0_SO_TPM 24 13 H_2P3 H_3P3 H_2P3 H_2P4X2P9N H_6P0N H_6P0N
<7> HOST_SPI_0_SO MISO NC
TPM@ 33_0402_5% 14
NC
+3VS_TPM 2 1 TPM_GPIO 6 15
GPIO NC
RT10 TPM@ 4.7K_0402_5% 16 @ @ @ @ @ @
NC
1
1
1
1@2 TPM_PP 7 25
PP NC
RT35 4.7K_0402_5% 26
NC
2 27
9 GND NC
28
23 GND NC
1
29
32 GND NC
RT12 30
33 GND NC
C 4.7K_0402_5% 31 FD1 FD2 FD3 FD4 C
PAD NC
TPM@
TPM@
2
SLB9670VQ1.2 FW6.40_VQFN32_5X5 @ @ @ @
1
SA00009N230
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
JESD JUMP@
1 2
1 2
JUMP_43X39
B B
A A

TPM/Screw
Rev
v0.3
DEPARTMENT EXCEPT AS AUT HO RIZED BY CO MPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMAT ION IT CONTAINS
5 4 3 2 1
A B C D E
https://vinafix.com
+5VS
1A 40 mils +3VS
1
R5177
1 Rshort@2+FAN1 L Layout notes
C4801 C5214 close to CONN
CONN@ 1
1
JFAN
0_0603_5% RE50 6
5 GND2
10K_0402_5%
GND1
10U_0603_10V6M
C4801
0.1U_0402_16V7K
C5214
1 1
+FAN1 4
4
2
Close to Connector <33> FAN_SPEED1
3
3
1 2
2 2 <33> EC_FAN_PWM1 1 2
CE24
1
0.01U_0402_25V7K
ACES_50271-0040N-001
2 SP02000TS00
+FAN1
RE51
1 @ 2 EC_FAN_PWM1
10K_0402_5%
2 2
3 3
4 4

Deciphered Date
FAN
Rev
DEPARTMENT EXCEPT AS AUT HO RIZED BY CO MPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMAT ION IT CONTAINS Custom v0.3
A B C D E
5 4 3 2 1
<27,28,32,33,34,36,40> +5VS
https://vinafix.com
+5VS
2.5" SATA HDD <12,34,38,39,40,48,49,52,53> +5VALW
<7,13,29,30,33,34,35,40,48,49,50,51> +3VALW
+5VALW
+3VALW
D D
<PV> change short pad

CONN@
+5VS JHDD
*Design Constraint:AC capacitors to be placed as close 1
as possible to the connector. +5VS_HDD1 1
Maximum distance from AC capacitors to connector is 500
mils.
2
C155 1 2 0.01U_0402_16V7K SATA_CTX_C_DRX_P0 2
R201 1 Rshort@20_0603_5% +5VS_HDD1 <11> SATA_CTX_DRX_P0 3
C156 1 2 0.01U_0402_16V7K 3
<11> SATA_CTX_DRX_N0 SATA_CTX_C_DRX_N0 4
4
R202 1 Rshort@20_0603_5% 5
C153 1 2 0.01U_0402_16V7K 5
SATA_CRX_C_DTX_N0 6
<11> SATA_CRX_DTX_N0 C154 1 2 0.01U_0402_16V7K 6
SATA_CRX_C_DTX_P0 7
<11> SATA_CRX_DTX_P0 7
8
8
2 9
GND
10
GND
C140
ACES_51524-00801-001
1 470P_0402_50V8J
EMI@ SP01001A910
C C
SATA ODD
+5VALW
1
ROD1
100K_0402_5%
2
JODD
1
D +5VS_ODD
1
S1
2 QOD2 ROD2 CS11 2 1 0.01U_0402_16V7K SATA_CTX_C_DRX_P1 S2 GND
<10> ODD_PWR <11> SATA_CTX_DRX_P1 A+
G 2N7002K_SOT23 1K_0402_5% <11> SATA_CTX_DRX_N1
CS14 2 1 0.01U_0402_16V7K SATA_CTX_C_DRX_N1 S3
S4 A-
S SB00000EN00 COD1
GND
3
2 1 CS15 2 1 0.01U_0402_16V7K SATA_CRX_C_DTX_N1 S5

<11> SATA_CRX_DTX_N1 B-
2 2
+5VS_ODD CS18 2 1 0.01U_0402_16V7K SATA_CRX_C_DTX_P1 S6

<11> SATA_CRX_DTX_P1 S7 B+
0.047U_0402_16V7K
1 Rshort@2 Vinafix.com ODD_PLUG#_R GND
G
80mil 3 1
80mil <11> ODD_PLUG# R5192 0_0402_5% 1 Rshort@2ODD_DA#_R R5193
+5VS <10> ODD_DA# 0_0402_5% P1
S
B P2 DP B
1 1 1 +5V
P3
COD2
QOD1 @
10U_0603_6.3V6M
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
COD
COD
PJ2301 1P SOT23-3 P4 +5V

SB00000T900 P5 MD 1
2 2 2 1 GND GND 2
P6
2@ 1 ESD@ GND GND
ROD3 0_0805_5% CS7
2 0.1U_0402_16V7K SDAN_603010-013041
3
SP010029L00
4
SDAN_603010-013041_13P
CONN@
A A

THIS SHEET O F ENGINEERING DRAW ING IS T HE PRO PRIET ARY PRO PERT Y O F COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENSTiIIzAeLDocumentNumber
HDD/ODD Conn
Rev
Custom v0.3
DEPART MENT EXCEPT AS AUT HO RIZED BY CO MPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMAT ION IT CONTAINS
MAY BE USED BY O R DISCLO SED T O ANY THIRD PART Y W IT HO UT PRIO R W RIT T EN CONSENT O F COMPAL ELECTRONICS, INC. LA-G07FP(KBL-U_UMA_6L)
5 4 3 2 1
A B C D E
RS2 EMI@ 0_0402_5%

2 1 USB3_CTX_C_DRX_N1 1 2 USB3_CTX_L_DRX_N1
<11> USB3_CTX_DRX_N1 <12,24,34,37,39,40,48,49,52,53> +5VALW +5VALW
CS2 0.1U_0402_16V7K
2
https://vinafix.com
RG75
@ 150_0402_5% +USB_VCCA
+5VALW
US1 W =100mils
1
W =100mils OUT
1
RS1 EMI@ 0_0402_5% 5
150U_B2_6.3VM_R45M
1
1 USB3_CTX_C_DRX_P1 1 IN
2 2 USB3_CTX_L_DRX_P1 2
1000P_0402_50V7K
<11> USB3_CTX_DRX_P1 GND 1
47U_0805_6.3V6M
0.1U_0402_16V7K
CS1 0.1U_0402_16V7K CS3 4 @
EN 1 1 1 +
CS6
3
CS22
0.1U_0402_16V7K OCB
2 CS4 CS5 CS28
2 1
RS6 EMI@ 0_0402_5% 1 EMI@ 390P_0402_50V7K
2 USB3_CRX_L_DTX_N1 EM5203J-20 SOT23 5P LOAD SW ITCH 2 2 2 2 EMI@
<11> USB3_CRX_DTX_N1
SA00008RA00
1 1
2
RG76 USB_ON# 1 2
<33,39> USB_ON#
@ 150_0402_5% RS4 Rshort@ 0_0402_5%
1
RS3 EMI@ 0_0402_5% 1
2 USB3_CRX_L_DTX_P1
<11> USB3_CRX_DTX_P1
USB2.0/USB3.0 port 1
RS47 @EMI@ +USB_VCCA
1 2 JUSB1
0_0201_5% DM2 ESD@ 1
VBUS
USB3_CTX_L_DRX_P1 1 1 10 9 USB3_CTX_L_DRX_P1 USB20_N1_R 2
D-
SM070005U00 DLM0NSN900HY2D_4P 1 USB20_P1_R 3
D+
1 2
2 USB20_P1_R USB3_CTX_L_DRX_N1 2 2 9 8 USB3_CTX_L_DRX_N1 4
<11> USB20_P1 USB3_CRX_L_DTX_N1 GND1
5
SSRX-
USB3_CRX_L_DTX_P1 4 4 7 7 USB3_CRX_L_DTX_P1 USB3_CRX_L_DTX_P1 6 10
SSRX+ GND3 11
4 3 USB20_N1_R 7
<11> USB20_N1 4 3 GND2 GND4
LM3 USB3_CRX_L_DTX_N1 5 5 6 6 USB3_CRX_L_DTX_N1 USB3_CTX_L_DRX_N1 8 12
EMI@ SSTX- GND5 13
USB3_CTX_L_DRX_P1 9
SSTX+ GND6
RS48 @EMI@ 3 3
1 2 ACON_TARAW -9U1395_9P-T
0_0201_5% 8 DC231709285
USB2.0 ChokePart:
Main:SM070005U00, S COM FI_ MURATA DLM0NSN900HY2D(MURATA) DT1140-04LP-7 U-DFN2510-10 CONN@
2nd: SM070004X00, S COM FI_ PANASONICEXC14CE900U(PANASONIC)
SC300005M00
2 2
DM1
USB20_P1_R 6 3 USB20_P2_R
USB2.0 ChokePart: I/O4 I/O2
Main:SM070005U00, S COM FI_ MURATA DLM0NSN900HY2D(MURATA)
2nd: SM070004X00, S COM FI_ PANASONICEXC14CE900U(PANASONIC)
RS49 @EMI@ +USB_VCCA 5 2

VDD GND
1 2
0_0201_5%
SM070005U00 DLM0NSN900HY2D_4P USB20_N1_R 4 1 USB20_N2_R

1 2 USB20_P2_R I/O3 I/O1
<11> USB20_P2 1 2
AZC099-04S.R7G_SOT23-6
SC300001G00
4 3 USB20_N2_R
<11> USB20_N2 3
LM5 4
EMI@
RS50 @EMI@
1 2
0_0201_5% USB2.0/USB3.0 port 2
RS8 EMI@ 0_0402_5% 1 +USB_VCCA
2 1 USB3_CTX_C_DRX_N2 2 USB3_CTX_L_DRX_N2
<11> USB3_CTX_DRX_N2
CS23 0.1U_0402_16V7K JUSB2
1
VBUS
2
USB20_N2_R 2
USB20_P2_R D-
RG106 3
D+
@ 150_0402_5% 4
USB3_CRX_L_DTX_N2 GND1
5
USB3_CRX_L_DTX_P2 6 SSRX-
10
SSRX+ GND3
1
7 11
USB3_CTX_L_DRX_N2 GND2 GND4 12
RS7 EMI@ 0_0402_5% 1 8
SSTX- GND5 13
2 1 USB3_CTX_C_DRX_P2 2 USB3_CTX_L_DRX_P2 USB3_CTX_L_DRX_P2 9
<11> USB3_CTX_DRX_P2 SSTX+ GND6
CS24 0.1U_0402_16V7K
ACON_TARAW -9U1395_9P-T
DC231709285
RS10 EMI@ 0_0402_5% 1
CONN@
3 2 USB3_CRX_L_DTX_N2 3
<11> USB3_CRX_DTX_N2 DM14 ESD@
USB3_CRX_L_DTX_N2 1 1 10 9 USB3_CRX_L_DTX_N2
2
USB3_CRX_L_DTX_P2 2 2 9 8 USB3_CRX_L_DTX_P2
RG107
@ 150_0402_5% USB3_CTX_L_DRX_N2 4 4 7 7 USB3_CTX_L_DRX_N2
USB3_CTX_L_DRX_P2 5 5 6 6 USB3_CTX_L_DRX_P2
1
RS9 EMI@ 0_0402_5% 1 3 3

2 USB3_CRX_L_DTX_P2
<11> USB3_CRX_DTX_P2 8
DT1140-04LP-7 U-DFN2510-10
SC300005M00
USB3.0 ESD Part:
Main:SC300005M00, S DIO(BR) DT1140-04LP-7 U-DFN2510-10(DIODES ))
2nd:SC300003Z00, S DIO(BR) PUSB3F96 DFN2510A-10 ESD(NXP)
3rd:SC300005N00, S DIO(BR) L02U5V0NA-4C SLP2510P8(LITE ON)
4 4

Issued Date 2017/08/24 Deciiphered Date 2018/08/24 Title
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT I A L
USB 3.0/2.0 conn
Sii zee Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom v0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G07FP(KBL-U_UMA_6L)
Date: Tuesday, January 09, 2018 Sheet 38 of 59
A B C D E
A B C D E
+3V_LID
+3VL <13,33,46,47,48> +3VL +3VL
Power Button Switch <12,24,34,37,38,40,48,49,52,53> +5VALW +5VALW
1
R215
<6,7,9,10,11,13,17,18,19,22,23,24,27,28,29,30,31,32,33,36,40,52,55> +3VS https://vinafix.com
+3VS
2
100K_0402_5% SW1 SN10000CU00
Q4108
G
SW TJG-533KQRH SPST DIP H1.55 6P <7,13,29,30,33,34,35,40,48,49,50,51,55> +3VALW +3VALW
2
<33> ON/OFF# ON/OFF# 1 3 ON/OFF#_R 1 3
S
2 4
2N7002K_SOT23-3
SB00000EN00 @
6
5
L Layout notes JP6
IO BD Connector ( USB2.0,Card reader,HDD & PWR LED )
1 2
JP6 place Bottom layer SHORT PADS
EMI@ C139 470P_0402_50V8J
1 1
1 2
CONN@
JIO
1
ESD Diode +5VALW
2
3
1
2
LID_SW# 4 3
5 4
ON/OFF#_R 6 5
+3VS 6
7
7
3
USB20_N4_R 8
USB20_P4_R 9 8
Card reader 10 9
ESD@
D1 USB20_N3_R 11 10
SCA00001B00 USB20_P3_R 12 11
AZ5123-02S.R7G 3P CASOT23
USB2.0 ( on small BD) 13 12
<33,38> USB_ON# 13
14
15 14
<11> SATA_LED# 15
16
<33> PWR_LED#
1
17 16
18 17
1 1 18
EMI@ EMI@
C138 C137 19
G1 20
2 2 G2
Lid Switch (Hall Effect Sensor)
470P_0402_50V8J
470P_0402_50V8J
CVILU_CF31181D0R4-10-NH
SP011411241
RB751V-40 SOD-323
+3V_LID
+3VL +3V_LID
1
DH2 R126
4.7K_0402_5% RS51 @EMI@
1 2
2 LM4 0_0201_5% 2
2
1 2
U4018 EMI@
3 LID_SW#_OUT 1 2 4 3 USB20_N3_R
OUT LID_SW# <33> <11> USB20_N3 4 3
2 R5197
VDD 1 0_0402_5% 3.3P_0402_50V8J CC152
J
10P_0402_50V8
GND 1 1
1 2 USB20_P3_R
C19
J
100P_0402_50V8
C5228
<11> USB20_P3 1 2
1 APX8131AI-TRG SOT-23
EMI@
C18 SA00009EM00 SM070005U00 DLM0NSN900HY2D_4P
2 2 ESD@ RS52 @EMI@
0.1U_0201_10V6K 1 2
2 0_0201_5%
RS53 @EMI@
1 2
0_0201_5%
LM6 EMI@
+3V_LID 4 3 USB20_N4_R
<11> USB20_N4 4 3
3.3P_0402_50V8J CC154
+3VL 1 2 USB20_P4_R
2
<11> USB20_P4 1 2
R13
EMI@
DB@ 470K_0402_5% SM070005U00 DLM0NSN900HY2D_4P
2
RS54 @EMI@
G
Q32 1 2
1
0_0201_5%
3 1
DB@
S
2N7002K_SOT23-3 +3V_LID
SB00000EN00
+3V_LID
U4019
2
LID_SW#_OUT 8 R125
1 CP VCC
3 DB@ 10K_0402_5% 3
2 1 R124 7
10K_0402_5% 2 D PR#
1
DB@ 6
3 Q# CLR#
5
4 GND Q
NL17SZ74USG US 8P FLIP-FLOP
SA00003ML00
DB@
DH3 DB@ RB751V-

40 SOD-323
2 1
+3V_SMBUS
2 1
+3VL
DH4
RB751V-40 SOD-323
2 1
<33,48> EC_ON
DH5
RB751V-40 SOD-323
4 4

Deciphered Date
IO CON
TH IS S H E E T O F E N G IN E E R IN G D R A W IN G IS TH E P R O P R IE TA R Y P R O P E R TY O F C O M P A L E L E C TR O N IC S , INC. A N D C O N TA IN S CONFIDEN TI A L
A N D TR A D E S E C R E T IN F O R M A TIO N . TH IS S H E E T M A Y N O T B E TR A N S F E R E D F R O M TH E C U S TO D Y O F TH E C O M P E TE N T DIVISION O F R & D
SS i z e Document Number Rev
D E P A R TM E N T E X C E P T A S A U TH O R IZ E D B Y C O M P A L E L E C TR O N IC S , INC. N E ITH E R TH IS S H E E T N O R TH E IN F O R M A TIO N IT C O N TA IN S Custom v0.3
M A Y B E U S E D B Y O R D IS C L O S ED TO A N Y TH IR D P A R TY W ITH O U T P R IO R W R ITTE N C O N S E N T O F C O M P A L E L E C TR O N IC S , INC. LA-G07FP(KBL-U_UMA_6L)
Date: Tuesday, January 09, 2018 Sheet 39 of 59
A B C D E
A B C D E
+3VS +3VS <6,7,9,10,11,13,17,18,27,28,29,30,31,32,33,36,39,52>
+5VS +5VS <27,28,32,33,34,36,37>

https://vinafix.com
+3VS
+5VALW
1
+3VALW
10U_0603_6.3V6M
C570
Q21
1 VR_ON <33,52>
14
2 VIN1 VOUT1 13 2
VIN1 VOUT1
6
+5VALW
1 For meet tPLT17 & tCPU28 power down sequence. 1
SUSP# 3 12 C557 1 2 680P_0402_50V7K @
ON1 CT1 tPLT17 : 1us (Max)
4 11 tCPU28 : 1us (Max) 2
VBIAS GND Q5002A
5 10 C554 1 2 100P_0402_50V8J L2N7002SDW1T1G 2N SC88-6
1
<12,33,49> SUSP# ON2 CT2 SB00001FF00
6 9
VIN2 VOUT2 +5VS +3VALW
7 8
VIN2 VOUT2
10U_0603_6.3V6M
22U_0805_6.3V6M
0.1U_0402_25V6
1 1 1
15 @RF@ @ESD@
C575
CC140
CC163
GPAD
1
EM5209VF_DFN14_3X2 R5096
2 2 2 EC_VCCST_PG_R <9,33>
1 1 1 1 1 SA00007PM00 @ 100K_0402_1%
CC162
CC158
CC161
CC160
CC157
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
3
2
@ Q5002B
2 2 2 2 2
PM_SLP_S3_H 5 SB00001FF00
4
@ESD@ @ESD@ @ESD@ @ESD@ @ESD@
6
@
PM_SLP_S3# 2
<9,12,33> PM_SLP_S3# Q5003A
L2N7002SDW1T1G 2N SC88-6 SUSP#
1
SB00001FF00
2 2
6
@
For +1.8V_PRIM Discharge For meet tPLT15 power down sequence(Un-Stuff) 2 Q5004A
tPLT15 : 1us (Max) L2N7002SDW1T1G 2N SC88-6
SB00001FF00
1
+5VALW +1.8V_PRIM
+3VALW
1
1
R5092 R5093
1
100K_0402_1% 22_0603_1%
SYSON <12,33,49>
R5095 @
2
3
32
100K_0402_1%
@
2
Q5004B
Q5001B PM_SLP_S4_H 5 L2N7002SDW1T1G 2N SC88-6
PCH_PWR_EN# 5 L2N7002SDW1T1G 2N SC88-6 SB00001FF00
3
SB00001FF00
4
@ Q5003B
4
5 SB00001FF00
<9,12,33,49> PM_SLP_S4#
6
4
Q5001A
2 L2N7002SDW1T1G 2N SC88-6
3 <33,51> PCH_PWR_EN SB00001FF00 3
1
4 4

THIS SHEET O F ENGINEERING DRAW ING IS T HE PRO PRIET ARY PRO PERT Y O F COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENSTiIzAeL DocumentNumber
DC Interface
Rev
DEPART MENT EXCEPT AS AUT HO RIZED BY CO MPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMAT ION IT CONTAINS Custom v0.3
MAY BE USED BY O R DISCLO SED T O ANY THIRD PART Y W IT HO UT PRIO R W RIT T EN CONSENT O F COMPAL ELECTRONICS, INC. LA-G07FP(KBL-U_UMA_6L)
A B C D E
5 4 3 2 1
https://vinafix.com
+19V_ADPIN EMIVGA@ PL12
+19V_VIN
5A_Z80_0805_2P
1 2
@ PJP1 EMI@ PL11

D ACES_51483-00801-001 5A_Z80_08 05_2 D
1 1 P @PR1
1 2
2 0_0402_5%
2
3 1 2ACIN_LED
1000P_0402_50V7K
0.022U_0402_25V7K
3 <33> AC_LED#
4
1000P_0402_50V7K
100P_0402_50V8J
4
5
5
1
EMI@ PC2
EMI@ PC4
EMI@ PC3
EMI@ PC1
6 ADP_SIGNAL
6
1
7 Charge_LED
7
2 1
21
8 ACIN_LED PR2
8
2
9 100K_0402_5%
10 GND
GND
2
PR3
10K_0402_5% PR4
ADP_SIGNAL1 2 750_0402_1%
ADP_ID <33> 1 2 Charge_LED
<33> BAT_CHG_LED
3
1
LUDZS3.6BT1G_SOD323-2
1000P_0402_50V7K
PR6
100P_0402_50V8J
1
100K_0402_5%
1
10K_0402_5%
2
PC6
PR5
@ PC5
PD3
2
ESD@ PD1 ESD@ PD2
1
2
L30ESD24VC3-2_SOT23-3 L30ESD24VC3-2_SOT23-3
C C
<33,47> ADP_I
+3VALW_EC
1
PR9 PR10
16.2K_0402_1% 5.9K_0402_1%
VCIN0_PH <33> VCIN1_PH <33>
1 2
1 2
PH1
100K_0402_1%_B25/50 4250K PR13
B 10K_0402_1% B
2
ECAGND <33>
A A

Deciphered Date
DC Conn
THIS SHEET O F ENG INEERING DRAW ING IS T HE PRO PRIET ARY PRO PERT Y O F COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENSSTiIzAeL Document Number
Rev
5 4 3 2 1
5 4 3 2 1
https://vinafix.com
D D
+3V_LID
@ PR18
0_0402_5% EMI@ PL13
1 2 5A_Z80_0805_2P
1 2 +12.6V_BATT +3V_LID +19VB
OCTEK_BTJ-08KPBR4B
GND
10 +12.6V_BATT+
9 EMI@ PL14
GND 8 5A_Z80_0805_2P
8 7 1 2
7 6 EC_SMB_CK1_R
100P_0402_50V8J
0.01U_0402_50V7K
6
1
PC9
5 EC_SMB_DA1_R
1.8K +-1%0805
@EMI@ PC10
5 4 +3V_LID_R EMI@ PC8 @EMI@ PR20
4
EMI@
3 B/I#_R 1000P_0402_50V7K PC11 470K_0402_5%
3
2 1
2 1
21
21
2
PR19
100P_0402_50V8J
2 1
1
2
2
@ PJPB1
6
PR14
100_0402_5%
1 2
C EC_SMB_CK1 <33,47> 2 PQ2A C
PR15 L2N7002SDW1T1G 2N SC88-6
100_0402_5%
3
1 2
EC_SMB_DA1 <33,47>
1
+3VL
1M_0402_5%
+3VL 5
PR21
1
PR16 PQ2B
4
100K_0402_5% L2N7002SDW1T1G 2N SC88-6 @
2
PR17
100_0402_5%
1 2 2
B/I# <33>
B B
A A

Deciphered Date
BATT Conn
THIS SHEET O F ENG INEERING DRAW ING IS T HE PRO PRIET ARY PRO PERT Y O F COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENSSTiIzAeL DocumentNumber
Rev
5 4 3 2 1
A B C D
Protection for reverse input

https://vinafix.com
1
D +19VB
2
G @ PQB2
2N7002KW_SOT323-3
CHG_N002
S
3
PRB2 @ @ PRB3
1 1M_0402_5% 3M_0402_5% 1
1 2 1 2
+19V_VIN +19VB_CHG
PQB11
P1 PQB12 P2
AON7506_DFN33-8-5 PRB1 PQB13
EMB04N03H_EDFN5X6-8-5 1 EMI@ PLB11 AON7506_DFN33-8-5
0.01_1206_1%
1 2 1UH_2.8A_30%_4X4X2_F
2 3 5 1 4 1 2 1
5 3 2
2 3 5 3
0.1U_0402_25V6
PCB25
10U_0805_25V6K
2200P_0402_50V7K
2200P_0402_50V7K
4
2 1
+19V_VIN
PCB7
10U_0805_25V6K
10U_0805_25V6K
0.01U_0402_50V7K
@ PCB6
@EMI@ PCB8
PCB4
PCB5
4
4
2 1
2 1
PCB9
2
2 1
2 1
2 1
3
2
PDB1
ACDRV_CHG_R BAS40CW _SOT323-3
BATDRV_CHG 1 2 BATDRV_CHG_R
0.1U_0402_25V6
0.1U_0402_25V6
PCB1
PRB5
PCB11
1 1
1 2 CHG_N003 PCB12 4.12K_0603_1%
2 1
2 1
0.047U_0402_25V7K PQB1
PRB6 10_1206_1%
PCB10 1 2 CHG_N001 AONH36334_DFN3X3A8-10
10
0.1U_0402_25V6
1
1
4
2.2_0603_5%
D1
5 S2 D1
PRB7
PDB2
2
RB751V-40_SOD323-2 3
2 6 S2 D1 2
VCC_CHG
2
7 S2 D1
2
+12.6V_BATT
D2/S1
1 UG_CHG
4.12K_0603_1%
4.12K_0603_1%
REGN_CHG
1
1
PCB13 8 G2 G1
BTST_CHG
PRB9
PRB10
PLB1
UG_CHG
1 2 PRB11
LX_CHG
9
4.7UH_5.5A_20%_7X7X3_M 0.01_1206_1%
1U_0603_25V6K 1 2
ACP_CHG
ACN_CHG
LX_CHG 1 2 CHG 1 4
2
2
PCB14
1U_0603_25V6K 2 3
20
19
18
17
16
1
VCC
BTST
REGN
HIDRV
PHASE
10U_0805_25V6K
10U_0805_25V6K
21
EMI@PRB12
4.7_1206_5%
1 SRN_R
1 SRP_R
PAD
0.1U_0402_25V6
0.1U_0402_25V6
PCB15
PCB16
1
1
1 15 LG_CHG
ACN LODRV
PCB17
PCB18
2
1 SNUB_CHG 2
2 14
ACP GND
PRB13
2
2
10_0603_1%
CMSRC_CHG 3 13 SRP1 2 SRP_R
CMSRC SRP
1
PUB1 PRB14
BQ24725ARGRR_QFN20_3P5X3P5 6.8_0603_1% PCB20
ACDRV_CHG 4 12 SRN1 2 SRN_R
680P_0402_50V7K
SRN .1U_0402_16V7K
2
ACDRV
EMI@ PCB19
2
1 2 5 11 BATDRV_CHG
+3VL PRB15
ACOK ACDET BATDRV
100K_0402_1%
IOUT
SDA
SCL
ILIM
3 3
<33> VCIN1_ACOK
6
10
+3VL
ILIM_CHG 1 2
IOUT_CHG
ACDET_CHG
SDA_CHG
SCL_CHG
PRB16
100K_0402_1%
1
453K_0402_1%
PRB20
1
PRB17
422K_0402_1% PCB21
1 2 0.01U_0402_50V7K
+19V_VIN
2
02_5% PRB19
2
0_0402_5% PRB18
1
1
2
2
@ 0_04
EC_SMB_CK1 <33,46>
0.22U_0402_16V7K
@
1
100P_0402_50V8
66.5K_0402_1%
PCB23
PRB21
PCB22
EC_SMB_DA1 <33,46>
2 1
2 1
@ PRB22
2
0_0402_5%
1 2
ADP_I <33,45>
J
PCB24
4 4
0.1U_0402_25V6
Vin Dectector
2
Min. Typ Max.

L-->H 17.16V 17.63V 18.12V Close EC chip
H-->L 16.76V 17.22V 17.70V
VILIM = 20*ILIM*Rsr Issued Date 2016/09/01 Deciphered Date 2019/09/01 Title
ILIM = 3.3*100/(100+620)/20/0.02
T H IS S H E E T O F E N G I N E E R I N G D R A W I N G IS T H E P R O P R I E T A R Y P R O P E R T Y O F C O MP A L E L E C T R O N IC S , IN C . A N D C O N T AIN S CONFIDEN T I A L
CHARGER
= 2.291 A A N D T R A D E S E C R E T IN F O R MAT IO N . T H IS S H E E T MA Y N O T B E T R A N S F E R E D F R O M T H E C U S T O D Y O F T H E C O MP E T E N T D IVISIO N O F R & D
SS iz e Document Number Rev
D E P A R T ME N T E X C E P T A S A U T H O R I Z E D B Y C O MP A L E L E C T R O N I C S , IN C . N EIT H ER T H IS S H E E T N O R T H E IN F O R MA T IO N IT C O N T AIN S v0.3
MA Y B E U S E D B Y O R D ISC LO S ED T O A N Y T H I R D P A R T Y W I T H O U T P R I O R W R IT T E N C O N S E N T O F C O MP A L E L E C T R O N IC S , IN C .
A B C D
5 4 3 2 1
+19VB EMI@ PL304

5A_Z80_0805_2P
PU301
SY8286BRAC_QFN20_3X3
@ PR302
0_0402_5%
PC302
0.1U_0201_10V6K
https://vinafix.com
1 2 +19VB_3V BST_3V 1 2 BST_3V_R 1 2
2200P_0402_50V7K
0.1U_0402_25V6
@EMI@ PC303
10U_0805_25V6K
2 1
EMI@ PC304
1
PC305
2 1
2 1
PL302
IN
IN
IN
IN
BS
1.5UH_6A_20%_5X5X3_M
LX_3V6 20 LX_3V 1 2
D LX LX +3VALWP D
7 19
GND LX
680P_0402_50V7K 4.7_1206_5%
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
+3VALW
1
8 18
PR303
@EMI@
GND GND
PC306
PC307
PC308
PC309
2 1
2 1
2 1
9 17
+3VLP
2
PG LDO
1
10 16
2N
NC NC
13V_S
PC310
OUT
EN2
EN1
2 1
PR304 21 4.7U_0603_6.3V6M
NC
FF
100K_0402_5% GND
@EMI@
2
11
12
13
14
15
3.3V LDO 150mA~300mA
PC311
2
<9> SPOK
ENLDO_3V5V PC312 PR305 Fsw : 600K Hz
1000P_0402_50V7K 1K_0402_1%
5V_3V_EN 3V_FB 1 2 3V_FB_1 1 2
@ PJ302
1 2
+3VALWP 1 2 +3VALW
JUMP_43X118
@ PJ303
JUMP_43X39
1 2
2 Cell battery : Cin=10uF*2pcs +3VLP 1 2 +3VL
C C
3 Cell ~ 4 Cell battery : Cin=10uF*1pcs
+19VB EMI@ PL303 +19VB_5V @ PR306 PC313
5A_Z80_0805_2P 0_0402_5% 0.1U_0201_10V6K
1 2 +19VB_5V BST_5V1 2 BST_5V_R 1 2
PU302
1
SY8288CRAC_QFN20_3X3
IN
IN
IN
IN
BS
PL301
LX_5V 6 20 2.2UH_7.8A_20%_7X7X3_M
2200P_0402_50V7K
0.1U_0402_25V6
10U_0805_25V6K
LX LX
7 19 LX_5V 1 2 +5VALWP
GND LX
EMI@ PC316
PC314
@EMI@ PC317
8 18
GND GND PC318
2 1
2 1
2 1
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
9 17 VCC_5V 1 2
PG VCC
1
1SPOK_5V
PC322
PC301
PC323
PC319
PC328
PR308
4.7_1206_5%
2 1
2 1
2 1
2 1
2 1
PR307 10 16
@EMI@
499K_0402_1% NC NC 2.2U_0402_6.3V6M
OUT
LDO
EN2
EN1
1 2 ENLDO_3V5V 21
+19VB
FF
GND
1
2
@ PR310
11
12
13
14
15
PR309 0_0402_5%
5V_SN
499K_0402_1%
2
SPOK
680P_0402_50V7K
+5VL
2
1
5V LDO 150mA~300mA
PC324
@EMI@
4.7U_0603_6.3V6M
ENLDO_3V5V
2
PC325
B B
PR301
Fsw : 600K Hz
2 1
2.2K_0402_5% 5V_3V_EN
1 2
<33,39> EC_ON @ PR311
0_0402_5%
1 2
<33> MAINPWON PC326 PR312
1000P_0402_50V7K 1K_0402_1%
5V_FB 1 2 5V_FB_1 1 2
5V_3V_EN
@PJ305
1 2
1M_0402_1%
+5VALWP +5VALW
4.7U_0402_6.3V6M
1 2
1
PC327
JUMP_43X118
PR313
2 1
2
A A

TH IS S H E E T O F E N G I N E E R I N G D R A W I N G IS T H E P R O P R I E T A R Y P R O P E R T Y O F C O M P A L E L E C T R O N I C S , IN C . A N D C O N TA IN S CONFIDENT IA L
3VALW/5VALW
A N D T R A D E S E C R E T I N F O R M A T I O N . TH IS S H E E T M A Y N O T B E T R A N S F E R E D F R O M T H E C U S T O D Y O F T H E C O M P E T E N T D IV IS IO N O F R & D
D E P A R T M E N T E X C E P T A S A U T H O R I Z E D B Y C O M P A L E L E C T R O N I C S , IN C . N E ITH E R TH IS S H E E T N O R T H E I N F O R M A T I O N IT C O N TA IN S Custom
M A Y B E U S E D B Y O R D IS C L O S E D T O A N Y T H I R D P A R T Y W I T H O U T P R I O R W R I T T E N C O N S E N T O F C O M P A L E L E C T R O N I C S , IN C . LA-G07FP(KBL-U_UMA_6L) v0.3
Date: Friday, J a n u a r y 05, 2 0 1 8 Sheet 48 of 59

5 4 3 2 1
5 4 3 2 1
https://vinafix.com
Vinafix.com
D D
EMI@ PLM2
5A_Z80_0805_2P
1 2 +19VB_DDR PRM1
+19VB 2.2_0603_5%
BST_DDR_R 1 2 BST_DDR
10U_0805_25V6K
+1.2VP
2200P_0402_50V7K
PCM2
@EMI@ PCM1
+0.6VSP
2 1
21
PCM4 UG_DDR
21
0.1U_0603_25V7K
LX_DDR
10U_0603_6.3V6M
10U_0603_6.3V6M
PCM5
PCM6
PUM1
16
17
18
19
20
G5616BRZ1U_TQFN20_3X3
2 1
21
LX
BST
DH
VTT
VLDOIN
21
PAD
LG_DDR 15 1
DL VTTGND
1
14 2
D1
D1
D1
G1
PLM1 PRM2 PGND VTTSNS
1UH_11A_20%_7X7X3_M 11.5K_0402_1%
1 2LX_DDR 10 9 1 2 CS_DDR 13 3
D1 CS
+1.2VP D2/S1 PCM7 GND
1
1U_0402_6.3V6K
1 2 12 4 VTTREF_DDR
G2
S2
S2
S2
PRM4 VPP VTTREF
@EMI@ PRM3
4.7_1206_5% 5.1_0603_5%
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
8
1 2 VDD_DDR 11 5
VDDQSET
1 2
+5VALW VCC VDDQSNS

+1.2VP
PCM8
PCM9
PCM10
PCM11
PCM12
PCM13
SNB_DDR PCM15
PGOOD
2 1
2 1
2 1
2 1
2 1
21
VDDP_DDR
2 1
TON
@EMI@ PCM14 0.033U_0402_16V7K
S5
S3
C 680P_0402_50V7K PCM16 C
2 1
2
1U_0402_6.3V6K
6
10
PQM1
AONH36334_DFN3X3A8-10 PRM5
5.1_0603_5%
FB_DDR
1 2 PRM6
TON_DDR
6.04K_0402_1%
S5_DDR
+1.2VP
S3_DDR
@ PW ROK_DDR PRM7 1 2
PTPM1 470K_0402_1%
@ PJM2 +19VB_DDR 1 2
JUMP_43X118
1
+1.2VP 1 2 +1.2V_VDDQ @ PRM8
12
0_0402_5%
PG_+2.5V 1 2 PRM9
10K_0402_1%
2
1 2
@ PJM3 <12,33,40> SYSON @ PRM10
0.1U_0402_10V7K
JUMP_43X39 0_0402_5%
PCM17
1 2
1 2 +0.6V_0.6VS
2 1
@ Vout=0.75* (1+PRM6/PRM9)=1.2V
@ PRM11
0_0402_5%
1 2
<12,33,40> SUSP#
@ PRM12
0_0402_5%
1 2
<6> SM_PG_CTRL
@ PCM18
2 1
0.1U_0402_10V7K
B B
@ PJ2502
JUMP_43X39
PC2501 1 2
1 2
22U_0603_6.3V6M +2.5VP +2.5V
12
PU2501
@ PJ2501 PL2501
JUMP_43X39 1UH_MHCD252012A-1R0M-A8S_3A_20%
+3VALW 1 2 IN_2.5V 4 3 LX_2.5V 1 2
1 2 VIN LX +2.5VP
2016.12.27 @ PR2501 1 2 5 2
+3VALW PG GND
68P_0402_50V8J
0_0402_5%
1 2 PR2504 6 1
PC2504
<9,12,33,40> PM_SLP_S4# VFB EN

22U_0603_6.3V6M
22U_0603_6.3V6M
1
100K_0402_5%
PC2505
PC2506
1
2 1
G5719CTB1U_SOT23-6
Enable 1.2V
2 1
21
@ PR2502 PG_+2.5V @EMI@ PR2505 PR2506

0_0402_5% 4.7_0402_5% 32.4K_0402_1%
SYSON 1 2 EN_2.5V
2
2
.1U_0402_16V7K
1
SNB_2.5V
PC2502
PR2503 FB_2.5V
1M_0402_1%
21
A @ A
2
@EMI@ PC2503
2 1
680P_0402_50V7K PRM2507
10K_0402_1% Vout=0.6V *(1+PR2506/PR2507)=2.544V
Imax= 2A, Ipeak= 3A
2

T HI S S H E E T O F E NG I NE E R I NG DRAW IIING I S T H E P R O P R I E T AR Y P R O P E R T Y O F C O M P AL EL ECTRONI I I CS, INC... A N D C O NT AI NS CONFIDENTSIiAzLe Documenttt Number

1.2VP/0.6VSP/2.5V
A N D T R A D E S E C R E T I NF ORMATI ON. . . T HI S S H E E T M A Y NO T B E T R A N S F E R E D F R O M T H E C US T O D Y O F T H E C O M P E T E N T DIIIVISION O F R & D Rev
D E P AR T M E NT E X C E P T A S AUT HO R I Z E D B Y C O M P AL EL ECTRONI CS, , , I NC . NEI I THER T HI S S H E E T N O R T H E I NF O R M AT I O N I T C O NT AI NS Custom v0.3
M A Y B E US E D B Y O R D I S C L O S E D T O A N Y T HI R D P A R T Y W I T H O U T P R I O R W R I T T E N C O NS E NT O F C O M P AL E L E C T R O NI C S , IIINC.
Date::: Friday,,, J a nua ry 0 5 , 2 0 1 8 Sheettt 49 of 59
5 4 3 2 1
A B C D
https://vinafix.com
+1.0V_PRIMP +1.0V_PRIM
@ PJ1002
1 JUMP_43X118 1
1 2
1 2
<33> +1.0VS_PG
@EMI@ @EMI@
PR1007 PC1009
PR1005
100K_0402_1% +3VALW 1 2SNB_1V 1 2
EMI@ PL1002 2 1
PU1001
5A_Z80_0805_2P
4.7_1206_5% 680P_0402_50V7K
1 2 +19VB_1V 2 9 @ PR1006 PC1007
+19VB IN PG 0_0402_5% 0.1U_0402_25V6
3 1 BST_1V 1 2 BST_1V_R 1 2 PL1001
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_50V7K
IN BS 1UH_6.6A_20%_5X5X3_M
1
1
4 6 LX_1V 1 2
PC1001
+1.0V_PRIMP
EMI@ PC1003
@EMI@ PC1004
IN LX
5 19
330P_0402_50V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2
2
IN LX
2
PR1008
PC1011
PC1012
PC1013
PC1010
7 20 20K_0402_1%
VGA@ PC1014
GND LX
2 1
2 1
2 1
2 1
8 14 FB_1V
2
GND FB
1
2
PR1001 18 17 VCC_1V 2
0_0402_5% GND VCC
1
1 2 EN_1V 11 10
<51> +1.8V_PG EN NC PC1008
2.2U_0402_6.3V6M
2 1
ILMT_1V 13 12
1K_0402_1%
ILMT NC
0.1U_0402_25V7K
1
1M_0402_1%
@ PC1005
PR1010
PR1002
15 16
+3VALW
2
BYP NC
FB=0.6V
2 1
21
+3VALW PAD
2
1
SY8286RAC_QFN20_3X3
1
1
PC1006 PR1009
@ PR1003 1U_0402_6.3V6K 30K_0402_1%
2
0_0402_5%
2
N :H>0.8V ; L<0.4V
2
N pin don't floating

f have pull down resistor at HW side,
1
lease delete PR601.

@ PR1004
0_0402_5%
2
3 3
The current limit is set to 6A, 9A or 12A when this pin

is pull low, floating or pull high.
4 4
Security Classification Compal Secret Data

T H I S S H E E T O F E N G I N E E R I N G D R A W I N G IS T H E P R O P R I E T A R Y P R O P E R T Y O F C O M P A L E L E C T R O N IC S , IN C . A N D C O N T A IN S CONFIDENT I L
1.0V_PRIM
S izze Document Number Rev
A N D T R A D E S E C R E T I N F O R MA T I O N . T H I S S H E E T M A Y N O T B E T R A N S F E R E D F R O M T H E C U S T O D Y O F T H E C O M P E T E N T D IVISIO N O F R & D
D E P A R T M E N T E X C E P T A S A U T H O R I Z E D B Y C O M P A L E L E C T R O N I C S , IN C . N E IT H E R T H IS S H E E T N O R T H E IN F O R MA T IO N IT C O N T A IN S Custom v0.3
M A Y B E U S E D B Y O R D I S C L O S E D T O A N Y T H I R D P A R T Y W I T H O U T P R IO R W R I T T E N C O N S E N T O F C O M P A L E L E C T R O N IC S , IN C .
A B C D
5 4 3 2 1
https://vinafix.com
D D
PC1801
22U_0603_6.3V6M
@PJ1802
12 1 2
+1.8VSP 1 2 +1.8V_PRIM
JUMP_43X79
PU1801
@PJ1801 PL1801
JUMP_43X39 1UH_MHCD252012A-1R0M-A8S_3A_20%
+3VALW 1 2 IN_1.8V 4 3 LX_1.8V 1 2
1 2 VIN LX +1.8VSP
1 2 5 2
C
+3V_PRIM PG GND
C
PR1801 6 1
68P_0402_50V8
VFB EN
22U_0603_6.3V6
22U_0603_6.3V6
1
PC1803
PC1804
PC1802
100K_0402_5%
<50> +1.8V_PG
1
@EMI@ PR1803
G5719CTB1U_SOT23-6
21
21
21
PR1802 20K_0402_1%
4.7_0603_5%
1 2 EN_1.8V
<33,40> PCH_PWR_EN
2
2
M
@PR1804
SNUB_1.8V
.1U_0402_16V7K
1
0_0402_5% 2016.11.23
PR1805
@PC1805
1M_0402_1
FB_1.8V
21
1
@EMI@
%
2
PC1806
680P_0402_50V7K PR1806
2
10K_0402_1%
Vout=0.6V*(1+PR1803/PR1806)=1.8V
2
Imax= 2A, Ipeak= 3A
B B
A A

T H I S S H E E T O F E N G I N E E R I N G D R A W I N G IS T H E P R O P R I E T A R Y P R O P E R T Y O F C O M P A L E L E C T R O N I C S , I N C . A N D C O N T A I N S CONFIDENT I A L
1.8V_PRIM Vinafix.com
A N D T R A D E S E C R E T IN FO R MA T IO N . THIS S H E E T MA Y N O T B E T R A N S FE R E D FR O M T H E C U S T O D Y O F T H E C O MP E T E N T DIVISION O F R & D

Si z e Document Number Rev
D E P A R T M E N T E X C E P T A S A U T H O R I Z E D B Y C O M P A L E L E C T R O N I C S , I N C . N E I T H E R T H I S S H E E T N O R T H E I N F O R M A T I O N IT C O N T A I N S B v0.3
M A Y B E U S E D B Y O R D I S C L O S E D T O A N Y T H I R D P A R T Y W I T H O U T P R I O R W R I T T E N C O N S E N T O F C O M P A L E L E C T R O N I C S , INC. LA-G07FP(KBL-U_UMA_6L)
Date: Sheet 51 of 59
5 4 3 2 1
1 2 3 4 5
https://vinafix.com
A A
RT3602_VREF Vref=0.6V
PCZ3
953_0402_1
0.1U_0402_50V7K
6.8K_0402_1
1
11K_0402_1% 1.78K_0402_1%
1
1
PRZ2
PRZ3
PRZ4
2
%
AISPVCCSA <53>
<53> AVCCSA
@ PCZ4
2
0.47U_0402_25V6K
12
+VCC_SA
1
10_0402_1%
VSSSA_SENSE
1
V6K
PRZ1 PRZ8 PRZ10
1
RT3602_VREF
16.2K_0402_1
<14>
PCZ228<1
PRZ6
VSSCORE_SENSE
100_0402_1% 10K_0402_1% 49.9K_0402_1%
PRZ11
0.47U_0402_6.3
PRZ5
1 2 VCCSA_SENSE_R 1 2 1 2 2 1 2 1
21
PRZ13 PRZ14
2
PRZ15
% 2
RT3602_SET1 1 2 1 2 64.9K_0402_1% 453_0402_1%

RT3602_SET2 <12> VCCSA_SENSE 1 2
RT3602_SET3 PCZ5 390P_0402_50V7K PCZ6 68P_0402_50V8J
2>
100_0402_1
VR_PSYS 0_0402_5%
RT3602_VREF 3.9_0402_1%
+3VS
1
PRZ23
PRZ24
1
PRZ22 100_0402_1%
1
10K_0402_5%
464_0402_1
10K_0402_1
5.23K_0402_1
1.1K_0402_1
1
close to chock
% PRZ94
0_0402_5%
PRZ20
1 PRZ18
PRZ19
1
1 2
FB_SA
PRZ17
VR_PWRGD <33>
2
1
@ PHZ1 PRZ26
2
% 2
2
1
2
2
1
1
%
PRZ21
%
100K_0402_1%_B25/50 4250K 42.2K_0402_1% PRZ95 PRZ25

%
2
2
@ PCZ7 1 2 PHZ1_R 1 2 0_0402_5% 0_0402_5%
0.1U_0402_10V6K RT3602_VREF 1 2 VR_ON <33,40>
2
1
+1.0V_VCCST
2
536_0402_1
2.21K_0402_1
2.1K_0402_1
0_0402_5
IMON_SA
RT3602_EN
PRZ29
PRZ30
1 PRZ31
1 2 IMON_CORE_R 1 2
PRZ28
E VR_PSYS
VSEN_COR
B PRZ33 RGND_MAIN B
RGND_SA
COMP_SA
%
38.3K_0402_1% PRZ35
2
14.7K_0402_1%
2
1
% 2
FB_SA
%
0.1U_0402_25V
PCZ22
100_0402_1
45.3_0402_1
75_0402_1
@ PCZ9
0.1U_0402_10V6K PUZ1
21
PRZ36
PRZ38
PRZ39
12
49
48
47
46
45
44
43
42
41
40
39
38
37
RT3602AEGQW_WQFN48_6X6
%
2
1
2
1
2
1
%
PRZ43 PRZ45
%
VSEN_MAI
PSY
S FB_SA
RGND_SA
COMP_SA
VREF06/PSE
T ISENN_SA
ISENP_SA
IMON_SA
VR_READY
GND
RGND_MAIN
EN
6
10K_0402_1% 52.3K_0402_1% VR_SVID_CLK <14>
1 2 1 2 VR_ALERT# <14>
+VCC_CORE PRZ41 VR_SVID_DATA <14>
100_0402_1% PCZ12 82P_0402_50V8J IMON_COR1E 36 PWM_SA <53>
1 2 VSEN_CORE IMON_MAIN PWM_SA 35 VR_HOT# <33>
1 2 1 2 RT3602_SET12 DRVEN <53>
SET1 DRVEN 34
PRZ47 FB_CORE 3 1 2
FB_MAIN VCLK RT3602_VREF
0_0402_5% 270P_0402_50V7K <53> AVCORE1 PCZ13 COMP_CORE4 33 PRZ98 49.9_0402_1%
0.1U_0402_50V7K COMP_MAIN ALERT#
<14> VCCCORE_SENSE 1 2 PCZ11 RT3602_SET2 5 32 PRZ991 210_0402_1% PRZ48
SET2 VDIO 31
1 2 RT3602_SET3 6 PR1Z100 100_20402_1% 28.7K_0402_1% PRZ49 866_0402_1%
SET3
U42@ PRZ106 Ra 7 VR_HOT# 30 IMON_GT 1 2 1 2
1 2 1 2 ISEN1N_MAIN 8 ISEN1N_MAIN IMON_AUXI 29 @PCZ15 0.47U_0402_25V6K
U42@ 0_0402_5% 9 ISEN2N_MAIN ISENP_AUXI 28 1 2
PCZ16 0.1U_0402_50V7K 10 ISEN2P_MAIN ISENN_AUXI 27 VSEN_GT
<53> AVCORE2 TSEN_CORE 11 ISEN1P_MAIN VSEN_AUXI 26
Ra Rb/Rc RT3602_V1IN2 TSEN_MAIN COMP_AUXI 25
COMP_GT AISP1 <53> PRZ50
1
Rb 2
VIN RGND_AUXI AVGT1 <53> 0_0201_5%
+5VALW
DRVEN_SE
PWM1_MAI
PWM2_MAI
TSEN_AUX
PWM_AUXI
U22@ PRZ105 10K_0402_1% 12 VSEN_GT 1 2
I FB_AUXI
VCCGT_SENSE <14>
0.22U_0402_25VA
2.2_0805_1
U22 N/A Stuff <53> AISPCORE2 PCZ18
0.1U_0402_50V7K PRZ59
T NC
PRZ54 PRZ56
PRZ53
Rc +VCC_GT
1 21
100_0402_1%
PCZ19
29.4K_0402_1% 10K_0402_1%
NC
NC
VC
1 2
N
C
N
C
1 2 1 2 1 2
+5VALW U22@ PRZ104
2
%
U42 Stuff N/A 10K_0402_1%
PRZ107
DRVEN_SET 18
TSEN_GT 23
14
15
16
19
20
21
22
17
13
2 1 RGND_AUXI
<53> AISPCORE1
FB_GT 24
1 2 1 2 1 2
RT3602_VREF
K
PRZ51 PRZ52
RT3602_VCC
1
110K_0402_1% 1.65K_0402_1% 0_0402_5% PCZ20 82P_0402_50V8J PCZ21
TSEN_CORE_R 1 2 1 2 270P_0402_50V7K
+19VB_CPU PCZ230
1U_0603_25V6K
PHZ2
PRZ93
C C
1 2 0_0201_5%
2
115_0402_1% 8.25K_0402_1%
FB_GT
1
100K_0402_1%_B25/50 4250K
PRZ64
<53>
<53>
<53>
PWM_GT
PRZ63
PWM_CORE
PWM_CORE
+5VALW PRZ65 VSSGT_SENSE <14>
2
2
10_0402_1%
8.25K_0402_1%
1 2
1
374_0402_1%
1
2
PRZ68
PRZ67
1
PCZ23
2
2 1
TSEN_CORE_R 4.7U_0603_10V6K PRZ66
TSEN_GT_R 110K_0402_1%
1
100K_0402_1%_B25/50
549K_0402_1
182K_0402_1
PRZ71
+5VALW
1 2
PRZ70
2
PHZ3
PRZ69
2
1
2
1
1.65K_0402_1%
%
@ PRZ72
4250K
1
0_0402_5%
11.5K_0402_1
4.02K_0402_1
PRZ74
TSEN_GT_R 2
PRZ73
DRVEN_SET
2
1 2
2
PRZ75
0_0402_5%
2
D D

Deciphered Date
CPU_CORE
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT IA L
SS iz e Document Number
AND TRADE SECRET INFORMATION. THIS SHEET M A Y NOT BE TRANSFERED F R O M THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-G07FP(KBL-U_UMA_6L) v0.3
M A Y BE USED BY O R DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 2 3 4 5
1 2 3 4 5
+19VB_CPU
EMI@ PLZ3
5A_Z80_0805_2P +19VB
1 2 +19VB_CPU
PRZ76
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
100U_25V_NC_6.3X6
100U_25V_NC_6.3X6
https://vinafix.com
2.2_0603_5%
PCZ31
PCZ32
1 1
0.1U_0402_25V6
@EMI@ PCZ29
EMI@ PCZ30
CORE1_BST 1 2 CORE1_BST_R
+ +
5
U22@ PCZ26 U42@ PRZ77
PCZ229
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
PQZ1 68U_25V_M_R0.36 2.2_0603_5%
U42@ PCZ26
EMIU42@ PCZ33
EMIU42@ PCZ36
0.1U_0402_25V6
2 1
2 1
PCZ28 CORE2_BST 1 2 CORE2_BST_R
U42@ PCZ37
U42@ PCZ34
2
2
PUZ2
2 1
5
AON6380_DFN5X6-8-5
2 2
1
0.1U_0402_25V6
U42@
2 1
2 1
2 1
4 3 CORE1_UG 1 2 CORE1_UG_R 4 PUZ3 U42@ PCZ35
2
BOOT UGATE
2 1
PRZ78 0.1U_0402_25V6
5 2 CORE1_LX 0_0603_5%
<52> PW M_CORE1 PW M PHASE
4 3 CORE2_UG 1 2 CORE2_UG_R 4
+5VALW BOOT UGATE
<52> DRVEN
1
EN PGND
6 Rdc=1.19 mohm U42@ PRZ79 U42@
3
2
1
+VCC_CORE 5 2 CORE2_LX 0_0603_5% PQZ3
PLZ1 <52> PW M_CORE2 PW M PHASE
1 PRZ802 VCC_CORE1 8 7 AON6380_DFN5X6-8-5
VCC LGATE 9
GND
1 4 +5VALW DRVEN1
EN PGND
6 Rdc=1.19 mohm
3
2
1
1_0402_5% +VCC_CORE
2 3 1 2 VCC_CORE2 8 7 U42@ PLZ2
A RT9610CGQW_WDFN8_2X2 PQZ2 VCC LGATE 9 1 4 A
4.7_1206_5%
@EMI@PRZ82
GND
5
PCZ40 U42@ PRZ81
0.24UH_22A_+-20%_ 7X7X3_M
2 1
2.2U_0402_16V6K 1_0402_5% 2 3
RT9610CGQW_WDFN8_2X2
AON6314_N_DFN56-8-5
AISPCORE1_R
U42@
4.7_1206_5%
@EMIU42@ PRZ84
5
PCZ41 0.24UH_22A_+-20%_ 7X7X3_M
2 1
AISPCORE2_R
2.2U_0402_16V6K
CORE1_LG 4 PCZ42
0.1U_0402_25V6
2 1CORE1_SNUB 2 1
121 2 12
CORE2_LG 4 U42@ PRZ87 U42@ PRZ103 U42@ PCZ43
PRZ85 PRZ102 2.1K_0603_1% 2.1K_0603_1% 0.1U_0402_25V6
2 1CORE2_SNUB 2 1
3
2
1
2.1K_0603_1% 2.1K_0603_1% PRZ88 1 2 1 2 1 2
4.22K_0402_1% U42@
@EMI@PCZ44
1 2 PQZ4 U42@ PRZ90
680P_0402_50V7K
3
2
1
AON6314_N_DFN56-8-5 4.22K_0402_1%
1 2
@EMIU42@ PCZ45
680P_0402_50V7K
AVCORE1 <52>
AVCORE2 <52>
AISPCORE1 <52>
AISPCORE2 <52>
+19VB_CPU
VCC_CORE VCC_GT VCC_SA
FSW=500kHz FSW=500kHz FSW=600kHz
Choke=0.24uH Choke=0.24uH DCR=6.2 mohm +/- 5%
PRG2
DCR=1.19 mohm +/- 5% DCR=1.19 mohm +/- 5%
PCG5
PCG6
PCG11
PCG10
10U_0805_25V6K
0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
EMI@ PCG12
2.2_0603_5%
U22
0.1U_0402_25V6
GT_BST 1 2 GT_BST_R
EMI@ PCG3
EMI@ PCG4
5 PQG1 U22 U22 LL=10.3 mohm
LL=2.4 mohm LL=3.1 mohm TDC=4A
2 1
2 1
2 1
2 1
2 1
2 1
21
B PCG2 B
PUG1
2 1
AON6380_DFN5X6-8-5
0.1U_0402_25V6
TDC=21A TDC=18A ICCMAX=4.5A
4 3 GT_UG 1 2 GT_UG_R 4
BOOT UGATE PRG3 ICCMAX=32A ICCMAX=31A OCP=9.5A
<52> PW M_GT
5
PW M PHASE
2 GT_LX 2.2_0603_5% OCP=40A OCP=39A
+5VALW DRVEN 1
EN
6 Rdc=1.19 mohm U42
3
2
1
PGND
1 PRG1 2 VCC_GT 8 7
PLG1
+VCC_GT
U42 U42 LL=10.3 mohm
VCC LGATE 9
GND
1 4 LL=2.4 mohm LL=3.1 mohm TDC=
1_0402_5%
2 3 TDC=42A TDC=12A ICCMAX=5A
PQG2
ICCMAX=64A ICCMAX=28A OCP=9.5A
4.7_1206_5%
EMI@ PRG4
5
PCG1
1
0.24UH_22A_20%_ 7X7X3_M
OCP=70A OCP=39A
2 1
2.2U_0402_16V6K
AON6314_N_DFN56-8-5
AISP1_R
2
GT_LG 4 PRG6 PRG9 PCG8

1.58K_0603_1% 1.58K_0603_1% 0.1U_0402_25V6
1 2 1 2 1 2
PRG7 PRG8
3
2
1
2 1GT_SNUB
3K_0402_1% 10K_0402_1%
1 2 1 2
AVGT1_R
330P_0402_50V7K
EMI@ PCG9
1 2
PHG1
10K_0402_1%_B25/50 3370K
AVGT1 <52>
AISP1 <52>
C C
+19VB_CPU
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
PRA2
0.1U_0402_25V6
@EMI@ PCA6
2.2_0603_5%
EMI@ PCA2
SA_BST 1 2 SA_BST_R
PCA4
PCA5
2 1
2 1
2 1
2 1
PCA3
PUA1
2 1
0.1U_0402_25V6
4 3 SA_UG
BOOT UGATE
5 2 SA_LX
<52> PW M_SA PW M PHASE
1
+5VALW DRVEN 1 6 PQA1

Rdc=6.2 mohm
G1
D1
D1
D1
EN PGND PLA1 +VCC_SA

AONH36334_DFN3X3A8-10
1 2 VCC_SA 8 7 1 4
VCC LGATE 10
9 9
GND D2/S1 D1
PRA1 1_0402_5% 2 3
4.7_1206_5%
G2
@EMI@ PRA4
0.47UH_NA 12.2A_20%
S
S
2
PCA1
2 1
2.2U_0402_16V6K
8
AISPVCCSA_R
SA_LG
PCA7
0.1U_0402_25V6
1 2 1 2 1 2
2 1 SA_SNUB 2 1
PRA6 PRA9 PRA7 PRA8

953_0603_1% 953_0603_1% 866_0402_1% 1K_0402_1%
1 2 1 2
AVCCSA_R
@EMI@ PCA8
680P_0402_50V7K
1 2
PHA1
1K_0402_5%_TSM0B102J3652RE
AVCCSA <52>
D D
AISPVCCSA <52>
Security Classification Compal Secret Data Com pal Electronics, Inc.

Deciphered Date
CPU Pow er stage
TH I S S H E E T O F E N G I N E E R I N G D R A W I N G I S TH E P R O P R I E T A R Y P R O P E R T Y O F C O M P A L E L E C T R O N I C S , I N C . A N D C O N TA I N S CONFIDENT IA L
A N D TR A D E S E C R E T I N F O R M A TI O N . TH I S S H E E T M A Y N O T B E TR A N S F E R E D F R O M TH E C U S T O D Y O F TH E C O M P E T E N T D I V I S I O N O F R & D
D E P A R T M E N T E X C E P T A S A U T H O R I Z E D B Y C O M P A L E L E C T R O N I C S , I N C . N E I TH E R TH I S S H E E T N O R TH E I N F O R M A T I O N I T C O N T A I N S LA-G07FP(KBL-U_UMA_6L) v0.3
M A Y B E U S E D B Y O R D I S C L O S E D T O A N Y TH I R D P A R T Y W I TH O U T P R I O R W R I TTE N C O N S E N T O F C O M P A L E L E C T R O N I C S , I N C .
Date: Friday, January 05, 2018 Sheet 5 3 of 5 9
1 2 3 4 5
A
B
C
D
2 1 2 1 2 1 2 1
+VCC_CORE
2
1
2
1
2
1
PCZ210 PCZ200 PCZ187 PCZ167 PCZ147 PCZ100 PCZ78
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
2
1
2
1
2
1
2
1
PCZ211 PCZ201 PCZ188 PCZ168 PCZ148 PCZ101 @ PCZ79

+
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M PCZ68
5
5
2 1 2 1 2 1 2 1 390U_2.5V_ESR10M_6.3X6
2
1
2
1
2
1
2
1
PCZ212 PCZ202 PCZ189 PCZ169 PCZ150 PCZ102 @ PCZ80

+
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M U42@ PCZ215

2 1 2 1 2 1 2 1 330U_2V_M
2
1
2
1
2
1
2 1 2 1 2 1 2 1
2
1
2
1
2
1

2016.12.29
2 1 2 1 2 1
2
1
2
1
PCZ205 PCZ192 PCZ172 PCZ127 PCZ83

1U_0201_6.3V6M 1U_0402_6.3V6K 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2
1
2
1
2016.11.21
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2
1
U42
U22
PCZ207 PCZ194 PCZ174 @ PCZ97

1U_0402_6.3V6K 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2016.11.21
1uF*35
1uF*35
2 1 2 1 2 1
22uF*22
390uF*2
390uF*1
22uF*18
2
1
PCZ208 PCZ195 PCZ175 @ PCZ98

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
VCC_CORE：
2 1 2 1 2 1
2
1
PCZ209 PCZ196 PCZ176 PCZ99

1U_0201_6.3V6M 1U_0402_6.3V6K 1U_0201_6.3V6M 22U_0603_6.3V6M
2016.11.21
4
4
+VCC_GT
2 1 2 1
2
1
2
1
2
1
2
1
2
1
+

1U_0201_6.3V6M 1U_0402_6.3V6K 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 390U_2.5V_ESR10M_6.3X6
2 1 2 1
2
1
2
1
2
1
2
1
PCZ198 PCZ178 PCZ158 PCZ132 PCZ110 PCZ71

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2016.11.21
2 1 2 1
2
1
2
1
2
1
2
1
PCZ199 PCZ179 PCZ159 PCZ134 PCZ111 PCZ72

2 1
2
1
2
1
2
1
2
1

2 1
2
2
1
1
2
1
2
1
1uF*13
22uF*33
390uF*1
PCZ181 U42@ PCZ161 PCZ136 PCZ113 PCZ74

VCC_GT：
BOM option
U22 & U42
2 1
2
1
2
1
2
1
2
1
2
1
2016.11.10
PCZ130 PCZ182 U42@ PCZ162 PCZ137 PCZ114 PCZ75
Issued Date
2 1
+VCC_GT_VR
2
1
2
1
1
3
3
2@
2
1
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PCZ133 2 1
2
1
2
1
2
1
22U_0603_6.3V6M
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1
2
1
2
1
2
1

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
by JU22(for GT) and JU42A (for IA)
2 1
2
1
2
1
2016/09/01
PCZ186 PCZ166 PCZ86
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
U42@
2
1
U42@ PCZ149
22U_0603_6.3V6M
+VCC_GTX_VR
2
1
Compal Secret Data

Deciphered Date
U42@ PCZ152
2016.11.21
+VCC_SA
22U_0603_6.3V6M
2 1
2
1
PCZ140 PCZ87
1U_0402_6.3V6K 22U_0603_6.3V6M
2
2
2 1
2
1
1uF*7
PCZ141 PCZ88
22uF*9
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
VCC_SA：
2
1
U22 & U42
PCZ142 PCZ89
2019/09/01
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
2
1
PCZ143 PCZ90
MAY BE U SED BY O R DISCLO S ED T O AN Y T H IR D PAR T Y W IT H O UT PR IO R W R IT T EN C O N SEN T O F C O MPAL ELEC T R O N IC S, INC.
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
2
1
D EPAR T MEN T EXC EPT AS AU T H O R IZ ED BY C O MPAL ELEC T R O N IC S, INC. NEIT HER T HIS SH EET N O R T H E IN F O R MAT IO N IT CONT AINS
PCZ144 PCZ91
AN D T R AD E SEC R ET IN F O R MAT IO N . T HIS SH EET MAY N O T BE T R AN SF ER ED F R O M T H E C U ST O D Y O F T H E C O MPET EN T DIVISION O F R &D
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
Date:
Title
2
1
PCZ145 PCZ119
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
2
1
PCZ146 PCZ93
1U_0201_6.3V6M 22U_0603_6.3V6M
2
1
PCZ94
22U_0603_6.3V6M
2
1
Friday, January 05, 2018
PCZ96
22U_0603_6.3V6M
2
1
1
1
PCZ95
@
PROCESSOR DECOUPLING
22U_0603_6.3V6M
https://vinafix.com
Sheet
of 54
59
Rev
v0.3
A
B
C
D

HP 250 g7 Compal La-G07fp Epw50 Rev 1.0 (v0.3)

Uploaded by

Copyright:

Available Formats

You might also like

HP 250 g7 Compal La-G07fp Epw50 Rev 1.0 (v0.3)

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

HP 250 g7 Compal La-G07fp Epw50 Rev 1.0 (v0.3)

Uploaded by

Copyright:

Available Formats

A B C D E

Project :2018OPP_Harry Potter(15.6")

UV6 UV7 ChA:JDIIIIMM1(REV)

P.27 SATA ODD P.30 (sub board) LS-G074P

SATA 3.0 Port 2

NGFF WLAN+BT PCIex1 Port#6 5Gb/s

Security Classification Compal Secret Data Compal Electronics, Inc.

P.45 Vout +3VALW +3VALW

Charge Charger +19.5VB

+1.0V_PRIM Vout +1.0V_PRIM

CPU_CORE Vout +VCC_CORE

+1.35VS_VGA Vout +1.35VS_VGA

DGPU_PWR_EN PGOOD VRAM_PG

Security Classification Compal Secret Data Compal Electronics, Inc.

Power rail Control (EC) Source (CPU)

+3V_PCH PCH_PWR_EN X Thermal

ZZZ ZZZ ZZZ ZZZ

UC1 UC1 2 USB2.0/USB3.0

U9 Thermal Sensor :G753T11U

[Diner-PWR Sequence_SKL-U22_DDR3L_Volume_NON CS]

G3->S0 S0->S3/DS3 S0/DS3->S0 S0->S5 https://vinafix.com

PCH_PWR_EN (SLP_SUS#) PCH_PWR_EN (SLP_SUS#)

EXT_PW R_GATE# If EXT_PW R_GATE# T offmin is too small, Pwr EXT_PWR_GATE#

T4 = Min : 20ms Max : 3 0ms(EC Control)

VR_PW RGD VR_PW RGD

SYS_PW ROK SYS_PW ROK

Security Classification Compal Secret Data Compal Electronics, Inc.

PCH_JTAG_TDI A56 SOC_XDP_TDO

RC11 2 @ 1 51_0402_5% SOC_XDP_TMS

RC13 2 @ 1 51_0402_5% SOC_XDP_TDI

RC15 2 1 51 +-1% 0402 SOC_XDP_TDO SD000008H80

RC364 2 @ 1 51_0402_5% CPU_XDP_TCK0

RC14 2 @ 1 51_0402_5% XDP_PREQ# XDP_PREQ# <11>

RC31 1 @ 2 1K_0402_5% XDP_ITP_PMODE XDP_ITP_PMODE <16>

4 RC365 2 @ 1 51_0402_1% SOC_XDP_TRST# 4

RC35 2 1 51_0402_1% CPU_XDP_TCK0 SD000008H80

RC37 2 @ 1 51_0402_5% PCH_JTAG_TCK1

Compal Electronics, Inc.

Date: Friday, January 05, 2018 Sheet 5 of 59

Interleaved Memory https://vinafix.com

RC904 0.1U_0201_10V6K 2 1 CC57

Date: Friday, January 05, 2018 Sheet 6 of 59

SML0ALERT# (Internal Pull Down):

EC_KBRST# AW13 AW9 CLK_PCI0 RC387 1 2 22_0402_5% RPC19 10K_0804_8P4R_5%

to SPI ROM UC2 Source From +3V_PRIM

+3V_PRIM +3VALW HOST_SPI_0_SIO3 RC51 1 ES@ 2 1K_0402_1%

From WW36 MOW f or SKL-U ES sample

EON SA000046400 S IC FL 64M EN25Q64-104HIP SOP 8P MXIC

Date: Friday, January 05, 2018 Sheet 7 of 59

HDA for AUDIO

<32> HDA_SYNC_R 2 7 HDA_SYNC

<32> HDA_BIT_CLK_R 2 EMI@ 1 HDA_BIT_CLK

Date: Friday, January 05, 2018 Sheet 8 of 59

RC91 1 2 20K_0402_5% PCH_SRTCRST#

RC93 1 2 20K_0402_5% PCH_RTCRST# CLOCKSIGNALS

CC11 1 2 1U_0402_6.3V6K D42

CLK_PCIE_N4 B40 RTCX1 AM20 PCH_RTCX2