Sheet 7

Q1) Implement the function Y  BC  ABC using a 4:1 multiplexer and one inverter gate.

Solution

A B Y
0 0 C
0 1 C
1 0 0
1 1 C

Q2) Write a minimized Boolean equation for the function performed by the circuit in Figure

Solution

C D X
0 0 1
0 1 0
1 0 0
1 1 0
The function performed by the first multiplexer is X  CD

A B Y
0 0 1
0 1 CD
1 0 CD
1 1 0
The function performed by the second multiplexer is Y  ABCD  ABCD  AB

The minimized Boolean expression is Y  AB  ACD  BCD

 Another Solution Using Truth Table

A B C D Y
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

The minimized Boolean expression is Y  AB  ACD  BCD

Q3) What is the function performed by the MUX configuration shown in Figure 1 below? Show
all your work and be sure to minimize the expression.

Solution

C D X
0 0 1
0 1 0
1 0 0
1 1 B
The function performed by the first multiplexer is X  CD  BCD

A Y
0 CD  BCD
1 1
The function performed by the second multiplexer is Y  A  A(C D  BCD )

The minimized Boolean expression is Y  A  CD  BCD

 Another Solution Using Truth Table

A B C D Y
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

Using K-map

The minimized Boolean expression is Y  A  CD  BCD

Q4) Demonstrate how to implement a FULL Adder circuit by using 3x8 Decoder circuit.

Solution
Q6) Draw the logic diagram of a two-to-four decoder using
(a) NOR gates only, and
(b) NAND gates only. Include an enable input.

Solution

EN A B Y0 Y1 Y2 Y3
0 X X 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

(a)

ABE  A  B  E

ABE  A  B  E

ABE  A  B  E

ABE  A  B  E

(b)
Q7) Construct a 4 to 16 decoder with two 3x8 decoders with enable and other needed gates.

Solution

A0
A1
A2
A3