Lecture Notes Computer Organization

Module 4
Arithmetic
➢ Numbers , Arithmetic operations and characters
Bit : Binary 0 or 1
Binary number : Representaion of a number in a computer system using string of bits
called a Binary number.
Character code : A text character is represented using string bits called character code.

➢ Number Representation
Three systems are used for representing both positive and Negative number.
1. Sign and Magnitude
2. 1s complement
3. 2s complement

1. Sign and Magnitude

Negative values are represented by changing the most significant bit(b3) from 0 to 1
Note: Here the Leftmost bit is 0 for positive number and 1 for Negative number.
Positive values have identical representations in all systems. Negative values have
different representations.
+5 = 0)101 = 0101
-5 = 1)101=1101

2. 1’s Complement

Negative values are obtained by complementing each bit of the corresponding positive
number
-5 = 1)101
1)010
3. 2’s Complement
The 2’s complement of a number is obtained by adding ‘1’ to the 1’s complement of
that number.
-5 = 1)101
= 1)010 1’s compliment

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= 1)010
+ 1
= 1)011 2’s compliment

Binary, signed number Representation

2’s compliment Representation

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Addition of 2 numbers

Subtraction of 2 numbers
To subtract 2 numbers X and Y (ie) to perform X-Y ,first take the 2’s complement of ‘Y’
and then add it to X.

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Full Adders

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➢ An n-bit ripple carry adder

• A cascaded connection of n full adder blocks, can be used to add two n-bit numbers.
Since the carries must propagate, or ripple, through this cascade, the configuration is
called an n-bit ripple-carry adder.

xn - yn - 1 x1 y1 x0 y0
1

c c
n- 1 1
c FA FA FA c
n 0

s s s
n- 1 1 0
Most significant bit Least significant bit
(MSB) position (LSB) position

Cascade of K n-bit adder

• The carry-in, Co, into the least-significant-bit (LSB) position [Ist stage] provides a
convenient means of adding 1 to a number. Take for instance; forming the 2's-
complement of a number involves adding 1 to the 1’s-complement of the number. The
carry signals are also useful for interconnecting k adders to form an adder capable of
handling input numbers that are kn bits long

Addition /Subtraction Logic unit

The n-bit adder can be used to add 2's-complement numbers X and Y, where the xn-
1 and yn-1 bits are the sign bits. In this case, the carry-out bit, cn is not part of the
answer.

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In an addition, overflow can only occur when the signs of the two operands are the
same. In this case, overflow obviously occurs if the sign of the result is different.
Therefore, a circuit to detect overflow can be added to the n-bit adder by
implementing the logic expression.

Overflow

• Also, an overflow can be detected by using the carry bits cn and cn-1. An overflow
occurs if cn and Cn-1 are different. Therefore, a much simpler alternative circuit for
detecting an overflow can be obtained by implementing the expression Cn ⊕ Cn-
1with an XOR gate.
Cn Cn-1
0 1
+7 0111
+6 0110
1101
Cn⊕Cn-1
0 ⊕ 1 = 1 OF=1

Cn Cn-1
0 0
+5 0101
+2 0010
0111
Cn⊕Cn-1
0 ⊕ 0 = 0 OF=0

• Subtraction operation on two numbers X & Y can be performed using 2's-complement

method. In order to perform X - Y, we form the 2's-complement of Y and add it to X.
The logic circuit shown in Figure-3 can be used to perform either addition or
subtraction based on the value applied to the Add/Sub input control line. This line is
set to 0 for addition, applying the Y vector unchanged to one of the adder inputs along
with a carry-in signal, co.

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When the Add/Sub control line is set to 1 , the Y vector is 1’s complemented by the
XOR gates and C0 is set to 1 to complete the 2’s complementation of Y.

➢ Carry-Look ahead Addition:

A fast adder circuit must speed up the generation of the carry signals.The logic
expressions for si (sum) and c i+1 (carry-out) of stage i are

The above expressions Gi and Pi are called carry generate and propagate functions for
stage i. If the generate function for stage i is equal to 1, then ci+1 = 1, independent of
the input carry, ci. This occurs when both xi and yi are 1.
The propagate function means that an input carry will produce an output carry when
either xi or yi equal to 1. Now, using Gi & Pi functions we can decide carry for ith
stage even before its previous stages have completed their addition operations.

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All Gi and Pi functions can be formed independently and in parallel in only one gate
delay after the Xi and Yi inputs are applied to an n-bit adder
However, a much simpler circuit can be derived by considering the propagate
function as Pi = xi ⊕yi, .when xi = yi =1 where Gi = 1 (so it does not matter whether Pi
is 0 or 1). Then, the basic diagram in Figure-5 can be used in each bit stage to predict
carry ahead of any stage completing its addition.

Ci+1 = Gi + PiCi
C1=G0 + P0C0
C2=G1+ P1C1
=G1+P1(G0+P0C0)
C2 = G1+P1G0+P1P0C0
C3=G2 + P2C2
=G2+P2[G1+P1G0 + P1P0C0]
C3= G2+P2G1+P2P2G0 +P2P1P0C0
C4 = G3 + P3C3
=G3+ P3[G2+P2G1+P2P1G0 + P2P1P0C0]
=G3+P3G2+P3P2G1+P3P2P1G0 +P3P2P1P0C0

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Booth Algorithm
13 X -6 = -78 0 0 0xM
0 1 +1 X M
1 0 -1 X M
1 1 0XM
1.Make one of them as M and the other Q [Note : Let Q be –Ve]
2. If the number is negative take 2’s compliment of it without changing the sign
1101 X 1110 1 1 1 0
0 0 1
+ 1
1 0 1 0 [Q]
3. Since 13 is +ve take the sign = 0 1 1 0 1 [M]
4. Since Q is 4 bits make it equal to M
Q=11010
Take 2’s compliment of M
M= 01101
10010
+ 1
2’s of M 1 0 0 1 1

-1 = 2’s of M
+1= M

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