65 Mohit Tiwari IT 2 STLD File

Digital Circuit and System Lab Manual
Experiment No.1
Aim: To study and verify the Truth Tables of AND, OR, NOT, NAND, NOR EXOR logic
gates for positive logic.
Objective:
 To get familiar with the usage of the available lab equipments.
 To get familiar with Prototyping board (breadboard)
 To describe and verify the operation for the AND, OR, NOT, NAND, NOR,
XOR gates.
 To study the representation of these functions by truth tables, logic diagrams
and Boolean algebra
 To Introduce a basic knowledge in integrated circuit devices operation
 To practice how to build a simple digital circuit using ICs and other digital
components .
 Learn how to Wire a circuit
Appararus/ Equipment Required:

 Prototyping board (breadboard)
 DC Power Supply 5V Batt
 Light Emitting Diode (LED)
 Digital ICs: 7404 :Hex Inverter
7408 :Quad 2 input AND
7432 :Quad 2 input OR
7400: Quad 2 input NAND
7402: Quad 2 inpu
7486: Quad 2 input EXOR
 Connecting Wires
Pin Diagram:
Not Gate: IC 7404(HEX Inverter)

14 Pin
Supply voltage :5V
1
AND Gate: IC 7408

14 Pin
Quad 2 input AND Gate
Supply voltage :5V
OR Gate: IC 7432
14 Pin
Quad 2 input OR Gate
Supply voltage :5V
NAND Gate: IC 7400

14 Pin
Quad 2 input NAND Gate
Supply voltage :5V
NOR Gate: IC 7402

14 Pin
Quad 2 input NOR Gate
Supply voltage :5V
EXOR Gate: IC 7486

14 Pin
Quad 2 input EXOR Gate
Supply voltage :5V
2
Theory: A Digital Logic Gate is an electronic device that makes logical decisions based on the
different combinations of digital signals present on its inputs.Logic gates are the building blocks
of digital circuits. Combinations of logic gates form circuits designed with specific tasks in
mind. They are fundamental to the design of computers. Digital logic using transistors is often
referred as Transistor-Transistor Logic or TTLgates. These gates are the AND, OR, NOT,
NAND, NOR, EXOR and EXNOR gates
AND Gate: A multi-input circuit in which the output is 1 only if all inputs are 1.The symbolic
representation of the AND gate is:
The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high.
A dot (.) is used to show the AND operation i.e. A.B .
OR gate : A multi-input circuit in which the output is 1 when any input is 1.

The symbolic representation of the OR gate is shown:
The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are
high. A plus (+) is used to show the OR operation.
NOT gate : The output is 0 when the input is 1, and the output is 1 when the
input is 0. The symbolic representation of an inverter is :
3
The NOT gate is an electronic circuit that produces an inverted version of the input at its output.
It is also known as an inverter. If the input variable is A, the inverted output is known as NOT
A. This is also shown as A', or A with a bar over the top, as shown at the outputs.
NAND gate: AND followed by INVERT. It is also known as universal gate.The symbolic
representation of the NAND gate is :
This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs
of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small
circle on the output. The small circle represents inversion.
NOR gate: OR followed by inverter. It is also known as universal gate.The symbolic

representation is:
This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all
NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on
the output. The small circle represents inversion.
EXOR gate : The output of the Exclusive –OR gate, is 0 when it’s two inputs are
the same and it’s output is 1 when its two inputs are different.It is also known as Anti-
coincidence gate.
4
The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of its
two inputs are high. An encircled plus sign ( ) is used to show the EOR operation.
Procedure:
1. Collect the components necessary to accomplish this experiment.
2. Plug the IC chip into the breadboard.
3. Connect the supply voltage and ground lines to the chips. PIN7 = Ground
and PIN14 = +5V.
4. According to the pin diagram of each IC mentioned above, wire only one
gate to verify its truth table.
5. Connect the inputs of the gate to the input switches of the LED.
6. Connect the output of the gate to the output LEDs.
7. Once all connections have been done, turn on the power switch of the
breadboard
8. . Operate the switches and fill in the truth table ( Write "1" if LED is ON and
"0" if LED is OFF Apply the various combination of inputs according to the truth table
and observe the condition of Output LEDs.
9. Repeat the above steps 1 to 5 for all the ICs.
Observation Table: LED ON(RED light): Logic 1

LED OFF(Green Light): Logic 0
Input variables: A ,B
Output variable: Y
S.No Input(A) Input(B) Output Output Output Output Output Output

(OR) (AND) (OR) (NAND) (NOR) (XOR)
LED LED Y=A Y=AB Y=A+B Y = AB Y= A+B Y=A B
1
2
3
4
Calculation: NA
Results and Analysis:

NOT Gate: When logic 1 is applied to one of NOT gate of 7404 IC, then output becomes zero.
When input LED is ON (RED), the output LED become OFF (Green) vice versa.
5
OR Gate: The output of an OR gate is a 1 if one or the other or both of the inputs are 1, but a 0 if
both inputs are 0. When One or the other or Both of the input LEDS are ON (RED Light), then
output LED is ON(RED) otherwise Output LED is OFF(Green Light)
AND Gate: The output of an AND gate is only 1 if both its inputs are 1. For all other possible
inputs the output is 0.When both the LEDS are On, then output LED is ON (RED Light)
otherwise Output LED is OFF.
NOR Gate: The output of the NOR gate is a 1 if both inputs are 0 but a 0 if one or the other or
both the inputs are 1.
NAND Gate: The output of the NAND gate is a 0 if both inputs are 1 but a 1 if one or the other
or both the inputs are 0.
EXOR gate: The output of the XOR gate is a 1 if either but not both inputs are 1 and a 0 if the
inputs are both 0 or both 1.
Conclusion: Any Boolean expression can be realized using NOT, AND, OR, NAND,NOR,
EXOR gates.
References:
Books:
(1) M. Morris Mano - Digital Design - PHI (3rd Edition)
(2) R.P. Jain - Modern Digital Electronics – TMH
(3) Tocci - Digital Systems - (PHI)
URLS:
 http://nptel.iitm.ac.in/video.php?courseId=1005
 http://www.electronics-tutorials.ws/logic/logic_1.html
 http://nptel.iitm.ac.in/courses/Webcourse-contents/IIT-
%20Guwahati/digital_circuit/frame/index.html
 http://www.scribd.com/doc/16066166/Logic-Gates-Experiment-1
 http://richardbowles.tripod.com/dig_elec/chapter1/chapter1.htm
 http://www.gyte.edu.tr/dosya/102/dersler/elm321/Lab1.pdf
Lab Tutorails:
1. The number of level in a digital signal is:

a) one
6
b) two
c) four
d) ten
2. A pure sine wave is:
a) a digital signal
b) analog signal
c) can be digital or analog signal
d) neither digital nor analog signal
3. The high voltage level of a digital signal in positive logic is:
a) 1
b) 0
c) either 1 or 0
3. A gate in which all input must be low to get a high output is called:
a) an inverter
b) A NOR gate
c) an AND gate
d) a NAND gate
4. A NAND circuit with positive logic will operate as:
a) NOR with negative logic
b) AND with negative logic
c) OR with negative logic input
d) AND with positive logic output
5. To implement all function of the basic logic function, is sufficient to have:
a) OR
b) NOT
c) AND NOT
d) none of these
6. Which of the following ICs has only one NAND gate:
a) 7410
b) 7420
c) 7430
d) 7447
7. OR operation is:
a) X + XY
7
b) XY
c) X+Y
d) (X+Y) (X+Y)
8. AND operation is:
a) X(X + Y)
b) XY
c) X+Y
d) (X+Y) (X+Y)
9. NOR operation is:
a) X + Y
b) XY
c) X+Y
d) (X+Y) (X+Y)
10. NAND operation is:
a) X + Y
b) XY
c) X+Y
d) (X+Y) (X+Y)
11. What is the no. of OR IC.:
a) 7402
b) 7486
c) 7432
d) 7404
12. What is the no. of AND IC.:
a) 7402
b) 7408
c) 7447
d) 7492
13. What is the no. of NOR IC.:
a) 7402
b) 7486
c) 7447
d) 7492
14. What is the no. of NAND IC.:
8
a) 7402
b) 7404
c) 7400
d) 7492
15. What is the no. of NOT IC.:
a) 7402
b) 7486
c) 7404
d) 7492
16. What is the no. of EX-OR IC.:
a) 7402
b) 7486
c) 7447
d) 7492
17. Which of the following ICs has three input NAND gate:
a) 7420
b) 7430
c) 7410
d) 7474
18. Which of the following is Boolean eq. of EX-OR gate:
a) A+B
b) A+B
c) AB
d) A B + A B
19. Which one is the universal gate:
a) AND gate
b) OR gate
c) NAND gate
d) EX-OR gate
20. Bubbles on the gate shows:
a) active high
b) active low
c) both a and b
d) none
9
Digital Circuit and System Lab
21. Which statement is verify NAND gate:

a) if all input are high output is low
b) if all input are low output is low
c) any one n are low output is low
d) none of them
22. In regard to NAND gate the following four statement are made:
a) it is equivalent to an AND gate followed by an inverter
b) if all input to it are low, the output is low
c) if all input are high, the output is low
23. NAND operation on two elements is equivalent to OR operation on them. OF
thses, the only true statements are
a) 1,2
b) 1,3
c) 1,4
Short Answer type questions:
1) What are logis gates?

2) What is the difference between Positive Logis and negative Logic?
3) Draw EX-OR gate using NAND and NOR gate.
4) Why NOR gate and NAND gate called "Universal logic gate"?
5) Draw the symbol and truth table of following gates.
1. NOT 2. AND 3. OR 4. NAND 5. Ex-OR.
6) Implement following expressions by NOR gate only.
1. (A + B) . (B + C)
2. (A + C) . (B)
1
Experiment No. 2
Aim: Design and verify the logic circuit of Half adder using logic gates.
Design and verify the logic circuit Full adder using of Half adder.
Objective:
a. To understand the principle of binary addition.
b. To understand and to differentiate half & full adder concept.
c. Use truth table, Karnaugh map, and Boolean Algebra theorems in
simplifying a circuit design.
d. To implement half adder and full adder circuit uing logic gates
Apparatus Required:
 DC Power Supply 5V Batery
 Digital ICs: 7408 :Quad 2 input AND
Pin Diagram:
Half Adder:
Fig 2.1: Pin Diagram Of Half Adder
1
Full adder:
Fig 2.2:Pin diagram of Full adder
Theory:
Half Adder: A half adder is a logical circuit that performs an addition operation on two binary
digits. The half adder produces a sum and a carry value which are both binary digits.
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Fig 2.3:Circuit Diagram Of Half Adder Truth Table
Boolean Expression: S= A B
C=AB
1
F ull A d d el a d d a logical circuit that performs an addition operation on three binary

In p u t O u t
di r:Ful peurt is uces a sum and carry value, which are both binary digits. It can be
co gitA TBfCul aSddrCpo ders or work on its own.
s. he il eod
m0bie0 w0it ot0he 0full
n d h r ad
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
Fig 2.4:Circuit Diagram Of Full Adder Truth Table
Boolean Expression: S= A B Ci
Co=AB+Ci(A B)
Procedure:

and PIN14 = +5V.
4. According to the pin diagram of each IC mentioned above, make the connections
according to circuit dsagram.
breadboard
1
Observation Table:
Half Adder Input Variable: A ,B
Output Variable: S, C
LED ON: RED Light:Logic 1
LED OFF: Green Light:Logic 0
INPUTS(LED) OUTPUT
(LEDS)
A B S C
Full adder: Input Variable: A ,B,Ci

Output Variable: SUM(S), Carry(Co)
LED ON: RED Lioght:Logic 1
INPUT(LED)
OUTPUT(LED)
A B Ci Sum S Carry Co
Calculation:
Half Adder:
KMap simplification:SUM:
CARRY:
1
Boolean expression: Sum:

Carry
Full adder:
K Map Simplification: SUM:
CARRY:
Boolean Expression: SUM:

CARRY:
Result and Analysis:Verified the truth table as follows.

Half Adder: Verified the truth table of Half Adder as S = 1 i.e LED which is connected to S
terminal glows when inputs are A B
Verified the truth table of Half Adder as C = 1 i.e LED which is connected to C terminal
glows when inputs are A B
Full Adder: Verified the truth table of Full Adder as S = 1 i.e LED which is connected to S
terminal glows when inputs are A B Ci
Verified the truth table of Full Adder as Co = 1 i.e LED which is connected to Co terminal
glows when inputs are A B Co
CONCLUSION :
1. To add two bits we require one EXOR gate(Ic 7486 ) to generate Sum and one AND (Ic 7408)
to generate carry.
2. To add three bits we require two half adders.
References:
Books:
1. M. Morris Mano - Digital Design - PHI (3rd Edition)
1
2. R.P. Jain - Modern Digital Electronics – TMH

3. Tocci - Digital Systems - (PHI)
4. Morris Mano - Digital logic and computer design (PHI)
5. Malvino/Leach : Digital Principles and Applications
URLS:
1) http://nptel.iitm.ac.in/video.php?courseId=1005
2)
http://www.piclist.com/images/ca/ualberta/phys/www/http/~gingrich/phys395/notes/n
ode129.html
3) http://www.doc.ic.ac.uk/~ih/teaching/lectures/comparch/logic/adder/
4)
http://msbte.com/docs/labmanual/Diploma%20in%20Engineering/Third%20Semester
/Principales%20of%20Digital%20Techniques%20(9040)/Exp-5.pdf
5) http://www.scribd.com/doc/18737197/Full-Adder-Experiment-5
Lab Tutorials:
1. Half Adder adds:

a) 2 bits
b) 1 bit
c) 3 bit
d) 4 Bit
2. Full Adder adds:
d) 1 Bit
e) 2 Bits
f) Three Bits
g) None of above
3. The expression for sum of A, B in the half adder is given by:
a) AB
b) A B
c) A+ B
d) none of these
4. Which expression for the sum of full adder circuit.:
1
a) AB
b) A+B
c) A B Ci
d) none of these
5. The expression for carry of A, B in the half adder is given by:
a) AB
b) A + B
c) AÐ B
d) none of these
6. Which expression for the Carry of full adder circuit.:
a) AB
b) A+B
c) AB+Ci(A B)
d) none of these
7. The sum of 1110102 and 110112 in decimal form will be
a) 65
b) 75
c) 85
d) 95
8. The digit 0 with carry of I is the sum of binary addition:
a) 1 + 1
b) 1 + 0
c) 0 + 1
d) 0 + 0
9. FULL adder require:
a) Two Half adders
b) One Half Adder
c) Three half adder
d) None of the above
Short Answer Type questions:
1
Ques1: What is truth table and boolean expression?

Ques2: What is combinational circuit?
Ques3: Implement half adder and Full adder with NAND Gate only?
Ques4: Implement half adder and Full adder with NOR Gate only?
Ques5: Prove that Sum of a full adder is a XOR Gate between its inputs?
1
Experiment No. 3
Aim: Design and verify the logic circuit of Half subtractor using logic gates.
Design and verify the logic circuit Full subtractor using of Half subtractor.
Objective:
a. To understand the principle of binary subtraction.
b. To understand and to differentiate half & full subtractor concept.
c. Use truth table, Karnaugh map, and Boolean Algebra theorems in
simplifying a circuit design.
d. To implement half subtractor and full subtractor circuit uing logic gates
Apparatus Required:
 Digital ICs: 7408 :Quad 2 input AND
7404: Hex invertor(NOT Gate)
Pin Diagram:
Half Subtractor:
Fig 3.1: Pin Diagram of Half Subtractor

Full Subtractor:
1
Fig 3.2: Pin Diagram of Full subtarctor
Theory :
Half Subtractor: The half-subtractor is a combinational circuit which is used to perform
subtraction of two bits. It has two inputs, X (minuend) and Y (subtrahend) and two outputs D
(difference) and B (borrow).
Fig 3.3: Circuit Diagram of Half Subtractor
Full subtractor: A full Subtractor is combinational circuit that performs a subtraction between
three bits,taking into account that a ‘1’ may have been borrowed by a lower significant stage.The
2
3 inputs denote minuend,subtrahend and previous borrow, respectively.The 2 outputs are

difference(D) and borrow(B).
Fig 3.4: Circuit Diagram of Full Subtractor
Procedure
:

and PIN14 = +5V.
according to circuit diagram.
breadboard
Observation Table:
Half Subtractor: Input Variable: x ,y
Output Variable: D,B
INPUTS(LED) OUTPUT
(LEDS)
X Y 21 D B
Full adder: Input Variable: A B BORin D BORout

Output Variable: D,B
LED ON: RED Lioght:Logic 1
INPUT(LED)
OUTPUT(LED)
A B BORin D BORout
Calculation:
Half Subtractor:
KMap simplification: Difference:
Borrow:
Boolean expression: Difference:

Borrow:
Full Subtractor:
K Map Simplification: Difference:
22
Borrow:
Boolean Expression: : Difference:

Borrow:
Result and Analysis:Verified the truth table as follows.
Half Subractor: Verified the truth table of Half Subtractor as D = 1 i.e LED which is connected
to D terminal glows when inputs are x y.
Verified the truth table of Half Subtractor as B = 1 i.e LED which is connected to B terminal
glows when inputs are x y
Full Subractor: Verified the truth table of Full Subtractor as D = 1 i.e LED which is connected
to D terminal glows when inputs are X Y Bin
Verified the truth table of Full Subtractor as BORout = 1 i.e LED which is connected to BORout
terminal glows when inputs are X Y BORin
CONCLUSION :
1. To add two bits we require one EXOR gate(Ic 7486 ) to generate Difference and one AND (Ic
7408) and NOT Gate(Ic 7432) to generate Borrow.
2. To add three bits we require two half subtractor.
Books:
2

URLS:
2) http://www.electronics-tutorials.ws.html
3)
ode129.html
5)
Lab Tutorials:
1. Half Subtractor subtracts:

a) 2 bits
b) 1 bit
c) 3 bit
d) 4 Bit
2. Full Subtractor subtracts:
a) 1 Bit
b) 2 Bits
c) Three Bits
d) None of above
3. The expression for differene of A, B in the half subtractor is given by:
a) AB
b) A B
c) A+ B
d) none of these
4. Which expression for the differnce of full subtractor circuit.:
a) AB
b) A+B
c) A B Ci
d) none of these
2
5. The expression for borrow of A, B in the half subtractor is given by:

a) AB
b) A + B
c) AÐ B
d) none of these
6. Which expression for the Borrow of full subtractor circuit.:
a) AB
b) A+B
c) AB+Ci(A B)
d) none of these
7.FULL Subtractor require:
a) Two Half Subtractor
b)One Half Subtractor
c) three half Subtractor
8. The difference of 110012 and 100012 is
a) 10000
b) 01000
c) 00100
d) 00001
Short Answer Questions:
Ques1: Implement half Subtractor with NAND Gate only?

Ques2: Implement half Subtractor with NOR Gate only?
Ques3: Implement Full Subtractor with NAND Gate only?
Ques4: Implement Full Subtractor with NOR Gate only?
Ques5: Implement Full Subtractor in Decoder?
2
Experiment: 4
Aim: To Design and verify the truth table of code conversion from binary to gray code (4 bit)
using basic Logic Gates.
Objective:
 Design of different combinational circuits and their applications using basic
logic gates.
 Creation and observation of the four-bit Gray code number representation
sequence
 Exercising the design of code conversion logic circuits,
 Creating the truth table of conversion functions from Binary to Gray code
 Developing skills in simplification of specified logical functions
Apparatus Required:
 Digital ICs:7486: Quad 2 input EXOR
Pin Diagram:
Fig 4.1:Pin diagram of Binary to gray code converter using 7486 Ic(Exor Gate)
2
Theory:
Code Converters:A code converter is a circuit that makes two digital systems using different
codes for the same information. It means that a code converter is a code translator from one code
to the other. The code converter is used since to systems using two different codes but they need
to use the same information. So the code converter is the solution.
Binary-to Gray Converter:An interesting application for the exclusive-OR gate is a logic gate
to change a binary number to its equivalent in Gray Code. The logic circuit can be used to
convert a 4-bit binary number ABCD into its Gray-code equivalent, G1,G2,G3 and G4.
Application: Some sensors send information in Gray code. These must be converted to binary in
order to do arithmetic with it. Occasionally, it is necessary to convert back.
Advantages: Higher speed or smaller code.
Circuit Diagram:
Fig 4.2: Circuit Diagram of Binary to Gray Code Converter
Truth Table:
2
INPUTS OUTPUTS
A B C D G4 G3 G2 G1
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
Procedure :
and PIN14 = +5V.
4. Make connections as shown in the respective circuit diagram.
2
7. Once all connections have been done, turn on the power switch of the breadboard
8. Operate the switches and fill in the truth table ( Write "1" if LED is ON and "0" if L1 is
OFF Apply the various combination of inputs according to the truth tabe and obseve the
condition of Output LEDs.
Observation Table: Input Variable: A B C D
Output Variable: G3 G2 G1 G0
INPUTS(LED) OUTPUTS(LED)
A B C D G3 G2 G1 G0
Calculation:
Kmap Simplification:
For G3
For G2
For G1
For G0
2
Boolean Expression: G3 =
G2 =
G1 =
G0=
Result and Discussions: The binary to gray code converter is used since two systems using
two different codes but they need to use the same information.Binary to Gray code converter
convert correctly binary 0000 to 1111 into gary codes.The circuit diagram is very simple and
only uses an 74886 IC i.e Exor gate. Unless the karnaugh map is used many gates may be
used.but result of karnaugh map minimization,it can work ony using EXOR Gate.Gray code is a
weigted ,cyclic and reflective code are used in instrumentation and acquisition syatem where
linaer or angular displacement is measured,shaft encoders,I/O devices ,A/D converters and oter
peripheral devices.
Conclusion: Binary to gray code converter has been designed using EXOR gate and its truth
table verified.
References:
Books :
URLs:
1. http://www.most.gov.mm/techuni/media/BinaryToGrayCodeConverter.pdf
2. http://www.dspguru.com/dsp/tricks/gray-code-conversion
3. http://eng.iiu.edu.my/~aisha/exp3.pdf
3
Lab tutorial
1) Gray code is:
a) Unit distance code
b) BCD code
c) Excess 3 Code
2) Gray code is also known as
a) Reflecting codes
b) Binary code
c) BCD code
3).The Gray code for number 7 is:
a) 1100
b) 1001
c) 0100
d) 0110
4) The gray code for number 2 is:
a) 0010
b) 0011
c) 1000
d) 0101
5) The gray code for number 6 is:
a) 1100
b) 1001
c) 0101
Short Answer types question:

3
Ques1: What are the gray codes?
Ques2: What are the properties of Gray codes?
Ques3: What is the advantages and application of Gray codes?
Ques4: Convert 1100 into binary code?
Ques 5: Convert 1101 into Gray Code?
3
Experiment: 5
Aim: To Design and verify the truth table of code conversion from gray to binary code (4 bit)
Objective:
logic gates.
 Creation and observation of the four-bit binary code number representation
sequence
 Creating the truth table of conversion functions from Gray to binary code
Apparatus Rgequired:
Pin Diagram:
Fig 5.1:Pin diagram of Gray to Binary code converter using 7486 Ic(Exor Gate)
3
Theory:
Code Converters:A code converter is a circuit that makes two digital systems using different
codes for the same information. It means that a code converter is a code translator from one code
to the other. The code converter is used since to systems using two different codes but they need
to use the same information. So the code converter is the solution.
Gray-to Binary Converter:An interesting application for the exclusive-OR gate is a logic gate
to change a gray number to its equivalent in binary Code. The logic circuit can be used to
convert a 4-bit gray number ABCD into its binary-code equivalent, B3,B2,B1 and B0.
Application: Some sensors send information in Gray code. These must be converted to binary in
order to do arithmetic with it. Occasionally, it is necessary to convert back.
Advantages: Higher speed or smaller code.
Circuit Diagram:
Fig 5.2: Circuit Diagram of Binary to Gray Code Converter
Truth Table of Binary to Gray Code Converter:

3
INPUTS OUTPUTS
A B C D B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
Procedure :
and PIN14 = +5V.
3
Output Variable: B3 B2 B1 B0
A B C D B3 B2 B 1 B0
Calculation:
For B3
For B2
36
For B1
For B0
Boolean Expression: B3 =
B2 =
B1 =
B0=
Result and Discussions: The gray to binary code converter is used since two systems using
two different codes but they need to use the same information. Gray to binary code converter
convert correctly gray 0000 to 1111 into binary codes. The circuit diagram is very simple and
only uses an 74886 IC i.e Exor gate. Unless the karnaugh map is used many gates may be
used.but result of karnaugh map minimization,it can work ony using EXOR Gate.Gray code is a
weigted ,cyclic and reflective code are used in instrumentation and acquisition syatem where
linaer or angular displacement is measured,shaft encoders,I/O devices ,A/D converters and oter
peripheral devices.
Conclusion: Gray to Binary code converter has been designed using EXOR gate and its truth
table verified.
References:
Books :
3
URLs:
Lab tutorial
1) Gray to binary code converter required:
a) EXOR gate
b) EXNOR gate
c) NOR gate
2) Gray code equivalent of binary 010 is:
a) 011
b) 010
c) 100
3).The binary code for number 7 is:
a) 1100
b) 0111
c) 0100
d) 0110
4) The binary code for number 10 is:
a) 1010
b) 1011
c) 1000
3
d) 1001
5) The difference between sequential and combinational circuit is:
a) Combinational circuits store bits.
b) Combinational circuits have memory.
c) Sequential circuits store bits.
d) Sequential circuits have memory.
Ques1: What are code converters?
Ques2: What is the need of code converter?
Ques3: Design 3-bit gray to binary code converter ?
Ques4: Convert 1100 into gray code?
Ques 5: Convert 1101 into binary Code?
3
Experiment: 6
Aim: To Design and verify the Truth Table of 3-bit Parity Generator and 4-bit Parity Checker
using basic Logic Gates with an even parity bit.
Objective:
logic gates.
 Exercising the design of parity generator and parity checker logic circuits for
even and odd parity,
 Creating the truth table of parity generator and parity checker.
Apparatus Required:
Pin Diagram:
Fig 6.1:Pin diagram of 3-Bit Even Parity Generator using 7486 Ic(Exor Gate)
4
Fig 6.2: Pin diagram of 4-Bit Even Parity Checker using 7486 Ic(Exor Gate)
Theory:
Parity bits are extra signals which are added to binary information to enable error checking.
There are two types of Parity - even and odd. An even parity generator will produce a logic 1 at
its output if the data word contains an odd number of ones. If the data word contains an even
number of ones then the output of the parity generator will be low. By concatenating the Parity
bit to the dataword, a word will be formed which always has an even number of ones i.e. has
even parity.
4
If a dataword is sent out with even parity, but has odd parity when it is received then the data has
been corrupted and must be resent. As its name implies the operation of an Odd Parity generator
is similar but it provides odd parity. A parity bit can be added to code either at the beginning or
at the end depending on the system design. However the total number of 1’s including parity bit
is even for even parity and odd for odd parity. The parity detector can detect a single error or an
odd number of errors but cannot check for two errors. Parity is used on communication links
(e.g. Modem lines) and is often included in memory systems. The message is transmitted and
then checked at the receiving end for errors. For this purpose a circuit is required which
generates parity bit in the transmiter and check the receiving message for errors.
Circuit Diagram:
Fig 6.3: Circuit Diagram of 3-bit parity generator(Even parity)
Fig 6.4: Circuit Diagram of 4-Bit parity checker (Even Parity)
Truth Table of 3-bit Even parity Generator:
4
Input Output
A B C P
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
Truth Table of 4-bit Even parity Checker:
Procedure:
Input Output
4
A B C P Ch
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
4

and PIN14 = +5V.
Observation Table:
Parity Generator: Input Variable: A,B,C
Output Variable: P
Input Output
A B C P
4
Parity checker: Input Variable: A, B, C, P

Output Variable: Ch
Input Output
A B C P Ch
Calculation:
Parity Generator:
K Map Simplification:
Parity Checker:
4
K Map Simplification:
Boolean Expression: Parity Generator P =
Parity Checker Ch =
Result and Discussions: Parity bit is the most common error detecting code. It is used to
detect single bit error in the transmited binary information. For detecting of error extra bit
known as parity bit is attached to each code word to make the number of ones in the code
even(even parity) or odd p(odd parity. At the receiving end parity checker is used to detect single
bit error in the transmitted code word by regenerate the parity bit in the same fashion as parity
genarator and compare it with the parity bit transmitted The circuit diagram is very simple and
only uses an 7486 IC i.e Exor gate. Parity is used on communication links (e.g. Modem lines)
and is often included in memory systems..
Conclusion: 3-bit Parity Generator and 4-bit parity Checker has been designed using EXOR
gate and its truth table verified.
References:
Books :
URLs:
4
Lab tutorial
1) Even Parity Genertor circuit required:
a) EXOR gate
b) EXNOR gate
c) NOR gate
2) Even Parity Checker Circuit Required:
a) EXNOR gate
b) EXOR gate
c) NAND gate
3). Parity genartor and Checker is :
a) Code Convertor
b) Error Detection Code
c) Error Correction Code
d) None of above
4) Parity genartor and Checker detect :
a) 2-bit error
b) 1-bit Error
c) 3-bit error
d) 4-bit error
5) Odd Parity Genertor circuit required:
a) EXOR gate and EXNOR gate
b) EXNOR gate and NAND GATE
c) NOR gate and EXNOR gate
4

6) Odd Parity Checker Circuit Required:
a) EXNOR gate
b) EXOR gate
c) NAND gate

Ques1: What is the need of parity generator and parity checker ?
Ques2: Why can’t the parity method detect even number of error in transmitted
data ?
Ques3: Design 3-bit parity generator and 4-bit parity checker circuit for odd
parity?
Ques4: What is the difference between odd parity and even parity?
Ques 5: Distinguish between error correcting codes and error detecting codes?
4
Experiment: 7
Aim: To Design and verify the truth table of code conversion from BCD to Excess-3
Objective:
logic gates.
 Creation and observation of the excess 3 code representation sequence
 Creating the truth table of conversion functions from BCD to EXCESS 3
code
Apparatus Required:
 Digital ICs: 7404 :Hex Inverter
7408 :Quad 2 input AND
Theory:
Code Converters: A code converter is a combinational circuit that must be inserted between the
two systems, to make them compatible even though each uses different code for same
information. It means that a code converter is a code translator from one code to the other. The
code converter is used since to systems using two different codes but they need to use the same
information. So the code converter is the solution.
BCD Codes: Numeric codes represent numeric information i.e. only numbers as a series of 0’s
and 1’s. Numeric codes used to represent decimal digits are called Binary Coded Decimal (BCD)
codes. A BCD code is one, in which the digits of a decimal number are encoded-one at a time
into group of four binary digits. There are a large number of BCD codes in order to represent
decimal digits0, 1, 2 …9, it is necessary to use a sequence of at least four binary digits. Such a
sequence of binary digits which represents a decimal digit is called code word.
4
EXCESS 3 Codes: It is a non-weighted code. It is also a self-complementing BCD code used in

decimal arithmetic units. . The Excess-3 code for the decimal number is performed in the same
manner as BCD except that decimal number 3 is added to the each decimal unit before encoding
it to binary.
Circuit Diagram:
Fig 7.1: Circuit Diagram of BCD to EXCESS 3 code converter
Truth Table for BCD to Excess -3 Code Conversion:
5
INPUTS(BCD) OUTPUTS(Excess-3)
A B C D W X Y Z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 1 0 1 0 1
0 0 1 0 0 1 1 0
0 1 1 0 0 1 1 1
0 1 1 1 1 0 0 0
0 1 0 1 1 0 0 1
0 1 0 0 1 0 1 0
1 1 0 0 1 0 1 1
1 1 0 1 1 1 0 0
Eqautions:
Z=D
Y = CD+C’D’=CD(C+D)’
X = B’C+B’D+BC’D’= B’(C+D) +BC’D
W = B’(C+D) +B(C+D)’
Procedure :
and PIN14 = +5V.
5
Output Variable: W X Y Z
A B C D W X Y Z
Calculation:
For W:
For X:
52
For Y
For Z
Boolean Expression: W =
X =
Y=
Z=
Result and Discussions: Excess-3 code is a 4-bit unweighted code and can be obtained from
the corresponding value of BCD code by adding three to each coded number.Excess-3 code is
self complemnting in nature because 1’s complement of the coded number yields 9’s
complement of number itself.
Conclusion: BCD to Excess-3 code converter has been designed using basic logic gates and
its truth table verified.
References:
Books :
URLs:
5
Lab tutorial
1) Excess-3 code are:
a) cyclic codes
b) self complemantary codes
c) Weighted codes
d) None of above
2) BCD is:
a) Binary coded digit
b) Binary coded decimal
c) binary cyclic decimal
d) none of the above
3) The Excess-3 code for 0111 is:
a) 1010
b) 1011
c) 1000
d) 1001
4) The Excess-3 code of 1000 is:
a) 0111
b) 1011
c) 10101
d) 1100
5) The BCD of Excess-3 code 0100 is:
a) 0010
b) 0001
c) 0011
d) 0100
6) The weights in the BCD codes are :
5
a) 1,2,4,8
b) 8,4,2,1
c) 8,6,4,2
d) 2,4,6,8
Ques1: Why Excess-3 code is known as self complementary code?
Ques2: Design a combinational circuit which converts Excess-3 code into BCD?
Ques3: A combinational network has four inputs( A,B,C,D) and four outputs
(W.X,Y,Z).W X Y Z represents an excess-3 coded number whosevvalue equal te
number of 1’s at the input.Write down the minimum expresion for the outputs?
Ques4: Design a combinational circuit whose input is 8421 BCD number and
whose outputs is the 9’s complement of the input number.
Ques 5: Design a combinational circuit whose input is a three bit number and
whose output is the 1’s complement of the input number.
5
Experiment: 8
Aim: a) To the Truth Table of 4:1 Multiplexer using IC
74153
b) To the Truth Table of 1:4 Demultiplexer using IC 74139
Objective:
 To get familiar with the concept of multiplexing and demultiplexing
 To get familiar with MSI (medium scale integration) technology.
Apparatus Required:
 Digital ICs:74153:Dual 4:1 MUX
74139:Dual 1:4 DEMUX
Pin Diagram:
Fig 8.1:Pin diagram of dual 4:1 Mux (IC 74153)
5
Fig 8.2: Pin diagram of Dual 1:4 DEMUX (IC74139)
Theory:
Multiplexer: A data selector, more commonly called a Multiplexer, shortened to "Mux" or

"MPX", is combinational logic switching devices that operate like a very fast acting multiple
position rotary switches. They connect or control, multiple input lines called "channels"
consisting of either 2, 4, 8 or 16 individual inputs, one at a time to an output. Then the job of a
multiplexer is to allow multiple signals to share a single common output. For example, a single
8-channel multiplexer would connect one of its eight inputs to the single data output.
Ref: http://www.electronics-tutorials.ws/combination/comb_3.html
The Boolean expression for this 4-to-1 Multiplexer above with inputs I0 to I3 and data select lines
S0 ,S1 is given as:
5
Y = S0S1I0 + S0S1I1 + S0S1I2 + S0S1I3
Multiplexer Symbol:
Truth Table of 4:1 Mux(IC 74153)( Channel A) with Active low mode:
Inputs(Channel A) Select lines Output

Ea Iao Ia1 Ia2 Ia3 S0 S1 Za
1 × × × × × × 0
0 0 × × × 0 0 0
0 1 × × × 0 0 1
0 × 0 × × 0 1 0
0 × 1 × × 0 1 1
0 × × 0 × 1 0 0
0 × × 1 × 1 0 1
0 × × × 0 1 1 0
0 × × × 1 1 1 1
Demultiplexer: The data distributor, known more commonly as a Demultiplexer or "Demux", is
the exact opposite of the Multiplexer. The demultiplexer takes one single input data line and then
switches it to any one of a number of individual output lines one at a time. The demultiplexer
converts a serial data signal at the input to a parallel data at its output lines
1- to-4 Channel De-multiplexer
5
Ref: http://www.electronics-tutorials.ws/combination/comb_3.html
The Boolean expression for this 1-to-4 Demultiplexer above with outputs D 0 to D3 and data select
lines S0 , S1 is given as:
E = S0S1 D0 + S0S1 D1 + S0S1 D2 + S0S1 D3
The function of the Demultiplexer is to switch one common data input line to any one of the 4
output data lines. Some standard demultiplexer IC´s also have an "enable output" input pin
which disables or prevents the input from being passed to the selected output. Also some have
latches built into their outputs to maintain the output logic level after the address inputs have
been changed. However, in standard decoder type circuits the address input will determine which
single data output will have the same value as the data input with all other data outputs having
the value of logic "0".
Truth table of 1:4 Demux(IC 74139) with Active low mode :
Input(Channel A) Output
Ea S0 S1 D0 D1 D2 D3
1 × × 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
5
0 1 1 1 1 1 0
Procedure:
and PIN14 = +5V.
Observation Table:
Multiplexer:: Input Variable: Ea, Ia0, Ia1, Ia2, Ia3
Selecct lines: S0, S1
Output Variable: Za
Inputs(Channel A) Select lines Output

Ea Iao Ia1 Ia2 Ia3 S0 S1 Za
6
Demultiplexer: Input Variable: Ea, S0, S1

Output Variable: D0, D1, D2, D3
Input(Channel A) Output
Ea S0 S1 D0 D1 D2 D3
Result and Discussions:Multiplexer and demultiplexer help in reducing the cost of

transmission of digital signals.Logic design is simple and boolean expression need not be
simplified.Mux and Demux acts as rotary switches. Multiplexers are used as one method of
reducing the number of logic gates required in a circuit or when a single data line is required to
carry two or more different digital signals i.e it converts parallel data into serial data and also
used for data selection.The demultiplexer converts a serial data signal at the input to a parallel
data at its output lines and used for data distribution.Both are available as Ics.
Conclusion: The truth table od 4:1 MUX using IC 74153 and 1:4 DEMUX using IC74139
has been verified.
References:
Books :
6

URLs:
1. http://www.electronics-tutorials.ws/combination/comb_3.html
Lab tutorial
1) The IC number of Dual 4:1 MUX is
a) 74152
b) 74153
c) 74139
2) IC number of Dual 1:4 DEMUX is
a) 74153
b) 74139
c) 74138
3). Multiplexer is also known as :
a) Data selector
b) Data Distributor
c) Data Collector
d) None of above
4) Demultiplexer is also known as:
a) Data selector
b) Data Distributor
c) Data Collector
d) None of above
6
5) Multiplexer converts:
a) Parallel into serial data
b) Serial into parallel data
c) Serial into Serial data
d) Parallel into parallel data
6) Demultiplexer converts:
a) Parallel into serial data
b) Serial into parallel data
c) Serial into Serial data
d) Parallel into parallel data
7) Decoder with enable input is:
a) Encoder
b) Demultiplexer
c) Multiplexer
d) Display Device

Ques1: Differentiate between Multiplexer and demultiplexer?
Ques2: What is the role of select lines in multiplexer?
Ques3: How can a decoder be used as a demultiplexer?
Ques4: What are the applications of MUX and DEMUX?
Ques 5: What are cthe advantages of using multiplexer as a logic function

generator?
6
Experiment: 9
Aim: To design the 8:1 MUX using two 4:1 MUX .
Objective:
 To get familiar with the concept of multiplexing .
 To get familiar with MSI (medium scale integration) technology.
 To get familiar with the expansion of multiplexing using standard IC
packages.
Apparatus Required:
 Digital ICs:74153:Dual 4:1 MUX
7432: Quad 2 input OR gate
7404 : Hex inverter
Pin Diagram:
Fig 9.1:Pin diagram of 8:1 Mux using two 4:1 Mux
Theory:
6
Multiplexer: A data selector, more commonly called a Multiplexer, shortened to "Mux" or

"MPX", is combinational logic switching devices that operate like a very fast acting multiple
position rotary switches. They connect or control, multiple input lines called "channels"
consisting of either 2, 4, 8 or 16 individual inputs, one at a time to an output. Then the job of a
multiplexer is to allow multiple signals to share a single common output. A single multiplexer as
Ic is 4:1, i.e., it can handle a maximum of 4 inputs.when te number of inputs is more then 4, a
multiplexer tree can be used ,also known as multiplexer stack.
Fig 9.2:Circuit of 8:1 Mux using dual 4:1 Mux
Truth Table of 8:1 Mux Using Dual 4:1 Mux
6
Select Lines Inputs Output

Ea S0 S1 Io I1 I2 I3 I4 I5 I6 I7 Za Zb Y
0 0 0 0 × × × × × × × 0 × 0
0 0 0 1 × × × × × × × 1 × 1
0 0 1 × 0 × × × × × × 0 × 0
0 0 1 × 1 × × × × × × 1 × 1
0 1 0 × × 0 × × × × × 0 × 0
0 1 0 × × 1 × × × × × 1 × 1
0 1 1 × × × 0 × × × × 0 × 0
0 1 1 × × × 1 × × × × 1 × 1
1 0 0 × × × 0 × × × × 0 0
1 0 0 × × × × 1 × × × × 1 1
1 0 1 × × × × × 0 × × × 0 0
1 0 1 × × × × × 1 × × × 1 1
1 1 0 × × × × × × 0 × × 0 0
1 1 0 × × × × × × 1 × × 1 1
1 1 1 × × × × × × × 0 × 0 0
1 1 1 × × × × × × × 1 × 1 1
Procedure:
and PIN14 = +5V.
6
Observation Table:
Multiplexer:: Input Variable: I0, I1, I2, I3, I4, I5, I6,I7
Selecct lines: Ea,S0, S1
Output Variable: Za, Za, Y,
Select Lines Inputs Output

Ea S0 S1 Io I1 I2 I3 I4 I5 I6 I7 Za Zb Y
Result and Discussions:Multiplexer help in reducing the cost of transmission of digital

signals.Logic design is simple and boolean expression need not be simplified.Mux acts as rotary
6
switches. Multiplexers are used as one method of reducing the number of logic gates required in
a circuit or when a single data line is required to carry two or more different digital signals i.e it
converts parallel data into serial data and also used for data selection.the special pins are
provided to expand the multiplexer capacity.The manufacturer provides Enable inputs to allow
for expansion to increase the multiplexer capacity.
Conclusion: The truth table of 8:1 MUX using IC 74153 has been verified.
References:
Books :
1. M. Morris Mano – Digital Design – PHI (3rd Edition)
2. R.P. Jain – Modern Digital Electronics – TMH
3. Tocci – Digital Systems – (PHI)
4. Morris Mano – Digital logic and computer design (PHI)
URLs:
1. http://www.electronics-tutorials.ws/combination/comb_3.html
Lab tutorial
1) A 4:1 multiplexer requires.......................Data select lines:
a) 1
b) 2
c) 3
d) 4
2) A 16:1 multiplexer requires.......................Data select lines:

a) 5
6
b) 2
c) 3
d) 4
3) Two 16:1 and one 2:1 multiplexer can be connected to form a
a) 16:1 multiplexer
b) 32:1 multiplexer
c) 64:1 multiplexer
d) None of above
4) In a Mux used as logic function generator,…..............Lines are used as input lines
a) input
b) select
c) output
d) enable
5) Two 4:1 and one 2:1 multiplexer can be connected to form a
a) 8:1 multiplexer
b) 16:1 multiplexer
c) 64:1 multiplexer
d) None of above
6) IC 74150 is a.......input mux:
a) 8
b) 16
c) 32
d) 4

Ques1: What is multiplexer tree?
Ques2: What is the need of multiplexer tree?
6
Ques3: Can a 4 variable input function be realized using 8:1 multiplexer? If yes
explain procedure for the same.
Ques4: Implement 16:1 mux using two 8:1 mux and a basic logic gate.
7
Experiment No. 10
Aim: To Design and verify the truth table of J K Flip flop using IC 7473.
Objective:
a. To understand the principle of operation of sequential circuit
b. To differentiate between combinational circuit and sequential circuit.
c. To get familiar with basic Flip flops
d. Determine the logic operation of JK flip flops.
e. Connect and observe the state transition of JK as connected to
the clock generator circuit.
Apparatus Required:
 Digital ICs: 7473:Dual master Slave J K Flip flop
Pin Diagram:
Fig 10.1: Pin Diagram of JK Flip Flop
Theory :
Sequential Logic circuits: In digital circuit theory, sequential logic is a type of logic circuit
whose output depends not only on the present input but also on the history of the input. This is in
contrast to combinational logic, whose output is a function of, and only of, the present input. In
other words, sequential logic has state (memory) while combinational logic does not.The
memory elements are devices capable of storing binary info. The binary info stored in the
memory elements at any given time defines the state of the sequential circuit. The input and the
7
present state of the memory element determines the output. Memory elements next state is also a
function of external inputs and present state. A sequential circuit is specified by a time sequence
of inputs, outputs, and internal states.
Flip Flop:. In electronics, a flip-flop is a circuit that has two stable states and can be used to
store state information. The circuit can be made to change state by signals applied to one or more
control inputs and will have one or two outputs.Flip-flops and latches are used as data storage
elements. There are four types of flip flops. These are SR, D, JK and T. On this experiment we
will explore the operation of JK flip flop.
JK flip flop: JK flip flop is considered as the universal flip flop. When configured in various
ways, it is capable of operating like most other types of flip flop.A JK flip-flop is a refinement of
the SR flip-flop in that the indeterminate state of the SR type is defined in the JK type. Inputs J
and K behave like inputs S and R to set and clear the flip-flop. When logic 1 inputs are applied to
both J and K simultaneously, the flip-flop switches to its complement state, ie., if Q=1, it
switches to Q=0 and vice versa. In that way it is like a toggle.A clocked JK flip-flop is
shown below. Output Q is ANDed with K and CLK inputs so that the flip-flop is cleared during
a clock pulse only if Q was previously 1. Similarly, ouput Q’ is ANDed with J and CLK inputs
so that the flip-flop is set with a clock pulse only if Q’ was previously 1.
Fig 10.2: Circuit Diagram of JK Flip Flop
Function Table of JK Flip Flop:

7
Clock Inputs Outputs

CLK J K Q
× × × Q (PS) (PS)
1 0 0 O(PS) 1(PS)
1 0 1 0 1
1 1 0 1 0
1 1 1 0( )(Toggle) 1 (Q) (Toggle)
Procedure:

and PIN14 = +5V.
according to circuit diagram.
breadboard
Observation Table:
JK Flip flop: Input Variable: CLR, CLK, J, K
Output Variable: Q,
Clear Clock Inputs Outputs
CLK J K Q
Result and Analysis: Flip-flops (FFs) are devices used in the digital field for a variety of
purposes. Flip-flops are a fundamental building block of digital electronics systems used in
7
computers, communications, and many other types of systems . In JK flip-flop, the letter J is for
set and the letter K is for clear. When logic 1 inputs are applied to both J and K simultaneously,
the flip-flop switches to its complement state, ie., if Q=1, it switches to Q=0 and vice versa. Flip-
flops and latches are used as data storage elements. Such data storage can be used for storage of
state, and such a circuit is described as sequential logic. When used in a finite-state machine, the
output and next state depend not only on its current input, but also on its current state (and hence,
previous inputs.) It can also be used for counting of pulses, and for synchronizing variably-timed
input signals to some reference timing signal.
CONCLUSION : The function table of JK flip flop using IC 7473 as been verified.
Books:

2. M. Morris Mano - Digital Design - PHI (3rd Edition
URLS:
2) http://www.electronics-tutorials.ws.html
3)
ode129.html
5)
Lab Tutorials:
7
1. Flip flop is a
a) Memory element
b) Combinational circuit
c) Logic gate
d) None of above
2. Flip flop has ……states:
a) 1
b) 2
c) 3
d) 4
3. Ic number of Jk Flip flop is:
a) 7450
b) 7453
c) 7451
d) 7452
4. Which of the following is susceptible to race condition:
a) JK Flip flop
b) RS Flip flop
c) D Flip flop
d) none of these
5. In level clocking the output can change:
a) on rising edge of clock cycle
b) on rising edge of clock cycle
c) during entire half cycle of the clock
d) none of these
6. In a JK Master slave flip flop:
a) both master and slave are positively clocked.
b) both master and slave are positively clocked
c) master is positively clocked and slave are negatively clocked
d) master is negatively clocked and slave are positively clocked
7. A Flip Flop can be used to redue the frequency by:
a) 4
b) 2
c) 6
8. Flip flop and latches are..................logic elements
a) monostable
b) bistable
7
c) tristable
d) none of above
Short Answer Questions:
Ques1: What is the differnce between latch and flip flop?

Ques2: Differentiate between truth table and excitation table?
Ques3: What is race around condition? How to overcome it?
Ques4: What are the applications of Flip flop?
Ques5: What are the uses of asynchronous inputs of flip flop?
7

65 Mohit Tiwari IT 2 STLD File

Uploaded by

Document Information

Original Description:

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

65 Mohit Tiwari IT 2 STLD File

Uploaded by

Copyright:

Available Formats

Digital Circuit and System Lab Manual

Appararus/ Equipment Required:

Not Gate: IC 7404(HEX Inverter)

AND Gate: IC 7408

NAND Gate: IC 7400

NOR Gate: IC 7402

EXOR Gate: IC 7486

OR gate : A multi-input circuit in which the output is 1 when any input is 1.

NOR gate: OR followed by inverter. It is also known as universal gate.The symbolic

Observation Table: LED ON(RED light): Logic 1

S.No Input(A) Input(B) Output Output Output Output Output Output

Results and Analysis:

1. The number of level in a digital signal is:

21. Which statement is verify NAND gate:

1) What are logis gates?

Fig 2.1: Pin Diagram Of Half Adder

Fig 2.2:Pin diagram of Full adder

Fig 2.3:Circuit Diagram Of Half Adder Truth Table

F ull A d d el a d d a logical circuit that performs an addition operation on three binary

Fig 2.4:Circuit Diagram Of Full Adder Truth Table

1. Collect the components necessary to accomplish this experiment.

Full adder: Input Variable: A ,B,Ci

Boolean expression: Sum:

Boolean Expression: SUM:

Result and Analysis:Verified the truth table as follows.

2. R.P. Jain - Modern Digital Electronics – TMH

1. Half Adder adds:

Short Answer Type questions:

Ques1: What is truth table and boolean expression?

Fig 3.1: Pin Diagram of Half Subtractor

Fig 3.2: Pin Diagram of Full subtarctor

Fig 3.3: Circuit Diagram of Half Subtractor

3 inputs denote minuend,subtrahend and previous borrow, respectively.The 2 outputs are

Fig 3.4: Circuit Diagram of Full Subtractor

1. Collect the components necessary to accomplish this experiment.

Full adder: Input Variable: A B BORin D BORout

Boolean expression: Difference:

Boolean Expression: : Difference:

Result and Analysis:Verified the truth table as follows.

4. Morris Mano - Digital logic and computer design (PHI)

1. Half Subtractor subtracts:

5. The expression for borrow of A, B in the half subtractor is given by:

Short Answer Questions:

Ques1: Implement half Subtractor with NAND Gate only?

Advantages: Higher speed or smaller code.

Fig 4.2: Circuit Diagram of Binary to Gray Code Converter

Short Answer types question:

Ques1: What are the gray codes?

Ques2: What are the properties of Gray codes?

Ques3: What is the advantages and application of Gray codes?

Ques4: Convert 1100 into binary code?

Ques 5: Convert 1101 into Gray Code?

Advantages: Higher speed or smaller code.

Fig 5.2: Circuit Diagram of Binary to Gray Code Converter

Truth Table of Binary to Gray Code Converter:

5. Malvino/Leach : Digital Principles and Applications

Short Answer types question:

Ques1: What are code converters?

Ques2: What is the need of code converter?

Ques3: Design 3-bit gray to binary code converter ?

Ques4: Convert 1100 into gray code?

Ques 5: Convert 1101 into binary Code?

Fig 6.3: Circuit Diagram of 3-bit parity generator(Even parity)