ae LINEAR R INTEGRA Teo D CIRCUITS wren | “7 aa 42 43 44 45 46 47 48 49 4.10 an 412 413 ana 445 4.16 4a7 4.18 419 420 421 422 Non LINEAR WAVE sHA TIMERS AND ptt ping ciRcutTs, — Clipper Circuit Classification of Chpper Series Diode Cipper Ci ‘Shunt Diode Clipper Circuit Biased Shun! Diode Clipper Double Clipper of Two Level Two Level Clipper Using Zener Diodes Clamper' Negative Vollaye Clamper Circuit Biased Clamper Applications of Clippers & Clampers ‘Sweep Circuits ‘Sweep Waveform & Important Definitions ‘Sweep Voltage Generation Bootstrap Sweep Circuit Miter Sweep Circuit Miller Integrator Using Op-Amp Current Time Base Generator Distinguish Between Voltage Sweep & Current Sweep Generators, Applications of Sweep Circuits ‘Mutivibrator Transistor Astable Mutivibrator 435 436 437 438 Astabie Ms Monostabie Bistable Applicaton of Mut IC 555 Menostable Mu 1C'555 Astable Muti Phase Locked Loop (PLL) Functional Block Description of PLL Type LM - 565, {Lock Range of PLL Capture Range of PLL Applications of PLL Frequercy Mut FM Demodulator Using PLL Voltage Controlled Oscillator LM 568 using PLLNS Ew I (mene HH CANO cH 4.0 INTRODUCTION mim is generated by multivibra, or gar multebratr Is used to produce singe tiny ered ne 2 applications monolithic devices aller advonngs ‘tired. Further IC mer provides mynog 6 ley he an triggering signal. In such #se of fewer circuit connections re class of timer circuits which uti Performance. There also exists a gates for the realisation of waveform generation 4 Phase locked loop (PLL) is basically a closed loop feedback system. Th, action of PLL is to lock or synchronise The implementation of PLL with complexity. For thi the frequency of a controlled oscillate, to that of an incoming signal. discrey components involves circuits of considerable cost ar reason, the use of PLL in the past has been limited to specialised measurement The development of integrated circuits PLL now makes it highly economica, as well as reliable. In this chapter we will study the application of 555 IC time, and description of phase locked loop. 4.1 CLIPPER CIRCUIT The clipper circuit is a common form of the nonlinear wave shaping circuit. Either i restricts the amplitude of a voltage waveform to some finite value or it cutoff the positive or negative peak of a waveform at some finite value. CLASSIFICATION OF CLIPPER CIRCUITS 4.2 The clipper circuits are classified according to the active element used. They ate |. Semiconductor diode clipper 2. Transistor clipper. The diode clippers are further classified as 1. Series diode clipper 2. Shunt diode clipper The clippers are also classified as 1. Un biased clipper 2 Biased clippervon WOT gLIPPER CIRCUIT 4 7h" og plo G i" “ene yeferred 10 as a series diode clipper circuit. lt Operates on the fol 3 Fig = ‘the wn «current ow through the resistor there is an output voltage ac : oltage across ther® the diode is forward biased, and hence acting as a closed swit + flow through the resistor. Therefore the positive half cycle vv biased the diode, hence the applied voltage effectively appears is ere th wine for spe Svetn o 7 ‘ v (b) | Output Waveform | FIG 4.1 : Positive Series Diode Clipper (a) Circuit (b) Input Waveforms During the negative half-cycle, the diode reverse biased and acts as an open switch, hence no current flow through resistor R and in turn there is no voltage drop across it. The resultant output voltage waveform is also shown in Fig. 4. 2. The reverse is happened if the diode is reverse as shown in Fig. 4.2— oO | uve nteceaten ca Ouspat Waveform (b) Input Ovrpat Waveforms FIG 42 : Negative Series Diode Clipper SHUNT DIODE CLIPPER CIRCUIT hunt 4.4 referred to as 2 per. In this circuit. for ele diode conducts positive half hen the diode conducts. it acts 25 hence -¥ hort circuit to the output voltage is zero. For negative output he diode does notave Shapine Circutte, Timers and Ph san bt yt ‘J : hunt DIODE CLIPPER iy [er Bie unt diode clipper is shown in Fig. 4.4. In th 5 te piase oe the output voltage equals the battery uhen the dlode jet sed ‘ne output voltage equals the inp Nher r wets Pal source has zero resistance, the batt edt apt voltage equals the input volta pene OF gative halfeycle r poring re ignal voltage | 19 Se aa inp Le respect t© the battery me : a voltage Eisof vA) Y 45 aiding iE The battery «& valtad® To reverse pias voltage the will equal the input o e the negativ| itive halt-eycle of the Sn he signal voltage 15 in series r ‘uith respect to the battery Frage E- The bias applied across the Spode equals the difference between the signal voltage and the battery voltage 2" ty of the v 4 has the polarit larger voltage. Therefore the output als the input when the input ls squalto orless than the battery voltage E When the input is greater than the| ~ rattery voltage the diode is forward pased, hence the output voltage equals the battery voltage E. The eer resultant output voltage is also shown ee ee : nFig. 4.4 DOUBLE CLIPPER OR TWO LEVEL CLIPPER Int 7 he circuit of Fig. 4.5 during the positive halfcycle of tage E;. The bies 277 and has the inpu the ing nas opposing with respect to the battery is fe ae aes difference between the signal voltage eae ae erciore the output equals the input when ay tage E;. When the input is greater * rd hence the output voltage equals the Daf SRP soe ees cae a ITTope: Wriefrs oy sages rrp Berets FIG 45 : Double Clipper 4.7 Two LEVEL CLIPPER USING ZENER DIODES The ceeut of Fig 4.6 5 simplified form vas of tac level biased cipper creat using “e z t a z, 7 Vz. \ zener diodes. in tis cect zener Goes to back. See are connected in series back During positive half cycle zener Z, 5 reverse biased and Z's forward tnset ‘As the input signal amplitude is increasing, the reverse bias on Z; isthe then the input nonconducting state. Wi signal amplitude exceeds Vzr Zi conducts and the output voltage wil be maintained at Vzi ony Further during Vz: oe the eye Viz ‘ Outpt waveform (») leper Outpet Waveforms amplitude & zener diode 2; ”vaops conduct This mercer ——— iene be eae ree"000 there, lly ecause it clamps the esade Voltage reference lage te, from wh gs The circuit is a a ledade Ry WO e the input -V with reference : anon 7 iC Sfround. Let the diode D is acting (©) Crem an ideal switch. Wit jorward biases. Hence the C ch this voltage capacitor cm ts +E. The bias of the diode arty tme is the algebraic sum of the reput voltage and the voltage across the capacitor. Hence the diode D is reverse biased by -V-E. the output voltage of the circuit. At t3 time the input is -V with reference to ground The input voltage and the voltage across the capacitor is series aiding Hence the output is -2V | 0 -V. Atty time Oupur Waveforn (b) Input Ourpur Waseforms Ii the diode is reversed, we get positive voltage clamper circuit | The above discussion is true, and get | (e) Cac wih Resist in Our camped output exactly at OV when| the diode is ideal. But practical FIG 4.7 : Negative Clamper if Sdodes are not deal. Therefore the ourput snot clamped exact t0-VToget annie in practical circuits, a resistor introduced in parallel to diode as shown in Fia.47(0) a4.10 BIASED CLAMPER Refer to Fig. 4.8 which illustrates a biased clamper circuit. In this circuit the output voltage is clamped to some value other than zero. A fixed biased voltage must be placed in series with parallel combination of resistor R and diode D in order to | clamp a signal voltage to some value other than zero The output voltage of the biased clamper circuit equals the algebraic sum of the signal voltage and the voltage across the capacitor Therefore the polarity and amplitude of the voltage to which the capacitor will charge must be established in order to ascertain the output voltage. When the input is -V, it is in series Output Waveform aiding with respect to the bias voltage. (2) tape Output Waseforms E. The polarity of the sum of these FIG 4.8 : Biased Clamper By voltage is correct to forward bias the diode. Hence the capacitor charges to the sum of these two voltage V + E with the polarity indicated in Fig, 4.8, When the diode is forward biased the output voltage equals the bias voltage E. When the diode is reverse biased the output voltage equals the algebraic sum of the input voltage and the voltage across the capacitor. Thus, when a fixed voltage is established 2cr08s capacitor C, the input voltage is + V at tg time and this input voltage isin series aiding with respect to the voltage across the capacitor. The polatity of this voltage reverse biases diode D. Hence the output voltage is 2V + E at tig time. At t,y time the input voltage is -V is in series opposing the V + E across the capacitor. The output voltage is the algebraic sum of the two ie. + E 4.11 APPLICATIONS OF CLIPPERS AND CLAMPERS Clippers : 1. Two level clipper can be used as square wave generator. 2. Clippers are used to remove unwanted portions like noise accumulated on peaks ete of waveforms.» vy Wave Sha? a, Timers and Pu pine pee yin TV, Receivers to separate pulses from er ey is mposite vide ve \ i far" igo used i” pulse position modulators ip? a1s0 & ON ate? lampers are used to restore the d.c into any He os Co of TV. receivers 7 ; irc put waveform for at p! ‘ oo jhown below for the 2 of V=10 ve voltage of V = 10 sin / | gs the Input and Output the Fig. 49 as | FiIG4s ward biases when the Je f0 ‘the a spe is greater than —2 Vo 0 an - input 90 Mig -2 V. For voltage less Jd / and OUP, from -2Vto-10V [ \ tna gde reverse biases and the a the a / output is same as input. ~ ieee nw FIG 4.10: Output Wave Forms Draw the Output waveform for the circuit shown below for the | a.c. Input voltage of V = 20 Sin 100 xt. Y FIG 4.11:[uean micceney g : CU Solution : 4 the Input and Output \ waveform for the circuit shown in Fig wy / 4.11 For positive hall cyele the diode of / \ D. e biases where as diode D; sa | / ative hall . L ; reverses upto +5 V For ne, eyele the diode D; is forward bi ae for input voltage from 0 to — 5 V. The : diode Dp is forward biases for input ‘ ’ i voltage form — 10 V to — 20 V Vi Ny io Output Waveform FIG 4.12 : Output Waveforms ese - Draw the Output waveform for the circuit shown for the a.c. Input voltage of V = 25 sin 300t. n. The Output is shifted -20V down words. That means the zero refe- rence voltage shifted 20V upwards. neue lus ‘Output Waveform eee jtivibrator fa Mult ag 4.14 : Output Waveforms of arave Shaping Circus, Timers and Pid a voltage or current wave shape which roduce ith reference to time. These cire ny Py a tinct rate wi uits a ov “id ‘base generators The circuits which produces a linear volta vine i me base generator, one which produces a linear “ - ie base generator IN practice, the sues cet ae a aoc rage wovestape linear, is called a voltage time base generator Scce, one we also called 25 ° linear ramp generators waveroaM ANE AND IMPORTANT DEFINITIONS: c wel eP yeep waverorrn shown in Fig. 4.15 (a) where as practeal wave sre i300! 4.15 (0) pow? in vieude # :Itis defined as the modulus of the difference between wee? AI tthe time equal to sweep duration t, and the initial Tract L ue pol {a) Ideal ee _) Feat ———___—_—_ FIG 4.15 : Sweep Waveform 2, Sweep Interval : It is defined as the period of time from the instant the voltage starts to raise to the instant it starts to fall. It is abbreviated as t,. Itis defined as the duration in which the sweep voltage | 4, Retrace or Flyback Interval : For ideal sweep waveform t, = 0 decreases to initial value. It is represented as ty. 4. Sweep Speed : It is defined as the rate of change of sweep voltage with time. For an ideal ramp waveform, the sweep speed is constant. s : weep Speed Error : It is defined as the ratio of the difference of the slopes at the beginning and ending of the slope. ——~— SShe initial portion of a voltage | { | | eration of sweep (9) Creu for Ne Generation of Sweep Vo hence capacitor C charges through | y,. | i oe BL teed ci, a, : Switch $ if moved to position 2, at th time, the capacitor starts to discharge | from V volts toward 0 volt. The discharge path is through the closed switch S and through resistor Res. : Output Voltage Sweep Waveforms. Normally, resistor Res << Ry, hence | capacitor C has time to discharge | completely as shown in Fig. 4.16 (b) If resistor Res = 0 the capacitor can discharge in practically zero time. If the capacitor is allowed to start charging again as soon as it has discharged, the me resultant sawtooth voltage waveform is ___(€) Ouput Votage Sweep Wavetorms = generated as shown in Fig. 4.16 (c). FIG 4.16 4.15 BOOTSTRAP SWEEP CIRCUIT Fig. 4.17 (a) shows the circuit diagram of a bootstrap time base generator using emilter follower as an amplifier. For excellent linearity the e er follower gain should be very close to unity. To achieve this it is necessary to use a transistor with very high value of fsave shal pings Cirewits, Tim y wer i wers and PLL t" . / ' circu _——_ 7 e— riG Tne Base Genera FIG 4.17 : Boo! 7 tstrap Time Base Gener tor aration of the circult assume that i initially s switch $ OFF state- load resistor Ri. The i appro: Se C, is charged to Joltage across the timing « : i . ing capacitor is also ze ne OP: he pacitor C starts charging by th harging ging by 2 5 opens. the ca ss cal pacitor C appears at the ba se and con wher € yoltage acre: Tro increase. Any change in output voltage a yoltage ® capacitor C1 to point P such that th acros oe 5 the current determining resistor R ane or Ris hel mnt P is Voc and as soon as switch is fateh is opened. the em drop the voltage and the necessary char: p the volt id the nece aint y char oltage at PO" sistor Ry harged 01 m\ ged feedback capacitor Cy is assu sumed to bi to be la: increases the re: reseed or eC ge across it constant ep the volta’ rresuvep speed is given by Sweep speed = a RC Sweep speed =use of the finite value of R, and gain A is not exactly unity The sweep «| V, = sweep vot jon of the sweep. Cj must recharge through the emitter fol) | mpedance in series - 4.16 MILLER SWEEP CIRCUIT | output rcuit of Mil + voltage sweep generator by using nega, Here the current lowing inthe timing capacitor Cis kept consis | ; 1 To understand the operation, let us assume the switch S to be ideal : — | iu Ma Rewace Tree | (2) Croat (©) Output Wave Form FIG 4.18 : Miller Sweep Generator Normally switch S remains closed and transistor T; is OFF. The timing capacitor C is charged to voltage Voc through the resistor Rc and switch S. At time 1 = 0, switch $ opens and the base-emitter voltage is coupled via capacitor C to the output voltage at 1 = +0 as shown in Fig. 4.18 (b). But the conduction through transistor T, causes decrease in voltage Vez of he transistor. This decrease in Vc¢ is coupled to the base terminal via capacitor C thereby preventing the emitter base junction of transistor T; from being heavily biased. Thus current i and voltage Vg¢ remain fairly constant. If weam linearly and harges se is given by rim tis 282 19 ¢ em y where es * e wher a given output voliage level, the slope ercr can be improw -qhus f0F ry large value. When the switch S is again close: Jewgned 10 have © ve . RoR, ‘ tof C| | withthe time const Rook aise! INTEGRATOR USING OP-AMP ile integrator circuit using op-emp is shown in Fig. 37 (a) and its equivalent The miler 9 1) ee ut MILLER and A the open circuit voltage gain.) The operation of the circuit is a that initially the capacitor is uncharged If we neglect Ro and close the su \#) will be zero at 0° since the capacitor voltage was zero before the Swita [unene Wey and it cannot change instantaneously and will rise expoy ra AV, with atime constant R'C , where VR, RR | i R L mpi om Thus the ouput waveform vo (0&8 a shmple exponential wth hy OxUr Soy starting at ze10 A RC (a¥ t “Alri JRC up tt) » WRC << The slope error in this case is 0 (1) | es (oiller) = ia, where ug (T,) = sweep amplitude ron wy (0) eg (mille : [ ® |, A (RvR) |' ug (F,) {14 B/R, or ester, = | Thus, for a given output voltage level, the slope error can be improved, since |Al an be designed to have a very large value, If an operational amplifier is used, e, = ()aswe would expect since the integration of a step yields a ramp. 4.18 CURRENT TIME BASE GENERATOR | A simple current sweep generator is shown in Fig. 4.20 (a) associated wal shown in Fig, 4.20 (b). ts explanation is as follows : Initially the transistor en because of reverse bias voltage V, on emitter base junction. Thus Vce ue | 0. The switch is turned ON, by applying a base drive v(t) = ¥ eel through the inductor because diode D is reverse biased. The curre Voc +Rsc exponentially 0 a target value of| yarrer [ss a ay | {a) Circuit (©) (0) Ingut Waveform | (i) Sweep Current Wavetor (ii) Collector Voltage Wavetor FIG 20 : Current Time Base Generator Where Ry, = Coil resistance Rsc. = transistor saturation resistance ‘The current growth is governed by the following equation during the sweep where t R, + Rsc Thus if t << Ts <~— | shown in Fig. 4.17. In the absence of trigger input, the timing capacitor C is| held in the discharged state. In this state | the output is Low. The d.c. level at the ; Thres! | nota], trigger terminal should be held at a value above the threshold level of the. lower comparator which is Vec/3. This can be done by connecting a resistor divider network at the trigger terminal When the negative going trigger pulse is applied at trigger terminal and its voltage passes through Vcc/3. Thus, the flip flop is set upon triggering i.e., @ = Oand FIG 4.17 : 555 IC Monostable Mutivibrt transistor T; becomes OFF. ing cycle begins i.e, capacitor C charges up exponential h the time constant R C. The charging up expression is wy ly through? Therefore, the timi towards Vcc wit etlRC) V = Vec (1 where V is the voltage at any time ¢. is applied to the threshold terminal. Hence, when the voltage e upper comparator 2 Vec'3 itor dischars* The voltage across C i ches the threshold level of th across the capacitor real ° = 1. This makes the transistor T, ONand the eae, a Jeted. Once the circuit is tt is com ration of" flip flop is reseti.e, @ d and the timing cycle is comp! he timing cycle er ope! rapidly towards groun: it is insensitive to further triggering pulses until t ig cyc! triggering pulse width must be less than the timin: ing the timer, The timing cycle may be interrupted by connecting th reve This turns transistor T, ON and the capacitor is P!Circuits Him suncar wave shonin ale vegsion tis shown thatthe bre Tof er pe above discus’ n be [Port oe 10 chats? ey ae ito’ . nea a gal vce c : pe ee 7 = RC log T= 11RC g period can be varied the monostable timin ‘ai. The output P fo the control terminal ASTABLE MI LTIVIBRATOR : erator using 1.059 (eee ave igshown in Fig. 4.18. During the charging up period transistor Ty is held open by the fip-flop and the capacitor charges through the series connected resistors. a and Rp. When the voltage across the capacitor reaches the reference level of the upper comparator 2 Vcc/3, the comparator changes the state of the flip- flop and this terms the transistor T ONn.| °F The capacitor discharges through resistor oe Rg until its voltage reaches the reference 430 1c 555 The astable mult - ofthe lower comparator Vcc'S. Ths _FIG4.18: 85510 ‘stable Mutvibrator mmparator changes the state of the fip-lop again. which in tum makes the transi T, OFF and the cycle repeats. The ie charging time of the cay rcitor is determined by Vee ~ Vee 3. Ty = C(Rq+ Re) loge Yonb Vee 3 oe) stor The abo starts rite oe (4) immediately follows from the fact that the charging of capacitor ‘cc/3 instead of zero. Further the charging continues upto 2 Vec/3, alter -nplifies to which thy e uy iPper comparator changes state. The equation (4) si a[users intecenre == Ty = C (Ry +R) loge un = 07 (Ry + Rel C i 3 towards zero volts, 1s from 2 Vec Hence the equation The capacitor dischar . period Ty is determined by the on Ty = CRp loge G- in Equation (6) Ra is not present because capacitor discharges only thray This equation can be further simplified to Tp = 0.7 RC Ugh Ry The total period is, therefore. T = T+ T2207 (Ra +2Re)C The charging and discharging intervals are different by 0.7 Rg C. 4.31 PHASE LOCKED LOOP (PLL) A phase locked loop (PLL) is basically a closed loop feedback system. The acio action « PLL is to lock or synchronise the frequency of a controlled oscillator to tha ‘oming signal. Basically PLL consists of three functional blocks. inc Y of an 1. Phase detector | 2. Voltage controlled oscillator (VCO) | 3. Low pass filter The basic loop may also contain an amplifier | 4 0urpus voltage FIG 4.19 : Block Diagram of Basic PLL Block diagram of basic PLL is shown in Fig. 4.19. The phase detector exhibits a multiple characteristics. With no input signal applied to the PLL, the output from the phase cece ie {error voltage applied as the control signal to V.C.O is also 28 anditey oe a at its free running frequency fo. This frequency is referred to as Spies ae input signal is applied to the loop the phase detector produces ‘a! which contains components as the sum and difference frequencies ef + fond i oF s+ foand f, ~ fo. ffs significantly different from f, then both components do n°!Timers and PLL uated. Unde er, and hence. are a w pass fill anged and the loop does not acquire 2 lock -o is note ney © alues such that the / froquencd f has ves se tat the regen) sign? ey pass fier, then thi component am f 4 ate eo eee the VCO frequency ‘0 v2! signal I quency aifference between f, and f = sulficie a a fete loop causes the VCO 1057 hrronize or Tock’ with ea the VO Frequency IS ‘dentical to that of the input signa! rea direct voltage er magnitude proportional 0 cosi) where 0 18 he between the Put signal and the VCO signal, The action © ifr on just that value which is required 10 a a - ge the frequency of the VCO from f to chan: fagnal. This action allows the PLL to ‘track any fr Jock has been acquired generate the dc contro e runni im of LM - 565 PLL is shown Fig. 4.20 (2) and pin di ter and demo lock diagra! 4.20 (b). It is a ‘self-contained. adaptable fi 1.001 Hz to 500 kHz, The circuit consis and a low pass filter. Rp, C2 form alow pas an internal resistor of va! ue 3.6 kQ. Here the wnge {rom ator, an amplifier ted externally while Re is free running frequency ‘of the VCO is determined by the values of an external resis A connected between Pin 8 and the positive supply line and an external capacitor C. connected between pin 9 and the negative supply line. A capacitor of value rypicall tool uF is normally connected betwee pins 7 and 8 to eliminate possible oscilason inthe VCO voltage controlled current source. ‘The square wave output signal of VCO is available at pin 4 and in order to close the loop, Pin 4 must be connected externally 0 the phase comparator input Pin 5. The amplified loop error voltage which is applied as the control signal to the VCO is available arPin 7 This signal is referenced to the positive supply line. reference voltage which ‘snominally equal to the voltage at Pin 7 in available at Pin 6 and this allows differential ae . te Loth biased and driven by connecting them to Pin 6 and 7 The signal pid ae Se wre differential at Pin 2 and Pin 3, and the dee level aap ust y rrade the same. If dual power supplies are used itis simplest 19 eae soot oy the common power supply line. With single supply ogee ent biased to a level in the lower half of the total power supply suitable potential divider.[ unene tec ary RATED cy R; | | + Demodulated —— ie $8 cusp v 3 tase mp Le Reference Ms tongs Hee Input f nar i le : Noor 4, 4 jet : veo Phase comparator st a st vos —— — Reference 0 P— 7 fr - Demodulated OF — 7 forte (2) Block Dagan FIG 4.20 : LM 565 PLL 7 4.33 LOCK RANGE OF PLL The range of frequencies over which @ PLL can maintain lock with an input son . ona called the ‘lock range’ ofthe system. This is always longer than the band of frequen (over which the PLL can acquire lock wth an incoming signal. The lock ranges deren, as higher order odd harmonics are used to achieve lock 4.34 CAPTURE RANGE OF PLL The range of frequencies over which a PLL can acquite lock is known as the ‘coptue range’. The greatest capture range possible is equal to the lock range but in gener the capture range is less than the lock range. The capture of an input signal does re take place as soon as the signal is applied, but takes finite time called the ‘Pullin’ tine to establish lock 4.35 APPLICATIONS OF PLL - 1. For FM demodulation 2. For AM demodulation 3. For frequency multiplication 4. For Frequency shift ke: 5. In modems 6. For frequency division 7. In Telemetry receivers.© wave Shaping Crremts Tomer ond # TIPLIER USING PLL a ‘ 10 yency MY 6 ener how 4 4 sho" a2 ncan «a practical circuit for frequency mut id in two dif be achieve! ft to harmonic of the input Locking juding a counter in the lop between Incl aes ‘ows the second method which can pr Fig 4.21 shi he input To set up the circuit, the frequency limits of adjusted by means of Ry and C; which ensure ‘nidway between the input frequency limits. The minate variations in the demodulated output vo to elit frequency is established. The output can now be taken output, and its fundamental will be the desired mukiple Jong as the loop is in lock. 4.37 FM DEMODULATOR USING PLL When the PLL is locked on a frequency modulates instantaneous frequency of the input signal The error from low pass filter, controls the VCO frequency. and cores output. The VCO characteristics determine i Fi 1g. 4.22 shows a practical circuit of FM demodulator. The VCO = F adjusted at the centre of the input signal ‘requency range. Br show! of2k Q to 20 kQ and C, is accordingly chosen to The he sox ice can be directly coupled to pi ee ~~resstancelckingintopin2 and3. The ouput ey yore wt by connecting pins 4 and 8 together & reign | dic. potential available at pin 7. Yo 7 g a resistor extemally across ping ¢ . $6 and 7 essed with ite change inthe de level at ased with little change in the 1 uF is connected between pins 7 and § P 6 Referee oP —3 nn 9 3s FIG 4.22 : FM Demodulator Using PLL 4.38 VOLTAGE CONTROLLED OSCILLATOR LM 566 The IC LM 566 is 2 general purpose voltage controlled oscillator (VCO) designed for linear frequency modulation. This IC provides triangular and square wave outputs simultaneously at frequencies upto 1 MHz. Sinusoidal waveforms can be obtained by Shaping the triangular waveform using external circuit, Fig. 4.23 (a) shows the pin diagram and 4.23 (b) shows the functional block diagram of 556 waveform generator An external capacitor C is connected between termival 7 and ground, R is an externa resistor connected between terminal 6 and supply voltage V. Vc is external conte voltage applied at terminal 5. The current source I charges and dischar7es the capaci” C. The value of curre ‘ource is determined by v0 9)peel tor Tsif OFF and the current | W aches the UPPEF tip point of schmitt eos oN Th gunds the emitters of ~ ounds nis 8° and To and current | stot tts through diode Ds Ty ow PO" ground. But the base a : {T; and Tz are , voltages © ‘nequalamount of current . st prough wanssler Ty. This . up in discharging int is Use’ 1 C (since Do is reverse tjased The capacitor discharges vn the vower point of the cchmittigge 8 reached at which eats. Same amount the cycle FePs ji current flows through the capacitor during charging and gischarging. Therefore, the charging and discharging rates are vame and equals 1/C volts/sec. The charge and discharge | intervals are given by Vc TE gee oll) whete Vy = Voltage difference between the upper | and lower trip point of schmitter ; | Note : In design of Schmitt we, Vris selected very nearly 5" of supply voltage) | 5 7 sae the value of I from * L (9) into Equ (10) and puttingRC TSWV (ny Hence the frequency of operation is FIG 4.24: Voltage Controlled Oscillator Using LM 566 In practice the value of control voltage Vc is fixed by means of a potential divider connection between the supply voltage terminal and ground. By adjusting Ve within allowable range, the frequency swept over a 10:1 range. A typical circuit connection o the LM 566 waveform generator is shown in Fig. 4.24.10, 0. 12, shaping Crrewtts, Timers and PLL ne either it restricts the amplity ver ecuit 154 of a voltage waveform + cutoff the positive or negative peak of a waveform at some d valle wes ciipper : TWO cHPPET diodes may be used in one clipper circuit to perform suo Level independent levels at o “ping @ or arcu : It establishes a de voltage reference level from with one extremity or er y i ‘in ac signal swings weak _prmerisan electronic device that causes the action in it, to accurately operated cae second circuit at desired time. ade jc 355: His 2 highly stable monolithic timing circuit capable of producing accurate wie delays oF osellations ic uM 566 = It's @ general purpose voltage controlled oscillator designed for linear frequency modulation This IC provides triangular and square wave output eeiteneously at frequencies up to 1 MHz, phase Locked Loop (PLL) : Itis basically a closed loop feedback system. The action of FLL isto lock as synchronise the frequency of a controlled oscilator 10 that of an incoming signal. IC LM 565 : It is a self contained, adaptable filter and demodulator for the frequency range from 0.001 Hz to 500 kHz. Lock Range : The range of frequencies, over which a PLL can maintain lock with an input signal. Capture Range : The range of frequencies over which a PLL can acquire lock. s jquare Wave Generator : It is a circuit which gives square wave output. Frequency of the signal. f= <2 — 4R,CR Astabl . le Multivibrator : It is a free running multivibrator. The two states of the multivi ‘brators are momentarily stable. Time 7 mepeiod = T = 2RCin [! | Ro= [aire NIGRAK be Latta A multoibrator Which as One stabs gM | Mat 13, Mono Stable Multivibrator quast stable state oe RK, | r2kCIn|! Time pettod What is meant by time base generator 2 Detine the terms (a) Sweep amplitude (b) Sweep interval (co) Rettace interval Sweep speed ww (e) Displacement error (i) Sweep speed enor & Discuss the basic idea of sweep generation Distinguish between voltage ancl earrent tine base generation andl Ist thelr appilaon, 13, 2008, 2007, Oct'Nov. 2012, 201) (March April. 2 List the applications of sweep citeuits (March April, 2016 ; Oct Now, 2011 April’ May, 2012) © Deline sweep voltage (Mareh April. 2010) Detine sweep voltage ancl mention its applicaitons Explans the operation of fixed positive regulator using 78 XX seties + 9 List the applications of astable mulnvibater 10 List the applications of bistable mulavibraten 11 List the applications of schmitt wn | (Oct Now 20 meant by multi vibrators yor! (Mar Apr 2013, 2008, April May, 2012 Oct N 3 List applications of muttagoins, Corenite, Hamers and PUL Wa wl rypes of euppets (Apel May 2011, m = on ore! lurch/Apal. 2013) iad : awn (March April. 2016) cs! se rypes of elamnper ence! (March April. 2014) bg alllele f st! plication ol champers (March April. 2016) ieee | appiication® ‘of photo conductive cell ve pin diaare of IC 655, (March April. 2016 , April May 2011) ar bya PLL? (March April. 2013) apiure range of PLI (March/April. 2016) nge of PLL (April May, 2010) sof PLL [March/April, 2014, 2008 ; April May. 2010 . Oct Nov 2010) sy lock lige OF PL (Oct Nov. 2009 ; Oct Now. 2010) son PLL (Oct Now. 2007) yp, Short Hol sy What ave the features of 656 timer (Oct Now. 2007) IC (March April. 2016) sy Draw the PIN diagrant of Ho! Fasay Type Questions: 1 Draw and explain bootstrap sweep cleat (March April, 2014 ; Oct Now. 2010) 4 Draw and explain miiller’s sweep using OP AMP (April May, 2010, Oct Now, 2012, 2007, March April, 2007) 4 Draw a simple tranglstor current sweop cireutit and explain (ts operation AL. Drow and Explain the working af OP-AMP astably muldvibrator with wavelet (March April, 2016) 2 Explain the working oF OP AME mone stable multivibrater © Draw the oi Diow the cireuit diagram of OP AMP bistable iuttivibrator and explain ie epetst typ Splain the following applications of OP AME ae Curent of voltage converter (O) Band pass tilter — —a - Ex [untae intecearen 8. Explain with neat sketch the working of shunt diode clipper my 9. (a) Explain the working principle of clamper circuit Apri ate WY. 201 (b) Explain double ended clipper circuit April May, , M2019, 10. Explain the working principle of photovoltaic cell (Maren areh April, » . 2044 D 11. Explain how photo conductive cell works 12. Draw and explain the block diagram of IC 555 (March/April. 2016 ; A, + APEIUMay, 9 015, 13. Explain the working of monostable multivibrator using 555 IC. (April/May. 2009, Oct/Nov. 2012, 2014, » . + 2007) 14. Draw the circuit of monostable multivibrator using OP-AMP, (Aprivim : lay. 201) 15. Explain the working of astable multivibrator using 555 IC. ; (March/April. 2016 ; April/May. 2015, 2012 ; OctiNov. 2010, 29g . 2010, 2009) 16. Draw the Pin and functional diagram of IC LM 566 and explain working of vc using LM 566. q 17. What is meant by phase locked loop (PLL). Explain (April/May. 2012, 2011, 2010 ; Oct/Nov. 2011) 18. Draw and explain the block diagram of PLL (LM565) (April/May. 2012) 19. Explain the frequency multiplier using PLL (March/April. 2016 ; April/May. 2010, Oct/Nov. 2009, Mar/Apr. 2008) 20. Expain the working of frequency multiplier and FM demodulator using PLL. (March/April. 2016) 21. Explain the FM demodulator using PLL. (March/April. 2016 ; Oct/Nov. 2011, 2010 ; April/May. 2011)