COMBINATIONAL LOGIC CIRCUITS Chapter Outline CONCEPT OF COMBINATIONAL LOGIC CIRCU ecco ITs ADDER CIRCUIT AND ITS FUNCTIONALITY USING TRUTH TABI LE HAL fuLLADDER CIRCUIT yatF SUBTRACTOR AND FULL SUBTRACTOR jp BIT PARALLEL ADDER USING FULL-ADDER 9/5 COMPLIMENT PARALLEL ADDER/SUBTRACTO R CIRCUIT WORKING OF A SERIAL ADDER COMPARISON BETWEEN SERIAL ADDER AND Pai RALLEL ADDER MULTIPLEXER peMULTIPLEXER ENCODERS DECODERS TRI-STATE BUFFER DIGITAL COMPARATOR> 3.0 CONCEPT oF COMBINATIONAL LOGIC CIRCUITS E A logic circuit which has no memory no feedback from output to input and the Present output depends on the present input. This logic circuit is called ag “combinational logic circuit”. el Combination logic circuit FIG 3.1: Combinational Logic Circuit Example of combinational logic circuits are adders, subtracter, encoder, decoder, multiplexer, demultiplexer & comparators etc., can be implemented by using a combination of logic gates. Inputs In combination logics, the output variables depends on the combination of input variables, => Arithmetic circuits are common in many digital circuits to perform arithmetic operations such as addition, subtration, multiplication and division. : In digital computer system these circuits are used in the design of Arithmetic and Logic Unit (ALU). 3.1__HALF ADDER CIRCUIT AND ITS FUNCTIONALITY USING TRUTH TABLE By VCR Le A }—= Sum’ Half Adder B }—-Canry) It is a combinational logic circuit. A logic circuit that adds two binary bits is known as “Half Adder”. Inputs ‘Ouputs The function of half adder is to add two binary bits and produces two outputs sum and carry. FIG 3.2: Half Adder The logic operation of the half adder i’s expressed in its truth table. i Inputs ~ Outputs i eee A Sum = A@B j A | B Sum Carry a " ° 0 0 0 0 1 1 0 | 1 0 1 0 63 Circuit 7 1 0 1 FIG 3.3 : Logic Circ 5 Carry output isa ‘T’ only when both A and B are 1's therefore carry output (C) cnt expressed as AND gate. ‘ C=ABSum output is a ‘1’ only if the input variables are not equal. Therefore ;the sum(s) can be expressed as X-OR gate S = A@B-=AB+BA B B AB >I >I 0 A A 2 3 Sum =AB+BA Carry = AB FIG 3.4: Half Adder Simplification Using K-map 3.1.1 Relization of a Half-adder Using Nand Gates and Nor Gates Half adder using NAND Gates : FIG 3.5: Half Adder using NAND GaSs The sum(s) Carry = AB=AB i tes’: Realization of Half Adder using NOR Gates’ (ee. ——s B+ @sBI+A+AtB) Lo a ) Sum = A@B FIG 3.6: Thesum = (By(A+B)+[A+(AB]) 9 ~ AB+AB = B+(A+B)+A+(A+B) = AB+AA+AB4BB = B+(A+B)+A-(A+B) (OR) = A(A+B)+BiA+B) = B-(A+B)+A(A+B) = (A+B)(A+B) = BA+BB+AA+4B ie =AB+BA Carry =Combinational Logie Circuits = 2 FULL ADDER CIRCUIT Alogic circuit that can add three bits ata 4 i “Full adder”. 2 (“gel | sum time is known as “Full adder’ eee etc: KS: i | ‘The function of Full adder is capable of | ~ |c—| 3 adding three bits and produce a output® sum and camry. FIG 3.7 : Combinational Logic Circuit ‘The input vatiables ate represented by A, B and C, where ‘A’ and ‘B’ represent the 2- input variables to be added and ‘C’ represents the carry from the previous lower significant position. TRUTH TABLE Inputs Outputs. A B c sum | Carry 0 0 0 0 0 - | 0 0 fi 1 0 0 1 0 1 0 0 1 a1 0 1 1 0 0 1 0 1 0 1 0 + 1 1 0 0 1 ie! 1 1 1 1 alg “ From truth table Sum = RBC-+AeG ABC + ABC A@B@C [-s=(A@B)eC] =sum = ABC+ABC+ABC+ABC Cay = AB+BC+AC = A@BOC in of I Full adder Using 2 Two. Half: f-adders and an OR - Gate 3.2. 1 _ Realicatio ICRAF Pen oa e constructed using two half adders as shown in Fig. 2.91 Full adder can b a Carry AB . =e $= A@B C(A@B is Carry ees HA ¢ a $= (A@B)OC FIG 3.9 : Full Adder Constructed From Two Half-adders and OR Gate aCombinational Logi FIG 3.10 : Construction of Full adder Using Two Half-adders and OR Gate Note : sum = ABC+ABC+ABC + ABC Carry = ABC +ABC +ABC + ABC = C(AB+AB)+C(AB + AB) = ABC+ABC+AB(C +0) S = CS+CS, S,=A@B=AB+BA = C(AB+AB)+AB S = $,eC S. = A®B=AB+AB = C(A@B)+AB 3.2.2 Realization of a Full-adder using NAND Gates and NOR Gates 41s -O> + ea == S=A@BOC Tho arry [> @ 3 1a! i; (AOBCAB =(A@BIC+= Construction of FA. Using NOR Gates A@B =X= (A+B)+A+B Ss A@®B®C=X@C Carry = (A@B)®C+AB A+B+C+A A+AtB+B+A+B=A@B=S P52 G, +Cy +S¥Cy =89C,, Ls, genes f AB we AB+SC, FIG 3.12: Construction of Full adder using NOR Gates 3.3 HALF SUBTRACTOR AND FULL SUBTRACTOR 3.3.1 Half Subtractor Difference Half Subtractor: A half subtractor is a combinational circuit that subtracts two bits and produces outputs difference and borrow, FIG 3.13 : Half Subtractor Input — az a > Borrow The operation A-B for all possible values of A and B is tabulated. nN pD=AeB [Inputs Outputs B p= [Es A B Diff Borrow | ea 0 0 0 0 Sle a - n i a i Q FIG 3.14: Logie Diagram of Half Subtaco”Combinational Logie Circuits Ts | K-Map Simplification : AN®_B B A3_ 3 B x © A |@ I@ A D= AB+AB-A@B Borrow = Kp 3.3.2 Full Subtractor Full subtractor is a combinational logic circuit that performs a subtraction of two bits, taking into account borrow of the lower significant stage. This circuit has 3-inputs and two outputs as shown in Fig. 3.15. This circuit has three inputs and two outputs. Inputs. A B + + minuend subtrahend Outputs > Difference and Borrow > Outputs Inputs and Cc + previous borrow L A B Cc Diff Borrow B 0c ¢ $—) >Paaspes Re FIG 3.16 : Implementation of Full Subtractor Difference = ABC +ABC + ABC +ABC = C(AB+AB)+C(AB +B) = CASB)+TA@B) = C@(ASB) K-map simplification of Difference and Borrow 2 @, oa D = ABC+ABC+A D= A@B@C BC Aaa A\3G_Bc DI Qer Full Subtractor by Using Two Half Subtractors : -—_—— Borrow rs [Difference Fc aaa al > Difference = A@BOC fl is |e ta ___| + = Borrow C(A@B) +AB FIG 3.18 : Full Subtractor by Using Two Half Subtractors and OR Gate 3.4 4-BIT PARALLEL ADDER USING FULL-ADDER ‘APRIL/MAY. 201 As Bs Ar Bo Ay By Ao Bo | eas tals epee | AB Cy AB Cu A B Cin A BCy| = FAs FA, FAL Fay Cour__S. Cons Cour __S Cour__S | | | ! CG Ss S2 Si So FIG 3.19 : 4-Bit Parallel Adder A single Full-adder is capable of adding three one bit numbers (ie., two one bit numbers and input carry). In order to add binary numbers with more than one | bit, additional Full-adder must be used. For n-bit numbers, n-parallel adders are required; for 4-bit numbers, 4-parallel adders are required. 4-bit parallel adder using Full-adder ar each adder is connected to the carry iny e connected in eascade i.e., the carry output of put of the next higher-order adder.3.5 2S ing two 4-bit numbers designateg A block diagram of a 4-bit parallel adder capable of addi as Ag Ap Aj Ap and Bg By By Bo is shown in Fis. GG “Gr Ay A «LSB MSB > Ag Ag Eee Boe BI Bo & ee First we should add the LSBs (Ao Bo) using FAg with Cin terminal grounded. It gives th the carry (Co) has to be added to the next FA, it giveg output Sum(So) and cary (Co). T eter {5;) and (Ci). This is repeated unti al the bits of the two numbers are added, Example : if Ag Ap Ay Ap = 1101 and Bg Bz By Bo = 0101 43 AD AL Ag SoC Ay Bo Cn Ms a [Least significant Stace. gums Te ee SO By Bp By By fee fA, Bh Cn SCout Geese ee ey Bp Cy Sa B@O]. This means the X-OR gate output is equal to the B input bits. The Full adder receives the values of B, the input carry is ‘0’ (because M-=0) and the circuit performs A+B. Subtractor : (ii) When M=1, the circuit becomes a subtractor, when M=1, B@1=B and Cj, = 1 (because M=1). The B inputs are all complemented and a ‘1’ is added through the input carry. In this condition this circuit perform the operation A + the 2’s complement of ‘B’ ie, A-B. (OR) Adder : When M = 0, the outputs of the EX-OR gates will be same as the B data bits. The carry input to the first FA is ‘0’. Hence A and B bits are applied as the two inputs to the parallel adder. Thus the output would corresponds to the sum of A and B. Subtractor ; When M = 1, then the output, of EX-OR gates will be the complements of the B data bits. The carry input to the first FA., is now ‘1’. We are applying a data bits directly and ‘B’ data bits are complemented at the inputs of the parallel adder. At the same time the binary is also added (through the carry to the first[3.14 | SEENON F FA). This is the process of subtracting a binary number from another usin, n the 2’s complement method. Thus the circuit can be used as an adder as well as a subtractor. A3 Az Ai Ao 1A ttt | | bit parallel adder 0 ml 741883 ce Discarded = Tcameal aia ! TTT IT \] Pe B3B2B;By $3 $2 $189 Result sum (a) 2's Complement addition Asha ; | ne aan | 4-bit paratlel adder =| Cy. | 74LS83 q Discarded | a Tn ee B;BzB\By $3 $2 SiS0 Inverted outputs register B Result sum (b) 2's Complement subtraction FIG 3.21 : 2's Complement Adder-Subtractor 3.6 _ WORKING OF A SERIAL ADDER A serial adi (OCTINOV. 2012 PP der is used to added bits serially, that is one pair of bits at a time, only one full-adder is required for this addition as shown in Fig. 3.23. In serial adder first two LSBs (Ao and Bo) are applied at the inputs of bit (Co) is taken and feedback to the input sum(So) and the carry (Co). This carry such a way that it adds on to the next bit (Ay and By), these three bi and gives sum (51) and carry (C1). This process is repeated until all the bits of the numbers are added. The carry from the previous position is added to the current position bits. This is achieved by time delay circuit. A Flip- Flop can be used for this purpose. the adder. West its are now add Se re Fiip-flop FIG 3.22 : (2) Serial Adderoe 5 } Ouputs, S2[8i]S0 Cout di) D-Flip-flop (Memory circuit) FIG 3.22 (b) : 4-bit Serial Adder Ag Ag AL Ao : A, Ao = 1010 T 0-10 ForExample: gp, B, By = 0111 4 8 & B Bo (Opera First the two LSB, Ao(0) and Bo(1) applied at the inputs of the adder. We get Sum Go(1) and the carry Co(0). The carry (Co) is delayed by the delay circuit and taken as input and adds along with A;(1), By(1) and gives output sum $;(0) and carry Cx(1). This process is repeated until the bits are added. .7__ COMPARISON BETWEEN SERIAL ADDER AND PARALLEL ADDER 'APRIL/MAY. 2012 ; OCT/NOV. 2010 5 MA\ Parallel Adder Serial Adder S.No Operation is faster Operation is slower 2. | All the bits can be added simultaneously | Only one bit can add at a time 3. | All the bits are added parallel Bits are added serially 4. | Number of Full adders required is equal | Only one Full adder is used to the number of bits 5. | Itis costly | It is economical 6. Circuit is complex circuit is simple 7. | Delay circuit is not required Delay circuit is required It is a sequential logic It is a Combinational logic 1.8 MULTIPLEXER Multiplexer (MUX) or data selector is a logic circuit that has several dat ita input lines and a single output line. A multiplexer accepts several data inputs and allows any one of them at a time to get through the output. The routing of the desired data input to the output is controlled by SELECT inputs (some referred to as Address inputs).16 Multiplexer is a digitally controlled multiposition - switch. The digital code applied the SELECT determines which data inputs will be to inputs switched to the output. Multiplexer has 2" data inputs, n-select inputs and single output. Ex: If 8 x 1 Multiplexer consists of data inputs - 8 select lines -3 8= 2° output -1 ie, n=3 Data inputs Select inputs FIG 3.23: Functional Diagram of a Digi Multiplexer Data inputs Si_ 82, Select inputs FIG 3.24: 8 x 1 Multiplexer 7 Operation of 4X 1 Multiplexer (0?) L-of-4 (or) 4-to-1 MUX 4-input multiplexer with data inputs Do, D1, Dz and Ds and sele Out of these four data inputs, one is selec! and single outputly) shown in fig. TNA) ct imputs So and! on the data present on So and S; as given in the truth table. Do | So y | og jm a 0 0 y=Do £25 4x1 7 = zZ MUX ‘ YeDiries D i S05} Truth Table FIG 3.25 :z= (i) When Sy= So = 0 is applied to the select inputs the data on input DO appear on i the output. Combinational Logic Circuits ie, ‘y’ is equal to Do. y= DpSiSo ( (i) Similarly when S1=0, Sg = 1 output y is equal to Dy y= DiS, So Similarly when Sy=1, So = 0 y=D2Si S when Sy = So=1 y = D381 So. The total output is Y = DoS; S59 +D, 5,8) +D,8,5) +D. 8 The logic levels applied to the So and S; determines which AND that its data input passes through the OR gate to the output, Do D Dy D3Sa 3.8.2 Operation of 8 X 1 Multiplexer (or) 1-of-8 (or) 8-to-1 MUX 8 x 1 Multiplexer consists of 8 data inputs and 3 select inputs and one output (y) shown in Fig. —<—<—$—<————— =] Data Select input Output | => a ae 1 D Sat ees S| OY | meal ales 50s eee i; a) 2-4 8x1 Output 2 ¥ 4 i MUX Dee S2_Si_So Data select input FIG 3.27 : Functional Diagram aeacics 4D ,SoSi 52 4 Dp5oS152 + PsSoSiSz +D45p 5; Sp +DsSpSiS2 y=DpS0 71 4 DgS0S182 * D,S0S182 DoS0 81 $2 ¥ (Output) _piagram of 8x 1 Multiplexer i FIG 9.28: 1° a =e_ ERE corraione Loge routs == 183 Applications of Multiplexer ¢ used in numerous applications like, where multiple data can be A Multiplexer is transmitted using a single line. Multiplexers are used in, 1. Communication systems. 2. Computer memory 3. Telephone network 4, Transmission from the Computer System of a Satellite. 1. Communication Systems : A Multiplexer is used in communication systems. A Multiplexer is used to increase the efficiency of the communication system by allowing the transmission of data such as audio and video data from different channels via cables and single lines. 2. Computer Memory : A Multiplexer is used in computer memory to keep up a vast amount of memory in the computers, and also to decrease the number of copper lines necessary to connect the memory to other parts of the computer. 3. Telephone Network : A multiplexer is used in telephone networks to integrate the multiple audio signals on a single line of transmission. 4. Transmission from the Computer System of a Satellite : A Multiplexer is used to transmit the data signals from the computer system of a satellite to the ground system by using a GSM communication. 3.9 DEMULTIPLEXER poe | Demultiplexer is a logic circuit that performs a reverse multiplexer function. oe The multiplexer is a circuit that receives Data 1x4 Dy 2 inforrnation on a single line and transmits opus DEMUX }|——p.f{ 8 this information on several output lines. Dy The dernultiplexer has single data input, T {! So Ss 2° outputs and ‘n’ select lines. Select input FIG 3.29 : 4 x 1 Multiplexertiplexer (or ) 3.9.1 Operation of 1 X 4 Demult TAE 1-of-4 (or) 1-to-4 DEMUX and four outputs (Do, Dy, Dy It contains one data input, two select input (So and S1) and D3). The data input is selected based on data present So and S$; as given in the truth table Data Select Input Output Do | nee : 5 ng Slee So selected pee ae 3 Poe a DEMUX p.{ é a Ue 5 0 | D3 eee Dy \ , | SoS . 4 Select input == FIG 3.30: 4 x 1 Multiplexer S: So | | 3.9.2 pa A Fj | | z Xe bet tO” a Logie diagram FIG 3.31 : Logic Diagram of 1 x 4 Demultiplexer ist A demultiplexer is a circuit that receives information on a single line and re be information on one of 2 possible output lines. The selection of specie O88 ag! controlled by the values of n selection lines. Fig. shows 1: 4 demultiplex®® q ae is di input variable Din only one of the output lines. has a path to all four outputs, but the input informationCombinational Logic Circuits 4 Demultiplexer TABLE : Function Table for 1 [enable | S1 | 0 1 0 0 (eel a cL 1 1 | 7 3.9.2 Operation of 1 X 8 Demultiplexer (or) 1-of-8 (or) 1-to-8 DEMUX 1 1 ‘The below figure shows the logic diagram for a demultiplexer that distributes one input line to eight output line. The single data input line D is connected to all eight AND gates, but only one of these gates will be enabled by the select input lines. «When Sp $1 So = 0, only the AND gate Yo will be enabled, and the data input D will appear at output Yo. When S» S; So = 1, only the AND gate Y7 will be enabled and the data input D will appear at output Y7. fs + When 5, 5, Sp = 001 then Y; = D, S, Si So = O11 then Yg = D 5S, Sp = 010 then Yz = D, S, 5, S> = 100 then Yq = D S, 5 Sp = 101 then Ys = D, Sp S, Sp = 110 then Yo = D © Demultiplexers are used as clock demultiplexers in synchronous data transmission systems in the receivers, and in security monitoring systems ete.ERE) Pans Select Code Outputs Sa Sy So Y7 Ye Ys Y4 Y3 ‘2 Y4 0 0 0 0 0 0 0 0 0 0 0 0 dae |) 0 0 0 0 Ooo) 0 1 0 0 0 0 0 0 Do 0 1 1 0 0 0 0 D Oma 1 0 0 0 0 0 D 0 oo 1 o iio 0 D 0 0 CO) | 4 1 0 0 D 0 0 0 ONO Lo 1 1 D 0 0 0 0 OaanG 1 Yo pas] a eal input DEMUX i La Selected inputs 2 §; Sy D Y7™ S28) SoD. FIG 3.32: Logic Diagram of 1 x 8 Demultiplexer »Note : 1 to 16 Demultiplexer : The Fig. 3.33 shows 1 to 16 demultiplexer. The data bit (Din) has a path to all sixteen outputs. ever, the input information How is directed to only one of the output lines depending on the So iines. For status of So, Si, example, when $3 $2 So = 0000, the upper AND gate is enabled while all other AND gates are disabled. Therefore, data bit D is transmitted only to the Yo output, | giving Yo = D. If D is low, Yo = © Tow and if D is high, Yo is high FIG 3.33 : 1: 16 Demultiplexer 3.9.3 Applications of Demuttiplexers Demultiplexers are used in, 1, Communication systems. Computer memory. Telephone network. Pen Transmission from the computer system of a satellite. 3.9.4 Demultiplexer IC Numbers of TTL and CMOS TIL De-multiplexer ICs 74137 3 to 8-line demultiplexer /decoder 74138 3 to 8-line demultiplexer/decoder 74139 dual 2 to 4-line demultiplexer/decoder 74154 4/line to 16-line demultiplexer/decoder 74155 dual 2-line to 4-line demultiplexer/decoder 74156 dual 2-line to 4-line demultiplexer/deco 74159 4-line to 16-line demultiplexer/dece zLe CMOS De-muttiplexer ICs : 8-channel Analogue multiplexer/demultiplexer (1-of-8 swi 4052 Analogue multiplexer/demultiplexer (Dual 1-of-4 switch) 4053 Analogue multiplexer/demultiplexer (Triple 1-of-2 switch) 4067 16-channel analogue multiplexer/demultiplexer (1-of-16 4051B 8-channel multiplexer/demultiplexer 4053B Tripple 2-channel multiplexer/demultiplexer 4052B Dual 4-channel multiplexer/demultiplexer 4067B 16-channel multiplexer/demultiplexer g 4097B Dual 8-channel multiplexer/demultiplexer 74HC4051 8-channel multiplexer/demultiplexer 74HC4052 Dual 4-channel multiplexer/demultiplexer 74HC4053 Tripple 2-channel multiplexer/demultiplexer 3.10 ENCODERS x Encoder is a combination circuit that f covers one form of data (decimal, octal, hexadecimal or symbols) into the coded output (binary or BCD). 28 data outputs * An encoder has 2" input lines and ‘n’ : ‘output lines. FIG 3.34 : Functional Diagram of FIG 3.35 : amposed Combinational Logie Circuits [3.25 | qua 4x2 encoder (or) 4 10 2 encoder This encoder has 4 inputs and 2 outputs as shown in figure. [input Output | A B ml - ee eee ‘ 4x2 Output Input P | o 2——-|_ Encoder ES |e 0 1 oll | an Zane 1 0 | 5 a , FIG 3.36 : Function Diagram 4 x 2 Encoder From truth table A is a 1 for the decimal digital 2, 3. This can be expressed as OR function as oosy, A=2+3 onesie OS ee Similarly B=14+3 es : B FIG 3.37 : Logic Diagram 4 x 2 Encoder 10.2 8 x 3 Encoder (or) 8 t0 3 Encoder (or) Octal to Binary Encoder It has eight inputs and three outputs as shown in figure. (octal Inputs | Outputs (binary) A 0 0 0 0 1 1 1 1Em Aisa ‘1’ for decimal digits 4, 5, 6 or 7 an! Dea i d this can be expressed as OR function as 3 follows, A=4+5+6+7 Similarly B=2+3+6+7 +5V 434547 1 C=1+3+5 ae When one of the decimal digit inputline |) 1 ; ee oe is at high, the appropriate levels occur on the three output lines. | 2 1, For example : If input line is ‘6’ is high | 3 1, 7 rt (assuming all other inputs are low). This. | 4). will produce output HIGH on ‘A’ and ‘B: sana 7 and LOW on‘C’.ie.110whichis3-bit [ 7 binary code for decimal ‘6’. oe Z 7 ae, Note : aaa) +] Ais al for data Da, Ds, De or D7 J ie., A =Dgq+Ds+De+D7 i A B c Similarly B =Dz+D3+De+D7 © Py Dy+ se Dy BE 3.39 : Logic Diagram for Octal-to-binayy Encoder D; Ds Ds Ds Ds Dr Dy f ’ pies t B=D2+D3+Ds+D7 y C©=Di+D3+Ds + Dy t Set ___tp 7 LL FIG 3.40 : 8 to 3 EncoderJad Decimal to BCD Encoder (0r) 10-to-4 Encoder (or) 10 4 Encoder 3.10. a 7 a oO — 1 pe! Ho o |e : 10 to 4 Vg = : Encoder v2 (6 3 | o| 0 a ; Ys }o4 0 o | 9 2 1 0 u 4 alo FIG 3.41: 1 1 1 0 0 0 0 0 =14+3+5+74+9 Y, = 24+3+6+7 Ys =4+5+6+7 Ya = 8+9 This type of encoder has 10-inputs, one 4 for each decimal digit, and 4 outputs i corresponding to the BCD as shown in 2 |? g . = —j Decimalto [—— = below figure. 45 _cle peer é This is a baisc 10 line to 4 line encoder. 2 The BCD code is listed in below truth table and from this we can determine the telationships between each BCD bit and the decimal digits.Dj D2D3 Dy DsDgD7Ds Do | i) 4 “ (c) Logic Diagram From the truth table we get Ag = Dg+Do Ap = Dat+ Ds + De + D7 Ay = Dg+ D3 + De +t D7 Ap = Di + D3 + Ds + D7 + Do 3.11__DECODERS © Decoder is a combinational logic circuit that performs a reverse function of encoder. « The basic function of a decoder is to detect specified output from its inputs. n:2n decoder a n data inputs * A decoder has n-input lines and 2n output lines. Je FIG 3.43 : Functional Diagram of Decod!EERIE cor tonel oni Grants [3.29 | Decoders : A decoder is a multile-input, multiple-output logic circuit which converts coded inputs into coded outputs, where the input and output codes are different, The input code generally has fewer bits than the output code. Each input code word produces a different output code word, i.e., there is one-to-one mapping from input code words into output code words. This one-to-one mapping can be expressed in a truth table. The Fig, 3.44 shows the general structure of the decoder circuit. As shown in the Fig. 3.44 the encoded information is presented as n inputs producing 2” possible outputs. The 2" output values are from 0 through 2" — 1. Sometimes an n-bit binary code is truncated to represent fewer output values than 2". For example, in the BCD code, the 4-bit combination 0000 through 1001 represent the decimal digits 0-9, and combinations 1010 through 1111 are not used. Usually, a decoder is provided with enable inputs to activate decoded output based on data inputs. When any one enable input is unasserted, all outputs of decoder are disabled. Ex: 1. 3 x 8 decoder (Binary - to - octal decoder) 2. BCD - to - decimal decoder (4 - line - to - 10 line decoder) 3. 4 « 16 decoder (Binary to hexadecimal decoder) NOTE-1 : Decoder Vs Demultiplexer 7 Decoder i Demultiplexer | 1. | Decoder is a many inputs to device Demuttiplexer is a one input to many outputs I device There are no selection lines The selection of specific output line is controll by the value of selection lines. NOTE-2 : Multiplexer Vs Decoder Multiplexer has several data-input lines and a single output line. The Particular input line is controlled by a set of selection lines. The data line is routed to the output line. On the otherhand, decoder foe Output lines. Each output line represents one minterm. D output line depending on the input combination.DIGITAL ELECT L3. Applications of Decoder : 1. It can be used to implement combinational circuit. 2. It can be used to convert BCD into 7-segment code. 3. It is used in memories to select particular register. i 3.11.1 2x 4 Decoder (or) 2 to 4 Decoder \ The 2 x 4 decoder has 2-inputs and 2?=4 output, In decoder only one output is ih for one combination of inputs and other outputs are low. 7 | Inputs. Outputs. | as i. AS BOR Yay va 4 A—-+ 2x4 ae Decoder ° ° ° ° Inputs Output (i) When inputs A = 0,B = 0, then 4 B the output Yo is active i.e., Yo = 1 I and other AND gates are low (i.e. Y1 = 0, Y2 = 0; Ys =(0) = i) WhenA=0,B=1 ; Yy=1 | rc (ii) WehnA=1,B=0 ; Yo=1 t ) Ye=AB (iv) WhenA=1,B=1 ; Y3= | 1 ‘org_— ESCORTED costo re 11,2 3x 8 Decoder (or) 3 to 8 Decoder 3.11.2 Caan 3.49 shows 3 * 8 decoder or binary-to-octal decoder. It has 3-inputs and 8-outputs. Fig. 3.49 shows 3 t ies Outputs a te Y7 Yo Ivs | Ya | Ys | Y2|¥a |¥o (| ne ° als ojo] ololojojoljojo|1 | i 0 Yo" olol4 5 ig | o| s 3 oe 7] B4s—l sxe ee Ja |a oj} 6 Decoder E 6 0 | 14 i le ' | 4 [0 0 oO" ine t|o4 ° 1/4 ]o 0 | FIG 3.46: Functional Diagram of 3 x 8 Decoder 1) 0 | When A = 0, B = 0, C = 0 then Yo =1 and all other AND gates are low outputs. Similarly When A=0;B=0;C=1; Yy=1 WhenA=0;B=1;C=0; Yo=1 When A=0;B=1;C=1; Y3= When A=1;B=0;C=0; Yq=1 When A=1;B=0;C=1; Y5= When A=1;B=1;C=0; Yg=1 WhenA=1;B=1;C=1; Y7= 3. 11.3 BCD to Decimal Decoder (or) 4-to-10 Decoder (01) « 43 x10 Decoder The Below figure shows the logic diagram for a 7442 BCD to decimal decoder. It available as a 74LS42 and 74HC42, An output goes LOW only when its corresponding BCD input is applied. F D, = 0 only when AgApAyAg = 0100 D; = 0 only when AsoAiAo = 01 This decoder can also be referred to as 4 - 10 decoder, or 1-of-1( The pin diagram and truth table for 7442 are shown in below Fig.BCD/DEC DECODER (b) Pin Diagram (a) Logic Diagram FIG 3.47:- Combinational Logic Circuits TRESTATE BUFFER : Buffer : The Buffer has only one input and one output. It behaves opposite to NOT gate, The Buffer is defined as the “The logic gate which produces the unchanged input as its output”. This means the input of the buffer will directly pass to the output port. The other name for Buffer is “Non- inverting digital logic gate”. ‘Tri-State Buffer : The word “Tri” means “Three”. The output of the buffer can be electronically disconnected from output circuitry as per our requirement, This type of Buffer is known as a 3-State Buffer or more commonly a Tri-state Buffer. Normal buffer will have only one input and one output but the tri state buffer has 2 inputs. The two inputs of tri state buffer are data input and the other is control input or Enable input A Tii-state Buffer can be thought of as an input controlled switch with an output that can be electronically turned "ON" or "OFF" by means of an external “Enable” (EN) signal input. This control signal can be either a logic "0" ‘Control” or or a logic "1" type signal resulting in the Tri-state Buffer being in one state allowing its output to CPerate normally producing the requited output or in another state were its output is blocked or disconnected, Then a tri-state buffer requires two inputs. One being the data input and the other being the enable or control input as shown, Enable FIG 3.48: Tri-state Buffer Switch Equivalent When activated into its third state it disables or turns "OFF" its output producing an en circuit condition that is neither at a logic "High" or "Low", but instead gives an SutPut state of very high impedance, High-Z, or more commonly Hi-Z. Then this type Of device has two logic state inputs, "0" or a "1" but can produce three different output states, "( “or” Hi-Z" which is why it is called a "3-state" device. Note that this third state is NOT equal to a logic level "0" or "1", but is an high State in which the buffers output is electrically disconnected from th Asa result, no current is drawn from the supply.‘State Buffers = ke microprocessors and mMicrocompiy, ets, any digital systems li ts may be required t in turn may be requil In m connected to a common Ii Ny 10 be 0n Tine wha SMe wate un as "bus outpul which connect! red to drive a number of gate ihpy, s puts to the bus, we have some difficult, These are f operation duejto the connection of o,., A- Ta Farally | CMOS Family as vet) 4LS07 - Hex buffer IC (Non inverting) __| HEF40244 Tri-state Octal Bu 7ALSO7 - Hex Non-inverting Buffer | C4503 - Hex Tri-state Buff || 74LS17 - 7ALS244 - Octal lex Buffer/Driver C4050 - Hex Non-inverting Buffer state buffer IC 74LS245 - Octal Bi-directional Buffer3.14 DIGITAL COMPARATOR : tes The XOR gate is a basic comparator; its output is 9 ‘1° and @ output is '0' if the inputs are equal, , 1 Inputs Output [| ATs Gab Y | { > Inputs are eugal Eero > 0 1 1 |» I | Input bits arenot equal 1 | ~» | FIG 3.49; XOR —> Inputs are equal a3 peas i # pot err « The X-NOR gate (co-incidence gate) is a ;basic comparator because its output is 2 ‘1’ only if its two bits are equal i.e., the output is ‘1’ if and only if the input bits are coincide (equal), Inputs | utput ah a ‘ > 9 f B 1 Oo i FIG 3.50 ; X-NOR Gate is a Basic Comparator 0 0 1 0 | 3.14.1 1 Bit Comparator A comparator is a logic circuit that compares the value of two numbers. Let us assume that the bits A and B are compared. The truth table for the comparator action as given in Table. In the truth table, A and B are the bits to be compared, If bit A is 1 and B is 0, then A > B (A > Bis high). If A is 0 and Bis 1 then A B A=B A B, A = Band A < B can be written as, A>B>AB A= B>AB+AB>A@B AAB 3.14.2 2-Bit Comparator CTT TA eT Let us use the technique discussed above to develop a comparator to cot 2-bit numbers, Let the numbers to be compared be A (Aj Ao) and B (B 1. When A; = 1, By = 0 irrespective of other bits. 2. fA, = By and Ag = 1, Bo = 0han B when any one of the following condi ition Ste A will be less ¢ 1. When Ay =9 By =1 jrrespective of other bits. 2 if Ay = By and Ao = 0 Bo=7 A will be equal to B when the following conditions satisfied i; A; = Bi Ao = Bo truth table requires 16 combinations ar ditions in the form ofa ‘ent these con is shown in Table. To repres ble hen! ce a function ta aa Del Inputs | Outputs ] B A=B | AB Ay & By | Ac Ay? Bi | 9 Ay < Bi Ay = Br Ay = Bs Ay = Br Fic 3.53: 2 8i Comparator In the function table, X indicates the don't care condition. From the function table, one can write the expressions for A 7 B, A= Band A< B. A>B = A,B, + OB: -Ap Bo A = B= A; OB, An Bo A = BoA, By + Ai @Bi Ao Bo