Lect 6 A

Memory Characteristics Memory Technology
CSC 213: Computer Architecture

Lecture 6a: Internal Memory
November 26, 2021

Agenda
1 Memory Characteristics
2 Memory Technology

Characteristics of Memory
“Location wrt Processor”
Inside CPU – temporary memory or registers

Inside processor – L1 cache
Motherboard – main memory and L2 cache
Main memory – DRAM and L3 cache
External – peripherals such as disk, tape, and networked
memory devices

“Capacity – Word Size”
The natural data size for a processor.

A 32-bit processor has a 32-bit word.
Typically based on processor’s data bus width (i.e., the width
of an integer or an instruction)
Varying widths can be obtained by putting memory chips in
parallel with same address lines

“Capacity – Addressable Units”
Varies based on the system’s ability to allow addressing at

byte level etc.
Typically smallest location which can be uniquely addressed
At mother board level, this is the word
It is a cluster on disks
Addressable units (N) equals 2 raised to the power of the
number of bits in the address bus

“Unit of transfer”
The number of bits read out of or written into memory at a

time.
Internal – Usually governed by data bus width, i.e., a word
External – Usually a block which is much larger than a word

“Access method”
Based on the hardware implementation of the storage device

Four types
Sequential
Direct
Random
Associative

Sequential Access Method
Start at the beginning and read through in order

Access time depends on location of data and previous location
Example: tape

Direct Access Method
Individual blocks have unique address

Access is by jumping to vicinity then performing a sequential
search
Access time depends on location of data within ”block” and
previous location
Example: hard disk

Random Access Method
Individual addresses identify locations exactly

Access time is consistent across all locations and is
independent previous access
Example: RAM

Associative Access Method
Addressing information must be stored with data in a general

data location
A specific data element is located by a comparing desired
address with address portion of stored elements
Access time is independent of location or previous access
Example: cache

Performance – Access Time
Time between ”requesting” data and getting it

RAM Memory
Time between presenting the address and getting the valid data
It’s predictable.
Other types, Sequential, Direct, Associative
Time it takes to position the read-write mechanism at the
desired location.
Not predictable.

Performance – Memory Cycle time
Primarily a RAM phenomenon

Adds “recovery” time to cycle allowing for transients to
dissipate so that next access is reliable.
Cycle time is access + recovery

Performance – Transfer Rate
Rate at which data can be moved

RAM – Predictable; equals 1/(cycle time)
Non-RAM – Not predictable; equals
N
TN = TA + ( )
R
where
TN = Average time to read or write N bits
TA = Average access time
N = Number of bits
R = Transfer rate in bits per second

Physical Types
Semiconductor – RAM
Magnetic – Disk & Tape
Optical – CD & DVD
Others
Bubble (old) – memory that made a ”bubble” of charge in an
opposite direction to that of the thin magnetic material that
on which it was mounted
Hologram (new) – much like the hologram on your credit card,
laser beams are used to store computer-generated data in three
dimensions. (10 times faster with 12 times the density)

Physical Characteristics
Decay
Power loss
Degradation over time
Volatility – RAM vs. Flash
Erasable – RAM vs. ROM
Power consumption – More specific to laptops, PDAs, and
embedded systems

Organization
Physical arrangement of bits into words

Not always obvious
Non-sequential arrangements may be due to speed or
reliability benefits, e.g. interleaved

Semiconductor Memory Types
Memory Type Category Erasure Write Mechanism Volatility
Random-access
Read-write memory Electrically, byte-level Electrically Volatile
memory (RAM)
Read-only
Masks
memory (ROM)
Read-only memory Not possible
Programmable
ROM (PROM)
Erasable PROM
UV light, chip-level
(EPROM) Nonvolatile
Electrically
Electrically Erasable Read-mostly memory

Electrically, byte-level
PROM (EEPROM)
Flash memory Electrically, block-level

Semiconductor Memory Types
RAM
Misnamed as all semiconductor memory is random access
Read/Write
Volatile
Temporary storage
Static or dynamic

Memory Cell Operation

Dynamic RAM
Bits stored as charge in capacitors

Charges leak
Need refreshing even when powered
Simpler construction
Smaller per bit
Less expensive
Need refresh circuits
Slower
Main memory
Essentially analogue
Level of charge determines value

Static RAM
Bits stored as on/off switches

No charges to leak
No refreshing needed when powered
More complex construction
Larger per bit
More expensive
Does not need refresh circuits
Faster
Cache
Digital
Uses flip-flops

SRAM v DRAM
Both volatile
Power needed to preserve data
Dynamic cell
Simpler to build, smaller
More dense
Less expensive
Needs refresh
Larger memory units
Static
Faster
Cache

Read Only Memory (ROM)
Permanent storage
Nonvolatile
Microprogramming
Library subroutines
Systems programs (BIOS)
Function tables

Types of ROM
Written during manufacture

Very expensive for small runs
Programmable (once)
PROM
Needs special equipment to program
Read “mostly”
Erasable Programmable (EPROM)
Erased by UV
Electrically Erasable (EEPROM)
Takes much longer to write than read
Flash memory
Erase whole memory electrically

Organisation in detail
A 16Mbit chip can be organised as 1M of 16 bit words

A bit per chip system has 16 lots of 1Mbit chip with bit 1 of
each word in chip 1 and so on
A 16Mbit chip can be organised as a 2048 × 2048 × 4-bit
array
Reduces number of address pins
Multiplex row address and column address
11 pins to address (211 = 2048)
Adding one more pin doubles range of values so ×4 capacity

Typical 16 Mb DRAM (4M × 4)

Refreshing
Refresh circuit included on chip

Disable chip
Count through rows
Read & Write back
Takes time
Slows down apparent performance

Packaging

Interleaved Memory
Collection of DRAM chips

Grouped into memory bank
Banks independently service read or write requests
K banks can service k requests simultaneously

Advanced DRAM Organization
Basic DRAM same since first RAM chips

Enhanced DRAM
Contains small SRAM as well
SRAM holds last line read (c.f. Cache!)
Cache DRAM
Larger SRAM component
Use as cache or serial buffer

Synchronous DRAM (SDRAM)
Access is synchronized with an external clock

Address is presented to RAM
RAM finds data (CPU waits in conventional DRAM)
Since SDRAM moves data in time with system clock, CPU
knows when data will be ready
CPU does not have to wait, it can do something else
Burst mode allows SDRAM to set up stream of data and fire
it out in block
DDR-SDRAM sends data twice per clock cycle (leading &
trailing edge)

SDRAM

SDRAM Read Timing

RAMBUS
Adopted by Intel for Pentium and Itanium

Main competitor to SDRAM
Vertical package – all pins on one side
Data exchange over 28 wires ¡ cm long
Bus addresses up to 320 RDRAM chips at 1.6Gbps
Asynchronous block protocol
480ns access time
Then 1.6 Gbps

RAMBUS Diagram

DDR SDRAM
SDRAM can only send data once per clock

Double-data-rate SDRAM can send data twice per clock cycle
Rising edge and falling edge


Simplified DRAM Read Timing

Lect 6 A

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Memory Characteristics Memory Technology

CSC 213: Computer Architecture

November 26, 2021

CSC 213: Computer Architecture

CSC 213: Computer Architecture

Inside CPU – temporary memory or registers

CSC 213: Computer Architecture

The natural data size for a processor.

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Varies based on the system’s ability to allow addressing at

CSC 213: Computer Architecture

The number of bits read out of or written into memory at a

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Based on the hardware implementation of the storage device

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Sequential Access Method

Start at the beginning and read through in order

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Direct Access Method

Individual blocks have unique address

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Random Access Method

Individual addresses identify locations exactly

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Associative Access Method

Addressing information must be stored with data in a general

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Performance – Access Time

Time between ”requesting” data and getting it

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Performance – Memory Cycle time

Primarily a RAM phenomenon

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Performance – Transfer Rate

Rate at which data can be moved

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Physical arrangement of bits into words

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Semiconductor Memory Types

Memory Type Category Erasure Write Mechanism Volatility

Electrically Erasable Read-mostly memory

Flash memory Electrically, block-level

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Semiconductor Memory Types

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Memory Cell Operation

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Bits stored as charge in capacitors

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Bits stored as on/off switches

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Read Only Memory (ROM)

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Written during manufacture

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A 16Mbit chip can be organised as 1M of 16 bit words

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Typical 16 Mb DRAM (4M × 4)

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