Adaptive S W to Compensate dc-link Voltage Ripple

for Component Minimized Voltage Source Inverters

Frede Blaabjerg, Dorin Neacsut, John K. Pedersen
Aalborg University, Institute of Energy Technology
Pontoppidanstraede 101, DK-9220 Aalborg East, Denmark

Technical University of Iasi, Electronics Department

PO Box 211 OP1, Iasi, RO-6600, Romania

-
Abstract An adaptive Space Vector Modulation approach to
compensate the dc-link voltage ripple in a B4 inverter is
examined in detail. The theory, design and performanceof this
PWM method are presented and the method effectiveness is
demonstrated by extensive simulations and experiments. High-
quality output currents are guaranteed by this approach even
with substantial dc voltage variations that might be caused by
unbalanced ac supply system, diode rectification of the line
voltages and circulation of one phase current through the split
capacitor bank. The application of this approach to induction
machine drives is also discussed. It is concluded that the dc
ripple effect on the B4 inverter output can be minimized by an
adaptive SVM algorithm with the advantage of improving the
response of the dc-link filter and the output quality is high.
tering. Since the dc voltage ripple problem varies at the B4
inverter, this approach is analyzed in this paper for the B4
inverter. Compared to a traditional B6 inverter the voltage
vectors in the B4 inverter have changes both in amplitudes
and angle when a ripple appear while a B6 inverter has chan-
ges only in voltage vector amplitude.
This paper shows first the basic topologies for a B4
inverter includingdifferent rectifier topologies. Its modulation
strategy is explained and the effect on voltage ripple in the
dc-link is analyzed. An adaptive method is proposed to
outcompensate the influence of the dc-link ripple on the
output. This method is verified both by simulations and
experiments.

I. INTRODUCTION 11. TOPOLOGIESAND DEFINWIONS

In the recent years, some research efforts have been
directed to developing new power converters with reduced
loss and costs. Among these circuits, the three-phase Voltage
Source Inverter (VSI) with only two inverter legs is an attrac-
tive solution (B4) [1]-[13]. In comparison with the usual
three-phase VSI with three legs (B6) the main features of this
converter are:
- reduced switch count;
- potential reduced price because of the reduction of
switches;
- reduction of the conduction loss by 113.
Despite these advantages, the main shortcomings of this
topology are:
- increased voltage stress on both power devices and
induction machine;
- large variations of the voltage over the two dc-link
capacitors caused by one phase current circulating
through the capacitive bank [4]-[5].
Avoiding the last shortcoming is often achieved at the
expense of large dc-link filter components that leads to a
bulky and heavy dc-link filter with a slow response and
increased cost. Furthermore, the unbalance in the ac supply
as well as the use of a diode rectifier to obtain the dc voltage
generate abnormal dc voltage harmonics which easily can
affect the load with subharmonics.
In [15], a solution is proposed to compensate the dc
voltage ripple by a special modulation technique for the three-
phase inverter with three legs (B6) without additional fil-
Fig. 1 presents the circuit diagrams of the component
minimized dc/ac converter [1]-[13] when fed by a single-
phase or three-phase diode rectifier.
The B4 inverter employs four switches and four diodes to
generate two line-to-line voltages, U& and U,.*, whereas Ubc is
generated according to Kirchhoff s voltage law from a split
capacitor bank. Due to the circuit configuration, the maxi-
mum obtainable peak value of the line-to-line voltage equals
UJ2. In order to get a higher dc-link voltage, an input
transformer can be considered as shown in Fig. ICor in the
single phase version connect one wire to the dc-bus. Since the
B4 inverter provides a low cost solution for motor drive
applications, the dc voltage is normally achieved by single-
phase or three-phase rectification.
For the analysis, the inverter is considered to be built by
ideal switches without introducing delay or overlapping. The
output voltages are defined by the gating signals of the two
leg switches and by the two dc voltages (U, and UJ. In this
way, it is further possible to take into account the influence
of the variations of the voltage on the two dc capacitors (C1
and C2).
The expressions of the output voltages and the dc-link
currents yield by writting the Kirchoff equations for the load,
and by taking into consideration two switching functions
(denoted S1 and S2) for the two inverter legs. These are
equal to 0 or 1 depending on the gating signals for T1 and
T2, or T3 and T4. Actually this is the same notation as for
the vector definition in Fig. 2a.

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 where
uao,ub0, uco = output voltages
U17 U2 = voltage across dc-link capacitors
220V,50Hz s1, s 2 = switching functions

The dc-link currents can also be expressed as a function of

the switching functions.

iDcl =i, SI +i, S2

Load iDa =i, * (1 -SI)+i, (1 - 2 2 )

t r:
' Dc1
.
where
iDcl, iDc2 = upper and lower dc-link currents (see Fig. 1)
i,, i, = phase currents

f "

Load

W
(c)
Fig. 1 . Converter circuit diagram for a B4 inverter.
a) Single-phase diode rectifier, low dc voltage.
b) Single-phase diode rectifier, high dc voltage.
b) Three-phase rectifier.

U, =-U1 ( -SI -S2) +- U2 ( 2-SI 42)

3 3

Fig. 2. Switching vector distributionin a B4 inverter.

a) Without dc-link ripple.
b) Large dc voltage ripple and U, >U,.

U1
uco=-(2 *S2-SI)+-(2
U2 *S2-SI-l)
Using all the possible combinations of (S1,S2),the line-to-
3 3
neutral voltages get the values given in Table I.

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 7r 7r
TABLE I --sa<-
4 4
SWITCHING FUNCTION
AND THE OUTPUT VOLTAGEs
FROM A B4 INVERTER t 377Jm
COS(^) -T- u2-u1
Output voltage
l O0

t =T-
U1+U,

2'
U1 +U2

-COS(CY+-) a (3)
U1+U2 ul+u, 6

1 1 T1 T3 -2'U,/3 u,/3 u,/3 -as a < 3 - 7r

When the dc-link filter is big enough to keep a constant

value of Udc/2 for both U, and U, voltages, the four switch-
ing combinations lead to the four voltage vectors presented in
Fig. 2a. Otherwise a small ripple in the dc-link voltages lead
to a deviation of these vectors from the previous positions. It
is presented in Fig. 2b as an example.
Taking into account the values of the voltages across the
split capacitors, the vector positions are defined as given in
Table 11.

TABLE II
SWITCHING FUNCTION
AND THE SIZE OF VECTORS IN A B4 INVEIRTER
Vector Amplitude

a
t =T- -cos(a+-)
01 u,+u, q+u2 6
1 1 -(2U,)/3 0

111. MODULATION to1=

6" cos(a)
-
Vl+U2
The discrete nature of the converter operation implies the
t00 --T- 1'
-cos(a+-) a
necessity of modulating the output pulses in order to ap-
proximate a desired reference waveform. This means to u,+u2 u1+u2 3
switch the converter between some active neighbouring states
over a constant sampling interval in order to obtain a desired
mean voltage vector U,. In comparison with the three-phase
inverter with three legs, the zero vectors are missing in the
case of the B4 inverter. Generally, on each sampling period where
there are used three vectors: the closest possible to the t, = time period for voltage vector xx
desired position and the two vectors that neighbour the first U, = mean voltage vector
one. The time portions allocated to each vector are generally T = switchingperiod
given by: 01 = voltage vector position

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 The time portions allocated to each vector can be split in
order to obtain a symmetrical distribution over the switching
period. Among the solutions analyrd in [ 6 ] , the solution
employing five vectors on a switching period is next con-
sidered. Furthermore, when U, = U;!, the same equations as
;m0i

00
,1,_..,
2000 4000 6000 BOO0
//, ,

10000
,,,,~~,,,,

12000
1
in the case of non-compensated dc-link ripple are achieved. I

If the inverter is used in fixed imd variable frequency 400 II

inverters for power supply and ac motor drives, the harmonic
content at the inverter output becomes important. For
instance, the fluctuation of torque of im ac motor drive has a
close relationship to the deviation from an ideal flux linkage
vector. Because this is the result of three-phase sinusoidal
waveforms, the resulting torque has no pulsations. The
difference between the ideal and real flux linkage vectors
which are generated in PWM inverters causes torque pul-
sations. Deviations in stator flux amplitude mainly cause
mechanical vibrations and emission of acoustic noise whereas
deviations in stator flux angle result iin torque ripple. In a
constant dc-link voltage inverter, the (deviationsin the flux
angle can be controlled by appropriate switch-sequencetiming
of the voltage vectors as discussed in [16],[17]. The Har-
monic Loss Factor HLF can be used as an optimization cri-
terium, and the best results this inverter can provide are
presented in Table 111, based on [5].Fig. 3 presents a sample
of the output voltage spectra for the three phase voltages.
IT-----
(7)
where
N = number of harmonics
HLF = harmonic loss factor
h = harmonic number
I@) = current of harmonic No. h
TABLE III
HLF (%) FOR f,=4 kHZ, R=5 R, L= 10 h4H AND U,, = 600 V
(m REPResENTS THE MODULATION INDEX AND THE SWITCHING
FREQUENCY fw IS CONSIDEREDCONSTANT)
E
g 200
‘0 2000 4000 moo aooo ioooo 12000 14000
400 ’ $ H
F:equency I
Frequency lHzl
Fig. 3. Output voltage spectra for f,=513 Hz,m=0.6, f8,,,=4 &
and free-ripple dc voltage and the (IC voltage is 600 V.
The component minimized inverter experiences a substan-
tial ripple in the dc-link voltages that cannot be ignored. This
ripple leads to the appearance of harmonics in the inverter
output not present in the PWM switching waveforms and the
results of Fig. 3 and Table I11 will ble worsened.
Furthermore, the interaction between the low harmonics
of the dc-link ripple causes subharmonics in the inverter
output waveforms that may bother in motor drive ap-
plications. The simplest solution consists in providing
additional filtering in the dc-link. By contrary, in the fol-
lowing, an Adaptive Space Vector Modulation algorithm is
proposed to compensate the dc-link voltage ripple.
IV. DC-LINK
RIPPLECOMPENSATION
A. 172emy
The dc-link ripple is composed froin several sources that
are identified for both situations of single-phase and three-
phase feeding (see Fig. 1).
Xkree-phase ac power supply with 50 ,Hz or 60 Hz
- the diode rectification of the ac network voltages causes
a 300 Hz or 360 Hz component of the voltage U, +U2;
- unbalance in the ac power supply generates a 100 Hz or

m HLF(%) HLF(%) 1 HLF(%) I 120 Hz component that also affects the whole dc bus
voltage (U, +UJ;
- opposite components in U, and U, on the fundamental
0.2 10.41 11.02 12.18
frequency of the inverter output phase currents caused by
0.4 5.04 5.33 , 5.89 circulatingphase current through the capacitor bank; these
I 3.14 I 3.33 1 3.68 11 components do not exist in a three-phase inverter with
0.8 2.12 1 2.25 I 2.48 1 three legs (B6) and are strongly depending on the load
current level;
- harmonics resulted from the interaction between these
components.

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Single-phase ac power supply with 50 Hz or 60 Hz B. Simulation-Based Analysis
- the diode rectification of the ac network voltage causes a In order to validate this new adaptive SVM algorithm to
100 Hz or 120 Hz component of the voltage U, +U2; compensate the dc voltage ripple, extensive simulations are
- opposite components in U, and U, on the fundamental performed in MATLAB-SIMULINK. This environment
frequency of the inverter output phase currents caused by allows to compare easily the three main operation modes of
circulating the phase current through the capacitor bank; a SVM B4 inverter: free-ripple dc-Sink voltages, uncompen-
- harmonics resulted from the interaction between these sated de voltage ripple and compensated dc voltage ripple.
components. The first simulations are performed for a converter having
a constant RL load and a slight dc-link filter that delivers a
The effect of the existence of the dc voltage ripple on the maximum ripple of about 30% for both U, and U, voltages
mean voltage vector definition is illustrated in Fig. 4. that would emphasize the effectiveness of the proposed
algorithm. The dc-lmk voltages U, and U, are sensed and
processed by a control unit at each PWM samplig period of
Re
250 ps.
Fig. 5 presents a sample of the simulation results for the
case of an RL load when implemented the dc voltage ripple
compensation, and Fig. 6 presents the results for the same
system in the case without compensation algorithm, both of
them for the three-phase rectification. Fig. 7 and Fig. 8
present the same comparison for the case of single-phase
(a 1 (bl
rectification.
Fig. 4. Definition of the mean voltage vector from the switching vectors. 500
(a) Free-ripple dc-link voltage. 1
(b) Ripple in both dc-link voltages (U,> U,) without compensation. s_
a 0
9
It is worthwhile to note that in a B6 inverter, the ripple 1
001 0015 002 0025 003 0035 004 0045 005
existence means a proportional alteration of all three output 500, Time 161
I
phase voltages and accordingly an amplitude error of the
switching vectors. In the case of a B4 inverter, the ripple
leads to different modification of the voltages on the three
I
phases (see Table I) and to both radial and angular errors of 001 0015 002 0025 0.09 0035 004 0045 005
5001 Time is\ I
the switching vectors. So, it is expected that the dc-link ripple
will affect the output waveforms more in a B4 inverter than s0 0
in a B6 inverter. Avoiding this dc voltage ripple is usually 3
achieved by extending the dc-link filter component values I
O 01 0.015 0.02 0.025 0.09 0.035 0.04 0.045 005
with the shortcomings of decreasing the system response, Time [SI
increasing loss and costs as well as a large size of the final
converter. Another approach previously developed for the B6
inverter [13],[14] only consists in using an adaptive SVM 20 1

algorithm for the inverter control. It is proposed to modify

the constants from the SVM algorithm by taking into account
the real value of the U, and U, voltages. This means using -201 I
001 0015 002 0025 003 0035 004 0045 005
[3]-[6]to calculate the active time durations. When neglecting
the variations of the inverter output currents, the de filter can
be ideally designed from the constraints of keeping the
constant dc voltages over the PWM sampling periods and of
-20‘
having always a sufficiently high enough value of the de-link 001 0015 00‘2 0025 OW 0035 004 0045 005
Time [SI
voltages. The existence of ripple in the de-link voltages 20 I

reduces the maximum rms value of the output voltage in the 9

case of SVM without overmodulation and this is the reason z a
s
why the lowest de-link voltage and ripple has to be limited. -20
0 01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05
A special case represents the application of this method to Time Is]
induction machine drive where current variations can occur
and the dc filter must keep the dc-link voltage variations at a
resonable level for all the operation points.

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 400

~ 3 0 -0

1001 I
'o$O1 Od15 Ob2 Od25 O W 0035 004 0045 005 0.01 0.015 002 0.025 0.a 0.035 0.04 0.045 0.05
700

"8.L o.di5 o.oz c.o~ 0.k

Time [SI
o.dss 0.b4 0.d45 0.L
Time [SI

(c)

Fig. 5 . Three-phase fed converter with dc ripple compensation algorithm Fig. 6.Three-phase fed converter without dc ripple compensation algorithm
(C,=C,=330 pF, L=0.6 mH, f,=4 k€h,f,=SO Hz, m=0.6). (C,=C,=330 pF, L=0.6 mH, f,=4 kHz, f,=SO Hz, m=0.6).
a) Output voltages. a) Output voltages.
b) dc-link and output currents. b) dc-link and output currents.

--
c) dc-link voltages. c) dc-link voltages.

-50
001 0015 002 0025 003 0035 OM OM5 005
Time Is]
'508bl 0dt.S Ob2 Od25 5063
0 - 0 400, I

500, Time [sl

I

"8bi odis ob2 Od25 ob3 5 0 -

-500L
001
500,
0015 002 0025 0.09
Tme Is]
0035 0.04 0045 005
"; ; ; , z
>

200
001 0015 002 0025 003 0035 O M OM5 005
l i m e Is]
001 0015 002 0025 CO3 0035 004 0045 005
Time Is] Fig. 7. Single-phase rectification with the compensation algorithm
(C,=C,=4700 pF, L= 10 mH, f,=40 Hz,f,,=4 k&, m=0.8)
(8)

50 I I
20

s+ o
0

-? 5

L;KA
20
-
s
A 0
0
l7me s
-20 400
0 5
20

9 >
:s* 200
001 001.5 002 0025 003 0035 O M OM5 005
-20 Ime 161
001 0015 002 0025 003 0005 004 0045 005
Time [SI
Fig. 8. Single-phase rectification without the compensation algorithm
@) (C,=C,=4700 pF, L=10 mH, f,=40 Hi,f,=4 WFZ, m=0.8).

585

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It can be seen in all cases the compensation algorithm
outcompensates the influence of the dc-link ripple and the
phase currents become symmetrical.
C. Peformance
In this section, the performance of the adaptive SVM
algorithm proposed to reduce the influence of the dc-link
ripple on the B4 inverter output waveforms is analyzed.
Computing HLF, voltage spectra and maximum voltage
inverter gain are performed by computer simulations.
1. Inverter Voltage Gain
After some geometrical computation in Fig. 4b, the
maximum attainable voltage yields:
R C 1- m C O S ( W / ~ ~ ) (11)
which is less strong than (10).
Equation (9) and (10) give the maximum ripple that can
be corrected completely by the proposed algorithm at each
modulation index. The allowed operating area is presented in
Fig. 9 and one can observe that the maximum value of the
corrected ripple is 38% at m = 0.62. This case is close to
the situation taken into consideration in Fig. 5 and Fig. 6. It
can be concluded that, approximatively, Fig. 5 and Fig. 6
present the worse case.
R

where
U,,, = maximum output voltage

So, the lowest de voltage limits the inverter voltage gain

and this depends also linearily on the maximum ripple in the
dc voltages.
2. Device Stress
The maximum voltage on the power devices and load is
increased by the ripple value. So, assuming a ripple on the de
voltage means a slight increase in the device stress.
3. Dependence of the maximum allowed ripple on the
modulation index
The proposed SVM algorithm leads to important harmonic
improvements if the voltage vector time periods calculated
from (3)-(6) remain positive for all the operating points. If
the result of one of these equations is negative, that time
constant is limited to zero and this distorts the output voltage
Fig. 9. Limitation in compensation of dc-link ripple in Beinverter.
4. Harmonic Pe@ormance
Calculating the HLF for the case of the RL, load leads to
results very close to the results presented in Table 111. If the
sampling period can be equal to the PWM switching period
or close enough, it may be concluded that the same load
currents are expected to be obtained. The spectra of the phase
voltages in the case of compensating the de voltage ripple are
presented in Fig. 11 for the same conditions as considered in
Fig. 3 for the ideal case. For comparison, Fig. 10 presents
the uncompensated operation.
1

1,
4m
waveforms. Accordingly, the output voltage spectra are af-
fected and a rich content define of low harmonics is introdu-
ced. g2.[
;2m[ 0
0
,
2000
,,,,
J",
4M0
,
6COO
I
8000
,
10300
,,IIy(l ,,,,
12000 14003
A variable R=AUI(Ud,12) is defined as the maximum I
FmwrwiM1
I
ripple of one of the voltages U, and U,. For symmetry -2
reasons, the maximum ripple has the same value for each of
E2m.
these two voltages. So far, imposing the condition of having
all the voltage vector time periods positive, the equations (3) '0
- 2600
. L . M k h -
4050 6000 8000 10200 12OCQ 14000
and (5) lead to the same conditions:

R€-.m6
4
Wom too> (9)

R C 1 -m @om z ,and
~ tol) (10)
Fig. 10. Output voltage spectra for L = 5 0 Hz,m=0.8, f,=4 lcHz
while equation (4) and (6) lead to and uncompensated DC voltage ripple.

586

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 1 1oaEII1
200 r

k.,,
I
* 1
;-I
4001

0
, ,,,,, , , . ,d",,,,,
g-tooo
wl o 01 02 03 04 05 06 07 08 09

o 2000 4000 smo Elmo imw izow 14000

Freumnwfl-tzl lime, Is]
I I r I

t II 1
z2mL00 2000 4000 6000 8000 10000 l2000 14000 01 0.2 03 04 05
lime 161
06 0.7 0.8 0.9

f-l
BOO, I

0
0
,
2000
,j,L
4000
,
6000
.,~,,,
8000
,
Im00
,.I,
12000
1
14000
, 1"

2000
I r 1' , ' , P ' l

01
I

02 03 04
.

Time Is]
05
-
06 07 08 09

Fig. 11. Output voltage spectra for f,=:50 Hz, m=0.8, f,=4 kHz Fig. 12. Main waveforms for the induction machine drive system.
and compensated DC voltage ripple.

The dc voltage ripple causes alteration of the fundamental

component in the three line voltage spectra. The adaptive
SVM algorithm compensates thest: variations and the line
voltage spectra are becoming close t'o each other. To illustrate
these, Table IV presents the first harmonic content of the I
0.345 0.35 0.355 0.36 0.365 0.37
spectra from Fig. 3, Fig. 10 and Fig. 11. Time [a]

TABLE N
SIMULATION BASED TEST OF B4 INVERTER WITHOUT AND WITH
ADAPTIVE ALGORITHM

Free-ripple
(Fig. 3)
Uncompensated Compensated
-20
0.345
' 0.35
0.355 0.36 0.365 0.37
Time Isl
Fig. 13. Zoom on the induction machine waveforms for the
time interval with a torque of 10 Nm.
307.8 V 306.7 V 308.1 V

U d ) V. IMPLEMENTATION

D. ac Motor Drive cme The implementation is carried out by a developed proces-

To prove the effectiveness of the compensation algorithm,
the induction machine drive case is considered with the next
system specifications: L = l mH, C1 ==C2=1100pF; a 4 kW
induction machine; f,, =4 kHz; fout=40 Hz, m= 0.8. Appen-
dix A gives the motor parameters for simulation. Fig. 12
presents the start-up without load and a 10 Nm to 25 Nm
torque step at 0.5 s.
Moreover, Fig. 12 and Fig. 13 show a close-up in the
system waveforms. At low load operation, the torque ripple
is very high and some low frequemy oscillations are still
present. The inverter output currents have low values and the
ripple on the two capacitors is also reduced.
sor system [17] which consists of two processors, a floating
point digital signal processor (DSP)SHARC 21062 and a
fixed point microcontroller SAB8OC167. The test system is
shown in Fig. 14.
The DSP is used for fast calculations and the microcon-
troller is used for advanced timinig functions of the usual
SVM algorithms.
The equations for computing the time portions allocated
to the switching states are re-calculated by taking into account
the real values of U, and U, and the dc-link voltages need to
be suitably sensed and processed by the control unit. Since
the variations of these voltages are on low frequencies,
sensing U, and U, is not required ,at each sampling period.
This can simplify the microcontroller task in an industrial
application.

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 Vbc [VI

'""I :
350

-1
. . . . . . * . . . . . . . I . . . . . . . .............. ...........
....................................
. >
ii
:-I
:
. . . . . . . . . . . . . . . . . . . . . . . . . . . ...... : : A
:...........

Control Unit 0 2 I 0 0 10 12
f [Wzl
PC-Pentium (c)
Fig. 15. Measured output voltage spectra for
fd = 40 Hz, m = 0.8, fsw= 4 kHz.
a) v, b) v,, c) v,
lation
Ram Fig. 15 shows that most harmonics are present at V, as
U expected. The adaptive compensation is done in the case of
single-phase rectifier with a reduced input filter (C1 = C2 =
Fig. 14. Implementation of the adaptive SVM algorithm in the 680 pF), so some ripple may be present in the dc-link. Fig.
developed processor system. 16 shows the voltage spectra without and with adaptive
To illustrate the SVM techniques Fig. 15 shows the voltage compensation for one phase-phase voltage.
measured voltage spectra of the three output phases. The dc-
link ripple is in this case fractional. (C1 = C2 = 3.3 mF).

. ................
Vab [VI .,
: I
...........
Ii Ili
_ 1

....................................
. . . . .;.
. ~ .
..........
....................................

) ..................................

...I :.
....... . . . . .
....................
.:.. .:.
...
ii
. . . . . .,. . .

50 ...

350 ...................... .,. . . . . . . . . . . . . ,...... _ , _...

Vac [VI MO ..................................................
250
......................
200 ..... ..... ... .........
....
.................................................

(3)
0 2 I 8 8 10 12
* [kHz1 Fig. 16. Measured output voltage spectra for
fDu = 40 Hz, m = 0.8, f, = 4 kHz and a reduced filter size.
a) Without compensation of dc-link ripple.
b) With compensation of dc-link ripple.

Comparing Fig. 16b and Fig. 15c it can be seen that using
the adaptive technique the fundamental of the voltage is kept.
Fig. 17 shows the dc-link voltages and the output currents in
the two cases.

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 350,
U, and U2
I
APPENDIX
A

Induction Machine Parameters

Power rating
- = 4 kW
= 0.659 61
-100 -50 0 50 100
Time [mr]
= 0.062H
Phase currcots
10.0 I
7.5
I
= 0.472 0
7 5.0
= 0.062H
2.5
E
L
0.0
-2.5 = 0.058 H
5 -5.0
= 0.014 kg m2
-7.5
-10.0
-100
' -50 0 50 1W
I
= 0.018
lime [ms]
of poles = 4
(4
350
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