MCIMX28RM

i.
MX28 Applications Processor

Reference Manual
Document Number: MCIMX28RM

Rev. 1, 2010
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
2 Freescale Semiconductor, Inc.
Contents
Section Number Title Page
Chapter 1
Product Overview
1.1 i.MX28 Overview...........................................................................................................................................................87
1.2 Hardware Features..........................................................................................................................................................87
1.3 i.MX28 Product Features................................................................................................................................................92
1.3.1 ARM9 CPU Subsystem...............................................................................................................................94
1.3.2 System Buses...............................................................................................................................................94
1.3.2.1 AXI Bus Segments....................................................................................................................95
1.3.2.2 AHB Buses................................................................................................................................96
1.3.2.3 APB Buses................................................................................................................................97
1.3.3 On-Chip RAM and ROM............................................................................................................................97
1.3.4 On-Chip One-Time-Programmable (OCOTP) ROM..................................................................................98
1.3.5 External Memory Controller (EMI)............................................................................................................99
1.3.6 Interrupt Collector.....................................................................................................................................100
1.3.7 Default First-Level Page Table..................................................................................................................100
1.3.8 DMA Controller........................................................................................................................................100
1.3.9 Clock Generation Subsystem....................................................................................................................101
1.3.10 Power Management Unit...........................................................................................................................102
1.3.11 Ethernet Interfaces.....................................................................................................................................103
1.3.12 CAN Interfaces..........................................................................................................................................103
1.3.13 USB Interfaces...........................................................................................................................................103
1.3.14 General-Purpose Media Interface (GPMI)................................................................................................104
1.3.15 Hardware Acceleration for ECC for Robust External Storage..................................................................104
1.3.15.1 Bose Ray-Choudhury Hocquenghem ECC Engine................................................................105
1.3.16 Data Co-Processor (DCP)—Memory Copy, Crypto.................................................................................105
1.3.17 I2C Interface..............................................................................................................................................106
1.3.18 General-Purpose Input/Output (GPIO)......................................................................................................106

Freescale Semiconductor, Inc. 3
1.3.19 Display and Capture Processing................................................................................................................106
1.3.19.1 Display Controllers / LCD Interfaces (LCDIF)......................................................................107
1.3.19.2 Pixel Processing Pipeline (PXP).............................................................................................108
1.3.20 SPDIF Transmitter.....................................................................................................................................109
1.3.21 Dual Serial Audio Interfaces......................................................................................................................109
1.3.22 Rotary Decoder..........................................................................................................................................109
1.3.23 UARTs.......................................................................................................................................................110
1.3.24 Low-Resolution ADC, Touch-Screen Interface and Temperature Sensor.................................................110
1.3.25 High Speed ADC (HSADC) Controller....................................................................................................111
1.3.26 Pulse Width Modulator (PWM) Controller...............................................................................................111
Chapter 2
ARM CPU Complex
2.1 Overview.......................................................................................................................................................................113
2.2 ARM 926 Processor Core.............................................................................................................................................113
2.3 JTAG Debugger............................................................................................................................................................116
2.4 Embedded Trace Macrocell (ETM) Interface...............................................................................................................116
Chapter 3
Default First-level Page Table (DFLPT)
3.1 Default First-Level Page Table (DFLPT) Overview.....................................................................................................117
3.2 Operation......................................................................................................................................................................118
3.2.1 Top-Level Symbol and Functional Overview............................................................................................120
3.2.2 Memory Map.............................................................................................................................................120
3.2.3 Default First-Level Page Table PIO Register Map Entry 2048.................................................................123
Chapter 4
Memory Map
4.1 Memory Map Overview................................................................................................................................................125
Chapter 5
Interrupt Collector (ICOLL)
5.1 Interrupt Collector (ICOLL) Overview........................................................................................................................129
5.2 Operation......................................................................................................................................................................130

5.2.1 Nesting of Multi-Level IRQ Interrupts......................................................................................................132
5.2.2 FIQ Generation..........................................................................................................................................134
5.2.3 Interrupt Sources.......................................................................................................................................134
5.2.4 CPU Wait-for-Interrupt Mode...................................................................................................................139
5.3 Behavior During Reset..................................................................................................................................................141
5.4 Programmable Registers...............................................................................................................................................141
5.4.1 Interrupt Collector Interrupt Vector Address Register (HW_ICOLLVECTOR).......................................148
5.4.2 Interrupt Collector Level Acknowledge Register (HW_ICOLLLEVELACK).........................................149
5.4.3 Interrupt Collector Control Register (HW_ICOLLCTRL).......................................................................150
5.4.4 Interrupt Collector Interrupt Vector Base Address Register (HW_ICOLLVBASE).................................152
5.4.5 Interrupt Collector Status Register (HW_ICOLLSTAT)...........................................................................153
5.4.6 Interrupt Collector Raw Interrupt Input Register 0 (HW_ICOLLRAW0)................................................154
5.4.10 Interrupt Collector Interrupt Register 0 (HW_ICOLLINTERRUPT0).....................................................157
5.4.20 Interrupt Collector Interrupt Register 10 (HW_ICOLLINTERRUPT10).................................................170




5.4.110 Interrupt Collector Interrupt Register 100 (HW_ICOLLINTERRUPT100).............................................296

5.4.138 Interrupt Collector Debug Register 0 (HW_ICOLLDEBUG)...................................................................335
5.4.139 Interrupt Collector Debug Read Register 0 (HW_ICOLLDBGREAD0)..................................................337
5.4.140 Interrupt Collector Debug Read Register 1 (HW_ICOLLDBGREAD1)..................................................337
5.4.141 Interrupt Collector Debug Flag Register (HW_ICOLLDBGFLAG)........................................................338
5.4.142 Interrupt Collector Debug Read Request Register 0 (HW_ICOLLDBGREQUEST0).............................339
5.4.146 Interrupt Collector Version Register (HW_ICOLLVERSION).................................................................342
Chapter 6
AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
6.1 AHB-to-APBH Bridge Overview.................................................................................................................................343
6.2 APBH DMA.................................................................................................................................................................345
6.3 Implementation Examples............................................................................................................................................350
6.3.1 NAND Read Status Polling Example........................................................................................................350
6.5.1 AHB to APBH Bridge Control and Status Register 0 (HW_APBHCTRL0)............................................358
6.5.4 AHB to APBH Bridge Channel Register (HW_APBHCHANNEL_CTRL)............................................367
6.5.5 AHB to APBH DMA Device Assignment Register (HW_APBHDEVSEL)............................................369
6.5.6 AHB to APBH DMA burst size (HW_APBHDMA_BURST_SIZE).......................................................370
6.5.7 AHB to APBH DMA Debug Register (HW_APBHDEBUG)..................................................................371
6.5.8 APBH DMA Channel 0 Current Command Address Register (HW_APBHCH0_CURCMDAR)..........372
6.5.9 APBH DMA Channel 0 Next Command Address Register (HW_APBHCH0_NXTCMDAR)...............373
6.5.10 APBH DMA Channel 0 Command Register (HW_APBHCH0_CMD)...................................................373
6.5.11 APBH DMA Channel 0 Buffer Address Register (HW_APBHCH0_BAR).............................................376

6.5.12 APBH DMA Channel 0 Semaphore Register (HW_APBHCH0_SEMA)................................................376
6.5.13 AHB to APBH DMA Channel 0 Debug Information (HW_APBHCH0_DEBUG1)...............................377


6.5.78 APBH DMA channel 10 Current Command Address Register (HW_APBHCH10_CURCMDAR).......450
6.5.79 APBH DMA channel 10 Next Command Address Register (HW_APBHCH10_NXTCMDAR)............451
6.5.80 APBH DMA channel 10 Command Register (HW_APBHCH10_CMD)................................................451
6.5.81 APBH DMA channel 10 Buffer Address Register (HW_APBHCH10_BAR)..........................................454
6.5.82 APBH DMA channel 10 Semaphore Register (HW_APBHCH10_SEMA).............................................454
6.5.83 AHB to APBH DMA channel 10 Debug Information (HW_APBHCH10_DEBUG1)............................455
6.5.85 APBH DMA Channel 11 Current Command Address Register (HW_APBHCH11_CURCMDAR)......458
6.5.86 APBH DMA Channel 11 Next Command Address Register (HW_APBHCH11_NXTCMDAR)...........458
6.5.87 APBH DMA Channel 11 Command Register (HW_APBHCH11_CMD)...............................................459
6.5.88 APBH DMA Channel 11 Buffer Address Register (HW_APBHCH11_BAR).........................................461
6.5.89 APBH DMA Channel 11 Semaphore Register (HW_APBHCH11_SEMA)............................................462
6.5.90 AHB to APBH DMA Channel 11 Debug Information (HW_APBHCH11_DEBUG1)...........................463

6.5.99 APBH DMA Channel 13 Current Command Address Register (HW_APBHCH13_CURCMDAR)......473
6.5.100 APBH DMA Channel 13 Next Command Address Register (HW_APBHCH13_NXTCMDAR)...........474
6.5.101 APBH DMA Channel 13 Command Register (HW_APBHCH13_CMD)...............................................474
6.5.102 APBH DMA Channel 13 Buffer Address Register (HW_APBHCH13_BAR).........................................477
6.5.103 APBH DMA Channel 13 Semaphore Register (HW_APBHCH13_SEMA)............................................477
6.5.120 APBH Bridge Version Register (HW_APBHVERSION).........................................................................496
Chapter 7
AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA)
7.1 AHB-to-APBX Bridge Overview.................................................................................................................................497
7.2 APBX DMA.................................................................................................................................................................499
7.3 DMA Chain Example...................................................................................................................................................503

7.5.1 AHB to APBX Bridge Control Register 0 (HW_APBXCTRL0)..............................................................511
7.5.2 AHB to APBX Bridge Control Register 1 (HW_APBXCTRL1)..............................................................511
7.5.3 AHB to APBX Bridge Control and Status Register 2 (HW_APBXCTRL2)............................................515
7.5.4 AHB to APBX Bridge Channel Register (HW_APBXCHANNEL_CTRL)............................................519
7.5.5 AHB to APBX DMA Device Assignment Register (HW_APBXDEVSEL)............................................521
7.5.6 APBX DMA Channel 0 Current Command Address Register (HW_APBXCH0_CURCMDAR)..........522
7.5.7 APBX DMA Channel 0 Next Command Address Register (HW_APBXCH0_NXTCMDAR)...............523
7.5.8 APBX DMA Channel 0 Command Register (HW_APBXCH0_CMD)...................................................523
7.5.9 APBX DMA Channel 0 Buffer Address Register (HW_APBXCH0_BAR).............................................525
7.5.10 APBX DMA Channel 0 Semaphore Register (HW_APBXCH0_SEMA)................................................526
7.5.11 AHB to APBX DMA Channel 0 Debug Information (HW_APBXCH0_DEBUG1)...............................527


7.5.76 APBX DMA Channel 10 Current Command Address Register (HW_APBXCH10_CURCMDAR)......594
7.5.77 APBX DMA Channel 10 Next Command Address Register (HW_APBXCH10_NXTCMDAR)...........595
7.5.78 APBX DMA Channel 10 Command Register (HW_APBXCH10_CMD)...............................................595
7.5.79 APBX DMA Channel 10 Buffer Address Register (HW_APBXCH10_BAR).........................................597
7.5.80 APBX DMA Channel 10 Semaphore Register (HW_APBXCH10_SEMA)............................................598
7.5.81 AHB to APBX DMA Channel 10 Debug Information (HW_APBXCH10_DEBUG1)...........................599


7.5.118 APBX Bridge Version Register (HW_APBXVERSION).........................................................................637
Chapter 8
Pin Descriptions
8.1 Pin Descriptions Overview...........................................................................................................................................639
8.2 Pin Definitions for 289-pin BGA..................................................................................................................................640
8.3 Functional Pin Groups..................................................................................................................................................649
Chapter 9
Pin Control and GPIO (PinCtrl)
9.1 Pin Control and GPIO Overview..................................................................................................................................669
9.2 Operation......................................................................................................................................................................670
9.2.1 Reset Configuration...................................................................................................................................671
9.2.2 Pin Interface Multiplexing.........................................................................................................................671
9.2.2.1 Pin Drive Strength Selection...................................................................................................680
9.2.2.2 Pin Voltage Selection...............................................................................................................681
9.2.2.3 Pullup Selection......................................................................................................................681
9.2.3 GPIO Interface...........................................................................................................................................684
9.2.3.1 Output Operation.....................................................................................................................684
9.2.3.2 Input Operation.......................................................................................................................685
9.2.3.3 Input Interrupt Operation........................................................................................................686
9.4.1 PINCTRL Block Control Register (HW_PINCTRLCTRL).....................................................................692
9.4.2 PINCTRL Pin Mux Select Register 0 (HW_PINCTRLMUXSEL0)........................................................694

9.4.12 PINCTRL Pin Mux Select Register 10 (HW_PINCTRLMUXSEL10)....................................................720
9.4.16 PINCTRL Drive Strength and Voltage Register 0 (HW_PINCTRLDRIVE0)..........................................730
9.4.26 PINCTRL Drive Strength and Voltage Register 10 (HW_PINCTRLDRIVE10)......................................759

9.4.36 PINCTRL Bank 0 Pull Up Resistor Enable Register (HW_PINCTRLPULL0).......................................785
9.4.41 PINCTRL Bank 5 Pad Keeper Disable Register (HW_PINCTRLPULL5)..............................................796
9.4.42 PINCTRL Bank 6 Pad Keeper Disable Register (HW_PINCTRLPULL6)..............................................798
9.4.43 PINCTRL Bank 0 Data Output Register (HW_PINCTRLDOUT0).........................................................800
9.4.48 PINCTRL Bank 0 Data Input Register (HW_PINCTRLDIN0)................................................................804
9.4.53 PINCTRL Bank 0 Data Output Enable Register (HW_PINCTRLDOE0)................................................808
9.4.58 PINCTRL Bank 0 Interrupt Select Register (HW_PINCTRLPIN2IRQ0)................................................812

9.4.63 PINCTRL Bank 0 Interrupt Mask Register (HW_PINCTRLIRQEN0)....................................................817
9.4.68 PINCTRL Bank 0 Interrupt Level/Edge Register (HW_PINCTRLIRQLEVEL0)...................................822
9.4.73 PINCTRL Bank 0 Interrupt Polarity Register (HW_PINCTRLIRQPOL0)..............................................826
9.4.78 PINCTRL Bank 0 Interrupt Status Register (HW_PINCTRLIRQSTAT0)...............................................831
9.4.83 PINCTRL EMI Slice ODT Control (HW_PINCTRLEMI_ODT_CTRL)................................................836
9.4.84 PINCTRL EMI Slice DS Control (HW_PINCTRLEMI_DS_CTRL)......................................................840
Chapter 10
Clock Generation and Control (CLKCTRL)
10.1 Clock Generation and Control (CLKCTRL) Overview................................................................................................843
10.2 Clock Structure.............................................................................................................................................................843
10.2.1 Table of System Clocks.............................................................................................................................844

10.2.2 Logical Diagram of Clock Domains..........................................................................................................847
10.2.3 Clock Domain Description........................................................................................................................848
10.2.3.1 CLK_P, CLK_H......................................................................................................................848
10.2.3.2 CLK_EMI...............................................................................................................................849
10.2.3.3 System Clocks.........................................................................................................................849
10.3 CLKCTRL Digital Clock Divider................................................................................................................................849
10.3.1 Integer Clock Divide Mode.......................................................................................................................850
10.3.2 Fractional Clock Divide Mode..................................................................................................................850
10.3.2.1 Fractional Clock Divide Example, Divide by 3.5...................................................................851
10.3.2.1.1 Fractional ClockDivide Example, Divide by 3/8..................................................851
10.3.3 Gated Clock Divide Mode.........................................................................................................................852
10.4 Clock Frequency Management.....................................................................................................................................852
10.5 Analog Clock Control...................................................................................................................................................853
10.6 CPU and EMI Clock Programming..............................................................................................................................853
10.7 Chip Reset.....................................................................................................................................................................854
10.8.1 System PLL0, System/USB0 PLL Control Register 0 (HW_CLKCTRLPLL0CTRL0)..........................856
10.8.2 System PLL0, System/USB0 PLL Control Register 1 (HW_CLKCTRLPLL0CTRL1)..........................858
10.8.3 System PLL1, USB1 PLL Control Register 0 (HW_CLKCTRLPLL1CTRL0).......................................859
10.8.4 System PLL1, USB1 PLL Control Register 1 (HW_CLKCTRLPLL1CTRL1).......................................861
10.8.5 System PLL2, Ethernet PLL Control Register 0 (HW_CLKCTRLPLL2CTRL0)...................................862
10.8.6 CPU Clock Control Register (HW_CLKCTRLCPU)...............................................................................863
10.8.7 AHB, APBH Bus Clock Control Register (HW_CLKCTRLHBUS)........................................................865
10.8.8 APBX Clock Control Register (HW_CLKCTRLXBUS).........................................................................867
10.8.9 XTAL Clock Control Register (HW_CLKCTRLXTAL)..........................................................................868
10.8.10 Synchronous Serial Port0 Clock Control Register (HW_CLKCTRLSSP0).............................................869

10.8.14 General-Purpose Media Interface Clock Control Register (HW_CLKCTRLGPMI)...............................874
10.8.15 SPDIF Clock Control Register (HW_CLKCTRLSPDIF).........................................................................875
10.8.16 EMI Clock Control Register (HW_CLKCTRLEMI)................................................................................876
10.8.17 SAIF0 Clock Control Register (HW_CLKCTRLSAIF0).........................................................................877
10.8.18 SAIF1 Clock Control Register (HW_CLKCTRLSAIF1).........................................................................878
10.8.19 CLK_DIS_LCDIF Clock Control Register (HW_CLKCTRLDIS_LCDIF).............................................880
10.8.20 ETM Clock Control Register (HW_CLKCTRLETM)..............................................................................881
10.8.21 ENET Clock Control Register (HW_CLKCTRLENET)..........................................................................882
10.8.22 HSADC Clock Control Register (HW_CLKCTRLHSADC)...................................................................883
10.8.23 FLEXCAN Clock Control Register (HW_CLKCTRLFLEXCAN)..........................................................884
10.8.24 Fractional Clock Control Register 0 (HW_CLKCTRLFRAC0)...............................................................885
10.8.25 Fractional Clock Control Register 1 (HW_CLKCTRLFRAC1)...............................................................887
10.8.26 Clock Frequency Sequence Control Register (HW_CLKCTRLCLKSEQ)..............................................889
10.8.27 System Reset Control Register (HW_CLKCTRLRESET).......................................................................891
10.8.28 ClkCtrl Status (HW_CLKCTRLSTATUS)................................................................................................892
10.8.29 ClkCtrl Version (HW_CLKCTRLVERSION)...........................................................................................893
Chapter 11
Power Supply
11.1 Overview.......................................................................................................................................................................895
11.2 DC-DC Converters........................................................................................................................................................897
11.2.1 DC-DC Operation......................................................................................................................................897
11.2.1.1 Brownout/Error Detection.......................................................................................................897
11.2.1.2 DC-DC Extended Battery Life Features.................................................................................899
11.3 Linear Regulators..........................................................................................................................................................900
11.3.1 USB Compliance Features........................................................................................................................901
11.3.2 5V to Battery Power Interaction................................................................................................................902
11.3.2.1 Battery Power to 5-V Power...................................................................................................902
11.3.2.2 5-V Power to Battery Power...................................................................................................902

11.3.2.3 5-V Power and Battery Power.................................................................................................903
11.3.3 Power-Up Sequence...................................................................................................................................903
11.3.4 Power-Down Sequence..............................................................................................................................904
11.3.4.1 Powered-Down State...............................................................................................................904
11.3.5 Reset Sequence..........................................................................................................................................904
11.4 PSWITCH Pin Functions..............................................................................................................................................905
11.4.1 Power On...................................................................................................................................................905
11.4.2 Power Down..............................................................................................................................................905
11.4.3 Software Functions/Recovery Mode.........................................................................................................906
11.5 Battery Monitor.............................................................................................................................................................907
11.6 Battery Charger.............................................................................................................................................................908
11.7 11.5.1 Battery Detection...............................................................................................................................................909
11.8 Silicon Speed Sensor....................................................................................................................................................909
11.9 Thermal-Overload Protection Circuit...........................................................................................................................910
11.10Bandgap Reference Generator......................................................................................................................................910
11.11Interrupts.......................................................................................................................................................................910
11.12Programmable Registers...............................................................................................................................................911
11.12.1 Power Control Register (HW_POWERCTRL).........................................................................................912
11.12.2 DC-DC 5V Control Register (HW_POWER5VCTRL)............................................................................915
11.12.3 DC-DC Minimum Power and Miscellaneous Control Register (HW_POWERMINPWR)......................917
11.12.4 Battery Charge Control Register (HW_POWERCHARGE).....................................................................919
11.12.5 VDDD Supply Targets and Brownouts Control Register (HW_POWERVDDDCTRL)..........................921
11.12.6 VDDA Supply Targets and Brownouts Control Register (HW_POWERVDDACTRL)...........................923
11.12.7 VDDIO Supply Targets and Brownouts Control Register (HW_POWERVDDIOCTRL)........................924
11.12.8 VDDMEM Supply Targets Control Register (HW_POWERVDDMEMCTRL)......................................926
11.12.9 DC-DC Converter 4.2V Control Register (HW_POWERDCDC4P2)......................................................927
11.12.10DC-DC Miscellaneous Register (HW_POWERMISC)............................................................................929
11.12.11DC-DC Duty Cycle Limits Control Register (HW_POWERDCLIMITS)...............................................930

11.12.12Converter Loop Behavior Control Register (HW_POWERLOOPCTRL)................................................931
11.12.13Power Subsystem Status Register (HW_POWERSTS).............................................................................933
11.12.14Transistor Speed Control and Status Register (HW_POWERSPEED).....................................................936
11.12.15Battery Level Monitor Register (HW_POWERBATTMONITOR)..........................................................937
11.12.16Power Module Reset Register (HW_POWERRESET).............................................................................938
11.12.17Power Module Debug Register (HW_POWERDEBUG)..........................................................................939
11.12.18Power Module Thermal Reset Register (HW_POWERTHERMAL)........................................................940
11.12.19Power Module USB1 Manual Controls Register (HW_POWERUSB1CTRL)........................................941
11.12.20Power Module Special Register (HW_POWERSPECIAL)......................................................................942
11.12.21Power Module Version Register (HW_POWERVERSION).....................................................................943
11.12.22Analog Clock Control Register (HW_POWERANACLKCTRL).............................................................943
11.12.23POWER Reference Control Register (HW_POWERREFCTRL).............................................................945
Chapter 12
Boot Modes
12.1 Overview.......................................................................................................................................................................949
12.2 Boot Modes...................................................................................................................................................................950
12.2.1 Boot Mode Selection Map.........................................................................................................................951
12.3 OTP eFuse and Persistent Bit Definitions....................................................................................................................952
12.3.1 OTP eFuse.................................................................................................................................................952
12.3.2 Persistent Bits............................................................................................................................................957
12.4 Memory Map................................................................................................................................................................958
12.5 General Boot Procedure................................................................................................................................................958
12.6 Program Image..............................................................................................................................................................959
12.6.1 Image Vector Table (IVT)..........................................................................................................................960
12.6.1.1 Image Vector Table Structure..................................................................................................961
12.6.2 Device Configuration Data (DCD)............................................................................................................962
12.6.2.1 Write Data Command.............................................................................................................964
12.6.2.2 Check Data Command............................................................................................................966
12.6.2.3 NOP Command.......................................................................................................................967

12.7 High Assurance Boot (HAB)........................................................................................................................................968
12.7.1 ROM Vector Table Addresses....................................................................................................................969
12.8 Constructing Boot Image (SB Files) to Be Loaded by ROM.......................................................................................969
12.8.1 ROM Commands.......................................................................................................................................970
12.9 I2C Boot Mode.............................................................................................................................................................972
12.10SPI Boot Mode..............................................................................................................................................................972
12.10.1 SSP Pin Configuration...............................................................................................................................973
12.10.2 Media Format............................................................................................................................................973
12.10.3 SSP............................................................................................................................................................974
12.11SD/MMC Boot Mode...................................................................................................................................................975
12.11.1 Boot Control Block (BCB) Data Structure................................................................................................977
12.11.2 Master Boot Record (MBR) Media Format..............................................................................................978
12.11.3 eMMC Fast Boot Media Format...............................................................................................................978
12.11.4 eSD Fast Boot Media Format....................................................................................................................979
12.11.5 Device Identification.................................................................................................................................979
12.12NAND Boot Mode........................................................................................................................................................979
12.12.1 Raw NAND Device Boot..........................................................................................................................979
12.12.1.1 Search Area.............................................................................................................................980
12.12.1.2 Search Count...........................................................................................................................980
12.12.1.3 Search Stride...........................................................................................................................980
12.12.1.4 Boot Control Blocks (BCB)....................................................................................................980
12.12.1.5 Redundant Boot Support in ROM NAND driver....................................................................982
12.12.1.6 NAND Patch Boot using FCB................................................................................................983
12.12.1.7 Expected NAND Layout.........................................................................................................983
12.12.1.8 Firmware Configuration Block...............................................................................................985
12.12.1.9 Single Error Correct and Double Error Detect (SEC-DED) Hamming..................................986
12.12.1.10Firmware Layout on the NAND..............................................................................................986
12.12.1.11Recovery From a Failed Boot Firmware Image Read.............................................................986

12.12.1.12Bad Block Handling in the ROM............................................................................................987
12.12.1.13Firmware Configuration Block Structure and Definitions......................................................989
12.12.1.14Discovered Bad Block Table Header Layout Block Structure and Definitions......................992
12.12.1.15Discovered Bad Block Table Layout Block Structure and Definitions...................................992
12.12.2 Typical NAND Page Organization............................................................................................................992
12.12.2.1 BCH ECC Page Organization.................................................................................................993
12.12.2.2 Metadata..................................................................................................................................994
12.12.2.3 efuses/OTP bits used by ROM NAND Driver........................................................................994
12.12.3 ONFi BA NAND Device Boot..................................................................................................................995
12.13USB Boot Driver...........................................................................................................................................................996
12.13.1 Boot Loader Transaction Controller (BLTC)............................................................................................996
12.13.2 Plug-in Transaction Controller (PITC)......................................................................................................996
12.13.3 USB IDs and Serial Number.....................................................................................................................997
12.13.4 USB Recovery Mode.................................................................................................................................997
Chapter 13
Data Co-Processor (DCP)
13.1 Data Co-Processor (DCP) Overview............................................................................................................................999
13.1.1 DCP Limitations for Software.................................................................................................................1001
13.2 Operation....................................................................................................................................................................1002
13.2.1 Memory Copy, Blit, and Fill Functionality.............................................................................................1002
13.2.2 Advanced Encryption Standard (AES)....................................................................................................1003
13.2.2.1 Key Storage...........................................................................................................................1003
13.2.2.2 OTP Key................................................................................................................................1003
13.2.2.3 Encryption Modes.................................................................................................................1004
13.2.3 Hashing....................................................................................................................................................1005
13.2.4 OTP Key..................................................................................................................................................1006
13.2.5 Managing DCP Channel Arbitration and Performance...........................................................................1006
13.2.5.1 DCP Arbitration....................................................................................................................1006
13.2.5.2 Channel Recovery Timers.....................................................................................................1007

13.2.6 Programming Channel Operations..........................................................................................................1007
13.2.6.1 Virtual Channels....................................................................................................................1008
13.2.6.2 Context Switching.................................................................................................................1008
13.2.6.3 Working with Semaphores....................................................................................................1010
13.2.6.4 Work Packet Structure...........................................................................................................1010
13.2.6.4.1 Next Command Address Field.............................................................................1011
13.2.6.4.2 Control0 Field......................................................................................................1011
13.2.6.4.3 Control1 Field......................................................................................................1013
13.2.6.4.4 Source Buffer.......................................................................................................1014
13.2.6.4.5 Destination Buffer...............................................................................................1014
13.2.6.4.6 Buffer Size Field..................................................................................................1015
13.2.6.4.7 Payload Pointer....................................................................................................1015
13.2.6.4.8 Status...................................................................................................................1015
13.2.6.4.9 Payload................................................................................................................1016
13.2.7 Programming DCP Functions..................................................................................................................1017
13.2.7.1 Basic Memory Copy Programming Example.......................................................................1017
13.2.7.2 Basic Hash Operation Programming Example.....................................................................1018
13.2.7.3 Basic Cipher Operation Programming Example...................................................................1020
13.2.7.4 Multi-Buffer Scatter/Gather Cipher and Hash Operation Programming Example...............1021
13.3 Programmable Registers.............................................................................................................................................1024
13.3.1 DCP Control Register 0 (HW_DCPCTRL).............................................................................................1025
13.3.2 DCP Status Register (HW_DCPSTAT)...................................................................................................1027
13.3.3 DCP Channel Control Register (HW_DCPCHANNELCTRL)..............................................................1028
13.3.4 DCP Capability 0 Register (HW_DCPCAPABILITY0).........................................................................1030
13.3.5 DCP Capability 1 Register (HW_DCPCAPABILITY1).........................................................................1031
13.3.6 DCP Context Buffer Pointer (HW_DCPCONTEXT).............................................................................1031
13.3.7 DCP Key Index (HW_DCPKEY)...........................................................................................................1032
13.3.8 DCP Key Data (HW_DCPKEYDATA)...................................................................................................1033

13.3.9 DCP Work Packet 0 Status Register (HW_DCPPACKET0)...................................................................1034
13.3.16 DCP Channel 0 Command Pointer Address Register (HW_DCPCH0CMDPTR)..................................1040
13.3.17 DCP Channel 0 Semaphore Register (HW_DCPCH0SEMA)................................................................1040
13.3.18 DCP Channel 0 Status Register (HW_DCPCH0STAT)..........................................................................1041
13.3.19 DCP Channel 0 Options Register (HW_DCPCH0OPTS).......................................................................1043
13.3.32 DCP Debug Select Register (HW_DCPDBGSELECT)..........................................................................1057
13.3.33 DCP Debug Data Register (HW_DCPDBGDATA)................................................................................1058
13.3.34 DCP Page Table Register (HW_DCPPAGETABLE)..............................................................................1058
13.3.35 DCP Version Register (HW_DCPVERSION).........................................................................................1059
13.4 Disclaimer...................................................................................................................................................................1060

Chapter 14
External Memory Interface (EMI)
14.1 Overview.....................................................................................................................................................................1061
14.1.1 Block Diagram.........................................................................................................................................1061
14.2 EMI Address Mapping................................................................................................................................................1062
14.2.1 DDR SDRAM Address Mapping Options..............................................................................................1063
14.2.2 Maximum Address Space........................................................................................................................1063
14.2.3 Memory Mapping to Address Space.......................................................................................................1064
14.3 EMI Clocking.............................................................................................................................................................1064
14.3.1 General System Behavior........................................................................................................................1064
14.3.2 Changing Input Clock Frequency............................................................................................................1064
14.4 EMI AHB and AXI Interface......................................................................................................................................1066
14.4.1 AHB-AXI Bridges...................................................................................................................................1066
14.4.2 AXI Interfaces.........................................................................................................................................1066
14.4.2.1 Internal Command Handling.................................................................................................1066
14.4.2.2 AHB Signal to AXI Signal Translation.................................................................................1068
14.4.2.3 Configured Options...............................................................................................................1068
14.4.3 Port Clocking...........................................................................................................................................1070
14.4.4 AXI Interface FIFOs................................................................................................................................1071
14.4.5 AXI Write Response Channel.................................................................................................................1072
14.4.6 AHB Register Port...................................................................................................................................1073
14.4.7 AXI Transactions.....................................................................................................................................1073
14.4.8 Exclusive Access.....................................................................................................................................1073
14.4.8.1 Initiating an Exclusive Access Request.................................................................................1074
14.4.8.2 Verifying the Request............................................................................................................1074
14.4.8.3 Validity of an Exclusive Request..........................................................................................1074
14.4.8.4 Read Commands to Exclusive Access Regions....................................................................1075
14.4.8.5 Non-Exclusive Write Commands to Exclusive Access Regions...........................................1075
14.4.8.6 Exclusive Writes....................................................................................................................1075

14.4.8.7 Passing Exclusive Access Check...........................................................................................1076
14.4.8.8 Failing Exclusive Access Check...........................................................................................1076
14.4.9 Error Responses.......................................................................................................................................1076
14.4.9.1 AXI Error Response..............................................................................................................1076
14.4.9.2 AXI Error Reporting.............................................................................................................1077
14.4.10 Arbiter......................................................................................................................................................1077
14.4.11 Write Data Queue....................................................................................................................................1077
14.4.12 DRAM Command Processing.................................................................................................................1077
14.4.13 Latency....................................................................................................................................................1078
14.5 EMI Multi-Port Arbiter...............................................................................................................................................1080
14.5.1 Arbitration Overview...............................................................................................................................1081
14.5.2 Understanding Round-Robin Arbitration................................................................................................1081
14.5.3 Understanding Port Priority.....................................................................................................................1082
14.5.4 Understanding Port Bandwidth...............................................................................................................1083
14.5.5 Understanding Port Bandwidth Hold-Off................................................................................................1085
14.5.6 Priority Round-Robin Arbitration Summary...........................................................................................1086
14.5.7 Arbitration Examples...............................................................................................................................1087
14.5.8 Configuring and Programming for Priority Round-Robin Arbitration....................................................1089
14.5.8.1 Definition of the Statistics Window and the Number of Counters........................................1089
14.5.8.2 Command Priority, Port Bandwidth, and Bandwidth Overflow...........................................1089
14.5.9 Command Queue with Placement Logic.................................................................................................1090
14.6 Core Command Queue with Placement Logic...........................................................................................................1090
14.6.1 Rules of the Placement Algorithm...........................................................................................................1090
14.6.1.1 Address Collision/Data Coherency Violation.......................................................................1091
14.6.1.2 Source ID Collision...............................................................................................................1091
14.6.1.3 Write Buffer Collision...........................................................................................................1092
14.6.1.4 Priority..................................................................................................................................1092
14.6.1.5 Bank Splitting.......................................................................................................................1092

14.6.1.6 Read/Write Grouping............................................................................................................1093
14.6.2 Command Execution Order After Placement..........................................................................................1093
14.6.2.1 Command Aging...................................................................................................................1093
14.6.2.2 High-Priority Command Swapping.......................................................................................1094
14.7 DDR PHY...................................................................................................................................................................1095
14.7.1 High Level Block Diagram......................................................................................................................1095
14.7.2 DFI...........................................................................................................................................................1096
14.7.3 I/O Timing of Address and Command.....................................................................................................1096
14.7.4 Data Slice Overview................................................................................................................................1098
14.7.5 Read Data Capture...................................................................................................................................1099
14.7.6 Synchronize Read Data From delayed_dqs to emi_clk Domain.............................................................1099
14.7.7 Write Data Path.......................................................................................................................................1101
14.7.8 Write Data Path Low-Latency Option ....................................................................................................1102
14.7.9 Digital DLL and the Delay-Line.............................................................................................................1102
14.7.10 Configure output enable of I/O Control..................................................................................................1105
14.8.1 DRAM Control Register 00 (HW_DRAMCTL00).................................................................................1111
14.8.2 AXI Monitor Control (HW_DRAMCTL01)...........................................................................................1112
14.8.11 AXI0 Debug 0 (HW_DRAMCTL10)......................................................................................................1118



14.8.95 DRAM Control Register 100 (HW_DRAMCTL100).............................................................................1188

14.8.100DRAM Control Register 105 (HW_DRAMCTL105).............................................................................1192


Chapter 15
General-Purpose Media Interface(GPMI)
15.1 General-Purpose Media Interface Overview...............................................................................................................1239
15.2 GPMI NAND Mode....................................................................................................................................................1240
15.2.1 Multiple NAND Support.........................................................................................................................1241
15.2.2 GPMI NAND Timing and Clocking........................................................................................................1241

15.2.3 Basic NAND Timing...............................................................................................................................1242
15.2.4 High-Speed NAND Timing.....................................................................................................................1242
15.2.5 NAND Command and Address Timing Example....................................................................................1244
15.2.6 Hardware BCH Interface.........................................................................................................................1245
15.3 Behavior During Reset................................................................................................................................................1245
15.4.1 GPMI Control Register 0 (HW_GPMICTRL0)......................................................................................1246
15.4.2 GPMI Compare Register (HW_GPMICOMPARE)................................................................................1248
15.4.3 GPMI Integrated ECC Control Register (HW_GPMIECCCTRL).........................................................1248
15.4.4 GPMI Integrated ECC Transfer Count Register (HW_GPMIECCCOUNT)..........................................1250
15.4.5 GPMI Payload Address Register (HW_GPMIPAYLOAD).....................................................................1250
15.4.6 GPMI Auxiliary Address Register (HW_GPMIAUXILIARY)...............................................................1251
15.4.7 GPMI Control Register 1 (HW_GPMICTRL1)......................................................................................1251
15.4.8 GPMI Timing Register 0 (HW_GPMITIMING0)...................................................................................1253
15.4.9 GPMI Timing Register 1 (HW_GPMITIMING1)...................................................................................1254
15.4.10 GPMI DMA Data Transfer Register (HW_GPMIDATA).......................................................................1254
15.4.11 GPMI Status Register (HW_GPMISTAT)...............................................................................................1255
15.4.12 GPMI Debug Information Register (HW_GPMIDEBUG).....................................................................1257
15.4.13 GPMI Version Register (HW_GPMIVERSION)....................................................................................1258
Chapter 16
20-BIT Correcting ECC Accelerator (BCH)
16.1 BCH Overview............................................................................................................................................................1259
16.2 Operation....................................................................................................................................................................1261
16.2.1 BCH Limitations and Assumptions.........................................................................................................1262
16.2.2 Flash Page Layout...................................................................................................................................1263
16.2.3 Determining the ECC layout for a device...............................................................................................1264
16.2.3.1 4K+218 flash, 10 bytes metadata, 512 byte data blocks, separate metadata........................1264
16.2.3.2 4K+128 flash, 10 bytes metadata, 512 byte data blocks, separate metadata........................1265
16.2.4 Data Buffers in System Memory.............................................................................................................1266

16.3 Memory to Memory (Loopback) Operation...............................................................................................................1268
16.4 Programming the BCH/GPMI Interfaces...................................................................................................................1269
16.4.1 BCH Encoding for NAND Writes...........................................................................................................1269
16.4.1.1 DMA Structure Code Example.............................................................................................1272
16.4.1.2 Using the BCH Encoder........................................................................................................1276
16.4.2 BCH Decoding for NAND Reads............................................................................................................1277
16.4.2.1 DMA Structure Code Example.............................................................................................1280
16.4.2.2 Using the Decoder.................................................................................................................1284
16.4.3 Interrupts..................................................................................................................................................1286
16.6.1 Hardware BCH ECC Accelerator Control Register (HW_BCHCTRL)..................................................1288
16.6.2 Hardware ECC Accelerator Status Register 0 (HW_BCHSTATUS0)....................................................1290
16.6.3 Hardware ECC Accelerator Mode Register (HW_BCHMODE)............................................................1292
16.6.4 Hardware BCH ECC Loopback Encode Buffer Register (HW_BCHENCODEPTR)............................1293
16.6.5 Hardware BCH ECC Loopback Data Buffer Register (HW_BCHDATAPTR)......................................1293
16.6.6 Hardware BCH ECC Loopback Metadata Buffer Register (HW_BCHMETAPTR)..............................1294
16.6.7 Hardware ECC Accelerator Layout Select Register (HW_BCHLAYOUTSELECT).............................1294
16.6.8 Hardware BCH ECC Flash 0 Layout 0 Register (HW_BCHFLASH0LAYOUT0)................................1296
16.6.16 Hardware BCH ECC Debug Register0 (HW_BCHDEBUG0)...............................................................1305
16.6.17 KES Debug Read Register (HW_BCHDBGKESREAD).......................................................................1307

16.6.18 Chien Search Debug Read Register (HW_BCHDBGCSFEREAD).......................................................1308
16.6.19 Syndrome Generator Debug Read Register (HW_BCHDBGSYNDGENREAD)..................................1308
16.6.20 Bus Master and ECC Controller Debug Read Register (HW_BCHDBGAHBMREAD).......................1309
16.6.21 Block Name Register (HW_BCHBLOCKNAME).................................................................................1309
16.6.22 BCH Version Register (HW_BCHVERSION)........................................................................................1310
Chapter 17
Synchronous Serial Ports (SSP)
17.1 Overview.....................................................................................................................................................................1311
17.2 External Pins...............................................................................................................................................................1313
17.3 Bit Rate Generation....................................................................................................................................................1313
17.4 Frame Format for SPI and SSI....................................................................................................................................1314
17.5 Motorola SPI Mode....................................................................................................................................................1314
17.5.1 SPI DMA Mode.......................................................................................................................................1315
17.5.2 Motorola SPI Frame Format....................................................................................................................1315
17.5.2.1 Clock Polarity.......................................................................................................................1315
17.5.2.2 Clock Phase...........................................................................................................................1315
17.5.3 Motorola SPI Format with Polarity=0, Phase=0.....................................................................................1315
17.6 Winbond SPI Mode.....................................................................................................................................................1320
17.7 Texas Instruments Synchronous Serial Interface (SSI) Mode....................................................................................1320
17.8 SD/SDIO/MMC Mode................................................................................................................................................1321
17.8.1 SD/MMC Command/Response Transfer.................................................................................................1322
17.8.2 SD/MMC Data Block Transfer................................................................................................................1323
17.8.2.1 SD/MMC Multiple Block Transfers.....................................................................................1325
17.8.2.2 eMMC DDR operation..........................................................................................................1325
17.8.2.3 SD/MMC Block Transfer CRC Protection...........................................................................1326
17.8.3 eMMC Boot Operation............................................................................................................................1326

17.8.4 SDIO Interrupts.......................................................................................................................................1327
17.8.5 SD/MMC Mode Error Handling.............................................................................................................1327
17.8.6 SD/MMC Clock Control.........................................................................................................................1329
17.10Programmable Registers.............................................................................................................................................1330
17.10.1 SSP Control Register 0 (HW_SSPCTRL0).............................................................................................1331
17.10.2 SD/MMC Command Register 0 (HW_SSPCMD0)................................................................................1333
17.10.3 SD/MMC Command Register 1 (HW_SSPCMD1)................................................................................1336
17.10.4 Transfer Count Register (HW_SSPXFER_SIZE)...................................................................................1336
17.10.5 SD/MMC BLOCK SIZE and COUNT Register (HW_SSPBLOCK_SIZE)..........................................1337
17.10.6 SD/MMC Compare Reference (HW_SSPCOMPREF)...........................................................................1337
17.10.7 SD/MMC compare mask (HW_SSPCOMPMASK)...............................................................................1338
17.10.8 SSP Timing Register (HW_SSPTIMING)..............................................................................................1338
17.10.9 SSP Control Register 1 (HW_SSPCTRL1).............................................................................................1339
17.10.10SSP Data Register (HW_SSPDATA).......................................................................................................1342
17.10.11SD/MMC Card Response Register 0 (HW_SSPSDRESP0)...................................................................1342
17.10.15SD/MMC Double Data Rate Control Register (HW_SSPDDR_CTRL)................................................1344
17.10.16SD/MMC DLL Control Register (HW_SSPDLL_CTRL)......................................................................1345
17.10.17SSP Status Register (HW_SSPSTATUS)................................................................................................1346
17.10.18SD/MMC DLL Status Register (HW_SSPDLL_STS)............................................................................1348
17.10.19SSP Debug Register (HW_SSPDEBUG)................................................................................................1349
17.10.20SSP Version Register (HW_SSPVERSION)...........................................................................................1350
Chapter 18
Boundary Scan Interface
18.1 Boundary Scan Interface.............................................................................................................................................1353

Chapter 19
Digital Control (DIGCTL) and On-Chip RAM
19.1 Overview.....................................................................................................................................................................1355
19.2 SRAM Controls..........................................................................................................................................................1356
19.3 Miscellaneous Controls...............................................................................................................................................1357
19.3.1 Performance Monitoring.........................................................................................................................1357
19.3.2 High-Entropy PRN Seed.........................................................................................................................1358
19.3.3 Write-Once Register................................................................................................................................1358
19.3.4 Microseconds Counter.............................................................................................................................1358
19.4.1 DIGCTL Control Register (HW_DIGCTLCTRL)..................................................................................1361
19.4.2 DIGCTL Status Register (HW_DIGCTLSTATUS)................................................................................1364
19.4.3 Free-Running HCLK Counter Register (HW_DIGCTLHCLKCOUNT)...............................................1366
19.4.4 On-Chip RAM Control Register (HW_DIGCTLRAMCTRL)...............................................................1367
19.4.5 EMI Status Register (HW_DIGCTLEMI_STATUS)..............................................................................1368
19.4.6 On-Chip Memories Read Margin Register (HW_DIGCTLREAD_MARGIN)......................................1369
19.4.7 Software Write-Once Register (HW_DIGCTLWRITEONCE)..............................................................1369
19.4.8 BIST Control Register (HW_DIGCTLBIST_CTL)................................................................................1370
19.4.9 DIGCTL Status Register (HW_DIGCTLBIST_STATUS).....................................................................1372
19.4.10 Entropy Register (HW_DIGCTLENTROPY).........................................................................................1375
19.4.11 Entropy Latched Register (HW_DIGCTLENTROPY_LATCHED).......................................................1376
19.4.12 Digital Control Microseconds Counter Register (HW_DIGCTLMICROSECONDS)...........................1376
19.4.13 Digital Control Debug Read Test Register (HW_DIGCTLDBGRD).....................................................1377
19.4.14 Digital Control Debug Register (HW_DIGCTLDBG)............................................................................1377
19.4.15 USB LOOP BACK (HW_DIGCTLUSB_LOOPBACK)........................................................................1378
19.4.16 SRAM Status Register 0 (HW_DIGCTLOCRAM_STATUS0)..............................................................1380

19.4.26 SRAM Status Register 10 (HW_DIGCTLOCRAM_STATUS10)..........................................................1387
19.4.30 Digital Control Scratch Register 0 (HW_DIGCTLSCRATCH0)............................................................1391
19.4.31 Digital Control Scratch Register 1 (HW_DIGCTLSCRATCH1)............................................................1392
19.4.32 Digital Control ARM Cache Register (HW_DIGCTLARMCACHE)....................................................1392
19.4.33 Debug Trap Control and Status for AHB Layer 0 and 3 (HW_DIGCTLDEBUG_TRAP)....................1393
19.4.34 Debug Trap Range Low Address for AHB Layer 0 (HW_DIGCTLDEBUG_TRAP_L0_ADDR_LOW).1395
19.4.35 Debug Trap Range High Address for AHB Layer 0 (HW_DIGCTLDEBUG_TRAP_L0_ADDR_HIGH).1396
19.4.36 Debug Trap Range Low Address for AHB Layer 3 (HW_DIGCTLDEBUG_TRAP_L3_ADDR_LOW).1396
19.4.37 Debug Trap Range High Address for AHB Layer 3 (HW_DIGCTLDEBUG_TRAP_L3_ADDR_HIGH).1397
19.4.38 Freescale Copyright Identifier Register (HW_DIGCTLFSL).................................................................1397
19.4.39 Digital Control Chip Revision Register (HW_DIGCTLCHIPID)..........................................................1398
19.4.40 AHB Statistics Control Register (HW_DIGCTLAHB_STATS_SELECT)............................................1399
19.4.41 AHB Layer 1 Transfer Count Register (HW_DIGCTLL1_AHB_ACTIVE_CYCLES)........................1400
19.4.42 AHB Layer 1 Performance Metric for Stalled Bus Cycles Register
(HW_DIGCTLL1_AHB_DATA_STALLED).........................................................................................1401
19.4.43 AHB Layer 1 Performance Metric for Valid Bus Cycles Register
(HW_DIGCTLL1_AHB_DATA_CYCLES)...........................................................................................1401

19.4.50 Default First Level Page Table Movable PTE Locator 0 (HW_DIGCTLMPTE0_LOC).......................1406
19.4.51 Default First-Level Page Table Movable PTE Locator 1 (HW_DIGCTLMPTE1_LOC).......................1407
19.4.60 Default First-Level Page Table Movable PTE Locator 10 (HW_DIGCTLMPTE10_LOC)...................1415
Chapter 20
On-Chip OTP (OCOTP) Controller
20.1 OCOTP Overview.......................................................................................................................................................1421
20.2 Operation....................................................................................................................................................................1422
20.2.1 Software Read Sequence.........................................................................................................................1424
20.2.2 Software Write Sequence........................................................................................................................1425
20.2.3 Write Postamble......................................................................................................................................1426

20.2.4 Shadow Registers and Hardware Capability Bus....................................................................................1427
20.4.1 OTP Controller Control Register (HW_OCOTPCTRL).........................................................................1430
20.4.2 OTP Controller Write Data Register (HW_OCOTPDATA)....................................................................1432
20.4.3 Value of OTP Bank0 Word0 (Customer) (HW_OCOTPCUST0)...........................................................1432
20.4.7 Value of OTP Bank0 Word4 (Crypto Key) (HW_OCOTPCRYPTO0)...................................................1434
20.4.11 HW Capability Shadow Register 0 (HW_OCOTPHWCAP0)................................................................1436
20.4.17 SW Capability Shadow Register (HW_OCOTPSWCAP)......................................................................1439
20.4.18 Customer Capability Shadow Register (HW_OCOTPCUSTCAP).........................................................1440
20.4.19 LOCK Shadow Register OTP Bank 2 Word 0 (HW_OCOTPLOCK).....................................................1441
20.4.20 Value of OTP Bank2 Word1 (Freescale OPS0) (HW_OCOTPOPS0)....................................................1443
20.4.24 Value of OTP Bank2 Word5 (Unassigned0) (HW_OCOTPUN0)...........................................................1445

20.4.27 Shadow Register for OTP Bank3 Word0 (ROM Use 0) (HW_OCOTPROM0)......................................1447
20.4.35 Shadow Register for OTP Bank4 Word0 (Data Use 0) (HW_OCOTPSRK0)........................................1457
20.4.43 OTP Controller Version Register (HW_OCOTPVERSION)..................................................................1461
Chapter 21
Performance Monitor (PERFMON)
21.1 Overview.....................................................................................................................................................................1463
21.2 Operation....................................................................................................................................................................1464
21.3.1 PerfMon Control Register (HW_PERFMONCTRL)..............................................................................1466
21.3.2 PerfMon Master Enable Register (HW_PERFMONMASTER_EN)......................................................1468
21.3.3 PerfMon Trap Range Low Address Register (HW_PERFMONTRAP_ADDR_LOW).........................1469
21.3.4 PerfMon Trap Range High Address Register (HW_PERFMONTRAP_ADDR_HIGH).......................1469
21.3.5 PerfMon Latency Threshold Register (HW_PERFMONLAT_THRESHOLD).....................................1470
21.3.6 PerfMon AXI Active Cycle Count Register (HW_PERFMONACTIVE_CYCLE)................................1470

21.3.7 PerfMon Transfer Count Register (HW_PERFMONTRANSFER_COUNT)........................................1471
21.3.8 PerfMon Total Latency Count Register (HW_PERFMONTOTAL_LATENCY)...................................1472
21.3.9 PerfMon Total Data Count Register (HW_PERFMONDATA_COUNT)...............................................1472
21.3.10 PerfMon Maximum Latency Register (HW_PERFMONMAX_LATENCY)........................................1473
21.3.11 PerfMon Debug Register (HW_PERFMONDEBUG)............................................................................1473
21.3.12 PerfMon Version Register (HW_PERFMONVERSION).......................................................................1474
Chapter 22
Real-Time Clock Alarm Watchdog Persistent Bits
22.1 RTC Overview............................................................................................................................................................1477
22.2 Programming and Enabling the RTC Clock...............................................................................................................1480
22.3 RTC Persistent Register Copy Control.......................................................................................................................1480
22.4 Real-Time Clock Function..........................................................................................................................................1482
22.4.1 Behavior During Reset............................................................................................................................1482
22.5 Millisecond Resolution Timing Function...................................................................................................................1482
22.6 Alarm Clock Function................................................................................................................................................1483
22.7 Watchdog Reset Function...........................................................................................................................................1483
22.8.1 Real-Time Clock Control Register (HW_RTCCTRL)............................................................................1485
22.8.2 Real-Time Clock Status Register (HW_RTCSTAT)................................................................................1486
22.8.3 Real-Time Clock Milliseconds Counter (HW_RTCMILLISECONDS).................................................1488
22.8.4 Real-Time Clock Seconds Counter (HW_RTCSECONDS)...................................................................1489
22.8.5 Real-Time Clock Alarm Register (HW_RTCALARM)..........................................................................1490
22.8.6 Watchdog Timer Register (HW_RTCWATCHDOG)..............................................................................1491
22.8.7 Persistent State Register 0 (HW_RTCPERSISTENT0)..........................................................................1492

22.8.13 Real-Time Clock Debug Register (HW_RTCDEBUG)..........................................................................1498
22.8.14 Real-Time Clock Version Register (HW_RTCVERSION).....................................................................1499
Chapter 23
Timers and Rotary Decoder (TIMROT)
23.1 Timers and Rotary Decoder (TIMROT) Overview.....................................................................................................1501
23.2 Timer...........................................................................................................................................................................1502
23.2.1 Fixed count mode....................................................................................................................................1502
23.2.2 Match count mode...................................................................................................................................1503
23.2.3 Using External Signals as Inputs.............................................................................................................1505
23.2.4 Timer 3 and Duty Cycle Mode................................................................................................................1505
23.3 Rotary Decoder...........................................................................................................................................................1507
23.4.1 Rotary Decoder Control Register (HW_TIMROTROTCTRL)...............................................................1510
23.4.2 Rotary Decoder Up/Down Counter Register (HW_TIMROTROTCOUNT)..........................................1513
23.4.3 Timer 0 Control and Status Register (HW_TIMROTTIMCTRL0).........................................................1513
23.4.4 Timer 0 Runing Count Register (HW_TIMROTRUNNING_COUNT0)...............................................1515
23.4.5 Timer 0 Fixed Count Register (HW_TIMROTFIXED_COUNT0).........................................................1516
23.4.6 Timer 0 Match Count Register (HW_TIMROTMATCH_COUNT0).....................................................1516
23.4.16 Timer 3 Running Count Register (HW_TIMROTRUNNING_COUNT3).............................................1526

23.4.17 Timer 3 Count Register (HW_TIMROTFIXED_COUNT3)...................................................................1527
23.4.19 TIMROT Version Register (HW_TIMROTVERSION)..........................................................................1528
Chapter 24
Debug UART (DUART)
24.1 Debug UART Overview..............................................................................................................................................1529
24.2 Operation....................................................................................................................................................................1530
24.2.1 Fractional Baud Rate Divider..................................................................................................................1531
24.2.2 UART Character Frame...........................................................................................................................1531
24.2.3 Data Transmission or Reception..............................................................................................................1531
24.2.4 Error Bits.................................................................................................................................................1532
24.2.5 Overrun Bit..............................................................................................................................................1532
24.2.6 Disabling the FIFOs................................................................................................................................1533
24.3.1 UART Data Register (HW_UARTDBGDR)...........................................................................................1534
24.3.2 UART Receive Status Register (Read) / Error Clear Register (Write) (HW_UARTDBGECR).............1535
24.3.3 UART Flag Register (HW_UARTDBGFR)............................................................................................1536
24.3.4 UART IrDA Low-Power Counter Register (HW_UARTDBGILPR)......................................................1537
24.3.5 UART Integer Baud Rate Divisor Register (HW_UARTDBGIBRD).....................................................1537
24.3.6 UART Fractional Baud Rate Divisor Register (HW_UARTDBGFBRD)...............................................1538
24.3.7 UART Line Control Register, HIGH Byte (HW_UARTDBGH)............................................................1539
24.3.8 UART Control Register (HW_UARTDBGCR).......................................................................................1539
24.3.9 UART Interrupt FIFO Level Select Register (HW_UARTDBGIFLS)....................................................1541
24.3.10 UART Interrupt Mask Set/Clear Register (HW_UARTDBGIMSC).......................................................1542
24.3.11 UART Raw Interrupt Status Register (HW_UARTDBGRIS).................................................................1543
24.3.12 UART Masked Interrupt Status Register (HW_UARTDBGMIS)...........................................................1545
24.3.13 UART Interrupt Clear Register (HW_UARTDBGICR)..........................................................................1546
24.3.14 UART DMA Control Register (HW_UARTDBGDMACR)...................................................................1547

Chapter 25
Controller Area Network (FlexCAN)
25.1 FlexCAN Introduction................................................................................................................................................1549
25.2 Overview.....................................................................................................................................................................1550
25.2.1 Features....................................................................................................................................................1550
25.2.2 Modes of Operation.................................................................................................................................1551
25.3 Message Buffer Structure...........................................................................................................................................1552
25.3.1 Rx FIFO Structure...................................................................................................................................1556
25.4 Functional Description................................................................................................................................................1558
25.4.1 Overview..................................................................................................................................................1558
25.4.2 Transmit Process......................................................................................................................................1558
25.4.3 Arbitration Process..................................................................................................................................1559
25.4.4 Receive Process.......................................................................................................................................1560
25.4.5 Matching Process.....................................................................................................................................1562
25.4.6 Data Coherence.......................................................................................................................................1564
25.4.6.1 Transmission Abort Mechanism............................................................................................1564
25.4.7 Message Buffer Deactivation...................................................................................................................1565
25.4.8 Message Buffer Lock Mechanism...........................................................................................................1566
25.4.9 Rx FIFO...................................................................................................................................................1567
25.4.10 CAN Protocol Related Features.....................................................................................................................?
25.4.10.1 Remote Frames.....................................................................................................................1568
25.4.10.2 Overload Frames...................................................................................................................1569
25.4.10.3 Time Stamp...........................................................................................................................1569
25.4.10.4 Protocol Timing.....................................................................................................................1569
25.4.10.5 Arbitration and Matching Timing.........................................................................................1571
25.4.11 Modes of Operation Details...........................................................................................................................?
25.4.11.1 Freeze Mode..........................................................................................................................1572
25.4.11.2 Module Disable Mode ..........................................................................................................1573
25.4.11.3 Stop Mode.............................................................................................................................1573

25.4.11.4 Interrupts...............................................................................................................................1575
25.5 Initialization/Application Information........................................................................................................................1575
25.5.1 FlexCAN Initialization Sequence............................................................................................................1575
25.6.1 Module Configuration Register (HW_CANMCR).................................................................................1578
25.6.2 Control Register (HW_CANCTRL)........................................................................................................1580
25.6.3 Free Running Timer (HW_CANTIMER)...............................................................................................1582
25.6.4 Rx Global Mask (HW_CANRXGMASK)..............................................................................................1583
25.6.5 Rx 14 Mask (HW_CANRX14MASK)....................................................................................................1583
25.6.6 Rx 15 Mask (HW_CANRX15MASK)....................................................................................................1584
25.6.7 Error Counter Register (HW_CANECR)................................................................................................1584
25.6.8 Error and Status Register (HW_CANESR).............................................................................................1586
25.6.9 Interrupt Masks 2 Register (HW_CANIMASK2)...................................................................................1587
25.6.10 Interrupt Masks 1 Register (HW_CANIMASK1)...................................................................................1588
25.6.11 Interrupt Flags 2 Register (HW_CANIFLAG2)......................................................................................1588
25.6.12 Interrupt Flags 1 Register (HW_CANIFLAG1)......................................................................................1589
25.6.13 Glitch Filter Width Register (HW_CANGFWR)....................................................................................1590
25.6.14 CAN Messager Buffer Registers (HW_CANMBn)................................................................................1590
25.6.15 Rx Individual Mask Registers (HW_CANRXIMRn)..............................................................................1591
Chapter 26
Ethernet Controller (ENET)
26.1 Overview.....................................................................................................................................................................1593
26.1.1 Block Diagram.........................................................................................................................................1593
26.1.2 Features....................................................................................................................................................1593
26.2 Unified DMA Block Guide.........................................................................................................................................1594
26.2.1 Introduction.............................................................................................................................................1594
26.2.1.1 Overview...............................................................................................................................1595
26.2.1.2 Features.................................................................................................................................1595
26.2.1.3 Modes of Operation..............................................................................................................1596

26.2.1.3.1 Legacy Mode.......................................................................................................1596
26.2.1.3.2 Enhanced Mode...................................................................................................1596
26.2.2 Functional Description............................................................................................................................1596
26.2.2.1 Legacy Buffer Descriptor Models.........................................................................................1597
26.2.2.1.1 Legacy FEC Receive Buffer Descriptor..............................................................1597
26.2.2.1.20 Legacy FEC Transmit Buffer Descriptor.............................................................1599
26.2.2.31 Enhanced Buffer Descriptor Models.....................................................................................1600
26.2.2.31.1 Enhanced uDMA Receive Buffer Descriptor......................................................1600
26.2.2.31.23Enhanced uDMA Transmit Buffer Descriptor.....................................................1604
26.3 Ethernet ENET-MAC Core.........................................................................................................................................1607
26.3.1 Introduction.............................................................................................................................................1607
26.3.2 10 100Mbps Ethernet ENET-MAC Core Features..................................................................................1608
26.3.2.1 Ethernet MAC Features.........................................................................................................1608
26.3.2.2 IP Protocol Performance Optimization Features..................................................................1609
26.3.2.3 IEEE 1588 Functions............................................................................................................1610
26.3.3 ENET-MAC Core Block Diagram...........................................................................................................1611
26.3.4 Ethernet MAC Frame Formats................................................................................................................1611
26.3.4.1 Overview...............................................................................................................................1611
26.3.4.2 Pause Frames.........................................................................................................................1613
26.3.4.3 Magic Packets.......................................................................................................................1613
26.3.5 IP and Higher Layers Frame Format.......................................................................................................1614
26.3.5.1 Definitions.............................................................................................................................1614
26.3.5.2 Ethernet Types.......................................................................................................................1614
26.3.5.3 IPv4 Datagram Format..........................................................................................................1614
26.3.5.4 IPv6 Datagram Format..........................................................................................................1615
26.3.5.5 ICMP Datagram Format........................................................................................................1616
26.3.5.6 UDP Datagram Format.........................................................................................................1617
26.3.5.7 TCP Datagram Format..........................................................................................................1617

26.3.6 IEEE 1588 Message Formats..................................................................................................................1618
26.3.6.1 Transport Encapsulation........................................................................................................1618
26.3.6.1.1 UDP/IP................................................................................................................1619
26.3.6.1.2 Native Ethernet (PTPv2)......................................................................................1619
26.3.6.2 PTP Header...........................................................................................................................1619
26.3.6.2.1 PTPv1 Header......................................................................................................1620
26.3.6.2.2 PTPv2 Header......................................................................................................1621
26.3.7 MAC Receive..........................................................................................................................................1622
26.3.7.1 Overview...............................................................................................................................1622
26.3.7.2 Collision Detection in Half Duplex Mode............................................................................1623
26.3.7.3 Preamble Processing.............................................................................................................1624
26.3.7.4 MAC Address Check...................................................................................................................?
26.3.7.4.1 Overview..............................................................................................................1624
26.3.7.4.2 Unicast Address Check........................................................................................1624
26.3.7.4.3 Multicast and Unicast Address Resolution..........................................................1624
26.3.7.4.4 Broadcast Address Reject....................................................................................1625
26.3.7.4.5 Miss-Bit Implementation.....................................................................................1625
26.3.7.5 Frame Length Type Verification..................................................................................................?
26.3.7.5.1 Payload Length Check.........................................................................................1626
26.3.7.5.2 Frame Length Check...........................................................................................1626
26.3.7.6 VLAN Frames Processing....................................................................................................1627
26.3.7.7 Pause Frame Termination......................................................................................................1627
26.3.7.8 CRC Check...........................................................................................................................1627
26.3.7.9 Frame Padding Remove........................................................................................................1628
26.3.8 MAC Transmit.........................................................................................................................................1628
26.3.8.1 Overview...............................................................................................................................1628
26.3.8.2 Frame Payload Padding.........................................................................................................1629
26.3.8.3 MAC Address Insertion.........................................................................................................1629
26.3.8.4 CRC-32 generation...............................................................................................................1629

26.3.8.5 Inter Packet Gap....................................................................................................................1630
26.3.8.6 Collision Detection and Handling - Half Duplex Operation Only........................................1630
26.3.9 Full Duplex Flow Control Operation.......................................................................................................1631
26.3.9.1 Overview...............................................................................................................................1631
26.3.9.2 Remote Device Congestion...................................................................................................1632
26.3.9.3 Local Device / FIFO Congestion..........................................................................................1632
26.3.10 Magic Packet Detection...........................................................................................................................1634
26.3.10.1 Overview...............................................................................................................................1634
26.3.10.2 Sleep Mode...........................................................................................................................1634
26.3.10.3 Magic Packet Detection........................................................................................................1634
26.3.10.4 Wakeup..................................................................................................................................1635
26.3.11 IP Accelerator Functions.........................................................................................................................1635
26.3.11.1 Checksum Calculation..........................................................................................................1635
26.3.11.2 Additional Padding Processing.............................................................................................1636
26.3.11.3 32-bit Ethernet Payload Alignment.......................................................................................1636
26.3.11.4 Received Frame Discard.......................................................................................................1637
26.3.11.5 IPv4 Fragments.....................................................................................................................1638
26.3.11.6 IP Version 6 IPv6 Support...........................................................................................................?
26.3.11.6.1 Receive Processing..............................................................................................1638
26.3.11.6.2 Transmit Processing............................................................................................1639
26.3.12 Resets and Stop Controls.........................................................................................................................1639
26.3.12.1 Hardware Reset.....................................................................................................................1639
26.3.12.2 Soft Reset..............................................................................................................................1639
26.3.12.3 Graceful Stop........................................................................................................................1639
26.3.12.4 Graceful Transmit Stop (GTS)..............................................................................................1640
26.3.12.5 Graceful Receive Stop (GRS)...............................................................................................1640
26.3.12.6 Graceful Stop Interrupt (GRA).............................................................................................1641
26.3.13 IEEE 1588 Functions...............................................................................................................................1641

26.3.13.1 Overview...............................................................................................................................1641
26.3.13.2 Adjustable Timer Module............................................................................................................?
26.3.13.2.1 Overview..............................................................................................................1642
26.3.13.2.2 Adjustable Timer Implementation.......................................................................1642
26.3.13.3 Timer Synchronization for Multi-Port Implementations......................................................1643
26.3.13.4 Transmit Timestamping........................................................................................................1644
26.3.13.5 Receive Timestamping..........................................................................................................1644
26.3.13.6 Time Synchronization...........................................................................................................1644
26.3.13.7 Capture/Compare Block........................................................................................................1645
26.3.14 FIFO Thresholds......................................................................................................................................1645
26.3.14.1 Overview...............................................................................................................................1645
26.3.14.2 Receive FIFO........................................................................................................................1645
26.3.14.3 Transmit FIFO.......................................................................................................................1647
26.3.15 Loopback Options...................................................................................................................................1648
26.3.15.1 Overview...............................................................................................................................1648
26.3.16 FIFO Protection.......................................................................................................................................1649
26.3.16.1 Transmit FIFO Underflow.....................................................................................................1649
26.3.16.2 Transmit FIFO Overflow.......................................................................................................1649
26.3.16.3 Receive FIFO Overflow........................................................................................................1650
26.3.17 PHY Management Interface....................................................................................................................1650
26.3.17.1 Overview...............................................................................................................................1650
26.3.17.2 MDIO Frame Format............................................................................................................1650
26.3.17.3 MDIO Clock Generation.......................................................................................................1651
26.3.17.4 MDIO Operation...................................................................................................................1651
26.3.17.5 MDIO Buffer Connection.....................................................................................................1652
26.3.18 MII Interface............................................................................................................................................1652
26.3.18.1 Transmit................................................................................................................................1652
26.3.18.2 Transmit with Collision - Half Duplex.................................................................................1653
26.3.18.3 Receive..................................................................................................................................1653

26.3.19 MII Interface Timing Characteristics......................................................................................................1654
26.4.1 ENET MAC Interrupt Event Register (HW_ENETMAC_EIR).............................................................1661
26.4.2 ENET MAC Interrupt Mask Register (HW_ENETMAC_EIMR)..........................................................1663
26.4.3 ENET MAC Receive Descriptor Active Register (HW_ENETMAC_RDAR).......................................1663
26.4.4 ENET MAC Transmit Descriptor Active Register (HW_ENETMAC_TDAR)......................................1664
26.4.5 ENET MAC Control Register (HW_ENETMAC_ECR)........................................................................1665
26.4.6 ENET MAC MII Management Frame Register (HW_ENETMAC_MMFR).........................................1666
26.4.7 ENET MAC MII Speed Control Register (HW_ENETMAC_MSCR)...................................................1667
26.4.8 ENET MAC MIB Control/Status Register (HW_ENETMAC_MIBC)..................................................1668
26.4.9 ENET MAC Receive Control Register (HW_ENETMAC_RCR)..........................................................1669
26.4.10 ENET MAC Transmit Control Register (HW_ENETMAC_TCR).........................................................1671
26.4.11 ENET MAC Physical Address Lower Register (HW_ENETMAC_PALR)............................................1672
26.4.12 ENET MAC Physical Address Upper Register (HW_ENETMAC_PAUR)............................................1673
26.4.13 ENET MAC Opcode/Pause Duration Register (HW_ENETMAC_OPD)..............................................1673
26.4.14 ENET MAC Descriptor Individual Upper Address Register (HW_ENETMAC_IAUR)........................1674
26.4.15 ENET MAC Descriptor Individual Lower Address Register (HW_ENETMAC_IALR).......................1674
26.4.16 ENET MAC Descriptor Group Upper Address Register (HW_ENETMAC_GAUR)............................1675
26.4.17 ENET MAC Descriptor Group Lower Address Register (HW_ENETMAC_GALR)............................1675
26.4.18 ENET MAC Transmit FIFO Watermark and Store and Forward Control Register
(HW_ENETMAC_TFW_SFCR)............................................................................................................1676
26.4.19 ENET MAC FIFO Receive Bound Register (HW_ENETMAC_FRBR)................................................1677
26.4.20 ENET MAC FIFO Receive FIFO Start Register (HW_ENETMAC_FRSR)..........................................1677
26.4.21 ENET MAC Pointer to Receive Descriptor Ring Register (HW_ENETMAC_ERDSR).......................1678
26.4.22 ENET MAC Pointer to Transmit Descriptor Ring Register (HW_ENETMAC_ETDSR)......................1679
26.4.23 ENET MAC Maximum Receive Buffer Size Register (HW_ENETMAC_EMRBR).............................1680
26.4.24 ENET MAC Receive FIFO Section Full Threshold Register (HW_ENETMAC_RX_SECTION_FULL).1681
26.4.25 ENET MAC Receive FIFO Section Empty Threshold Register

(HW_ENETMAC_RX_SECTION_EMPTY).........................................................................................1681

26.4.26 ENET MAC Receive FIFO Almost Empty Threshold Register

(HW_ENETMAC_RX_ALMOST_EMPTY).........................................................................................1682
26.4.27 ENET MAC Receive FIFO Almost Full Thresholdt Register (HW_ENETMAC_RX_ALMOST_FULL).1682
26.4.28 ENET MAC Transmit FIFO Section Empty Threshold Register

(HW_ENETMAC_TX_SECTION_EMPTY).........................................................................................1683
26.4.29 ENET MAC Transmit FIFO Almost Empty Threshold Register

(HW_ENETMAC_TX_ALMOST_EMPTY).........................................................................................1683
26.4.30 ENET MAC Transmit FIFO Almost Full Threshold Register (HW_ENETMAC_TX_ALMOST_FULL).1684
26.4.31 ENET MAC Transmit Inter-Packet Gap Register (HW_ENETMAC_TX_IPG_LENGTH)..................1684
26.4.32 ENET MAC Frame Truncation Length Register (HW_ENETMAC_TRUNC_FL)...............................1685
26.4.33 ENET MAC Accelerator Transmit Function Configuration Register

(HW_ENETMAC_IPACCTXCONF).....................................................................................................1685
26.4.34 ENET MAC Accelerator Receive Function Configuration Register

(HW_ENETMAC_IPACCRXCONF).....................................................................................................1686
26.4.35 ENET MAC RMON Tx packet drop (HW_ENETMAC_RMON_T_DROP)........................................1687
26.4.36 ENET MAC RMON Tx packet count (HW_ENETMAC_RMON_T_PACKETS)................................1688
26.4.37 ENET MAC RMON Tx Broadcast Packets (HW_ENETMAC_RMON_T_BC_PKT)..........................1688
26.4.38 ENET MAC RMON Tx Multicast Packets (HW_ENETMAC_RMON_T_MC_PKT)..........................1689
26.4.39 ENET MAC RMON Tx Packets w CRC/Align error (HW_ENETMAC_RMON_T_CRC_ALIGN)....1689
26.4.40 ENET MAC RMON Tx Packets < 64 bytes, good CRC (HW_ENETMAC_RMON_T_UNDERSIZE).1690
26.4.41 ENET MAC RMON Tx Packets > MAX_FL bytes, good CRC
(HW_ENETMAC_RMON_T_OVERSIZE)...........................................................................................1690
26.4.42 ENET MAC RMON Tx Packets < 64 bytes, bad CRC (HW_ENETMAC_RMON_T_FRAG).............1691
26.4.43 ENET MAC RMON Tx Packets > MAX_FL bytes, bad CRC (HW_ENETMAC_RMON_T_JAB).....1691
26.4.44 ENET MAC RMON Tx collision count (HW_ENETMAC_RMON_T_COL)......................................1692
26.4.45 ENET MAC RMON Tx 64 byte packets (HW_ENETMAC_RMON_T_P64).......................................1692
26.4.46 ENET MAC RMON Tx 65 to 127 byte packets (HW_ENETMAC_RMON_T_P65TO127N).............1693
26.4.47 ENET MAC RMON Tx 128 to 255 byte packets (HW_ENETMAC_RMON_T_P128TO255N).........1693
26.4.48 ENET MAC RMON Tx 256 to 511 byte packets (HW_ENETMAC_RMON_T_P256TO511)............1694
26.4.49 ENET MAC RMON Tx 512 to 1023 byte packets (HW_ENETMAC_RMON_T_P512TO1023)........1694

26.4.50 ENET MAC RMON Tx 1024 to 2047 byte packets (HW_ENETMAC_RMON_T_P1024TO2047).....1695
26.4.51 ENET MAC RMON Tx packets w > 2048 bytes (HW_ENETMAC_RMON_T_P_GTE2048)............1695
26.4.52 ENET MAC RMON Tx Octets (HW_ENETMAC_RMON_T_OCTETS)............................................1696
26.4.53 ENET MAC Frames Transmitted count drop (HW_ENETMAC_IEEE_T_DROP)...............................1696
26.4.54 ENET MAC Frames Transmitted OK (HW_ENETMAC_IEEE_T_FRAME_OK)...............................1697
26.4.55 ENET MAC Frames Transmitted with Single Collision (HW_ENETMAC_IEEE_T_1COL)..............1697
26.4.56 ENET MAC Frames Transmitted with Multiple Collisions (HW_ENETMAC_IEEE_T_MCOL)........1698
26.4.57 ENET MAC Frames Transmitted after Deferral Delay (HW_ENETMAC_IEEE_T_DEF)...................1698
26.4.58 ENET MAC Frames Transmitted with Late Collision (HW_ENETMAC_IEEE_T_LCOL).................1699
26.4.59 ENET MAC Frames Transmitted with Excessive Collisions (HW_ENETMAC_IEEE_T_EXCOL).....1699
26.4.60 ENET MAC Frames Transmitted with Tx FIFO Underrun (HW_ENETMAC_IEEE_T_MACERR)....1700
26.4.61 ENET MAC Frames Transmitted with Carrier Sense Error (HW_ENETMAC_IEEE_T_CSERR).......1700
26.4.62 ENET MAC Frames Transmitted with SQE Error (HW_ENETMAC_IEEE_T_SQE)..........................1700
26.4.63 ENET MAC Frames Transmitted flow control (HW_ENETMAC_IEEE_T_FDXFC)..........................1701
26.4.64 ENET MAC Frames Transmitted error (HW_ENETMAC_IEEE_T_OCTETS_OK)............................1701
26.4.65 ENET MAC RMON Rx packet count (HW_ENETMAC_RMON_R_PACKETS)................................1702
26.4.66 ENET MAC RMON Rx Broadcast Packets (HW_ENETMAC_RMON_R_BC_PKT).........................1702
26.4.67 ENET MAC RMON Rx Multicast Packets (HW_ENETMAC_RMON_R_MC_PKT).........................1703
26.4.68 ENET MAC RMON Rx Packets w CRC/Align error (HW_ENETMAC_RMON_R_CRC_ALIGN)....1703
26.4.69 ENET MAC RMON Rx Packets < 64 bytes, good CRC (HW_ENETMAC_RMON_R_UNDERSIZE).1704
26.4.70 ENET MAC RMON Rx Packets > MAX_FL, good CRC (HW_ENETMAC_RMON_R_OVERSIZE).1704
26.4.71 ENET MAC RMON Rx Packets < 64 bytes, bad CRC (HW_ENETMAC_RMON_R_FRAG)............1705
26.4.72 ENET MAC RMON Rx Packets > MAX_FL bytes, bad CRC (HW_ENETMAC_RMON_R_JAB).....1705
26.4.73 ENET MAC RMON Rx 64 byte packets (HW_ENETMAC_RMON_R_P64)......................................1706
26.4.74 ENET MAC RMON Rx 65 to 127 byte packets (HW_ENETMAC_RMON_R_P65TO127)................1706
26.4.75 ENET MAC RMON Rx 128 to 255 byte packets (HW_ENETMAC_RMON_R_P128TO255)............1707
26.4.76 ENET MAC RMON Rx 256 to 511 byte packets (HW_ENETMAC_RMON_R_P256TO511)............1707
26.4.77 ENET MAC RMON Rx 512 to 1023 byte packets (HW_ENETMAC_RMON_R_P512TO1023)........1708

26.4.78 ENET MAC RMON Rx 1024 to 2047 byte packets (HW_ENETMAC_RMON_R_P1024TO2047).....1708
26.4.79 ENET MAC RMON Rx packets w > 2048 bytes (HW_ENETMAC_RMON_R_P_GTE2048)............1709
26.4.80 ENET MAC RMON Rx Octets (HW_ENETMAC_RMON_R_OCTETS)............................................1709
26.4.81 ENET MAC Frames Received count drop (HW_ENETMAC_IEEE_R_DROP)...................................1709
26.4.82 ENET MAC Frames Received OK (HW_ENETMAC_IEEE_R_FRAME_OK)...................................1710
26.4.83 ENET MAC Frames Received with CRC Error (HW_ENETMAC_IEEE_R_CRC).............................1710
26.4.84 ENET MAC Frames Received with Alignment Error (HW_ENETMAC_IEEE_R_ALIGN)................1711
26.4.85 ENET MAC Frames Received overflow (HW_ENETMAC_IEEE_R_MACERR)................................1711
26.4.86 ENET MAC Frames Received flow control (HW_ENETMAC_IEEE_R_FDXFC)..............................1712
26.4.87 ENET MAC Frames Received error (HW_ENETMAC_IEEE_R_OCTETS_OK)................................1712
26.4.88 ENET MAC IEEE1588 Timer Control Register (HW_ENETMAC_ATIME_CTRL)...........................1713
26.4.89 ENET MAC IEEE1588 Timer value Register (HW_ENETMAC_ATIME)...........................................1715
26.4.90 ENET MAC IEEE1588 Offsetvalue for one-shot event generation Register
(HW_ENETMAC_ATIME_EVT_OFFSET)..........................................................................................1715
26.4.91 ENET MAC IEEE1588 Timer Period Register (HW_ENETMAC_ATIME_EVT_PERIOD)...............1716
26.4.92 ENET MAC IEEE1588 Correction counter wrap around value Register
(HW_ENETMAC_ATIME_CORR)........................................................................................................1716
26.4.93 ENET MAC IEEE1588 Clock period of the timestamping clock (ts_clk) in nanoseconds and correction
increment Register (HW_ENETMAC_ATIME_INC)............................................................................1717
26.4.94 ENET MAC IEEE1588 Timestamp of the last Frame Register (HW_ENETMAC_TS_TIMESTAMP).1718
26.4.95 ENET MAC Supplemental MAC Address 0 (HW_ENETMAC_SMAC_0_0)......................................1719
26.4.100ENET MAC Supplemental MAC Address 2 (HW_ENETMAC_SMAC_2_1)......................................1721
26.4.103ENET MAC Compare register 0 (HW_ENETMAC_COMP_REG_0)...................................................1722

26.4.107ENET MAC Capture register 0 (HW_ENETMAC_CAPT_REG_0)......................................................1724
26.4.111ENET MAC IEEE1588 Interrupt register. (HW_ENETMAC_CCB_INT)............................................1726
26.4.112ENET MAC IEEE1588 Interrupt enable mask register (HW_ENETMAC_CCB_INT_MASK)...........1727
Chapter 27
Inter IC (I2C)
27.1 I2C Overview..............................................................................................................................................................1729
27.2 Operation....................................................................................................................................................................1730
27.2.1 I2C Interrupt Sources..............................................................................................................................1731
27.2.2 I2C Bus Protocol.....................................................................................................................................1732
27.2.2.1 Simple Device Transactions..................................................................................................1734
27.2.2.2 Typical EEPROM Transactions.............................................................................................1735
27.2.2.3 Master Mode Protocol...........................................................................................................1736
27.2.2.4 Clock Generation..................................................................................................................1736
27.2.2.5 Master Mode Operation........................................................................................................1737
27.2.2.6 Slave Mode Protocol.............................................................................................................1741
27.2.3 Programming Examples..........................................................................................................................1744
27.2.3.1 Five Byte Master Write Using DMA....................................................................................1745
27.2.3.2 Reading 256 bytes from an EEPROM..................................................................................1747
27.3 Internal Interface Modes.............................................................................................................................................1749
27.3.1 PIO Mode................................................................................................................................................1749
27.3.2 PIO Queue Mode.....................................................................................................................................1750
27.4.1 Pinmux Selection During Reset...............................................................................................................1751
27.4.1.1 Correct and Incorrect Reset Examples..................................................................................1752

27.5.1 I2C Control Register 0 (HW_I2CCTRL0)..............................................................................................1753
27.5.2 I2C Timing Register 0 (HW_I2CTIMING0)...........................................................................................1755
27.5.5 I2C Control Register 1 (HW_I2CCTRL1)..............................................................................................1758
27.5.6 I2C Status Register (HW_I2CSTAT).......................................................................................................1761
27.5.7 I2C Queue control reg. (HW_I2CQUEUECTRL)..................................................................................1764
27.5.8 I2C Queue Status Register. (HW_I2CQUEUESTAT).............................................................................1766
27.5.9 I2C Queue command reg (HW_I2CQUEUECMD)................................................................................1767
27.5.10 I2C Controller Read Data Register for queue mode only. (HW_I2CQUEUEDATA).............................1769
27.5.11 I2C Controller DMA Read and Write Data Register (HW_I2CDATA)..................................................1770
27.5.12 I2C Device Debug Register 0 (HW_I2CDEBUG0)................................................................................1770
27.5.13 I2C Device Debug Register 1 (HW_I2CDEBUG1)................................................................................1772
27.5.14 I2C Version Register (HW_I2CVERSION)............................................................................................1774
Chapter 28
Pulse-Width Modulator (PWM) Controller
28.1 Pulse Width Modulator (PWM) Overview.................................................................................................................1775
28.2 Operation....................................................................................................................................................................1775
28.2.1 XTAL OSC Driving Mode......................................................................................................................1778
28.2.2 HSADC Driving Mode............................................................................................................................1779
28.2.3 Multi-Chip Attachment Mode.................................................................................................................1780
28.2.4 Channel 2 Analog Enable Function.........................................................................................................1781
28.2.5 Channel Output Cutoff Using Module Clock Gate.................................................................................1781
28.4.1 PWM Control and Status Register (HW_PWMCTRL)..........................................................................1782
28.4.2 PWM Channel 0 Active Register (HW_PWMACTIVE0)......................................................................1784
28.4.3 PWM Channel 0 Period Register (HW_PWMPERIOD0)......................................................................1785

28.4.18 PWM Version Register (HW_PWMVERSION).....................................................................................1804
Chapter 29
Programmable 3-Port Ethernet Switch with QOS (SWITCH)
29.1 3-Port Ethernet Switch Features.................................................................................................................................1805
29.2 Block Diagram............................................................................................................................................................1806
29.3 Switch Configuration..................................................................................................................................................1807
29.3.1 Overview..................................................................................................................................................1807
29.3.2 Passthrough Mode...................................................................................................................................1808
29.3.3 Switch Mode............................................................................................................................................1809
29.3.4 Port 0 Input Buffer...................................................................................................................................1810
29.3.5 Port 0 Input Backpressure/Congestion Indication...................................................................................1811
29.4 Switch Functional Description....................................................................................................................................1811
29.4.1 Overview..................................................................................................................................................1811
29.4.2 VLAN Input Processing Function.................................................................................................................?
29.4.2.1 Overview...............................................................................................................................1812

29.4.2.2 Terms and Definitions...........................................................................................................1812
29.4.2.3 Configuration Information....................................................................................................1812
29.4.2.4.1 Frame Processing.................................................................................................1813
29.4.2.4.2 Mode 1 -- Single Tagging with Passthrough.......................................................1813
29.4.2.4.3 Mode 2 -- Single Tagging with Replace..............................................................1813
29.4.2.4.4 Mode 3 -- Double Tagging with Passthrough......................................................1813
29.4.2.4.5 Mode 4 -- Double Tagging with Replace............................................................1814
29.4.3 IP Snooping.............................................................................................................................................1814
29.4.4 TCP/UDP Port Number Snooping...........................................................................................................1814
29.4.5 VLAN Output Processing Function...............................................................................................................?
29.4.5.1 Overview...............................................................................................................................1815
29.4.5.2 Configuration Information....................................................................................................1815
29.4.5.3.1 Overview..............................................................................................................1815
29.4.5.3.2 Mode 0: disabled.................................................................................................1815
29.4.5.3.3 Mode 1: Strip Mode.............................................................................................1816
29.4.5.3.4 Mode 2: Tag Thru Mode......................................................................................1816
29.4.5.3.5 Mode 3: Transparent Mode.................................................................................1816
29.4.6 Frame Classification and Priority Resolution................................................................................................?
29.4.6.1 Overview...............................................................................................................................1816
29.4.6.2 VLAN Priority Look-Up.......................................................................................................1816
29.4.6.3 Ipv4 and Ipv6 Priority Look Up............................................................................................1817
29.4.6.3.1 Overview..............................................................................................................1817
29.4.6.3.2 Classification Table Programming Model...........................................................1817
29.4.6.4 Priority Resolution................................................................................................................1818
29.4.6.5 Bridge Control Protocol Identification.................................................................................1819
29.4.7 Input Port Selection.................................................................................................................................1819

29.4.8 Layer 2 Look Up Engine...............................................................................................................................?
29.4.8.1 Overview...............................................................................................................................1819
29.4.8.2 Hash Code.............................................................................................................................1820
29.4.8.3 Address Memory...................................................................................................................1820
29.4.9 Layer 2 Lookup Tasks Overview...................................................................................................................?
29.4.9.1 MAC Address Lookup..........................................................................................................1821
29.4.9.2 Forced Forwarding................................................................................................................1822
29.4.9.3 Learning................................................................................................................................1822
29.4.9.4 Migration...............................................................................................................................1824
29.4.9.5 Aging.....................................................................................................................................1824
29.4.10 Frame Forwarding Tasks................................................................................................................................?
29.4.10.1 Overview...............................................................................................................................1824
29.4.10.2 VLAN Domain Verification..................................................................................................1825
29.4.10.3 Broadcast Multicast VLAN Domain Resolution..................................................................1826
29.4.10.3.1 Overview..............................................................................................................1826
29.4.10.3.2 VLAN Resolution Table......................................................................................1826
29.4.10.3.3 VLAN Switching and Resolution Mechanism....................................................1827
29.4.10.4 Port Mirroring.......................................................................................................................1828
29.4.10.5 Protocol Snooping.................................................................................................................1829
29.4.10.6 Bridge Protocol Frame Resolution........................................................................................1829
29.4.10.6.1 Overview..............................................................................................................1829
29.4.10.6.2 Input Port Blocking.............................................................................................1829
29.4.10.6.3 Input Port Learning Disable................................................................................1829
29.4.10.6.4 Management Port Forwarding.............................................................................1829
29.4.10.6.5 Management Frame Forwarding.........................................................................1830
29.4.10.7 Congestion Resolution..........................................................................................................1830
29.4.10.7.1 Overview..............................................................................................................1830
29.4.10.7.2 Unique Destination (one input to one output).....................................................1830
29.4.10.7.3 Multiple Destinations (Flooding)........................................................................1830

29.4.10.8 Switching..............................................................................................................................1831
29.5 Output Frame Queuing...............................................................................................................................................1831
29.5.1 Overview..................................................................................................................................................1831
29.5.2 Cell and Queue Concept..........................................................................................................................1832
29.5.3 Write Control Module.............................................................................................................................1833
29.5.4 Cell Factory Module................................................................................................................................1833
29.5.5 Output Queue Manager..................................................................................................................................?
29.5.5.1 Overview...............................................................................................................................1833
29.5.5.2 Weighted Fair Queuing scheduling algorithm......................................................................1834
29.5.6 Congestion Management.........................................................................................................................1834
29.5.7 Implementation Notes.............................................................................................................................1834
29.6 Reset and Stop Functions............................................................................................................................................1835
29.6.1 Stop Controls...........................................................................................................................................1835
29.6.2 Port Disable.............................................................................................................................................1835
29.6.3 Port 0 Input Protection.............................................................................................................................1836
29.6.4 Port 1,2 Input Protection..........................................................................................................................1836
29.6.5 DMA Bus Error.......................................................................................................................................1836
29.7 Firmware Architecture and Tasks...............................................................................................................................1837
29.7.1 Overview..................................................................................................................................................1837
29.7.2 Firmware Environment............................................................................................................................1837
29.7.3 Firmware Overview.................................................................................................................................1837
29.7.3.1 Application Main..................................................................................................................1837
29.7.3.2 Learning Task........................................................................................................................1837
29.7.3.3 Timer Task.............................................................................................................................1837
29.7.3.4 Aging Task............................................................................................................................1838
29.8 FIFO Interface Data Structure....................................................................................................................................1838
29.9.1 ENET SWI revision (HW_ENET_SWIREVISION)..............................................................................1845

29.9.2 ENET SWI Scratch Register (HW_ENET_SWISCRATCH).................................................................1846
29.9.3 ENET SWI Port Enable Bits. (HW_ENET_SWIPORT_ENA)..............................................................1846
29.9.4 ENET SWI Verify VLAN domain. (HW_ENET_SWIVLAN_VERIFY)..............................................1847
29.9.5 ENET SWI Default broadcast resolution. (HW_ENET_SWIBCAST_DEFAULT_MASK)..................1848
29.9.6 ENET SWI Default multicast resolution. (HW_ENET_SWIMCAST_DEFAULT_MASK).................1849
29.9.7 ENET SWI Define port in blocking state and enable or disable learning.
(HW_ENET_SWIINPUT_LEARN_BLOCK)........................................................................................1850
29.9.8 ENET SWI Bridge Management Port Configuration. (HW_ENET_SWIMGMT_CONFIG)...............1851
29.9.9 ENET SWI Defines several global configuration settings. (HW_ENET_SWIMODE_CONFIG).........1853
29.9.10 ENET SWI Define behavior of VLAN input manipulation function

(HW_ENET_SWIVLAN_IN_MODE)...................................................................................................1854
29.9.11 ENET SWI Define behavior of VLAN output manipulation function

(HW_ENET_SWIVLAN_OUT_MODE)...............................................................................................1855
29.9.12 ENET SWI Enable the input processing according to the VLAN_IN_MODE for a port
(HW_ENET_SWIVLAN_IN_MODE_ENA).........................................................................................1856
29.9.13 ENET SWI The VLAN type field value to expect to identify a VLAN tagged frame.
(HW_ENET_SWIVLAN_TAG_ID).......................................................................................................1857
29.9.14 ENET SWI Port Mirroring configuration. (HW_ENET_SWIMIRROR_CONTROL)..........................1857
29.9.15 ENET SWI Port Mirroring Egress port definitions. (HW_ENET_SWIMIRROR_EG_MAP)..............1859
29.9.16 ENET SWI Port Mirroring Ingress port definitions. (HW_ENET_SWIMIRROR_ING_MAP)............1860
29.9.17 ENET SWI Ingress Source MAC Address for Mirror filtering. (HW_ENET_SWIMIRROR_ISRC_0).1861
29.9.18 ENET SWI Ingress Source MAC Address for Mirror filtering. (HW_ENET_SWIMIRROR_ISRC_1).1861
29.9.19 ENET SWI Ingress Destination MAC Address for Mirror filtering.
(HW_ENET_SWIMIRROR_IDST_0)....................................................................................................1862
29.9.20 ENET SWI Ingress Destination MAC Address for Mirror filtering.
(HW_ENET_SWIMIRROR_IDST_1)....................................................................................................1862
29.9.21 ENET SWI Egress Source MAC Address for Mirror filtering. (HW_ENET_SWIMIRROR_ESRC_0).1863
29.9.22 ENET SWI Egress Source MAC Address for Mirror filtering. (HW_ENET_SWIMIRROR_ESRC_1).1863
29.9.23 ENET SWI Egress Destination MAC Address for Mirror filtering.
(HW_ENET_SWIMIRROR_EDST_0)...................................................................................................1864

29.9.24 ENET SWI Egress Destination MAC Address for Mirror filtering.
(HW_ENET_SWIMIRROR_EDST_1)...................................................................................................1864
29.9.25 ENET SWI Count Value for Mirror filtering. (HW_ENET_SWIMIRROR_CNT)................................1865
29.9.26 ENET SWI Memory Manager Status. (HW_ENET_SWIOQMGR_STATUS)......................................1865
29.9.27 ENET SWI Low Memory threshold. (HW_ENET_SWIQMGR_MINCELLS).....................................1867
29.9.28 ENET SWI Statistic providing the lowest number of free cells reached in memory
(HW_ENET_SWIQMGR_ST_MINCELLS)..........................................................................................1867
29.9.29 ENET SWI Port Congestion status (internal). (HW_ENET_SWIQMGR_CONGEST_STAT).............1868
29.9.30 ENET SWI Switch input and output interface status (internal).
(HW_ENET_SWIQMGR_IFACE_STAT)..............................................................................................1869
29.9.31 ENET SWI Queue weights for each queue. (HW_ENET_SWIQM_WEIGHTS)..................................1870
29.9.32 ENET SWI Define congestion threshold for Port0 backpressure.

(HW_ENET_SWIQMGR_MINCELLSP0)............................................................................................1871
29.9.33 ENET SWI Enable forced forwarding for a frame processed from port 0
(HW_ENET_SWIFORCE_FWD_P0)....................................................................................................1871
29.9.34 ENET SWI Port Snooping function. Eight independent entries are available.
(HW_ENET_SWIPORTSNOOP1).........................................................................................................1872
29.9.42 ENET SWI IP Snooping function1 (HW_ENET_SWIIPSNOOP1).......................................................1882

29.9.50 ENET SWI Port 0 VLAN priority resolution map (HW_ENET_SWIVLAN_PRIORITY0).................1890
29.9.53 ENET SWI IPv4 and IPv6 priority resolution table programming (HW_ENET_SWIIP_PRIORITY)..1893
29.9.54 ENET SWI Port 0 Priority resolution configuration (HW_ENET_SWIPRIORITY_CFG0).................1894
29.9.57 ENET SWI Port 0 VLAN-ID field for VLAN input manipulation function
(HW_ENET_SWISYSTEM_TAGINFO0).............................................................................................1898
29.9.60 ENET SWI VLAN domain resolution entry 0. (HW_ENET_SWIVLAN_RES_TABLE_0).................1900

29.9.70 ENET SWI VLAN domain resolution entry 10. (HW_ENET_SWIVLAN_RES_TABLE_10).............1906
29.9.92 ENET SWI Total number of incoming frames processed (HW_ENET_SWITOTAL_DISC)................1921
29.9.93 ENET SWI Sum of bytes of frames counted in TOTAL_DISC (HW_ENET_SWITOTAL_BYT_DISC).1921
29.9.94 ENET SWI Total number of incoming frames processed (HW_ENET_SWITOTAL_FRM)................1922
29.9.95 ENET SWI Sum of bytes of frames counted in TOTAL_FRM (HW_ENET_SWITOTAL_BYT_FRM).1922
29.9.96 ENET SWI Port 0 Outgoing frames discarded due to output Queue congestion
(HW_ENET_SWIODISC0)....................................................................................................................1923

29.9.97 ENET SWI Port 0 incoming frames discarded due to mismatching or missing VLAN id
(HW_ENET_SWIIDISC_VLAN0).........................................................................................................1923
29.9.98 ENET SWI Port 0 incoming frames discarded due to missing vlan tag
(HW_ENET_SWIIDISC_UNTAGGED0)..............................................................................................1924
29.9.99 ENET SWI Port 0 incoming frames discarded (after learning) as port is configured in blocking mode
(HW_ENET_SWIIDISC_BLOCKED0).................................................................................................1924
29.9.100ENET SWI Port 1 Outgoing frames discarded due to output Queue congestion
(HW_ENET_SWIODISC1)....................................................................................................................1925
29.9.101ENET SWI Port 1 incoming frames discarded due to mismatching or missing VLAN id
29.9.102ENET SWI Port 1 incoming frames discarded due to missing vlan tag
29.9.103ENET SWI Port 1 incoming frames discarded (after learning) as port is configured in blocking mode
29.9.104ENET SWI Port 2 Outgoing frames discarded due to output Queue congestion
(HW_ENET_SWIODISC2)....................................................................................................................1927
29.9.105ENET SWI Port 2 incoming frames discarded due to mismatching or missing VLAN id
29.9.106ENET SWI Port 2 incoming frames discarded due to missing vlan tag
29.9.107ENET SWI Port 2 incoming frames discarded (after learning) as port is configured in blocking mod
29.9.108ENET SWI Interrupt Event Register (HW_ENET_SWIEIR).................................................................1929
29.9.109ENET SWI Interrupt Mask Register (HW_ENET_SWIEIMR)..............................................................1930
29.9.110ENET SWI Pointer to Receive Descriptor Ring (HW_ENET_SWIERDSR).........................................1931
29.9.111ENET SWI Pointer to Transmit Descriptor Ring (HW_ENET_SWIETDSR).......................................1932
29.9.112ENET SWI Maximum Receive Buffer Size (HW_ENET_SWIEMRBR)..............................................1932
29.9.113ENET SWI Receive Descriptor Active Register (HW_ENET_SWIRDAR)...........................................1933
29.9.114ENET SWI Transmit Descriptor Active Register (HW_ENET_SWITDAR).........................................1933
29.9.115ENET SWI Learning Records A (0) and B (1) (HW_ENET_SWILRN_REC_0)..................................1934
29.9.116ENET SWI Learning Record B(1) (HW_ENET_SWILRN_REC_1).....................................................1934
29.9.117ENET SWI Learning data available status. (HW_ENET_SWILRN_STATUS).....................................1935

29.9.118ENET SWI lookup MAC address memory start (HW_ENET_SWILOOKUP_MEMORY_START)....1845
29.9.119ENET SWI lookup MAC address memory end (HW_ENET_SWILOOKUP_MEMORY_END)........1936
Chapter 30
Application UART (AUART)
30.1 Application UART Overview.....................................................................................................................................1937
30.2 Operation....................................................................................................................................................................1939
30.2.1 Fractional Baud Rate Divider..................................................................................................................1939
30.2.2 Automatic Baud Rate Detection..............................................................................................................1939
30.2.3 UART Character Frame...........................................................................................................................1940
30.2.4 DMA Operation.......................................................................................................................................1940
30.2.5 Data Transmission or Reception..............................................................................................................1940
30.2.6 Error Bits.................................................................................................................................................1941
30.2.7 Overrun Bit..............................................................................................................................................1941
30.2.8 Disabling the FIFOs................................................................................................................................1942
30.4.1 UART Receive DMA Control Register (HW_UARTAPPCTRL0).........................................................1943
30.4.2 UART Transmit DMA Control Register (HW_UARTAPPCTRL1)........................................................1944
30.4.3 UART Control Register (HW_UARTAPPCTRL2).................................................................................1945
30.4.4 UART Line Control Register (HW_UARTAPPLINECTRL)..................................................................1948
30.4.5 UART Line Control 2 Register (HW_UARTAPPLINECTRL2).............................................................1949
30.4.6 UART Interrupt Register (HW_UARTAPPINTR)..................................................................................1950
30.4.7 UART Data Register (HW_UARTAPPDATA)........................................................................................1952
30.4.8 UART Status Register (HW_UARTAPPSTAT).......................................................................................1954
30.4.9 UART Debug Register (HW_UARTAPPDEBUG).................................................................................1955
30.4.10 UART Version Register (HW_UARTAPPVERSION)............................................................................1957
30.4.11 UART AutoBaud Register (HW_UARTAPPAUTOBAUD)....................................................................1957

Chapter 31
USB High-Speed On-the-Go Host Device Controller
31.1 USB High-Speed OTG-capable USB Controller Overview.......................................................................................1959
31.2 Difference between USB0 and USB1.........................................................................................................................1960
31.3 USB Programmed I/O (PIO) Target Interface............................................................................................................1961
31.4 USB DMA Interface...................................................................................................................................................1961
31.5 USB UTM Interface....................................................................................................................................................1961
31.5.1 Digital/Analog Loopback Test Mode......................................................................................................1961
31.6 USB Controller Flowcharts.........................................................................................................................................1962
31.6.1 References...............................................................................................................................................1964
31.7.1 Identification Register (HW_USBCTRLID)...........................................................................................1967
31.7.2 General Hardware Parameters Register (HW_USBCTRLHWGENERAL)...........................................1968
31.7.3 Host Hardware Parameters Register (HW_USBCTRLHWHOST)........................................................1969
31.7.4 Device Hardware Parameters Register (HW_USBCTRLHWDEVICE).................................................1969
31.7.5 TX Buffer Hardware Parameters Register (HW_USBCTRLHWTXBUF).............................................1970
31.7.6 RX Buffer Hardware Parameters Register (HW_USBCTRLHWRXBUF)............................................1971
31.7.7 General-Purpose Timer 0 Load (Non-EHCI-Compliant) Register (HW_USBCTRLGPTIMER0LD)....1971
31.7.8 General-Purpose Timer 0 Control (Non-EHCI-Compliant) Register (HW_USBCTRLGPTIMER0CTRL).1972
31.7.9 General-Purpose Timer 1 Load (Non-EHCI-Compliant) Register (HW_USBCTRLGPTIMER1LD)....1973
31.7.10 General-Purpose Timer 1 Control (Non-EHCI-Compliant) Register (HW_USBCTRLGPTIMER1CTRL).1974
31.7.11 System Bus Configuration (Non-EHCI-Compliant) Register (HW_USBCTRLSBUSCFG).................1975
31.7.12 Capability Length and HCI Version (EHCI-Compliant) Register (HW_USBCTRLCAPLENGTH).....1976
31.7.13 Host Control Structural Parameters (EHCI-Compliant with Extensions) Register

(HW_USBCTRLHCSPARAMS)............................................................................................................1976
31.7.14 Host Control Capability Parameters (EHCI-Compliant) Register (HW_USBCTRLHCCPARAMS).....1978
31.7.15 Device Interface Version Number (Non-EHCI-Compliant) Register (HW_USBCTRLDCIVERSION).1979
31.7.16 Device Control Capability Parameters (Non-EHCI-Compliant) Register

(HW_USBCTRLDCCPARAMS)...........................................................................................................1980
31.7.17 USB Command Register (HW_USBCTRLUSBCMD)..........................................................................1980

31.7.18 USB Status Register (HW_USBCTRLUSBSTS)...................................................................................1983
31.7.19 USB Interrupt Enable Register (HW_USBCTRLUSBINTR).................................................................1987
31.7.20 USB Frame Index Register (HW_USBCTRLFRINDEX)......................................................................1989
31.7.21 Frame List Base Address Register (Host Controller mode) (HW_USBCTRLPERIODICLISTBASE)..1990
31.7.22 USB Device Address Register (Device Controller mode) (HW_USBCTRLDEVICEADDR)..............1991
31.7.23 Next Asynchronous Address Register (Host Controller mode) (HW_USBCTRLASYNCLISTADDR).1992
31.7.24 Endpoint List Address Register (Device Controller mode) (HW_USBCTRLENDPOINTLISTADDR).1993
31.7.25 Embedded TT Asynchronous Buffer Status and Control Register (Host Controller mode)
(HW_USBCTRLTTCTRL).....................................................................................................................1993
31.7.26 Programmable Burst Size Register (HW_USBCTRLBURSTSIZE)......................................................1994
31.7.27 Host Transmit Pre-Buffer Packet Timing Register (HW_USBCTRLTXFILLTUNING).......................1995
31.7.28 Inter-Chip Control Register (HW_USBCTRLIC_USB).........................................................................1997
31.7.29 ULPI Viewport Register (HW_USBCTRLULPI)...................................................................................1998
31.7.30 Endpoint NAK Register (HW_USBCTRLENDPTNAK).......................................................................1999
31.7.31 Endpoint NAK Enable Register (HW_USBCTRLENDPTNAKEN).....................................................2000
31.7.32 Port Status and Control 1 Register (HW_USBCTRLPORTSC1)...........................................................2001
31.7.33 OTG Status and Control Register (HW_USBCTRLOTGSC).................................................................2007
31.7.34 USB Device Mode Register (HW_USBCTRLUSBMODE)...................................................................2010
31.7.35 Endpoint Setup Status Register (HW_USBCTRLENDPTSETUPSTAT)...............................................2012
31.7.36 Endpoint Initialization Register (HW_USBCTRLENDPTPRIME).......................................................2012
31.7.37 Endpoint De-Initialize Register (HW_USBCTRLENDPTFLUSH).......................................................2014
31.7.38 Endpoint Status Register (HW_USBCTRLENDPTSTAT).....................................................................2015
31.7.39 Endpoint Complete Register (HW_USBCTRLENDPTCOMPLETE)...................................................2016
31.7.40 Endpoint Control 0 Register (HW_USBCTRLENDPTCTRL0).............................................................2017

Chapter 32
Integrated USB 2.0 PHY
32.1 USB PHY Overview...................................................................................................................................................2031
32.2 Operation....................................................................................................................................................................2032
32.2.1 UTMI.......................................................................................................................................................2032
32.2.2 Digital Transmitter...................................................................................................................................2032
32.2.3 Digital Receiver.......................................................................................................................................2032
32.2.4 Analog Receiver......................................................................................................................................2033
32.2.4.1 HS Differential Receiver.......................................................................................................2033
32.2.4.2 Squelch Detector...................................................................................................................2034
32.2.4.3 LS/FS Differential Receiver..................................................................................................2034
32.2.4.4 HS Disconnect Detector........................................................................................................2034
32.2.4.5 USB Plugged-In Detector.....................................................................................................2034
32.2.4.6 Single-Ended USB_DP Receiver..........................................................................................2034
32.2.4.7 Single-Ended USB_DN Receiver.........................................................................................2035
32.2.4.8 9X Oversample Module........................................................................................................2035
32.2.5 Analog Transmitter..................................................................................................................................2035
32.2.5.1 Switchable High-Speed 45Ω Termination Resistors.............................................................2035
32.2.5.2 Low-Speed/Full-Speed Differential Driver...........................................................................2035
32.2.5.3 High-Speed Differential Driver.............................................................................................2036
32.2.5.4 Switchable 1.5KΩ USB_DP Pullup Resistor........................................................................2036
32.2.5.5 Switchable 15KΩ USB_DP Pulldown Resistor....................................................................2036
32.2.6 Recommended Register Configuration for USB Certification................................................................2039
32.4.1 USB PHY Power-Down Register (HW_USBPHYPWD).......................................................................2040
32.4.2 USB PHY Transmitter Control Register (HW_USBPHYTX)................................................................2041

32.4.3 USB PHY Receiver Control Register (HW_USBPHYRX)....................................................................2043
32.4.4 USB PHY General Control Register (HW_USBPHYCTRL).................................................................2044
32.4.5 USB PHY Status Register (HW_USBPHYSTATUS).............................................................................2047
32.4.6 USB PHY Debug Register (HW_USBPHYDEBUG).............................................................................2048
32.4.7 UTMI Debug Status Register 0 (HW_USBPHYDEBUG0_STATUS)...................................................2050
32.4.8 UTMI Debug Status Register 1 (HW_USBPHYDEBUG1)...................................................................2051
32.4.9 UTMI RTL Version (HW_USBPHYVERSION)....................................................................................2052
32.4.10 USB PHY IP Block Register (HW_USBPHYIP)...................................................................................2052
Chapter 33
LCD Interface (LCDIF)
33.1 LCD Interface (LCDIF) Overview.............................................................................................................................2055
33.2 Operation....................................................................................................................................................................2056
33.2.1 Bus Interface Mechanisms.......................................................................................................................2057
33.2.1.1 Bus Master Operation in Write/Display Modes....................................................................2058
33.2.1.2 DMA Operation in MPU Read Mode...................................................................................2058
33.2.2 Write Datapath.........................................................................................................................................2059
33.2.3 Read Datapath.........................................................................................................................................2064
33.2.4 LCDIF Interrupts.....................................................................................................................................2068
33.2.5 Initializing the LCDIF.............................................................................................................................2068
33.2.5.1 Write Modes..........................................................................................................................2068
33.2.5.2 MPU Read Mode..................................................................................................................2069
33.2.6 MPU Interface.........................................................................................................................................2070
33.2.6.1 Code Example to Initialize the LCDIF in MPU Write Mode...............................................2072
33.2.7 VSYNC Interface....................................................................................................................................2072
33.2.7.1 Code Example to initialize LCDIF in VSYNC mode...........................................................2073
33.2.8 DOTCLK Interface..................................................................................................................................2074
33.2.8.1 Code Example.......................................................................................................................2075
33.2.9 ITU-R BT.656 Digital Video Interface (DVI).........................................................................................2075
33.2.10 LCDIF Pin Usage by Interface Mode......................................................................................................2076

33.4.1 LCDIF General Control Register (HW_LCDIFCTRL)..........................................................................2082
33.4.2 LCDIF General Control1 Register (HW_LCDIFCTRL1)......................................................................2085
33.4.3 LCDIF General Control2 Register (HW_LCDIFCTRL2)......................................................................2088
33.4.4 LCDIF Horizontal and Vertical Valid Data Count Register (HW_LCDIFTRANSFER_COUNT)........2090
33.4.5 LCD Interface Current Buffer Address Register (HW_LCDIFCUR_BUF)...........................................2091
33.4.6 LCD Interface Next Buffer Address Register (HW_LCDIFNEXT_BUF).............................................2091
33.4.7 LCD Interface Timing Register (HW_LCDIFTIMING).........................................................................2092
33.4.8 LCDIF VSYNC Mode and Dotclk Mode Control Register0 (HW_LCDIFVDCTRL0).........................2093
33.4.13 Digital Video Interface Control0 Register (HW_LCDIFDVICTRL0)....................................................2098
33.4.18 RGB to YCbCr 4:2:2 CSC Coefficient0 Register (HW_LCDIFCSC_COEFF0)....................................2102
33.4.20 RGB to YCbCr 4:2:2 CSC Coefficent2 Register (HW_LCDIFCSC_COEFF2).....................................2104
33.4.23 RGB to YCbCr 4:2:2 CSC Offset Register (HW_LCDIFCSC_OFFSET)..............................................2107
33.4.24 RGB to YCbCr 4:2:2 CSC Limit Register (HW_LCDIFCSC_LIMIT)..................................................2107
33.4.25 LCD Interface Data Register (HW_LCDIFDATA).................................................................................2109
33.4.26 Bus Master Error Status Register (HW_LCDIFBM_ERROR_STAT)....................................................2109

33.4.27 CRC Status Register (HW_LCDIFCRC_STAT).....................................................................................2110
33.4.28 LCD Interface Status Register (HW_LCDIFSTAT)................................................................................2110
33.4.29 LCD Interface Version Register (HW_LCDIFVERSION).....................................................................2112
33.4.30 LCD Interface Debug0 Register (HW_LCDIFDEBUG0)......................................................................2112
Chapter 34
Pixel Pipeline (PXP)
34.1 Pixel Pipeling (PXP) Overview..................................................................................................................................2117
34.1.1 Image Support.........................................................................................................................................2118
34.1.2 Block Size Selection................................................................................................................................2119
34.1.3 PXP Limitations/Issues...........................................................................................................................2119
34.2 Operation....................................................................................................................................................................2120
34.2.1 Pixel Handling.........................................................................................................................................2121
34.2.2 S0 Cropping/Masking..............................................................................................................................2122
34.2.3 Scaling.....................................................................................................................................................2124
34.2.4 Color Space Conversion (CSC)...............................................................................................................2125
34.2.5 Overlays...................................................................................................................................................2126
34.2.6 Alpha Blending........................................................................................................................................2127
34.2.7 Color Key.................................................................................................................................................2128
34.2.8 Raster Operations (ROPs)........................................................................................................................2129
34.2.9 Rotation...................................................................................................................................................2129
34.2.10 In-place Rendering..................................................................................................................................2131
34.2.11 Interlaced Video Support.........................................................................................................................2132
34.2.12 Queueing Frame Operations....................................................................................................................2132
34.3 Examples.....................................................................................................................................................................2134
34.3.1 Basic QVGA Example.............................................................................................................................2134
34.3.2 Basic QVGA with Overlays....................................................................................................................2136
34.3.3 Cropped QVGA Example........................................................................................................................2138

34.3.4 Upscale QVGA to VGA with Overlays...................................................................................................2140
34.3.5 Downscale VGA to WQVGA (480x272) to fill screen...........................................................................2142
34.3.6 Downscale VGA to QVGA with Overlapping Overlays.........................................................................2144
34.4.1 PXP Control Register 0 (HW_PXPCTRL).............................................................................................2149
34.4.2 PXP Status Register (HW_PXPSTAT)....................................................................................................2152
34.4.3 Output Frame Buffer Pointer (HW_PXPOUTBUF)...............................................................................2154
34.4.4 Output Frame Buffer Pointer #2 (HW_PXPOUTBUF2)........................................................................2154
34.4.5 PXP Output Buffer Size (HW_PXPOUTSIZE)......................................................................................2155
34.4.6 PXP Source 0 (video) Input Buffer Pointer (HW_PXPS0BUF).............................................................2156
34.4.7 Source 0 U/Cb or 2 Plane UV Input Buffer Pointer (HW_PXPS0UBUF)..............................................2156
34.4.8 Source 0 V/Cr Input Buffer Pointer (HW_PXPS0VBUF)......................................................................2157
34.4.9 PXP Source 0 (video) Buffer Parameters (HW_PXPS0PARAM)..........................................................2158
34.4.10 Source 0 Background Color (HW_PXPS0BACKGROUND).................................................................2158
34.4.11 Source 0 Cropping Register (HW_PXPS0CROP)..................................................................................2159
34.4.12 Source 0 Scale Factor Register (HW_PXPS0SCALE)...........................................................................2160
34.4.13 Source 0 Scale Offset Register (HW_PXPS0OFFSET)..........................................................................2161
34.4.14 Color Space Conversion Coefficient Register 0 (HW_PXPCSCCOEFF0)............................................2162
34.4.17 PXP Next Frame Pointer (HW_PXPNEXT)...........................................................................................2165
34.4.18 PXP S0 Color Key Low (HW_PXPS0COLORKEYLOW)....................................................................2167
34.4.19 PXP S0 Color Key High (HW_PXPS0COLORKEYHIGH)..................................................................2168
34.4.20 PXP Overlay Color Key Low (HW_PXPOLCOLORKEYLOW)..........................................................2168
34.4.21 PXP Overlay Color Key High (HW_PXPOLCOLORKEYHIGH).........................................................2169
34.4.22 PXP Debug Control Register (HW_PXPDEBUGCTRL).......................................................................2170
34.4.23 PXP Debug Register (HW_PXPDEBUG)...............................................................................................2171
34.4.24 PXP Version Register (HW_PXPVERSION)..........................................................................................2171

34.4.25 PXP Overlay 0 Buffer Pointer (HW_PXPOL0)......................................................................................2172
34.4.26 PXP Overlay 0 Size (HW_PXPOL0SIZE)..............................................................................................2173
34.4.27 PXP Overlay 0 Parameters (HW_PXPOL0PARAM).............................................................................2173
34.4.28 PXP Overlay 0 Parameters 2 (HW_PXPOL0PARAM2)........................................................................2175

Chapter 35
Serial Audio Interface (SAIF)
35.1 Serial Audio Interface (SAIF) Overview....................................................................................................................2201
35.2 Operation....................................................................................................................................................................2202
35.2.1 Sample Rate Programming and Codec Clocking Operation...................................................................2203
35.2.2 Transmit Operation..................................................................................................................................2207
35.2.3 Receive Operation...................................................................................................................................2208
35.2.4 DMA Interface.........................................................................................................................................2209
35.2.5 PCM Data FIFO......................................................................................................................................2209
35.2.6 Serial Frame Formats...............................................................................................................................2210
35.2.7 Pin Timing...............................................................................................................................................2211
35.3.1 SAIF Control Register (HW_SAIFCTRL)..............................................................................................2212
35.3.2 SAIF Status Register (HW_SAIFSTAT).................................................................................................2216
35.3.3 SAIF Data Register (HW_SAIFDATA)...................................................................................................2218
35.3.4 SAIF Version Register (HW_SAIFVERSION).......................................................................................2219
Chapter 36
Sony-Philips Digital Interface Format Transmitter (SPDIF)
36.1 Overview.....................................................................................................................................................................2221
36.2 Operation....................................................................................................................................................................2221
36.2.1 Interrupts..................................................................................................................................................2225
36.2.2 Clocking..................................................................................................................................................2225
36.2.3 DMA Operation.......................................................................................................................................2226
36.2.4 PIO Debug Mode.....................................................................................................................................2228
36.3.1 SPDIF Control Register (HW_SPDIFCTRL).........................................................................................2229

36.3.2 SPDIF Status Register (HW_SPDIFSTAT).............................................................................................2231
36.3.3 SPDIF Frame Control Register (HW_SPDIFFRAMECTRL)................................................................2232
36.3.4 SPDIF Sample Rate Register (HW_SPDIFSRR)....................................................................................2234
36.3.5 SPDIF Debug Register (HW_SPDIFDEBUG).......................................................................................2235
36.3.6 SPDIF Write Data Register (HW_SPDIFDATA)....................................................................................2236
36.3.7 SPDIF Version Register (HW_SPDIFVERSION)..................................................................................2237
Chapter 37
High-Speed ADC (HSADC)
37.1 Overview.....................................................................................................................................................................2239
37.2 High-Speed ADC Block Features...............................................................................................................................2240
37.2.1 Sample Rate and Sample Precision.........................................................................................................2240
37.2.2 Trigger Modes.........................................................................................................................................2241
37.2.3 APBH-DMA Channel.............................................................................................................................2241
37.2.4 Synchronization with PWM Block..........................................................................................................2241
37.2.5 Clock Domains........................................................................................................................................2241
37.2.6 Sample Precision, Endian, Half-word Swap and Bits Left-Shift............................................................2241
37.3 Operation....................................................................................................................................................................2242
37.3.1 Trigger Modes.........................................................................................................................................2243
37.3.2 Sample Data Bits Left Shift.....................................................................................................................2244
37.3.3 Bits Location...........................................................................................................................................2245
37.3.4 Configuration of APBH-DMA................................................................................................................2245
37.3.5 Configuration of PWM............................................................................................................................2246
37.3.6 Configuration of High-speed ADC..........................................................................................................2246
37.3.7 Interrupt Sources.....................................................................................................................................2247
37.3.8 Working Modes.......................................................................................................................................2247
37.3.8.1 Single Mode..........................................................................................................................2247
37.3.8.2 Loop Mode............................................................................................................................2247
37.3.9 Debugging Information...........................................................................................................................2248

37.4 Programming Example...............................................................................................................................................2248
37.5.1 HSADC Control Register 0 (HW_HSADCCTRL0)...............................................................................2249
37.5.4 HSADC Sequence Samples Number Register (HW_HSADCSEQUENCE_SAMPLES_NUM)..........2256
37.5.5 HSADC Sequence Number Register (HW_HSADCSEQUENCE_NUM).............................................2256
37.5.6 HSADC FIFO Data Register (HW_HSADCFIFO_DATA)....................................................................2257
37.5.7 HSADC Debug Information 0 Register (HW_HSADCDBG_INFO0)...................................................2258
37.5.10 HSADC Version Register (HW_HSADCVERSION).............................................................................2260
Chapter 38
Low-Resolution ADC (LRADC) and Touch-Screen Interface
38.1 LRADC Overview......................................................................................................................................................2261
38.2 Operation....................................................................................................................................................................2263
38.2.1 External Temperature Sensing with a Diode...........................................................................................2263
38.2.2 Internal Die Temperature Sensing...........................................................................................................2264
38.2.3 Scheduling Conversions..........................................................................................................................2265
38.2.4 Delay Channels........................................................................................................................................2266
38.3 Channel Threshold Detection.....................................................................................................................................2267
38.5.1 LRADC Control Register 0 (HW_LRADCCTRL0)...............................................................................2271
38.5.5 LRADC Status Register (HW_LRADCSTATUS)..................................................................................2282
38.5.6 LRADC 0 Result Register (HW_LRADCCH0)......................................................................................2284

38.5.13 LRADC 7 (BATT) Result Register (HW_LRADCCH7)........................................................................2296
38.5.14 LRADC Scheduling Delay 0 (HW_LRADCDELAY0)..........................................................................2298
38.5.18 LRADC Debug Register 0 (HW_LRADCDEBUG0).............................................................................2304
38.5.19 LRADC Debug Register 1 (HW_LRADCDEBUG1).............................................................................2304
38.5.20 LRADC Battery Conversion Register (HW_LRADCCONVERSION)..................................................2306
38.5.22 LRADC Theshold0 Register (HW_LRADCTHRESHOLD0)................................................................2311
38.5.23 LRADC Theshold1 Register (HW_LRADCTHRESHOLD1)................................................................2313
38.5.24 LRADC Version Register (HW_LRADCVERSION).............................................................................2314
Chapter 39
Register Macro Usage
39.1 Overview.....................................................................................................................................................................2317
39.2 Definitions..................................................................................................................................................................2317
39.3 Background.................................................................................................................................................................2318
39.3.1 Multi-Instance Blocks.............................................................................................................................2319
39.3.1.1 Examples...............................................................................................................................2319
39.4 Naming Convention....................................................................................................................................................2320
39.5 Examples.....................................................................................................................................................................2321
39.5.1 Setting 1-Bit Wide Field..........................................................................................................................2322
39.5.2 Clearing 1-Bit Wide Field........................................................................................................................2322

39.5.3 Toggling 1-Bit Wide Field.......................................................................................................................2322
39.5.4 Modifying n-Bit Wide Field....................................................................................................................2322
39.5.5 Modifying Multiple Fields......................................................................................................................2322
39.5.6 Writing Entire Register (All Fields Updated at Once)............................................................................2323
39.5.7 Reading a Bit Field..................................................................................................................................2323
39.5.8 Reading Entire Register...........................................................................................................................2323
39.5.9 Accessing Multiple Instance Register.....................................................................................................2323
39.5.10 Correct Way to Soft Reset a Block..........................................................................................................2324
39.5.10.1 Pinmux Selection During Reset............................................................................................2324
39.5.10.1.1 Correct and Incorrect Reset Examples................................................................2324
39.6 Summary Preferred.....................................................................................................................................................2325
39.7 Summary Alternate Syntax.........................................................................................................................................2325
39.8 Assembly Example.....................................................................................................................................................2325

Chapter 1
Product Overview
1.1 i.MX28 Overview

The i.MX28 is a low-power, high performance application and a multi-media processor
aimed at the following market segments:
• Human Machine Interface (HMI) panels: industrial, home.
• Industrial drive, PLC, I/O control display, factory robotics display.
• Graphical remote controls.
• Handheld scanners and printers.
• Electronic point-of-sale (POS) terminals.
• Smart energy gateways/meters.
• Media gateways.
• Portable medical devices.
• Media phones, VoIP.
• Automotive infotainment.
1.2 Hardware Features

The Hardware Features of the i.MX28 are as follows:
• ARM926 CPU Running at greater than 450 MHz at 1.45 V
• Integrated ARM926EJ-S CPU
• 32-Kbyte data cache and 16-Kbyte instruction cache
• ARM Embedded Trace Macrocell (ETM CoreSight 9)

Hardware Features
• Parallel JTAG interface

• Resistor-less boot mode selection using integrated OTP values
• 128 Kbytes of Integrated Low-Power On-Chip RAM

• 128 Kbytes of Integrated Mask-Programmable On-Chip ROM
• High Performance and Flexible External Memory Interface (EMI)
• Supports DDR2-400 (1.8 V), LP-DDR1-400 (1.8 V) and LV-DDR2-400 (1.5 V)
• 16-bit data-width with up to two chip-selects
• Rich arbitration features and high-performance AXI & AHB bus interface
• Integrated ODT and control for DDR2 applications
• Up to 200 MHz DDR clock frequency with voltage over drive
• 1280 bits of On-Chip One-Time-Programmable (OCOTP) ROM
• Two 802.3 compatible 10/100 Ethernet MAC supporting IEEE® 1588 protocols and
one 3-port L2 switch
• Two FlexCAN2 interfaces supported
• Full Implementation of the CAN protocol specification, Version 2.0B
• 64 Message Buffers of zero to eight bytes data length
• Low power modes, with programmable wake up on bus activity
• Two instances of Universal Serial Bus (USB) High-Speed — Up to 480 Mb/s

• One USB 2.0 on-the-go (OTG) device/host and one USB 2.0 host
• Fully integrated high/full/low-speed/ Physical Layer Protocol (PHY)
• OTG capable (uncertified by USB-IF)
• Power Management Units

• Single DC-DC switched converter supporting Li-Ion batteries.
• Features multi-channel outputs for VDDIO (3.3 V), VDDD (1.2 V), VDD1P5 (1.5
V), VDDA (1.8 V) and regulated 4.2 V source

Chapter 1 Product Overview
• 1.5 V linear regulator with programmable current limits for load and battery charge
circuits
• Silicon speed and temperature sensors enable adaptive power management over
temperature and silicon process
• Integrated temperature based power shut-down safety modes
• Optimized for very long battery life

• 16-Channel Low-Resolution ADC
• Seven independent channels and nine dedicated channels
• 4/5 wires resistive touchscreen controller
• 8 × 8 key pad panel matrix
• Temperature sensor controller
• Absolute accuracy of 1.3%
• Up to 0.5% with bandgap calibration
• Single Channel High Speed ADC (HSADC)

• Up to 2 Msps sample rate
• Sample precision configurable for 8/10/12 bits
• Three trigger modes supporting to start ADC conversion
• Security Features
• Read-only unique ID for digital rights management algorithms
• Secure boot using 128-bit AES hardware decryption
• SHA-1 and SHA-256 hashing hardware
• Customer-programmed (OTP) 128 bit AES key is never visible to software
• High Assurance Boot (HAB4)
• Wide Assortment of External Media Interfaces

• Up to eight NAND Flash memories with hardware management of device
interleaving

Hardware Features
• High-speed MMC, secure digital (SD)

• Hardware BCH ECC engine allowing for up to 20-bit correction with programmable
NAND page layout.
• Dual Peripheral Bus Bridges with 32 DMA Channels

• Multiple peripheral clock domains to save power while optimizing performance
• Direct Memory Access (DMA) with sophisticated linked DMA command
architecture saves power and off-loads the CPU
• Highly Flexible Display Controller

• Up to 24-bit RGB (DOTCK) modes
• Up to 24-bit system-mode including VSYNC and WSYNC modes
• 8-bit data ITU-R/BT.656 D1 digital video stream output mode (PAL/NTSC), with
on-the-fly RGB to YCbCr color-space-conversion
• Flexible input formats
• Pixel Processing Pipeline (PXP)

• Provides full path from color-space conversion, scaling, alpha-blending to rotation
without intermediate memory access
• Bi-linear scaling algorithm with cropping and letterboxing with up to 4:1
downscaling (720p to QVGA for example)
• Alpha-blend, color-keying
• Memory efficient block-based rotation engine
• Supports up to eight overlays
• 8 × 8 and 16 × 16 programmable block size for DRAM bus-width matching resulting
in optimized efficiency.
• Data Co-Processor (DCP)

• AES 128-bit encryption/decryption
• SHA-1 and SHA256 hashing

• High-speed memory copy

• Bit Blit
• Six Universal Asynchronous Receiver-Transmitters (UARTs)

• Five high-speed application UARTs operating up to 3.25 Mb/s with hardware flow
control, dual DMA and auto baud-rate detection
• Debug UART operates at up to 115 Kb/s using programmed I/O
• Two I2C Master/Slave Interfaces

• Up to 400 Kb/s
• DMA control of an entire EEPROM or other device read/write transaction without
CPU intervention
• PIO and PIO queue modes controlled by CPU. In PIO queue mode, commands and
data are queued up with FIFOs
• Both 7-bit and 10-bit device address supported in master mode. Programmable
7-bit address employed in slave mode
• Four Synchronous Serial Ports (for SPI, MMC, SDIO, Triflash)

• Up to 52 MHz external SSP clock for SD/MMC mode
• 1-bit, 4-bit and 8-bit MMC/SD/SDIO modes
• Compliant with SDIO Rev. 2.0
• Support eMMC4.3 and eMMC4.4
• SPI with single, dual and quad modes
• Four-Channel 32-Bit Timer with Rotary Decoder

• Eight-Channel Pulse Width Modulator (PWM)
• Real-Time Clock
• Alarm clock can turn the system on
• Uses the existing 24-MHz XTAL for low cost or optional low power crystal (32.768
KHz or 32.0 KHz), customer-selectable through OTP

i.MX28 Product Features
• SPDIF Transmitter
• Dual Serial Audio Interface (SAIF), Three Stereo Pairs
• Full-duplex stereo transmit and stereo receive operations
• Cell phone baseband processor connection and external ADCs and DACs
• Bluetooth hands-free connection (with full-duplex voice)
• Analog I/O for peripheral bus breakouts
• I2S, left-justified, right-justified, PCM, and non-standard formats
• Customer-Programmable One-Time-Programmable (OTP) ROM through Integrated

eFuse Block
• Resistorless boot mode selection
• 128-bit boot mode crypto key
• Boot mode specification of NAND characteristics for device that the customer is
soldering to the board. This means no more costly delays waiting for new device
support in the boot ROM.
• Fully software-programmable and accessible
• Flexible I/O Pins

• All digital pins have drive-strength controls as described in Pin Drive Strength
Selection.
• Almost all non-EMI digital pins have general-purpose input/output (GPIO) mode
• Offered in 289-Pin Ball Grid Array (BGA)
1.3 i.MX28 Product Features

The following figure shows the block diagram of a typical system based on the i.MX28.

USB Host Cellular USB FS/HS 32.0/32.768 kHz

Connectivity Host/Device & 24.0 MHz Crystals
USB PHY USB PHY Dual XTAL,

USB
(HS/FS/LS) USB
(HS/FS/LS) USB ,WDog
RTC,ALARM
Host, Debug,
5+1 UARTs
Bluetooth, GPS
USB 2.0 USB 2.0 PLLs and
OTP 1.25Kbit USB
Host USB
Device/Host CLKGEN
eePROM 50MHz/25MHz Clock
Sensors 2 x I2C 50MHz PLL Output for Ethernet
AXI/AHB/APB Busses (ENET) PHY
UI: LED/Switches GPIO / Pin Cntl
High- Speed 1-2MHz Data
ETM
UI: Rotary 4 x Timers /1 x ROT 16 KB 32 KB E.g. Linear Image
ADC Sensor
Serial Audio I$ D$
Input/Output
In/Out 2x SAIF TX/RX
ICOLL
Class-D Temperature
DSP
SPDIF Out SPDIF TX Thermal Protection
I/O Pin Multiplexer ARM926EJ-S
454 MHz
JTAG
SD, SDIO, MMC,
4 x SSP
CE-ATA , SPI, SSI Low- UI: Buttons,
General Purpose
Touch-Screen
Media Interface Resolution
NAND Flash
ADC x16
Controller
SLC/MLC ECC (20-bit) On-Chip On-Chip
ROM RAM
32 K x 4x8Kx
Beep, LED, Control
Pulse Width
32 bits 32 bits 3-Channel 1.2V
Modulator 1.5V
(128 KB) (128 KB) Battery DC-DC / 1.8V
Charger 5-Channel 3.3V
RGB, 68/80, LCD Interface LDO 4.2V
BT.601/BT.656 Data Co-
Processor
Ethernet MAC (Memcpy/Crypto) 5 V Input
Dual 10/100 Ethernet, Controller (USB or
IEEE1588 Wall Supply)
Pixel Pipeline
L2 Switch
Controller Area
Network 2 x FlexCAN APBH/APBX
16-bit
LP-DDR1-400,
DDR2-400
EMI
DMA
i.MX28x Rechargeable
Li-ION Battery
LV -DDR2-400
Key:
- Mixed signal
- Applications processing and peripherals
Figure 1-1. System Block Diagram
The i.MX28 features low power consumption to enable long battery life in portable
applications. The integrated power management unit includes highly-efficient on-chip
DC-DC converters. The power management unit also includes an intelligent battery charger
and detector for Li-Ion cells and is designed to support Adaptive Voltage Control (AVC),
which can reduce the system power consumption by half. AVC also allows the chip to
operate at a higher peak CPU operating frequency than typical voltage control systems. The
DC-DC converters and the clock generators can be reprogrammed on-the-fly to trade off
power versus performance dynamically.
To provide the maximum application flexibility, the i.MX28 integrates a wide range of I/O
ports. It can efficiently interface to nearly any type of flash memory, serial bus, LCD or
HDMI/MHL transmitter. It is also ready for advanced connectivity applications such as
Bluetooth, WiFi and Cellular Data Model through its integrated 4-bit SDIO controller,
high-speed (3.25 Mb/s) UARTs and secondary USB host PHY.

An ARM926EJ-S CPU with 16K I$ & 32K D$ L1-caches and 128 Kbytes of on-chip SRAM
provides the processing power needed to support advanced features such as web browsing
and portable gaming (together with graphics and video processing hardware). Contact the
local Freescale representative for more information on the software board support packages
available for the i.MX28.
Execution always begins in on-chip ROM after reset, unless overridden by the debugger.
A number of devices are programmed only at initialization or application state change, such
as DC-DC converter voltages, clock generator settings and so on. Certain other devices
either operate in a crystal clock domain or have significant portions that operate in a crystal
clock domain, for example, ADC, PLLs and so on. These devices operate on a slower speed
asynchronous peripheral bus. Write posting in the ARM core, additional write post buffering
in the peripheral AHB, and set/clear operations at the device registers make these operations
efficient.
1.3.1 ARM9 CPU Subsystem

The on-chip RISC processor core is an ARM926EJ-S CPU. This CPU implements the ARM
v5TE instruction set architecture. This CPU has two instructions sets, a 32-bit instruction
set used in the ARM state and a 16-bit instruction set used in the Thumb state. The core
offers the choice of running in the ARM state or the Thumb state or a mix of the two states.
This enables optimization for both code density and performance. ARM studies indicate
that Thumb code is typically 65% the size of the equivalent ARM code, while providing
160% of the effective performance in a constrained memory bandwidth applications. The
ARM CPU is described in Overview.
The ARM RISC CPU is the central controller for the entire SOC, as shown in System Buses.
• AHB1—Used for ARM instruction fetches
• AHB2—Used for ARM data load/stores
1.3.2 System Buses

The i.MX28 uses buses based on ARM's Advanced Microcontroller Bus Architecture
(AMBA) for the on-chip peripherals. The AMBA2 specification
(http://www.arm.com/products/solutions/AMBA_Spec.html) outlines two bus types: AHB
and APB. The AMBA3 specification (http://www.arm.com/products/solutions/axi_Spec.html)
additionally outlines the AXI fabric. The three bus types are explained as follows:

• AXI is the highest-performance AMBA bus that supports de-coupled R/W channels,
multiple outstanding transactions, and out-of-order data capability. This leads to higher
performance and more efficient use of external memory.
• AHB is a higher-performance bus that supports multiple masters such as the CPU and
DMA controllers.
• The APB is a lower-speed peripheral bus.
As shown below, the i.MX28 uses a three-layer AHB, one AXI 64bit bus and two APB
buses (APBH and APBX).
S M
M
USB1 APBX Bridge/DMA
M S ASYNC
S M
M
APBH Bridge/DMA ETM9 SPDIF
USB0 M S DUART
slave TX
S
DFLPT CAN0 DIGCTL AUART 0 UTM1
S
S (MAC0) M
uDMA0 S DRAM_REGS
AUART 1
CAN1 GPMI UTM2
ahb2apbs
2xMAC
APB 3:1
S (MAC1) S
+
Switch 128K
S (SW)
M HSADC ICOLL AUART 2 POWER
uDMA1 OCROM
APBH (v3) – 200MHz
APBX (v3) – 24MHz

S
OCOTP AUART 3 PWM

64 S
ETM9 Coresight DCP
AHB_ARB1
M
M 32 AHB
Instr Fetch PINCTRL AUART 4 RTC
Axi0 (PL301 4x2) - 200MHz
ARM 926 32K+16K 64 S

(D$) ( I$) BCH
AHB_ARB2
M
M 32 AHB
Data R/Write SSP0 I2C0 LRADC
64 S
AHB_ARB3
32K SRAM PXP

M
32K SRAM OCRAM I2C1
SSP1 TIMROT
Controller
32K SRAM (word intlv) 64 S
32 AHB0
LCDIF
32K SRAM M
SSP2 SAIF0 CLKCTRL
64 S
PERFMON
S
SSP3 SAIF1
32 32 32 64
SYNC/ SYNC/ SYNC/ SYNC/
ASYNCH ASYNCH ASYNCH ASYNCH
EMI – DDR2-400, LV -DDR2-400, LP-DDR1-400 16-bit
Figure 1-2. i.MX28 SOC System Buses
1.3.2.1 AXI Bus Segments

The AXI0 bus-segment on the i.MX28 provides several high-bandwidth/performance-critical
peripherals, a tightly-coupled and efficient interface to Port-0 of the external memory
controller. The peripherals are as follows:
• DCP (Crypto/Memcpy)


• Display Controller (LCDIF)
• BCH-ECC Engine
i.MX28 also contains one bus performance monitor modules (PERFMON). There is one
PERFMON per AXI segment. The key features of the PERFMON are as follows:
• Real-time performance statistics collection on three AXI buses
• Single or multiple master transactions monitoring
• Various interrupts support: address trap, latency threshold and so on
• AXI protocol and out-of-order sequence support
• Parameterized performance monitor for scalability
1.3.2.2 AHB Buses

The AHB is the main high-performance system bus and is implemented in three layers, as
follows:
• Layer 1 (AHB1)—CPU instruction access to OCRAM, OCROM
• Layer 2 (AHB2)—CPU data access to OCRAM, OCROM, all bridges, Ethernet, USB
and DFLPT slaves
• Layer 3 (AHB3)—APBH DMA, APBX DMA, Ethernet and USB masters
The ARM926 instruction bus (AHB1) is a single-master layer as the ARM926 data bus
(AHB2). The AHB3 has multiple masters, as shown in Figure 1-2.
The ARM926 data bus connects to all the slaves in the system, including RAMs, ROMs,
bridge slaves, Ethernet and USB slaves. The APB peripherals can act as AHB slaves through
the AHB-APB bridge. The AHB has nine slaves:
• USB slave
• Ethernet slave
• On-chip RAM
• On-chip ROM

• Default first-level page table

• Two APB bridges
Each layer of the AHB bus allows one active transaction at a time. A transaction is initiated
by a master, controlled by an arbiter, and serviced by the slave at the corresponding address.
A transaction can be as short as a single byte, or as long as a CPU cache line (32 bytes).
For the USB, a transaction can be much longer, up to 512 bytes.
AHB bus clock is named as the abbreviated "HCLK" or "clk_h" in the reference manual.
1.3.2.3 APB Buses

There are two APB buses on the i.MX28:
• APBH - The APBH (H DMA) is an AMBA2 APB system peripheral bus. This bus
comprises of the APBH peripherals such as those accessed through the APBH DMA
engine. The APBH peripherals are typically high-speed I/Os.
• APBX - The APBX (X DMA) is an AMBA2 APB system peripheral bus. This bus is
asynchronous to other system buses. This bus comprises of the APBX peripherals such
as those accessed through the APBX DMA engine. The APBX peripherals are typically
low speed I/Os or analog control related.
The “H” in APBH denotes that the APBH is synchronous to AHB's HCLK, as compared
to APBX, which runs on the crystal-derived XCLK. The APBX bus clock is named as the
abbreviated "XCLK" or "clk_x" in the reference manual.
The ARM926 data bus connects to all the slaves in the system, including RAMs, ROMs,
bridge slaves, USB and Ethernet slaves.
1.3.3 On-Chip RAM and ROM

The device includes 128 KB of on-chip RAM (OCRAM) implemented as four physical
banks. It adopts a 4-port, word interleaved topology to maximize performance in a multi-layer
bus system.
The device also includes 128 KB of on-chip mask-programmable ROM. The ROM contains
initialization code written by Freescale Inc. to handle the initial boot and hardware
initialization. Software in this ROM offers a large number of boot configuration options,
including manufacturing boot modes for burn-in and tester operation.

Other boot modes are responsible for loading the application code from off-chip into the
on-chip RAM. It supports initial program loading from a number of sources:
• NAND Flash devices
• SD2.0/MMC4.4, 4.3,4.2
• SPI from EEPROM devices or NOR Flash devices
• USB recovery mode
• I2C
At power-on time, the first instruction executed by the ARM core comes from this ROM.
The reset boot vector is located at 0xFFFF0000. The on-chip boot code includes a firmware
recovery mode. If the device fails to boot from NAND Flash, or hard drive, for example,
the device will attempt to boot from a PC host connected to its USB port.
The ROM boot loader can be restricted to boot only properly certified load packages. This
function is enabled by an OTP bit. Additional laser fuse bits select one of the 16 customer
keys, which are further modified by laser fuses. A polynomial LSFR is used to decrypt the
supplied boot package. A second polynomial computes an authentication code for the load
package. If the decrypted package does not compute the correct authentication code, then
the boot loader will enter recovery mode and attempt to boot from the USB device.
See Boot Modes for more information.
Memory Map Overview shows the memory map as seen by the processor. Any blank entries
indicate that nothing is mapped at that address. No accesses should be made to these
addresses because the results are indeterminate. The Decode Block column indicates the
decode group to which each peripheral belongs. Most peripherals reside on the APBH,
APBX and Axi0 (through AHB0).
1.3.4 On-Chip One-Time-Programmable (OCOTP) ROM

The device contains 1280 bits of One-Time-Programmable (OTP) ROM. The OTP is
segmented into five distinct physical banks. Each bank is further divided logically into eight
32-bit words. The OTP serves several functions:
• Housing of hardware and software capability bits (copied into shadow registers).
• Housing of Freescale operations and unique-ID fields.
• Housing the customer-programmable cryptography key.
• Four words for customer general use.

• A 32-bit word is dedicated to controller read and write locking of the various OTP
regions (copied into a shadow register).
• Storage of various ROM configuration bits.
• Storage of HAB data.
Access to the OTP is done through a memory-mapped APBH slave interface. Each of the
32 words is memory-mapped on APBH for the purpose of reading (requires a bank-opening
sequence). Writing to the OTP is done through an address and data interface, where software
provides the OTP word number (one of 32) and a programming mask.
See OCOTP Overview for more information.
1.3.5 External Memory Controller (EMI)

The i.MX28 contains a fully embedded DRAM controller solution including a multi-port
AXI & AHB arbiter, control and PHY. The key features are as follows:
• Support for DDR2 (1.8 V), LP-DDR1 (1.8 V) and LV-DDR2 (1.5 V) up to 200 MHz
clock rate (400 MHz data-rate).
• Support for up to 1024 MB with any combination of DRAMs up to two chip-enables.
• Fully pipelined command, read and write data interfaces to the memory controller.
• Advanced bank look-ahead features for high memory throughput.
• Front-end interface to three AHB ports and one AXI port with optimized buffering for
high-bandwidth capability.
• A programmable register interface to control memory device parameters.
• Full initialization of memory on memory controller reset.
• Delay-Line for reliable data capture timing across process, temperature and all supported
voltage ranges.
• Integrated On Device Termination (ODT) for DDR2 applications.
• Supports all levels of power modes for various device types.
See Overview for more information on the EMI.

1.3.6 Interrupt Collector

The i.MX28 contains a 128-bit vectored interrupt collector for the CPU's IRQ input and a
separate non-vectored interrupt collection mechanism for the CPU's FIQ input. Each interrupt
can be assigned to one of the four levels of priority. The interrupt collector supports nesting
of interrupts that preempt an interrupt service routine running at a lower priority level. Each
of the 128 interrupts is assigned its own 32-bit programming register and can be set for HW
source IRQ, SW source IRQ or HW source FIQ.
See Interrupt Collector (ICOLL) Overview for additional information.
1.3.7 Default First-Level Page Table

The device contains a default first-level page table (DFLPT) implemented as an AHB slave.
This device provides an economical way to present 16 Kbytes of L1 page table entry data
to the ARM CPU's MMU. This page-table is connected to the AHB bus at base address
0x800C0000. The DFLPT provides 16 movable and scalable entries such that each entry
can span up to128 locations. This allows the DFLPT to be used for systems with large
external memories.
See Default First-Level Page Table (DFLPT) Overview for additional information.
1.3.8 DMA Controller

Many peripherals on the i.MX28 use direct memory access (DMA) transfers. Some
peripherals, such as the USB controller, make high random accesses to the system memory
for a large number of descriptor, queue heads, and packet payload transfers. This high
random access nature is supported by integrating a dedicated DMA into the USB controller
and connecting it directly to the high-speed AHB bus.
Similarly, the DCP (crypto/memcpy), BCH-ECC and LCD controller (legacy DMA mode)
devices contain their own bus masters to allow more random accesses to the system memory.
Other peripherals have small number of high sequential transactions, for example the ADC
streams, SPDIF transmitter, and so on. These devices share a centralized address generation
and a data transfer function that allows them to share a single shared master on the AHB.
As mentioned previously, there are two AMBA peripheral buses on the i.MX28:
• The APBH bus runs at 200 MHz clock domain.
• The APBX bus runs in an independent XCLK clock domain that can be slowed down
significantly for power reduction.
See AHB-to-APBH Bridge Overview and AHB-to-APBX Bridge Overview for more detailed
information.
The two bridge DMAs are controlled through linked DMA command lists. The CPU sets
up the DMA command chains before starting the DMA. The DMA command chains include
set-up information for a peripheral and associated DMA channel. The DMA controller reads
the DMA command, writes any peripheral set up, informs the peripheral to start running
and then transfers data, all without CPU intervention. The CPU can add commands to the
end of a chain to keep data moving without interventions.
The linked DMA command architecture off loads most of the real-time aspects of I/O control
from the CPU to the DMA controller. This provides better system performance, while
allowing longer interrupt latency tolerances for the CPU.
1.3.9 Clock Generation Subsystem

The i.MX28 uses several different clock domains to provide clocks to various subsystems,
as shown in Figure 10-1. These clocks are either derived from the 24-MHz crystal or from
one of the integrated high-speed PLLs. There are three PLLs in the i.MX28:
• PLL0 - 480 MHz with multiple phase-fractional and integer post-dividers used to clock
the AXI and APB buses (except for APBX), I/O peripherals, multimedia/display
hardware and the external memory interface. It also acts as the primary PLL for USB0.
• PLL1 - 480 MHz dedicated purely for USB1.
• PLL2 - 50 MHz dedicated to the Ethernet hardware with additional post-divider for
lower frequencies.
See Clock Generation and Control (CLKCTRL) Overview for additional information about
the system clock architecture.
The system also includes a real-time clock that can use either the 24-MHz system crystal
or an optional low power crystal oscillator running at either 32.768 KHz or 32.0 KHz
(customer-configurable through OTP). An integrated watchdog reset timer is also available
for automatic recovery from an errant code execution.
See RTC Overview for more information about these features.

1.3.10 Power Management Unit

The i.MX28 contains a sophisticated Power Management Unit (PMU), including one
integrated DC-DC converter, four linear regulators, one regulated 4.2 V output and battery
chargers. The PMU can operate from a Li-Ion battery using the DC-DC converters or a 5-V
supply using the linear regulators and can automatically switch between them without
interrupting the operation. The PMU includes circuits for battery and system voltage
brownout detection, as well as the on-chip temperature, digital speed, and process monitoring.
In addition, there exist safety features such as thermal shut-down and battery charge current
cut-off based on the external thermistor (through LRADC). The integrated PMU converter
can be used to provide programmable power for the device as well as the entire application
on up to five rails:
• VDD4P2 (nominal 4.2 V) -- when connected to 5 V source, can source the DC-DCs
• VDDIO (nominal 3.3 V) -- DC-DC or linear-regulator from 5 V
• VDDA (nominal 1.8 V) -- DC-DC or linear-regulator from VDDIO
• VDD1P5 (nominal 1.5 V) -- linear-regulator from VDDIO for LVDDR2
• VDDD (nominal 1.2 V) -- DC-DC or linear-regulator from VDDA
The 4.2 V regulated output also allows the programmable current limits:
• Total load plus battery charge current (5 V limit)
• Battery charge current
• Load current -- for both on-chip and off-chip circuits
The 4.2 V circuit is capable of adjusting distribution of current supply between the load and
the battery-charger depending on the programmed current-limits and the load conditions.
For example, when the battery charging exceeds the 5 V current limit, the 4.2 V regulator
steals the current from the battery-charger circuit and diverts it to the load circuit. The
converter can be configured to operate from the standard Li-Ion battery up to 4.2 V. These
converters use off-chip reactive components (L/C) in a pulse-width or frequency-modulated
DC-DC converter. The real-time clock includes an alarm function that can be used to
wake-up the DC-DC converters, which then wakes up the rest of the system.

1.3.11 Ethernet Interfaces

The i.MX28 includes extensive Ethernet connectivity support. Ethernet controller includes
two programmable 10/100 IEEE 802.3 Ethernet MACs. There is one time stamping module
for each MAC to support Ethernet applications requiring precise timing references for
incoming and outgoing frames to implement a distributed time synchronization protocol
such as the IEEE 1588.
In addition to this, a hardware 3-port switch is supported for either redundancy (dual cables)
or daisy-chaining (packet forwarding) to support automatic extension of control networks.
Two unified DMA blocks allows backward compatibility to legacy FEC interface (note that
all uDMA programming is performed through the MAC0 and MAC1 register interfaces).
1.3.12 CAN Interfaces

The i.MX28 includes dual FlexCAN2 controllers which are compatible with the CAN 2.0B
protocol specification [Ref. 1]. The CAN Protocol Interface (CPI) manages the serial
communication on the CAN bus, requesting RAM access for receiving and transmitting
message frames, validating received messages and performing error handling. The Message
Buffer Management (MBM) handles Message Buffer selection for reception and transmission,
taking care of arbitration and ID matching algorithms.
1.3.13 USB Interfaces

The i.MX28 includes two high-speed Universal Serial Bus (USB) version 2.0 controllers
and integrated USB Transceiver Macrocell Interface (UTMI) PHYs. The i.MX28 device
interface can be attached to USB 2.0 hosts and hubs running in the USB 2.0 high-speed
mode at 480 Mbits per second. It can be attached to USB 2.0 full-speed interfaces at 12
Mbits per second. Note that a dual-device configuration is not supported.
The USB controllers and integrated PHYs support high-speed Host modes for peer-to-peer
file interchange. The USB controller can also be configured as a high-speed host.
The USB subsystem is designed to make efficient use of system resources within the i.MX28.
It contains a random-access DMA engine that reduces the interrupt load on the system and
reduces the total bus bandwidth that must be dedicated to service the five on-chip physical
endpoints.

Each USB is a dynamically configured port that can support up to seven RX and seven TX
endpoints besides EP0, each of which may be configured for bulk, interrupt, or isochronous
transfers. The USB configuration information is read from on-chip memory through the
USB controller's DMA.
See USB High-Speed OTG-capable USB Controller Overview and USB PHY Overview
for more information.
1.3.14 General-Purpose Media Interface (GPMI)

The chip includes a general-purpose media interface (GPMI) controller that supports NAND
devices (all packages).
The NAND Flash interface provides a state machine that provides all the logic necessary
to perform DMA functions between on-chip or off-chip RAM and up to eight NAND Flash
devices. The controller and DMA are sophisticated enough to manage the sharing of a single
8-bit wide data bus among eight NAND devices, without detailed CPU intervention. This
allows the i.MX28 to provide unprecedented levels of NAND performance.
The general-purpose media interface can be described as two fairly independent devices in
one. The three operating modes are integrated into one overall state machine that can freely
intermix cycles to different device types on the media interface. There are eight chip selects
on the media interface. Each chip select can be programmed to have a different type device
installed.
The GPMI pin timings are based on a dedicated clock divider from PLL0, allowing the
CPU clock divider to change without affecting the GPMI.
See General-Purpose Media Interface Overview for more information.
1.3.15 Hardware Acceleration for ECC for Robust External Storage

The hardware ECC accelerator provides a forward error-correction function for improving
the reliability of various storage media that may be attached to the i.MX28. Modern
high-density NAND Flash devices presume the existence of forward error-correction
algorithms to correct some soft and/or hard bit errors within the device, allowing higher
device yields and, therefore, lower NAND device costs.
The i.MX28 contains an Error Correction Code (ECC) hardware engine implementing the
Bose Ray-Choudhury Hocquenghem algorithm for up to 20 bits of correction. The ECC
engine is tightly coupled to the GPMI and has a dedicated programming model and a DMA
structure.

1.3.15.1 Bose Ray-Choudhury Hocquenghem ECC Engine

The Bose, Ray-Chaudhuri, Hocquenghem (BCH) Encoder and Decoder module is capable
of correcting from 2 to 20 single bit errors within a block of data not larger than about 900
bytes (512 bytes is typical) in applications such as protecting data and resources stored on
modern NAND Flash devices. The correction level in the BCH block is programmable to
provide flexibility for varying applications and configurations of flash page size. The design
can be programmed to encode protection of 2, 4, 8, 10, 12, 14, 16, 18, or 20 bit errors when
writing into the flash and to correct the corresponding number of errors on decode. The
correction level when decoding MUST be programmed to the same correction level as that
was used during the encode phase.
BCH-codes are a type of block-code, which implies that all error-correction is performed
over a block of N-symbols. The BCH operation will be performed over GF (213 = 8192),
which is the Galois Field consisting of 8191 one-bit symbols. BCH encoding (or encode
for any block-code) can be performed by either of the two algorithms: systematic encoding
or multiplicative encoding. Systematic encoding is the process of reading all the symbols
which constitute a block. These symbols are divided continuously by the generator
polynomial for the GF (8192) and the resulting t parity symbols are appended to the block
to create a BCH codeword (where t is the number of correctable bits).
The BCH sits on the AXI fabric with close coupling to both the GPMI and the external
memory controller.
See BCH Overview for more information.
1.3.16 Data Co-Processor (DCP)—Memory Copy, Crypto

The device contains a data co-processor consisting of four virtual channels. Each channel
is essentially a memory-to-memory copy engine. The linked list control structure can be
used to move the byte-aligned blocks of data from a source to the destination. In the process
of copying from one place to another, the DCP can be programmed to encrypt or decrypt
the block using AES-128 in one of the several chaining modes. An SHA-1 or SHA256 hash
can be calculated as part of the memory-copy operation.
See Data Co-Processor (DCP) Overview for more information.

2
1.3.17 I C Interface
The i.MX28 contains two two-wire SMB/I2C bus interfaces. Each interface can act either
as a slave or a master on the SMB interface. The on-chip ROM supports boot operations
from I2C mastered EEPROMs, as well as slave I2C boot mode. I2C flexibly supports three
transaction modes: DMA, PIO and PIO queue modes.
See I2C Overview for more information.
1.3.18 General-Purpose Input/Output (GPIO)

The i.MX28 contains 124 GPIO pins in the 289-pin BGA package. Most digital pins (except
for EMI pins) that are available for specific functions are also available as GPIO pins if
they are not otherwise used in a particular application. All GPIO pins support both 1.8V
and 3.3V VDDIO. See Pin Control and GPIO Overview for more information.
1.3.19 Display and Capture Processing

In order to support a variety of multimedia-rich use-cases, the i.MX28 contains a powerful
and flexible display and capture sub-system comprised of the following components:
• Display Controller (LCDIF)

8 x Overlays Video YUV

RGB (S1) (S0)
PXP Block
CSC + Scale
Colorkey / Alpha-Blend
Rotation
LCDIF Block
Display Out
(RGB, System,
BT.656)
To LCD Pins
Figure 1-3. i.MX28 Display System
1.3.19.1 Display Controllers / LCD Interfaces (LCDIF)

The device contains the LCDIF display controller module which connects to the AXI bus.
Some of the key features of the LCDIFs are as follows:
• Very flexible display support which allows for connection to a wide variety of display
interfaces.
• AXI master on the AXI bus segment with large efficient request sizes and support for
outstanding transfer requests.
• Ability to drive 24-bit RGB/DOTCK displays up to WVGA at 60 Hz. High robustness
guaranteed by 512-pixel FIFO with under-run recovery.
• Support for full 24-bit system mode (8080/6080/VSYNC/WSYNC).

• ITU-R/BT.656 compliant D1 digital video output mode with on-the-fly RGB to YCbCr
color-space-conversion. This output mode is suitable for driving the external
TV-Encoder.
• Support for a wide variety of input and output formats that allows for conversion between
input and output (for example, RGB565 input to RGB888 output). Also support for
packed byte formats.
The APB DMA mode still exists for backward compatibility, but is not recommended for
driving displays larger than QVGA (320 × 240).
See LCD Interface (LCDIF) Overview for more information.
1.3.19.2 Pixel Processing Pipeline (PXP)

The PXP performs all necessary post display frame pre-processing in hardware with minimal
CPU overhead. The PXP operation and features can be described as follows:
• The PXP can be programmed to operate in either 8 × 8 or 16 × 16 block modes. When
using 32-bit memories with the EMI, 16 ×16 block mode is recommended to allow for
efficient memory access. Because the PXP accesses the blocks by requesting a line of
block, a 16-pixel fetch (one line of a block) will make full use of a 16-byte burst on the
EMI.
• The background image (for example, decoded video frames) is read from an external
memory (single-plane YUV, dual-plane Y/UV and three plane Y/U/V inter-leaved
source buffer formats are supported) into the internal buffers as either 8 × 8 or 16 ×16
pixel blocks. These buffers are then fed into a color-space converter (for example, YUV
to RGB) followed by the scaling engine which utilizes an advanced bi-linear weighted
scaling algorithm. The scaling operation is defined in terms of the output image (through
programmable offsets and cropping registers). The output of the scaler is fed into yet
another internal buffer called S0. If the background image is already in the RGB
color-space, it is assumed to be scaled appropriately for the required output format and
can thus be read directly into the internal S0 buffer. In order to maintain the efficient
use of an external memory, only the relevant (visible) portion of the background image
is fetched.
• The scaled RGB image (in the internal S0 buffer) can be blended with up to eight
programmable overlays. The co-ordinates of the overlays can once again be described
in terms of the resultant output image. Each overlay can have either a global
programmable opacity or a per-pixel resolution if constructed with RGB color-space.
In addition to this, each overlay can have a relative priority level such that when
constructing the output image, the PXP only fetches the visible overlay in the current

8 × 8 or 16 ×16 block. The overlays are fetched into the internal S1 buffer. Alpha
blending is performed on the S0 and S1 buffers to generate the blended output into the
internal S3 buffer. Other operations such as BITBLT and color-keying can also be
performed at this stage.
• The final stage of the PXP operation is the rotator which can perform flips and 90, 180
and 270 rotations. The rotator operates on the 8 × 8 or 16 ×16 pixel blocks in the S3
buffer to maximize external memory fetch efficiency. It writes 8 × 8 or 16 ×16 blocks
to the external memory in this final stage.
• The PXP supports scaling down up to 4:1 in single-pass mode. This is useful for scaling
720p decoded content to a QVGA display. The PXP can also be used to further scale
down images using a multi-pass approach which is enabled by the ability of the PXP
to write YUV output.
See Pixel Pipeling (PXP) Overview for more information on the PXP.
1.3.20 SPDIF Transmitter

The device includes a Sony-Phillips Digital Interface Format (SPDIF) transmitter. It includes
independent sample-rate conversion hardware so that the A/D, D/A and SPDIF can run
simultaneously. The SPDIF has a dedicated DMA channel. The SPDIF has its own clock
divider from the PLL.
See FlexCAN Introduction for more information.
1.3.21 Dual Serial Audio Interfaces

The i.MX28 SOC includes two Serial Audio Interfaces (SAIF), each with three stereo pairs.
The pin multiplexing scheme for i.MX28 allows a stereo transmitter and a stereo receiver
to be connected to external devices, either D/A and A/D converters or to a host processor,
such as a cell phone or BlueTooth controller.
See Serial Audio Interface (SAIF) Overview for more information.
1.3.22 Rotary Decoder

An automatic rotary decoder function is integrated into the chip. Two digital inputs are
monitored to determine which is leading and by how much. In addition, the hardware
automatically determines the period for rotary inputs.
See Timers and Rotary Decoder (TIMROT) Overview for more information.

1.3.23 UARTs
There are six UARTs (similar to 16550 UART) provided; five for application use and one
for debug. The application UARTs are high-speed devices capable of running up to 3.25
Mbits per second with 16-byte receive and transmit FIFOs. The application UARTs support
DMA and flow control (RTS/CTS). The debug UART does not use DMA channels.
See Application UART Overview and Debug UART Overview for more information.
1.3.24 Low-Resolution ADC, Touch-Screen Interface and

Temperature Sensor
The LRADC provides 16 physical channels of 12-bit resolution for analog-to-digital
conversion. Only eight "virtual" channels can be used at one time, but those eight channels
can be mapped to any of the 16 physical channels. Some physical channels have dedicated
inputs:
• Channel 15—VDD5V
• Channel 14—Bandgap reference
• Channel 13—VDDD
• Channel 12—VDDA
• Channel 11—VTH
• Channel 10—Sample VDDIO
• Channel 8 and 9—Internal temperature sense input
• Channel 7—Battery
The USB_DN/DP inputs can only be sampled with the LRADC in non-USB mode (see
HW_USBPHY_CTRL_DATA_ON_LRADC).
The remaining seven channels are available for other uses and can be used for resistive
button sense, touch-screens or other analog input. Channels 0 and 1 have integrated drivers
for external temperature monitor thermistors. Channels 2–6 have integrated drivers for
resistive touch-screens. The LRADC provides typical performance of 12-bit
no-missing-codes, 9-bit SNR, and 1% absolute accuracy (limited by the bandgap reference).
See LRADC Overview for more information.

1.3.25 High Speed ADC (HSADC) Controller

The high-speed ADC module is designed for driving the linear image scanner sensor (for
example, TOSHIBA TCD1304DG linear image scanner sensor). It can also support some
other general user cases which need to sample analog source with up to 2 Msps data rate
and then move the sample data to the external memory. The high-speed ADC module
integrates an 12-bit analog ADC module. This analog ADC module can support up to 2
Msps sample rate. In order to improve the flexibility, the high-speed ADC module can
co-work with PWM module which can generate driving signals of external device such as
the linear image scanner sensor. The PWM can also generate trigger signal which is
synchronous with high-speed ADC module to start the conversion of ADC. An APBH-DMA
channel is connected to the high-speed ADC module to move the sample data from the
asynchronous FIFO inside the high-speed ADC module to the external memory.
1.3.26 Pulse Width Modulator (PWM) Controller

The device contains eight PWM output controllers that can be used in place of GPIO pins.
Applications include LED brightness control, HSADC signal driving and high-voltage
generators for electroluminescent lamp (EL) display backlights. Independent output control
of each phase allows 0, 1, or high impedance to be independently selected for the active
and inactive phases. Individual outputs can be run in lock step with guaranteed
non-overlapping portions for differential drive applications.
See Pulse Width Modulator (PWM) Overview for more information.


Chapter 2
ARM CPU Complex
2.1 Overview
This chapter describes the ARM CPU included on the i.MX28 and includes sections on the
processor core, the JTAG debugger, and the embedded trace macrocell (ETM) interface.
2.2 ARM 926 Processor Core

The on-chip Reduced Instruction Set Computer (RISC) processor core is an ARM926EJ-S
CPU. This CPU implements the ARM v5TE instruction set architecture, which includes
the enhanced DSP instructions.
The ARM9EJ-S has two instruction sets: a 32-bit instruction set used in the ARM state and
a 16-bit instruction set used in the Thumb state. The core offers the choice of running in
the ARM state or the Thumb state or a mix of the two. This enables optimization for both
code density and performance. ARM studies indicate that Thumb code is typically 65% the
size of an equivalent ARM code, while providing 160% of the effective performance in
constrained memory bandwidth applications.
A block diagram of the ARM926EJ-S core is shown in Figure 2-1.
See http://www.arm.com/documentation/ARMProcessor_Cores/index.html to download
the following ARM documentation on the ARM926EJ-S core:
• ARM926EJ-S Technical Reference Manual, DDI0198D
• ARM926EJ-S Development Chip Reference Manual, DDI0287A
The ARM9 core has a total of 37 programmer-visible registers, including 31 general-purpose

32-bit registers, six 32-bit status registers, and a 32-bit program counter, as shown in Figure
2-2. In ARM state, 16 general-purpose registers and one or two status registers are accessible
at any one time. In privileged modes, mode-specific banked registers become available.

ARM 926 Processor Core
The ARM state register set contains 16 directly addressable registers, r0 through r15. An
additional register, the Current Program Status Register (CPSR), contains condition code
flags and the current mode bits. Registers r0–r13 are general-purpose registers used to hold
data and address values, with r13 being used as a stack pointer. Register r14 is used as the
subroutine link register (lr) to hold the return address. Register r15 holds the program counter
(PC).
The Thumb state register set is a subset of the ARM register set. The programmer has access
to eight general-purpose registers, r0–r7, the PC (ARM r15), the stack pointer (ARM r13),
the link register (ARM r14), and the CPSR.
Exceptions arise whenever the normal flow of program execution has to be temporarily
suspended, for example, to service an interrupt from a peripheral. Before attempting to
handle an exception, the ARM core preserves the current processor state, so that the original
program can resume when the handler is finished.
Unused Unused
ARM926EJ-S
Instruction Data
Embedded Trace
TCM TCM
Macrocell (ETM)
Interface Interface
Interface
Instruction Data
Cache
ARM9EJ-S Cache
(16Kbytes) Core (32Kbytes )
MMU MMU
Write
Buffer
Control Logic and Bus Interface Unit
Interrupts
AMBA AHB Integrated AMBA AHB
VINITHI
Interface Coprocessor Interface

IRQ
FIQ
AHB1 AHB2
Figure 2-1. ARM926 RISC Processor Core

Chapter 2 ARM CPU Complex
The following exceptions are recognized by the core:

• SWI—Software interrupt
• UNDEF—Undefined instruction
• PABT—Instruction prefetch abort
• FIQ—Fast peripheral interrupt
• IRQ—Normal peripheral interrupt
• DABT—Data abort
• RESET—Reset
• BKPT—Breakpoint
The vector table pointing to these interrupts can be located at physical address 0x00000000
or 0xFFFF0000. The i.MX28 maps its 64-Kbyte on-chip ROM to the address 0xFFFF0000
to 0xFFFFFFFF. The core is hardwired to use the high address vector table at hard reset
(core port VINITHI =1).
The ARM 926 core includes a 16-Kbyte instruction cache and a 32-Kbyte data cache and
has two master interfaces to the AMBA AHB, as shown below.
The i.MX28 always operates in a little-endian mode.
r0
Thumb mode low registers
r1
r2
r3
r4
r5
r6
r7
r8 r8
Thumb mode high registers
r9 r9
r10 r10
r11 r11
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)
cpsr
spsr spsr spsr spsr spsr
USER FIQ IRQ ABORT SVC undef
Figure 2-2. ARM Programmable Registers

JTAG Debugger
2.3 JTAG Debugger

The TAP controller of the ARM core in the i.MX28 performs the standard debugger
instructions.
2.3.1 JTAG READ ARM ID (TAP)

The TAP controller returns the following 32-bit data value in response to a JTAG READ
ID instruction: 0x079264F3 when the pin DEBUG=1 (JTAG interface works for ARM
debugging).
2.3.2 JTAG Hardware Reset

The JTAG reset instruction can be accomplished by writing 0xDEADC0DE to ETM address
0x70. The ETM is on scan chain 6. The bitstream is 0xF0DEADC0DE. The digital wide
reset does not affect the DC-DC converters or the contents of the persistent registers in the
analog side of the RTC.
2.3.3 JTAG Interaction with CPUCLK

Because the JTAG clock is sampled from the processor clock CPUCLK, there are cases in
which the behavior of CPUCLK affects the ability to make use of JTAG. Specifically, the
JTAG block will not function as expected if:
• CPUCLK is stalled due to an interrupt
• CPUCLK is less than 3x the JTAG clock
• CPUCLK is disabled for any reason
2.4 Embedded Trace Macrocell (ETM) Interface

The i.MX28 includes a stand-alone ARM CoreSight Embedded Trace Macrocell,
ETM9CSSingle, which provides a instruction trace and a data trace for the ARM9
microprocessor. For more details, see the CoreSight ETM9 Technical Reference Manual.
Also, see the pin list in the data sheet for pinout information.

Chapter 3
Default First-level Page Table (DFLPT)
3.1 Default First-Level Page Table (DFLPT) Overview

The DFLPT provides a unique method of implementing the ARM MMU first-level page
table (L1PT) using a hardware-based approach. The ARM MMU L1PT must consist of
4096 page-table entries (PTE), each of which maps to a 1-Mbyte section of the 4-Gbyte
system memory. Each PTE consists of a 32-bit descriptor, such that 16 Kbytes of memory
is required to implement the L1PT. Using 16 Kbytes of system memory for the L1PT can
be an issue for memory-constrained embedded systems (especially those without SDRAM).
The DFLPT implements a very sparse L1PT in hardware, as shown in Figure 3-1. This is
achieved by having sixteen movable and expandable page table entries (MPTE) that are
fully programmable and one semi-programmable fixed PTE. Any of the sixteen MPTEs
can be bound to 4095 of the 4096 sections using sixteen locator registers in the DIGCTL
block (MPTE0_LOC).
This implementation, although sparse, is very useful in low-memory applications. For small
SDRAM systems (where the L1PT would typically be placed in SDRAM), the DFLPT
provides significant speed and power advantages (as well as saving 16 Kbytes). For larger
DRAM system, it provides a performance advantage. Large memory systems are
accommodated through the spanning option (for example, in cases such as multimedia
buffers, large amounts of memory are typically marked with the same attributes, and the
memory is contiguous physically). Using the DFLPT, a level-one descriptor fetch takes two
HCLK cycles to complete.
EMI
OCROM ARM Core OCRAM
Slave Data Master Slave Slave
AHB Layer 2
Slave Slave Slave Slave
USB APBH APBX

Default
Bridge Bridge
First-Level
Page Table
Figure 3-1. Default First-Level Page Table (DFLPT) Block Diagram

Operation
3.2 Operation
The DFLPT provides the following features as part of the memory management within the
i.MX28 embedded software system:
• 16-Kbyte AHB slave located at addresses 0x800C_0000–0x800C_3FFF supports the
required 4K L1 PTEs. To use the DFLPT, point the ARM TTB to 0x800C_0000.
• Only 32-bit word accesses are supported.
• All AHB burst types are supported.
• Each access has a fixed 1-cycle AHB wait state.
• Bus errors are supported when accessing an unbound PTE (that is, an address not
bound to an MPTE or spanned MPTE).
• Sixteen fully programmable (value and location) page table entries. All 32-bits are
programmable. The location/binding of each MPTE is determined through the
HW_DIGCTL_MPTEn_LOC register fields in the DIGCTL module. The span (1-128
MB) of MPTE is determined through the HW_DIGCTL_MPTEn_SPAN register fields
in the DIGCTL module. In addition, each of the sixteen entries can be disabled through
HW_DIGCTL_MPTEn_DIS if less than sixteen entries are required (this avoids the
need to bind an entry to some unused area of physical memory):
• When an entry is disabled (through HW_DIGCTL_MPTEn_DIS), it cannot be
bound, so programming its HW_DIGCTL_MPTEn_LOC field has no effect. This
means that another entry which is not disabled (HW_DIGCTL_MPTEn_DIS=0)
can have the same value for HW_DIGCTL_MPTEn_LOC as the disabled entry.
• A read from an unbound PTE returns 0x0000_0000. When the MMU is enabled,
this results in a section translation fault if the read is the result of a page-walk.
• When using the span feature, the entire span is bound to the MPTE. This means
that up to 128 32-bit word locations/addresses can be bound to any MPTE (see
below for a more detailed explanation).
• A write to an un-bound PTE shall result in a slave error, which shall in turn result
in an ARM data-abort. Note that when writing to a PTE encompassed in a span,
the descriptor will apply to the span of the MPTE with the exception of the
base-address, which only applies to the base MPTE (at location LOC). Subsequent
base addresses within a span are generated linearly from this LOC value (see below).
• Each MPTE has a reset value of 0x0000_0000.

Chapter 3 Default First-level Page Table (DFLPT)
• One fixed PTE at location 2048 covers the i.MX28 PIO and register space. The location
is fixed as virtual = real, is non-cacheable, and includes programmable bufferable,
domain, and AP fields.
• Each MPTE requires a location register, such that it can be mapped to any of the 4K
L1 section descriptors. In addition, each of these location registers can be programmed
to be bound to up to 128 locations each (covering up to 128 MB of physical each).
These location registers (HW_DIGCTL_MPTEn where n = 0...15) are located in the
DIGCTL module. Refer to MPTE0_LOC for a description of the MPTEn_LOC registers.
• Each HW_DIGCTL_MPTEn_LOC must be programmed with a 12-bit value that
corresponds to one of the 4K section entries. Once programmed, the AHB physical
address of the MPTE is determined as:
0x800C_0000 + (HW_DIGCTL_MPTEn_LOC << 2)
HW_DIGCTL_MPTEn_LOC = 0x000 – 0xFFF
• The reset state of each HW_DIGCTL_MPTEn_LOC register is n (n = 0...15), for
example, HW_DIGCTL_MPTE3_LOC has reset value of 0x0000_0003.
• None of the MPTEn_LOC registers should be programmed to 0x800 (2048). This
corresponds to the fixed entry that covers the i.MX28 register space.
• No checking/status is given for incorrect programming (for example, overlap). If
multiple MPTEs are programmed to the same address in the DFLPT, the behavior
is non-deterministic. The only exception is that all but one of the entries has DIS=1
set (disabled).
• The spanning feature can be enabled by adjusting the value of

HW_DIGCTL_MPTEn_SPAN. This is a 3-bit value which determines the size of the
span as 2^SPAN. This means that any access to the L1PT within the span will have the
following properties:
• The span allows any MPTE to bind to a range of MPTEn_LOC * 4 through to
(MPTEn_LOC + (2^SPAN – 1) ) * 4, where SPAN is an integer from 0 to 7.
• Because spanning binds a single MPTE to multiple L1PT entries, the DFLPT must
generate unique base addresses for each spanned entry, otherwise each 1 MB section
would map to the same physical section. The DFLPT achieves this by assuming
contiguous 1 MB section addressing for all sections covered within a span.

Operation
3.2.1 Top-Level Symbol and Functional Overview

The DFLPT connects to the AHB as shown in Figure 3-2. Note that due to the internal
pipelining (single wait-state), the bus interfaces have little or no combinatorial logic. The
read and address paths connect directly to the registers. The write-path connects to the
register bank through one level 1-hot muxing. All address and locator decodes are also
performed using 1-hot logic. Offset address generated from the AHB address (for purposes
of generating spanned base addresses) use a registered version of the AHB address.
APBH Bridge APBH DIGCTL
MPTEn_LOC / SPAN MPTEn_DIS
DFLPT
ahb_addr,
ahb_trans,
ahb_write,
ahb_ready_in Locate/Span Reg Select
Logic
Movable PTE regs

ahb_wdata (MPTE0-15)
+
Span base-addr Gen
ahb_resp,
ahb_ready_out
State Logic
AHB Layer 2 (ARM D$)
ahb_rdata
Entry 2048 (PIO)
17:1 Read data

mux
Figure 3-2. DFLPT System Level Block Diagram
3.2.2 Memory Map

The virtual memory view of the DFLPT can be seen in the figure below. This example
shows how a MPTE can be spanned and how it will appear to the ARM MMU. In this
example, MPTE0 is set as follows:
• HW_DIGCTL_MPTE0_DIS = 0x0
• HW_DIGCTL_MPTE0_SPAN = 0x2

• HW_DIGCTL_MPTE0_LOC = 0x700
• TTB (0xBASE) = 0x800C_0000
Based on these settings, MPTE0 spans 22=4 entries in the page table. Because only one
LOC value is specified, the DFLPT must generate section base-address values for each
location in the span as a linear offset to the base LOC. Even though this represents some
constraint in the view of virtual-to-physical memory mapping, it is quite common in an
embedded system to have large chunks of virtual memory to be contiguous.
FLPT Virtual
Address Address
0xFFFXXXXX
@0x800C3FFC
PTE 0x801–0xFFF
available for MPTE1–15
PTE 2048
(non-cacheable,
- V==R) PIO
PTE 0x900–0xFFF
available for MPTE1–15
0x703XXXXX Automatically return Base-address = LOC + 3,
Base-address=0x703 DFLPT returns value (MPTE0 + (3 << 20))
@0x800C1C0C
0x702XXXXX Automatically return Base-address = LOC + 2,
Base-address=0x702
@0x800C1C08 DFLPT returns value (MPTE0 + (2 << 20))
0x701XXXXX Base-address=0x701 Automatically return Base-address = LOC + 1,
@0x800C1C04 DFLPT returns value (MPTE0 + (1 << 20))
0x700XXXXX MPTE0_LOC=0x700, MPTE0 with base of 0x700 and span of 2^SPAN = 4,
@0x800C1C00 MPTE0_SPAN=2
Returns Base-address = LOC, DFLPT returns value MPTE0
AR926
PTE 0x000–0x6FF
MMU available for MPTE1–15
Translation
Table Base
Register
@0x800C0000
0x000XXXXX
Figure 3-3. DFLPT Virtual Memory Map
The table below lists the page-table entries available in the DFLPT.

Operation
Table 3-1. Default First-Level Page Table

RE-
GISTER
NAME ADDRESS DESCRIPTION
MPTE15 0x800C0000 + (HW_DIGCTL_MPTE15_LOC <<2) <= Address Moveable PTE15 + ((Address[13:2] -

< 0x800C0000 + ((HW_DIGCTL_MPTE15_LOC + 2^SPAN)<<2) HW_DIGCTL_MPTE15_LOC) << 20)

MPTE8 0x800C0000 + (HW_DIGCTL_MPTE8_LOC <<2) <= Address< Moveable PTE8 + ((Address[13:2] -
0x800C0000 + ((HW_DIGCTL_MPTE8_LOC + 2^SPAN)<<2) HW_DIGCTL_MPTE8_LOC) << 20)
PTE_2048 0x800C2000 PTE 2048 is semi-programmable, as shown in
Default First-Level Page Table PIO Register Map
Entry 2048.

3.2.3 Default First-Level Page Table PIO Register Map Entry 2048
The 1-Mbyte PIO region at physical address 0x800XXXXX is mapped as "virtual equal
real" by the default first-level page table PTE_2048, as shown below.
DFLPT_PTE_2048 0x800C2000
Table 3-2. First-Level Page Table Entry 2048 (0x80000000–0x800FFFFF) at 0x800C2000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Virtual == Real Section, i.e., 0x80000 AP 0 DOMAIN 1 C B 10
Table 3-3. PTE 2048 Bit Field Descriptions

BITS Label RW reset Definition
This section points to 0x80000000 and is always

31:12 POINTER RO 0x80000
available.
Initially set to 0x3 for allowing ALL accesses. Set

11:10 AP RW 0x3
to other values as desired.
9 ALWAYS_ZERO RO 0x0 Always reads back a 0.
8:5 DOMAIN RW 0x0 Set as desired.
Always reads back a 1, as required in ARM926

4 ALWAYS_ONE RO 0x1
Technical Reference Manual.
3 CACHEABLE RO 0x0 Always reads back a 0 (uncached).
2 BUFFERABLE RW 0x0 Always reads back a 0 (unbuffered).
1:0 FIRST_LEVEL RO 0x2 Always reads back 0x2 for section descriptor.

Operation

Chapter 4
Memory Map
4.1 Memory Map Overview

The following table shows the memory map as seen by the processor. Any blank entries
indicate that nothing is mapped at that address. No accesses should be made to these
addresses since the results are indeterminate. The Decode Block column indicates the decode
group to which each peripheral belongs. Most peripherals reside on the APBH or APBX
peripheral buses.
Table 4-1. Address Map for i.MX28
DECODE DEVICE MNEMONIC START ADDRESS END ADDRESS SIZE
BLOCK
AHB On-Chip RAM OCRAM 0x00000000 0x0001FFFF 128KB
On-Chip RAM alias OCRAM 0x00020000 0x7FFFFFFF
External Memory EMI 0x40000000 0x7FFFFFFF 1GB
APBH Interrupt Controller ICOLL 0x80000000 0x80001FFF 8KB
High Resolution ADC HSADC 0x80002000 0x80003FFF 8KB
APBH DMA APBH 0x80004000 0x80005FFF 8KB
Performance Monitor PERFMON 0x80006000 0x800067FF 2KB
0x80006800 0x80006FFF 2KB
0x80007000 0x800077FF 2KB
0x80007800 0x80007FFF 2KB
0x80008000 0x80009FFF 8KB
BCH ECC BCH 0x8000A000 0x8000BFFF 8KB
General Purpose Media Interface GPMI 0x8000C000 0x8000DFFF 8KB
0x8000E000 0x8000FFFF 8KB
Sync Serial Port 0 SSP0 0x80010000 0x80011FFF 8KB
Pin Control PINCTRL 0x80018000 0x80019FFF 8KB

Memory Map Overview

BLOCK
0x8001A000 0x8001BFFF 8KB
Digital Control DIGCTL 0x8001C000 0x8001DFFF 8KB
0x8001E000 0x8001FFFF 8KB
0x80020000 0x80021FFF 8KB
ETM ETM 0x80022000 0x80023FFF 8KB
APBX DMA APBX 0x80024000 0x80025FFF 8KB
0x80026000 0x80027FFF 8KB
Data CoProcessor DCP 0x80028000 0x80029FFF 8KB
Pixel Pipeline PXP 0x8002A000 0x8002BFFF 8KB
One Time Prog Controller OCOTP 0x8002C000 0x8002DFFF 8KB
AXI Control AXI_AHB0 0x8002E000 0x8002FFFF 8KB
LCD Interface LCDIF 0x80030000 0x80031FFF 8KB
CAN0 CAN0 0x80032000 0x80033FFF 8KB
CAN1 CAN1 0x80034000 0x80035FFF 8KB
0x80036000 0x80037FFF 8KB
0x80038000 0x80039FFF 8KB
0x8003A000 0x8003BFFF 8KB
SIMDBG SIMDBG 0x8003C000 0x8003C1ff
SIMGPMISEL SIMGPMISEL 0x8003C200 0x8003C2ff
SIMSSPSEL SIMSSPSEL 0x8003C300 0x8003C3ff
SIMMEMSEL SIMMEMSEL 0x8003C400 0x8003C4ff
GPIOMON GPIOMON 0x8003C500 0x8003C5ff
SIMENET SIMENET 0x8003C700 0x8003C7ff
ARMJTAG ARMJTAG 0x8003C800 0x8003C8ff
APBX Clock Controller CLKCTRL 0x80040000 0x80041FFF 8KB
Serial Audio Interface 0 SAIF0 0x80042000 0x80043FFF 8KB
Power Control POWER 0x80044000 0x80045FFF 8KB
Serial Audio Interface 1 SAIF1 0x80046000 0x80047FFF 8KB
0x80048000 0x80049FFF 8KB
0x8004A000 0x8004BFFF 8KB
0x8004C000 0x8004DFFF 8KB
0x8004E000 0x8004FFFF 8KB
Low Resolution ADC LRADC 0x80050000 0x80051FFF 8KB
0x80052000 0x80053FFF 8KB
Sony/Phillips Digital Interface SPDIF 0x80054000 0x80055FFF 8KB

Chapter 4 Memory Map

BLOCK
Real Time Clock RTC 0x80056000 0x80057FFF 8KB
Inter-Integrated Circuit 0 I2C0 0x80058000 0x80059FFF 8KB
Inter-Integrated Circuit 1 I2C1 0x8005A000 0x8005BFFF 8KB
0x8005C000 0x8005DFFF 8KB
0x8005E000 0x8005FFFF 8KB
0x80060000 0x80061FFF 8KB
0x80062000 0x80063FFF 8KB
Pulse Width Modulation PWM 0x80064000 0x80065FFF 8KB
0x80066000 0x80067FFF 8KB
Timers/Rotary TIMROT 0x80068000 0x80069FFF 8KB
Application UART 0 UARTAPP0 0x8006A000 0x8006BFFF 8KB
Application UART 1 UARTAPP1 0x8006C000 0x8006DFFF 8KB
Application UART 2 UARTAPP2 0x8006E000 0x8006FFFF 8KB
Application UART 3 UARTAPP3 0x80070000 0x80071FFF 8KB
Application UART 4 UARTAPP4 0x80072000 0x80073FFF 8KB
Debug Uart UARTDBG 0x80074000 0x80075FFF 8KB
0x80076000 0x80077FFF 8KB
0x80078000 0x80079FFF 8KB
0x8007A000 0x8007BFFF 8KB
Univeral Serial Bus Physical IF USBPHY0 0x8007C000 0x8007DFFF 8KB
Univeral Serial Bus Physical IF USBPHY1 0x8007E000 0x8007FFFF 8KB
AHB USB Controller 0 USBCTRL0 0x80080000 0x8008FFFF 64KB
USB Controller 1 USBCTRL1 0x80090000 0x8009FFFF 64KB
0x800A0000 0x800AFFFF 64KB
0x800B0000 0x800BFFFF 64KB
Default First-Level Page Table DFLPT 0x800C0000 0x800CFFFF 64KB
0x800D0000 0x800DFFFF 64KB
External Memory Interface (REG) DRAM 0x800E0000 0x800EFFFF 64KB
ENET MAC0 ENET 0x800F0000 0x800F3FFF 16KB
ENET MAC1 ENET 0x800F4000 0x800F7FFF 16KB
ENT Switch SWITCH 0x800F8000 0x800FFFFF 32KB
AHB On-Chip ROM OCROM 0xC0000000 0xFFFFFFFF 128KB

Memory Map Overview

Chapter 5
Interrupt Collector (ICOLL)
5.1 Interrupt Collector (ICOLL) Overview

The ARM9 CPU core has two interrupt input lines, IRQ and FIQ. As shown in the following
figure, the Interrupt Collector (ICOLL) can steer any of the 128 interrupt sources to either
the FIQn or IRQn lines of the ARM9 CPU.
HW Int
Sources
127
0
.
.
.
HW_ICOLL_INTERRUPT0-127[ENFIQ] HW_ICOLL_INTERRUPT0-127[ENABLE] HW_ICOLL_RAW0-3
HW_ICOLL_RAW0-3
HW_ICOLL_RAW0-3
HW_ICOLL_RAW0-3
128
128
HW_ICOLL_INTERRUPT0-127[SOFTIRQ]
128
128 128
128
HW_ICOLL_INTERRUPT0-127[PRIORITY]
128 128
128
Priority Encoder
OR x128
Vector Address = Vector Base Address + 4 * Source Bit Number

FIQ
HW_ICOLL_VECTOR
IRQ
ARM9
Figure 5-1. Interrupt Collector System Diagram

Operation
5.2 Operation
Within an individual interrupt request line (IRQ only), the ICOLL offers four-level priority
(above base level) for each of its interrupt sources. Preemption of a lower priority interrupt
by a higher priority is supported (interrupt nesting). Interrupts assigned to the same level
are serviced in a strict linear priority order within level from lowest to highest interrupt
source bit number. FIQ interrupts are neither prioritized nor vectorized. All the interrupt
lines can be configured as a FIQ. If more than one is routed to the FIQ, then they must be
discriminated by a software. It is highly recommended to reserve FIQ assignment to time
critical events such as voltage brownouts or timers.
Vector Address = Vector Base Address + 4 * Source Bit Number

HW_ICOLL_VBASE
(Vector Table Base Addr )
HW_ICOLL_VECTOR
HW_ICOLL_INTERRUPT33[PRIORITY]
APBH
HW_ICOLL_INTERRUPT33[SOFTIRQ]
1:4
AHB
HW_ICOLL_INTERRUPT33[ENABLE]
HW_ICOLL_RAW1
32
(Read-Only)
.
.
.
63 IRQ
ARM
926
FIQ
HW_ICOLL_INTERRUPT33[ENFIQ]
Other sources
Figure 5-2. Interrupt Collector IRQ/FIQ Logic for Source 33
For a single interrupt source bit, there is an enable bit that gates it to the priority logic
(HW_ICOLL_INTERRUPTn[ENABLE]). A software interrupt bit per source bit can be
used to force an interrupt at the appropriate priority level directed to the corresponding
vector address. Each source can be applied to one of the four interrupt levels.

Chapter 5 Interrupt Collector (ICOLL)
The enable bit, FIQ-enable, the software interrupt bit, and the two-bit priority level
specification for each interrupt source bit are contained with a single programmable register
for each interrupt. The path from any interrupt source to the FIQ or IRQ logic is shown in
Figure 5-2 using HW_ICOLL_INTERRUPT33 as an example.
The data path for generating the vector address (readable by software) for the IRQ generation
portion of the interrupt collector is implemented as a multicycle path, as shown in Figure
5-3. The interrupt sources are continuously sampled in the holding register until one or more
arrive. The FSM causes the holding register to stop sampling while a vector address is
computed. Each interrupt source bit is applied to one of the four levels based on the two-bit
priority specification of each source bit. When the holding register closes, there can be more
than one newly arrived source bit. Thus, the source bits could be assigned such that more
than one interrupt level is requesting an interrupt. The pipeline first determines the highest
level requesting interrupt service. All interrupt requests on that level are presented to the
linear priority encoder. The result of this stage is a six-bit number corresponding to the
source bit number of the highest priority requesting an interrupt. This six-bit source number
is used to compute the vector address as follows:
VectorAddress = VectorBase + (Pitch * SourceBitNumber)
Pitch = 4,8, 12,16,20,24, or 28 as desired, see HW_CTRL_VECTOR_PITCH.

Operation
Multicycle
Path 3x
INTERRUPT37[PRIORITY]
Compute vector address
HW_ICOLL_VECTOR
Pick Hghest Level
Holding Register
INTERRUPT37[ENABLE]
Linear Priority
INTERRUPT37[SOFTIRQ]
APBH
1:4
AHB
(1x)
FIQ
HW_ICOLL_RAW1
32 FSM ARM9
(Read-Only)
. IRQ
. [37]
.
63 APB PIO Cycles
INT
Sources
Figure 5-3. IRQ Control Flow
5.2.1 Nesting of Multi-Level IRQ Interrupts

There are a number of very important interactions between the interrupt collector's FSM
and the interrupt service routine (ISR) running on the CPU. See Figure 5-4.
As soon as the interrupt source is recognized in the holding register, the FSM delays two
clocks, then grabs the vector address and asserts IRQ to the CPU. After the CPU enters the
interrupt service routine, it must notify the interrupt collector as soon as possible. Software
indicates the in-service state by writing to the HW_ICOLL_VECTOR register. The contents
of the data bus on this write do not matter. Optionally, firmware can enable the ARM read
side-effect mode. In this case, the in-service state is indicated as a side effect of having read
the HW_ICOLL_VECTOR register at the exception vector (0xFFFF0018). At this point,

the FSM reopens the holding register and scans for new interrupt sources. Any such IRQ
sources are presented to the CPU, provided that they are at a level higher than any currently
in-service level.
Whenever the ARM CPU takes an IRQ exception, it turns off the IRQ enable in the CPU
status register (CSR), as shown in Figure 5-4. If a higher priority interrupt is pending at this
point, then another IRQ exception is taken.
Critical section
Critical section
Critical section
CSR IRQ
IRQ
IRQ LEVEL 3
IRQ LEVEL 2
IRQ LEVEL 1
IRQ LEVEL 0
INSERVICE
Re-enable IRQ
INSERVICE
Re-enable IRQ
ACKLEVEL2
ACKLEVEL0
INSERVICE
Re-enable IRQ
Base
ACKLEVEL3
Figure 5-4. Nesting of Multi-Level IRQ Interrupts
The example in shows going from the base to a level 0 ISR. When the ISR at level 0 was
ready, it enabled IRQ interrupts. At this point, it nests IRQ interrupts up to a level 3 interrupt.
The level 3 ISR marks its in-service state, which causes the interrupt collector to open the
holding register to search for new interrupt sources. In this example, none comes in, so the
level 3 ISR completes. As part of the return process, the ISR disables IRQ interrupts, then
acknowledges the level 3 service state. This is accomplished by writing the level number
(3 in this case) to the interrupt collector's Level Acknowledge register. The interrupt collector
resets the in-service bit for level 3. If this enables an IRQ at level 3, then it asserts IRQ and
goes through the nesting process again. Since IRQ exceptions are masked in the level 3
ISR, this nesting does not take place until the level 3 ISR returns from interrupt. This return
automatically re-enables IRQ exceptions. At this point, another exception could occur.
Figure 5-4 shows a second nesting of the IRQ interrupt by the arrival of a level 2 interrupt
source bit. Finally, the figure shows the point at which the level 0 ISR enters its critical
section (masks IRQ) and acknowledges level 0 to the interrupt collector and returns from
the interrupt.
Operation
The FSM reverts to its BASE level state waiting for an interrupt request to arrive in the
holding register. The waveform for the IRQ mask in the CPU status register (CSR) and the
waveform for the IRQ input to the CPU as they relate to the interrupt collector action are
shown in Figure 5-4.
NOTE
There is an inherent race condition between notifying the interrupt
collector that an ISR has been entered and having that ISR
re-enable IRQ exceptions in the CSR. The in-service notification
can take a number of cycles to percolate through the write buffer,
through the AHB and APB bridge and into the interrupt collector
where it removes the IRQ assertion to the CPU. This ICOLL IRQ
must be deasserted before the CSR IRQ on the CPU is re-enabled
or the CPU will see a phantom interrupt. This is why the ARM
vectored interrupt controller provides this in-service notification
as a read side effect of the vector address read. Alternatively, the
ISR can read the interrupt collector's CSR. The value received is
unimportant, but the time required to do the read ensures that the
write data has arrived at the interrupt collector. If firmware uses
this method, it should allow clocks after the read for the FSM and
for the CPU to recognize that the IRQ has been deasserted.
5.2.2 FIQ Generation

On this device, all interrupt sources can be configured as FIQ. This is controlled through
the HW_ICOLL_INTERRUPTn[ENFIQ] register bit as shown in Figure 5-2. When enabled
to the FIQ, the software interrupt associated with these bits can be used to generate the FIQ
from these sources for test purposes. When an interrupt source is programmed as an FIQ,
and IRQ cannot be generated from that source.
5.2.3 Interrupt Sources

The following table lists all of the interrupt sources on the device. Use hw_irq.h to access
these bits.
Table 5-1. i.MX28 Interrupt Sources
Source
Number Interrupt Vector Description
Power module battery brownout detect IRQ, recom-

0 batt_brownout_irq 0x0000 mend to set as FIQ.

Source
Power module VDDD brownout detect IRQ, recom-

1 vddd_brownout_irq 0x0004
mend to set as FIQ.
Power module VDDIO brownout detect IRQ, recom-
2 vddio_brownout_irq 0x0008
mend to set as FIQ.
Power module VDDA brownout detect IRQ, recom-
3 vdda_brownout_irq 0x000C
mend to set as FIQ.
4 vdd5v_droop_irq 0x0010 5V Droop IRQ, recommend to be set as FIQ.
4.2V regulated supply brown-out IRQ, recommend

5 dcdc4p2_brownout_irq 0x0014 to be set as FIQ.
6 vdd5v_irq 0x0018 IRQ on 5V connect or disconnect also OTG 4.2V
7 0x001C
Reserved
8 can0_irq 0x0020
CAN0 IRQ.
9 can1_irq 0x0024
CAN1 IRQ.
10 lradc_touch_irq 0x0028
(Touch Screen) Touch detection IRQ.
11 0x002C
Reserved
12 0x0030
Reserved
13 hsadc_irq 0x0034
HSADC IRQ.
14 lradc_thresh0_irq 0x0038
LRADC0 Threshold IRQ.
15 lradc_thresh1_irq 0x003C
LRADC1 Threshold IRQ.
16 lradc_ch0_irq 0x0040
LRADC Channel 0 conversion complete IRQ.
19 lradc_ch3_irq 0x004C
23 lradc_ch7_irq 0x005C
24 lradc_button0_irq 0x0060
LRADC Channel 0 button detection IRQ.
25 lradc_button1_irq 0x0064
LRADC Channel 1 button detection IRQ.
26 0x0068
Reserved

Operation
Source
27 perfmon_irq 0x006C
Performance monitor IRQ.
28 rtc_1msec_irq 0x0070
RTC 1ms event IRQ.
29 rtc_alarm_irq 0x0074
RTC alarm event IRQ.
30 0x0078
Reserved
31 comms_irq 0x007C JTAG debug communications port IRQ.
32 emi_error_irq 0x0080 External memory controller IRQ.
33 0x0084
Reserved
34 0x0088
Reserved
35 0x008C
Reserved
36 0x0090
Reserved
37 reserved 0x0094
Reserved
38 lcdif_irq 0x0098
LCDIF IRQ.
39 pxp_irq 0x009C
PXP IRQ.
40 0x00A0
Reserved
41 bch_irq 0x00A4 BCH consolidated IRQ.
42 gpmi_irq 0x00A8
GPMI internal error and status IRQ.
43 0x00AC
Reserved
44 0x00B0
Reserved
45 spdif_error_irq 0x00B4
SPDIF FIFO error IRQ.
46 0x00B8
Reserved
47 duart_irq 0x00BC
Debug UART IRQ.
48 timer0_irq 0x00C0
Timer0 IRQ, recommend to set as FIQ.
51 timer3_irq 0x00CC
52 dcp_vmi_irq 0x00D0 DCP Channel 0 virtual memory page copy IRQ.
53 dcp_irq 0x00D4
DCP (per channel and CSC) IRQ.

Source
54 dcp_secure_irq 0x00D8
DCP secure IRQ.
55 0x00DC
Reserved
56 0x00E0
Reserved
57 0x00E4
Reserved
58 saif1_irq 0x00E8
SAIF1 FIFO & Service error IRQ.
59 saif0_irq 0x00EC
SAIF0 FIFO & Service error IRQ.
60 0x00F0
Reserved
61 0x00F4
Reserved
62 0x00F8
Reserved
63 0x00FC
Reserved
64 0x0100
Reserved
65 0x0104
Reserved
66 spdif_dma_irq 0x0108 SPDIF DMA channel IRQ.
67 0x010C
Reserved
68 i2c0_dma_irq 0x0110
I2C0 DMA channel IRQ.
69 i2c1_dma_irq 0x0114
I2C1 DMA channel IRQ.
70 auart0_rx_dma_irq 0x0118
Application UART0 receiver DMA channel IRQ.
71 auart0_tx_dma_irq 0x011C
Application UART0 transmitter DMA channel IRQ.
73 auart1_tx_dma_irq 0x0124 Application UART1 transmitter DMA
77 auart3_tx_dma_irq 0x0134
80 saif0_dma_irq 0x0140
SAIF0 DMA channel IRQ.

Operation
Source
81 saif1_dma_irq 0x0144
SAIF1 DMA channel IRQ.
82 ssp0_dma_irq 0x0148
SSP0 DMA channel IRQ.
83 ssp1_dma_irq 0x014C
86 lcdif_dma_irq 0x0158
LCDIF DMA channel IRQ.
87 hsadc_dma_irq 0x015C
HSADC DMA channel IRQ.
88 gpmi_dma_irq 0x0160
GPMI DMA channel IRQ.
89 digctl_debug_trap_irq 0x0164
Layer 0 or Layer 3 AHB address access trap IRQ.
90 0x0168
Reserved
91 0x016C
Reserved
92 usb1_irq 0x0170
USB1 IRQ.
93 usb0_irq 0x0174
USB0 IRQ.
94 usb1_wakeup_irq 0x0178
UTM1 IRQ.
95 usb0_wakeup_irq 0x017C
UTM0 IRQ.
96 ssp0_error_irq 0x0180 SSP0 device-level error and status IRQ.
99 ssp3_error_irq 0x018C SSP3 device-level error and status IRQ.
100 enet_swi_irq 0x0190

Switch IRQ.
101 enet_mac0_irq 0x0194
MAC0 IRQ.
102 enet_mac1_irq 0x0198
MAC1 IRQ.
103 enet_mac0_1588_irq 0x019C
1588 of MAC0 IRQ.
104 enet_mac1_1588_irq 0x01A0
1588 of MAC1 IRQ.
105 0x01A4
Reserved
106 0x01A8
Reserved
107 0x01AC
Reserved

Source
108 0x01B0
Reserved
109 0x01B4
Reserved
I2C1 device detected errors and line conditions
110 i2c1_error_irq 0x01B8
IRQ.
I2C0 device detected errors and line conditions
111 i2c0_error_irq 0x01BC
IRQ.
112 auart0_irq 0x01C0 Application UART0 internal error IRQ.
115 auart3_irq 0x01CC Application UART3 internal error IRQ.
116 auart4_irq 0x01D0 Application UART4 internal error IRQ.
117 0x01D4
Reserved
118 0x01D8
Reserved
119 0x01DC
Reserved
120 0x01E0
Reserved
121 0x01E4
Reserved
122 pinctrl5_irq 0x01E8 GPIO bank 5 interrupt IRQ.
123 pinctrl4_irq 0x01EC GPIO bank 4 interrupt IRQ.
124 pinctrl3_irq 0x01F0 GPIO bank 3 interrupt IRQ.
127 pinctrl0_irq 0x01FC GPIO bank 0 interrupt IRQ.
5.2.4 CPU Wait-for-Interrupt Mode

To enable wait-for-interrupt mode, two distinct actions are required by the programmer.
1. Set the INTERRUPT_WAIT bit in the HW_CLKCTRL_CPUCLKCTRL register. This
must be done through a RMW operation. For example:
uclkctrl = HW_CLKCTRL_CPUCLKCTRL_RD();

Operation
uclkctrl |= BM_CLKCTRL_CPUCLKCTRL_INTERRUPT_WAIT;
HW_CLKCTRL_CPUCLKCTRL_WR(uclkctrl);
2. After setting the INTERRUPT_WAIT bit, a coprocessor instruction is required.
asm (
// Note: R0 is used in the following example, but any usual <Rd> register may be used.
"mov R0, 0;" // Rd SBZ (should be zero)

"mcr p15,0,r0,c7,c0,4;" //Drain write buffers, idle CPU clock & processor, and stop
//processor at this instruction
"nop"); // The lr sent to handler points here after RTI
The coprocessor instruction sequence above enables an internal gating signal. This internal
signal guarantees that write buffers are drained and ensures that the processor is in an idle
state. On execution of the MCR coprocessor instruction, the CPU clock is stopped and the
processor halts on the instruction—waiting for an interrupt to occur.
The INTERRUPT_WAIT bit can be thought of as a Wait-for-Interrupt enable bit. Therefore,
it must be set prior to the execution of the MCR instruction. It is recommended that, when
the Wait-for-Interrupt mode is to be used, the INTERRUPT_WAIT bit be set at initialization
time and left on.
With the INTERRUPT_WAIT bit set, after the execution of the MCR WFI command, the
processor halts on the MCR instruction. When an interrupt or FIQ occurs, the MCR
instruction completes and the IRQ or FIQ handler is entered normally. The return link that
is passed to the handler is automatically adjusted by the above MCR instruction, such that
a normal return from an interrupt results in a continuous execution of the instruction
immediately following the MCR. That is, the LR will contain the address of the MCR
instruction plus eight, such that a typical return from an interrupt instruction (for example,
subs pc, LR, 4) will return to the instruction immediately following the MCR (the NOP in
the example above).
Whenever the CPU is stopped because the clock control HW_CLKCTRL_
CPUCLKCTRL_INTERRUPT_WAIT bit is set and the MCR WFI instruction is executed,
the CPU stops until an interrupt occurs. The actual condition that wakes up the CPU is
determined by ORing together all enabled interrupt requests including those that are directed
to the FIQ CPU input. The ICOLL_BUSY output signal from the ICOLL communicates
this information to the clock control. This function does not pass through the normal ICOLL
state machine. It starts the CPU clock as soon as an enabled interrupt arrives.

5.3 Behavior During Reset

A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set
CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See
Correct Way to Soft Reset a Block, for additional information on using the SFTRST and
CLKGATE bit fields.
5.4 Programmable Registers

ICOLL Hardware Register Format Summary
HW_ICOLL memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
8000_0000 Interrupt Collector Interrupt Vector Address Register 32 R/W 0000_0000h 5.4.1/148
(HW_ICOLL_VECTOR)
8000_0010 Interrupt Collector Level Acknowledge Register 32 R/W 0000_0000h 5.4.2/149
(HW_ICOLL_LEVELACK)
8000_0020 Interrupt Collector Control Register (HW_ICOLL_CTRL) 32 R/W C003_0000h 5.4.3/150
8000_0040 Interrupt Collector Interrupt Vector Base Address Register 32 R/W 0000_0000h 5.4.4/152
(HW_ICOLL_VBASE)
8000_0070 Interrupt Collector Status Register (HW_ICOLL_STAT) 32 R 0000_007Fh 5.4.5/153
8000_00A0 Interrupt Collector Raw Interrupt Input Register 0 32 R 0000_0000h 5.4.6/154
(HW_ICOLL_RAW0)
8000_00B0 Interrupt Collector Raw Interrupt Input Register 1 32 R 0000_0000h 5.4.7/154
(HW_ICOLL_RAW1)
8000_00C0 Interrupt Collector Raw Interrupt Input Register 2 32 R 0000_0000h 5.4.8/155
(HW_ICOLL_RAW2)
8000_00D0 Interrupt Collector Raw Interrupt Input Register 3 32 R 0000_0000h 5.4.9/156
(HW_ICOLL_RAW3)
8000_0120 Interrupt Collector Interrupt Register 0 32 R/W 0000_0000h 5.4.10/157
(HW_ICOLL_INTERRUPT0)

Programmable Registers
HW_ICOLL memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
8000_01A0 Interrupt Collector Interrupt Register 8 32 R/W 0000_0000h 5.4.18/167
8000_01B0 Interrupt Collector Interrupt Register 9 32 R/W 0000_0000h 5.4.19/168
8000_01C0 Interrupt Collector Interrupt Register 10 32 R/W 0000_0000h 5.4.20/170
8000_01D0 Interrupt Collector Interrupt Register 11 32 R/W 0000_0000h 5.4.21/171
8000_01E0 Interrupt Collector Interrupt Register 12 32 R/W 0000_0000h 5.4.22/172
8000_01F0 Interrupt Collector Interrupt Register 13 32 R/W 0000_0000h 5.4.23/174


Absolute
Width Section/
(in bits) page
(hex)


Absolute
Width Section/
(in bits) page
(hex)


Absolute
Width Section/
(in bits) page
(hex)


Absolute
Width Section/
(in bits) page
(hex)


Absolute
Width Section/
(in bits) page
(hex)
8000_1120 Interrupt Collector Debug Register 0 (HW_ICOLL_DEBUG) 32 R 0000_0000h 5.4.138/335
8000_1130 Interrupt Collector Debug Read Register 0 32 R ECA9_4567h 5.4.139/337
(HW_ICOLL_DBGREAD0)
8000_1140 Interrupt Collector Debug Read Register 1 32 R 1356_DA98h 5.4.140/337
(HW_ICOLL_DBGREAD1)
8000_1150 Interrupt Collector Debug Flag Register 32 R/W 0000_0000h 5.4.141/338
(HW_ICOLL_DBGFLAG)


Absolute
Width Section/
(in bits) page
(hex)
8000_1160 Interrupt Collector Debug Read Request Register 0 32 R 0000_0000h 5.4.142/339
(HW_ICOLL_DBGREQUEST0)
8000_11E0 Interrupt Collector Version Register (HW_ICOLL_VERSION) 32 R 0301_0000h 5.4.146/342
5.4.1 Interrupt Collector Interrupt Vector Address Register

(HW_ICOLL_VECTOR)
This register is read by the Interrupt Service Routine using a load PC instruction. The priority
logic presents the vector address of the next IRQ interrupt to be processed by the CPU. The
vector address is held until a new ISR is entered..
HW_ICOLL_VECTOR: 0x000
HW_ICOLL_VECTOR_SET: 0x004
HW_ICOLL_VECTOR_CLR: 0x008
HW_ICOLL_VECTOR_TOG: 0x00C
This register mediates the vectored interrupt collectors interface with the CPU when it enters
the IRQ exception trap. The exception trap should have a LDPC instruction from this address.
EXAMPLE
LDPC HW_ICOLL_VECTOR_ADDR; IRQ exception at 0xffff0018
Address: HW_ICOLL_VECTOR – 8000_0000h base + 0h offset = 8000_0000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IRQVECTOR[31:16]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
IRQVECTOR[15:2]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_ICOLL_VECTOR field descriptions

Field Description
31–2 This register presents the vector address for the interrupt currently active on the CPU IRQ input. Writing to
IRQVECTOR this register notifies the interrupt collector that the interrupt service routine for the current interrupt has been
entered (alternatively when ARM_RSE_MODE is set, reading this register is required).
1–0 Always write zeroes to this field.

RSRVD1
5.4.2 Interrupt Collector Level Acknowledge Register

(HW_ICOLL_LEVELACK)
The Interrupt Collector Level Acknowledge Register is used by software to indicate the
completion of an interrupt on a specific level.
This register is written to advance the ICOLL internal IRQ state machine. It advances from
an in-service on a level state to the next pending interrupt level or to the idle state. This
register is written at the very end of an interrupt service routine. If nesting is used then the
CPU IRQ must be turned on before writing to this register to avoid a race condition in the
CPU interrupt hardware. WARNING: the value written to the levelack register is decoded
not binary, i.e. 8, 4, 2, 1.
EXAMPLE
HW_ICOLL_LEVELACK_WR(HW_ICOLL_LEVELACK__LEVEL3);
Address: HW_ICOLL_LEVELACK – 8000_0000h base + 10h offset = 8000_0010h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
IRQLEVELACK
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_ICOLL_LEVELACK field descriptions

Field Description
31–4 Any value can be written to this bitfield. Writes are ignored.
RSRVD1

HW_ICOLL_LEVELACK field descriptions (continued)

Field Description
3–0 This bitfield is written by the processor to acknowledge the completion of an interrupt. The value written
IRQLEVELACK must correspond to the priority level of the completed interrupt
0x1 LEVEL0 — level 0
5.4.3 Interrupt Collector Control Register (HW_ICOLL_CTRL)

The Interrupt Collector Control Register provides overall control of interrupts being routed
to the CPU. This register is not at offset zero from the block base because that location is
needed for single 32 bit instructions to be placed in the exception vector location.
HW_ICOLL_CTRL: 0x020
HW_ICOLL_CTRL_SET: 0x024
HW_ICOLL_CTRL_CLR: 0x028
HW_ICOLL_CTRL_TOG: 0x02C
This register handles the overall control of the interrupt collector, including soft reset and
clock gate. In addition, it handles state machine variations like NO_NESTING and ARM
read side effect processing on the vector address register.
EXAMPLE
HW_ICOLL_CTRL_CLR(BM_ICOLL_CTRL_SFTRST | BM_ICOLL_CTRL_SFTRST );
Address: HW_ICOLL_CTRL – 8000_0000h base + 20h offset = 8000_0020h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IRQ_FINAL_
FIQ_FINAL_
ARM_RSE_
NESTING
BYPASS_
R RSRVD3
CLKGATE
ENABLE
ENABLE
SFTRST
MODE
FSM
NO_
VECTOR_PITCH
W
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_ICOLL_CTRL field descriptions

Field Description
31 When set to one, this bit causes a soft reset to the entire interrupt collector. This bit must be turned off for
SFTRST normal operation.
0x0 RUN — Allow the interrupt collector to operate normally.
0x1 IN_RESET — Hold the interrupt collector in its reset state.
30 When set to one, this bit causes all clocks within the interrupt collector to be gated off. NOTE: Do not set
CLKGATE this bit at the same time as SFTRST. Doing so, causes the soft reset to have no effect. Setting SFTRST will
cause the CLKGATE bit to set automatically four clocks later.
0x0 RUN — Enable clocks for normal operation of interrupt collector.
0x1 NO_CLOCKS — disable clocking within the interrupt collector.
29–24 Always write zeroes to this bitfield.
RSRVD3
23–21 When an interrupt occurs one of the 128 input requests becomes the winning bit number, i.e. 127. This bit
VECTOR_PITCH field selects one of eight constant multiplier values to multiply the winning bit number. The multiplied bit
number is added to the vector table base to become the vector address. 0x0 and 0x1 yield a multiplier of 4
bytes. 0x2 yields a multiplier of 8 bytes while 0x3 yields a multiplier of 12 bytes, that is, (8 + 4) bytes per
step.
0x0 DEFAULT_BY4 — one word pitch
0x1 BY4 — one word pitch
0x2 BY8 — two word pitch
0x3 BY12 — three word pitch
0x4 BY16 — four word pitch
0x5 BY20 — five word pitch
0x6 BY24 — six word pitch
0x7 BY28 — seven word pitch
20 Set this bit to one to bypass the FSM control of the request holding register and the vector address. With
BYPASS_FSM this bit set to one, the vector address register is continuously updated as interrupt requests come in. Turn
off all enable bits and walk once through the software interrupts, observing the vector address changes. Set
to zero for normal operation. This control is included as a test mode, and is not intended for use by a real
application.
0x0 NORMAL — Normal
0x1 BYPASS — no FSM handshake with CPU
19 Set this bit to one disable interrupt level nesting, that is, higher priority interrupt interrupting lower priority.
NO_NESTING For normal operation, set this bit to zero.
0x0 NORMAL — Normal
0x1 NO_NEST — no support for interrupt nesting
18 Set this bit to one enable the ARM-style read side effect associated with the vector address register. In this
ARM_RSE_ mode, interrupt inservice is signalled by the read of the HW_ICOLL_VECTOR register to acquire the interrupt
MODE vector address. Set this bit to zero for normal operation, in which the ISR signals inservice explicitly by
means of a write to the HW_ICOLL_VECTOR register.

HW_ICOLL_CTRL field descriptions (continued)

Field Description
17 Set this bit to one to enable the final FIQ output to the CPU. Set this bit to zero for testing the interrupt
FIQ_FINAL_ collector without causing actual CPU interrupts.
ENABLE
0x0 DISABLE — Disable
0x1 ENABLE — Enable
16 Set this bit to one to enable the final IRQ output to the CPU. Set this bit to zero for testing the interrupt
IRQ_FINAL_ collector without causing actual CPU interrupts.
ENABLE
RSRVD1
5.4.4 Interrupt Collector Interrupt Vector Base Address Register

(HW_ICOLL_VBASE)
This register is used by the priority logic to generate a unique vector address for each of
the 80 interrupt request lines coming into the interrupt collector. The vector address is
formed by multiplying the interrupt bit number by 4 and adding it to the vector base address.
HW_ICOLL_VBASE: 0x040
HW_ICOLL_VBASE_SET: 0x044
HW_ICOLL_VBASE_CLR: 0x048
HW_ICOLL_VBASE_TOG: 0x04C
This register provides a mechanism to specify the base address of the interrupt vector table.
It is used in the computation of the value supplied in HW_ICOLL_VECTOR register.
EXAMPLE
HW_ICOLL_VBASE_WR(pInterruptVectorTable);
Address: HW_ICOLL_VBASE – 8000_0000h base + 40h offset = 8000_0040h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TABLE_ADDRESS[31:16]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
TABLE_ADDRESS[15:2]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_ICOLL_VBASE field descriptions

Field Description
31–2 This bitfield holds the upper 30 bits of the base address of the vector table.
TABLE_
ADDRESS
RSRVD1
5.4.5 Interrupt Collector Status Register (HW_ICOLL_STAT)

Read only view into various internal states, including the Vector number of the current
interupt.
This register is used to test interrupt collector state machine and its associated request
holding register.
EXAMPLE
if(HW_ICOLL_STAT_VECTOR_NUMBER_READ() == 0x00000017) ISR_vector_23(); // ISR

for vector 23 decimal, 17 hex
Address: HW_ICOLL_STAT – 8000_0000h base + 70h offset = 8000_0070h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1 VECTOR_NUMBER
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
set
HW_ICOLL_STAT field descriptions

Field Description
RSRVD1
6–0 Vector number of current interrupt. Multiply by 4 * HW_ICOLL_CTRL[VECTOR_PITCH] and add to vector
VECTOR_ base address to obtain the value in HW_ICOLL_VECTOR.
NUMBER

5.4.6 Interrupt Collector Raw Interrupt Input Register 0

(HW_ICOLL_RAW0)
The lower 32 interrupt hardware-source states are visible in this read-only register.
HW_ICOLL_RAW0: 0x0A0
HW_ICOLL_RAW0_SET: 0x0A4
HW_ICOLL_RAW0_CLR: 0x0A8
HW_ICOLL_RAW0_TOG: 0x0AC
This register provides a read-only view of the raw interrupt request lines coming from
various parts of the chip. Its purpose is to improve diagnostic observability. Note that these
only capture the state of hardware interrupt sources.
EXAMPLE
ulTest = HW_ICOLL_RAW0.RAW_IRQS;
Address: HW_ICOLL_RAW0 – 8000_0000h base + A0h offset = 8000_00A0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RAW_IRQS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_ICOLL_RAW0 field descriptions

Field Description
31–0 read-only view of the lower 32 hardware interrupt request bits.
RAW_IRQS

(HW_ICOLL_RAW1)
Interrupt hardware-source states 32-63 are visible in this read-only register.
HW_ICOLL_RAW1: 0x0B0
HW_ICOLL_RAW1_SET: 0x0B4
HW_ICOLL_RAW1_CLR: 0x0B8

HW_ICOLL_RAW1_TOG: 0x0BC
various parts of the chip. The purpose is to improve diagnostic observability. Note that these
EXAMPLE
Address: HW_ICOLL_RAW1 – 8000_0000h base + B0h offset = 8000_00B0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RAW_IRQS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 read-only view of hardware interrupt request bits 32-63.
RAW_IRQS

(HW_ICOLL_RAW2)
HW_ICOLL_RAW2: 0x0C0
HW_ICOLL_RAW2_SET: 0x0C4
HW_ICOLL_RAW2_CLR: 0x0C8
HW_ICOLL_RAW2_TOG: 0x0CC
EXAMPLE

Address: HW_ICOLL_RAW2 – 8000_0000h base + C0h offset = 8000_00C0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RAW_IRQS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RAW_IRQS

(HW_ICOLL_RAW3)
HW_ICOLL_RAW3: 0x0D0
HW_ICOLL_RAW3_SET: 0x0D4
HW_ICOLL_RAW3_CLR: 0x0D8
HW_ICOLL_RAW3_TOG: 0x0DC
EXAMPLE
Address: HW_ICOLL_RAW3 – 8000_0000h base + D0h offset = 8000_00D0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RAW_IRQS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RAW_IRQS

5.4.10 Interrupt Collector Interrupt Register 0 (HW_ICOLL_INTERRUPT0)

This register provides a mechanism to specify the priority level for an interrupt source. It
also provides an enable and software interrupt for each one, as well as security designation.
HW_ICOLL_INTERRUPT0: 0x120
HW_ICOLL_INTERRUPT0_SET: 0x124
HW_ICOLL_INTERRUPT0_CLR: 0x128
HW_ICOLL_INTERRUPT0_TOG: 0x12C
This register provides a mechanism to specify the priority associated with an interrupt bit.
In addition, this register controls the enable and software generated interrupt. WARNING:
Modifying the priority of an enabled interrupt may result in undefined behavior. You should
always disable an interrupt prior to changing its priority.
EXAMPLE
HW_ICOLL_INTERRUPT0_SET(0,0x00000001);
Address: HW_ICOLL_INTERRUPT0 – 8000_0000h base + 120h offset = 8000_0120h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_ICOLL_INTERRUPT0 field descriptions

Field Description
RSRVD1
4 Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through
ENFIQ the main IRQ FSM and priority logic.

HW_ICOLL_INTERRUPT0 field descriptions (continued)

Field Description
3 Set this bit to one to force a software interrupt.
SOFTIRQ
0x0 NO_INTERRUPT — turn off the software interrupt request.
0x1 FORCE_INTERRUPT — force a software interrupt
2 Enable the interrupt bit through the collector.
ENABLE
1–0 Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest).
PRIORITY
0x0 LEVEL0 — level 0, lowest or weakest priority
0x3 LEVEL3 — level 3, highest or strongest priority

EXAMPLE

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE


Field Description
PRIORITY

EXAMPLE

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY

EXAMPLE


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


Field Description


EXAMPLE

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY

HW_ICOLL_INTERRUPT8: 0x1A0
HW_ICOLL_INTERRUPT8_SET: 0x1A4
HW_ICOLL_INTERRUPT8_CLR: 0x1A8
HW_ICOLL_INTERRUPT8_TOG: 0x1AC
EXAMPLE

Address: HW_ICOLL_INTERRUPT8 – 8000_0000h base + 1A0h offset = 8000_01A0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY

HW_ICOLL_INTERRUPT9: 0x1B0
HW_ICOLL_INTERRUPT9_SET: 0x1B4

HW_ICOLL_INTERRUPT9_CLR: 0x1B8
HW_ICOLL_INTERRUPT9_TOG: 0x1BC
EXAMPLE
Address: HW_ICOLL_INTERRUPT9 – 8000_0000h base + 1B0h offset = 8000_01B0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


Field Description

5.4.20 Interrupt Collector Interrupt Register 10

HW_ICOLL_INTERRUPT10: 0x1C0
HW_ICOLL_INTERRUPT10_SET: 0x1C4
HW_ICOLL_INTERRUPT10_CLR: 0x1C8
HW_ICOLL_INTERRUPT10_TOG: 0x1CC
EXAMPLE
Address: HW_ICOLL_INTERRUPT10 – 8000_0000h base + 1C0h offset = 8000_

01C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY

HW_ICOLL_INTERRUPT11: 0x1D0
HW_ICOLL_INTERRUPT11_SET: 0x1D4
HW_ICOLL_INTERRUPT11_CLR: 0x1D8
HW_ICOLL_INTERRUPT11_TOG: 0x1DC
EXAMPLE

Address: HW_ICOLL_INTERRUPT11 – 8000_0000h base + 1D0h offset = 8000_

01D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY

HW_ICOLL_INTERRUPT12: 0x1E0

HW_ICOLL_INTERRUPT12_SET: 0x1E4
HW_ICOLL_INTERRUPT12_CLR: 0x1E8
HW_ICOLL_INTERRUPT12_TOG: 0x1EC
EXAMPLE
Address: HW_ICOLL_INTERRUPT12 – 8000_0000h base + 1E0h offset = 8000_

01E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE


Field Description
PRIORITY

HW_ICOLL_INTERRUPT13: 0x1F0
HW_ICOLL_INTERRUPT13_SET: 0x1F4
HW_ICOLL_INTERRUPT13_CLR: 0x1F8
HW_ICOLL_INTERRUPT13_TOG: 0x1FC
EXAMPLE
Address: HW_ICOLL_INTERRUPT13 – 8000_0000h base + 1F0h offset = 8000_

01F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE
Address: HW_ICOLL_INTERRUPT14 – 8000_0000h base + 200h offset = 8000_

0200h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0210h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1


Field Description
SOFTIRQ
ENABLE
PRIORITY

EXAMPLE


0220h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0230h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE


Field Description
PRIORITY

EXAMPLE

0240h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0250h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0260h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1


Field Description
SOFTIRQ
ENABLE
PRIORITY

EXAMPLE


0270h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0280h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE


Field Description
PRIORITY

EXAMPLE

0290h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE
Address: HW_ICOLL_INTERRUPT24 – 8000_0000h base + 2A0h offset = 8000_

02A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE
Address: HW_ICOLL_INTERRUPT25 – 8000_0000h base + 2B0h offset = 8000_

02B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1


Field Description
SOFTIRQ
ENABLE
PRIORITY

EXAMPLE


02C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

02D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE


Field Description
PRIORITY

EXAMPLE

02E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

02F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0300h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1


Field Description
SOFTIRQ
ENABLE
PRIORITY

EXAMPLE


0310h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0320h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE


Field Description
PRIORITY

EXAMPLE

0330h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0340h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0350h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1


Field Description
SOFTIRQ
ENABLE
PRIORITY

EXAMPLE


0360h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0370h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE


Field Description
PRIORITY

EXAMPLE

0380h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0390h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

03A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1


Field Description
SOFTIRQ
ENABLE
PRIORITY

EXAMPLE


03B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

03C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE


Field Description
PRIORITY

EXAMPLE

03D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

03E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

03F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1


Field Description
SOFTIRQ
ENABLE
PRIORITY

EXAMPLE


0400h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0410h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE


Field Description
PRIORITY

EXAMPLE

0420h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0430h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0440h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1


Field Description
SOFTIRQ
ENABLE
PRIORITY

EXAMPLE


0450h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0460h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE


Field Description
PRIORITY

EXAMPLE

0470h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0480h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0490h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1


Field Description
SOFTIRQ
ENABLE
PRIORITY

EXAMPLE


04A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

04B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE


Field Description
PRIORITY

EXAMPLE

04C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

04D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

04E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1


Field Description
SOFTIRQ
ENABLE
PRIORITY

EXAMPLE


04F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0500h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE


Field Description
PRIORITY

EXAMPLE

0510h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0520h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0530h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1


Field Description
SOFTIRQ
ENABLE
PRIORITY

EXAMPLE


0540h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0550h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE


Field Description
PRIORITY

EXAMPLE

0560h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0570h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0580h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1


Field Description
SOFTIRQ
ENABLE
PRIORITY

EXAMPLE


0590h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

05A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE


Field Description
PRIORITY

EXAMPLE

05B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

05C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

05D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1


Field Description
SOFTIRQ
ENABLE
PRIORITY

EXAMPLE


05E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

05F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE


Field Description
PRIORITY

EXAMPLE

0600h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0610h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0620h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1


Field Description
SOFTIRQ
ENABLE
PRIORITY

EXAMPLE


0630h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0640h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE


Field Description
PRIORITY

EXAMPLE

0650h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0660h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0670h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1


Field Description
SOFTIRQ
ENABLE
PRIORITY

EXAMPLE


0680h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0690h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE


Field Description
PRIORITY

EXAMPLE

06A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

06B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

06C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1


Field Description
SOFTIRQ
ENABLE
PRIORITY

EXAMPLE


06D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

06E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE


Field Description
PRIORITY

EXAMPLE

06F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0700h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0710h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1


Field Description
SOFTIRQ
ENABLE
PRIORITY

EXAMPLE


0720h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0730h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE


Field Description
PRIORITY

EXAMPLE

0740h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0750h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0760h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1


Field Description
SOFTIRQ
ENABLE
PRIORITY

EXAMPLE


0770h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0780h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE


Field Description
PRIORITY

EXAMPLE

0790h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

07A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

07B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1


Field Description
SOFTIRQ
ENABLE
PRIORITY

EXAMPLE


07C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

07D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE


Field Description
PRIORITY

EXAMPLE

07E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

07F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0800h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1


Field Description
SOFTIRQ
ENABLE
PRIORITY

EXAMPLE


0810h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0820h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE


Field Description
PRIORITY

EXAMPLE

0830h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0840h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0850h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1


Field Description
SOFTIRQ
ENABLE
PRIORITY

EXAMPLE


0860h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0870h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE


Field Description
PRIORITY

EXAMPLE

0880h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0890h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

08A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1


Field Description
SOFTIRQ
ENABLE
PRIORITY

EXAMPLE


08B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

08C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE


Field Description
PRIORITY

EXAMPLE

08D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

08E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

08F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1


Field Description
SOFTIRQ
ENABLE
PRIORITY

EXAMPLE


0900h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE
PRIORITY


EXAMPLE

0910h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFTIRQ
R RSRVD1[15:5]
ENABLE
ENFIQ
PRIORITY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
SOFTIRQ
ENABLE


Field Description
PRIORITY
5.4.138 Interrupt Collector Debug Register 0 (HW_ICOLL_DEBUG)

The contents of this register will be defined as the hardware is developed.
HW_ICOLL_DEBUG: 0x1120
HW_ICOLL_DEBUG_SET: 0x1124
HW_ICOLL_DEBUG_CLR: 0x1128
HW_ICOLL_DEBUG_TOG: 0x112C
This register provides diagnostic visibility into the IRQ request state machine and its various
inputs.
EXAMPLE
if (BF_RD(ICOLL_DEBUG, LEVEL_REQUESTS) != HW_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3)

Error();
TPRINTF(TP_MED, ("ICOLL INSERVICE = 0x%x\n", BF_RD(ICOLL_DEBUG, INSERVICE)));
TPRINTF(TP_MED, ("ICOLL STATE = 0x%x\n", BF_RD(ICOLL_DEBUG, VECTOR_FSM)));
Address: HW_ICOLL_DEBUG – 8000_0000h base + 1120h offset = 8000_1120h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R INSERVICE LEVEL_REQUESTS REQUESTS_BY_LEVEL RSRVD2 FIQ IRQ
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1 VECTOR_FSM
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

HW_ICOLL_DEBUG field descriptions

Field Description
31–28 read-only view of the Inservice bits used for nesting IRQs.
INSERVICE
0x1 LEVEL0 — LEVEL0
27–24 read-only view of the requsts by priority level for the current IRQ.
LEVEL_
REQUESTS
23–20 read-only view of the requsts by priority level for the current IRQ.
REQUESTS_BY_
LEVEL
RSRVD2
17 Read-Only View of the FIQ output to the CPU.
FIQ
0x0 NO_FIQ_REQUESTED — No FIQ Requested
0x1 FIQ_REQUESTED — FIQ Requested
16 Read-Only View of the FIQ output to the CPU.
IRQ
0x0 NO_IRQ_REQUESTED — No IRQ Requested
0x1 IRQ_REQUESTED — IRQ Requested
RSRVD1
9–0 Empty description.
VECTOR_FSM
0x000 FSM_IDLE — FSM_IDLE
0x001 FSM_MULTICYCLE1 — FSM_MULTICYCLE1
0x004 FSM_PENDING — FSM_PENDING
0x020 FSM_ISR_RUNNING1 — FSM_ISR_RUNNING1

5.4.139 Interrupt Collector Debug Read Register 0

(HW_ICOLL_DBGREAD0)
This register always returns a known read value for debug purposes.
HW_ICOLL_DBGREAD0: 0x1130
HW_ICOLL_DBGREAD0_SET: 0x1134
HW_ICOLL_DBGREAD0_CLR: 0x1138
HW_ICOLL_DBGREAD0_TOG: 0x113C
This register is used to test the read mux paths on the APBH.
EXAMPLE
if (HW_ICOLL_DBGREAD0_RD != 0xECA94567)
Error();
Address: HW_ICOLL_DBGREAD0 – 8000_0000h base + 1130h offset = 8000_1130h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VALUE
W
Re- 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1
set
HW_ICOLL_DBGREAD0 field descriptions

Field Description
31–0 Fixed read-only value.
VALUE
5.4.140 Interrupt Collector Debug Read Register 1

(HW_ICOLL_DBGREAD1)
This register always returns a known read value for debug purposes.
HW_ICOLL_DBGREAD1: 0x1140
HW_ICOLL_DBGREAD1_SET: 0x1144
HW_ICOLL_DBGREAD1_CLR: 0x1148
HW_ICOLL_DBGREAD1_TOG: 0x114C

This register is used to test the read mux paths on the APBH.
EXAMPLE
if (HW_ICOLL_DBGREAD1_RD != 0x1356DA98)
Error();
Address: HW_ICOLL_DBGREAD1 – 8000_0000h base + 1140h offset = 8000_1140h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VALUE
W
Re- 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 0 1 0 0 1 1 0 0 0
set
HW_ICOLL_DBGREAD1 field descriptions

Field Description
31–0 Fixed read-only value.
VALUE
5.4.141 Interrupt Collector Debug Flag Register (HW_ICOLL_DBGFLAG)

The Interrupt Collector debug flag register is used to post diagnostic state into simulation.
HW_ICOLL_DBGFLAG: 0x1150
HW_ICOLL_DBGFLAG_SET: 0x1154
HW_ICOLL_DBGFLAG_CLR: 0x1158
HW_ICOLL_DBGFLAG_TOG: 0x115C
This register provides a posting register to synchronize C program execution and the internal
simulation environment.
EXAMPLE
BF_WR(ICOLL_DBGFLAG, FLAG, 3);

// ... do some diagnostic action
// ... do some more diagnostic actions

Address: HW_ICOLL_DBGFLAG – 8000_0000h base + 1150h offset = 8000_1150h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
FLAG
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_ICOLL_DBGFLAG field descriptions

Field Description
RSRVD1
15–0 This debug facility is probably temporary.
FLAG
5.4.142 Interrupt Collector Debug Read Request Register 0

read-only view into the low 32 bits of the request holding register.
HW_ICOLL_DBGREQUEST0: 0x1160
HW_ICOLL_DBGREQUEST0_SET: 0x1164
HW_ICOLL_DBGREQUEST0_CLR: 0x1168
HW_ICOLL_DBGREQUEST0_TOG: 0x116C
holding register.
EXAMPLE
if (HW_ICOLL_DBGREQUESTn_RD(0) != 0x00000000)
Error();
Address: HW_ICOLL_DBGREQUEST0 – 8000_0000h base + 1160h offset = 8000_1160h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

HW_ICOLL_DBGREQUEST0 field descriptions

Field Description
31–0 Low 32 bits of the request holding register.
BITS

read-only view into bits 32-63 of the request holding register.
holding register.
EXAMPLE
if (HW_ICOLL_DBGREQUESTn_RD(n) != 0x00000000)
Error();

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Bits 32-63 of the request holding register.
BITS


holding register.
EXAMPLE
Error();

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
BITS

holding register.
EXAMPLE

Error();

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
BITS
5.4.146 Interrupt Collector Version Register (HW_ICOLL_VERSION)

This register always returns a known read value for debug purposes it indicates the version
of the block.
EXAMPLE
if (HW_ICOLL_VERSION.B.MAJOR != 3)
Error();
Address: HW_ICOLL_VERSION – 8000_0000h base + 11E0h offset = 8000_11E0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MAJOR MINOR STEP

W
Re- 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_ICOLL_VERSION field descriptions

Field Description
31–24 Fixed read-only value reflecting the MAJOR field of the RTL version.
MAJOR
23–16 Fixed read-only value reflecting the MINOR field of the RTL version.
MINOR
15–0 Fixed read-only value reflecting the stepping of the RTL version.
STEP

Chapter 6
AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
6.1 AHB-to-APBH Bridge Overview

The AHB-to-APBH bridge provides the i.MX28 with an inexpensive peripheral attachment
bus running on the AHB's HCLK. (The H in APBH denotes that the APBH is synchronous
to HCLK, as compared to APBX, which runs on the crystal-derived XCLK.)
As shown in the following figure, the AHB-to-APBH bridge includes the AHB-to-APB
PIO bridge for a memory-mapped I/O to the APB devices, as well as a central DMA facility
for devices on this bus and a vectored interrupt controller for the ARM926 core. Each one
of the APB peripherals, including the vectored interrupt controller, is documented in their
own chapters elsewhere in this document.

AHB-to-APBH Bridge Overview
AHB
AHB Slave AHB Master
AHB-to-APBH DMA
APBH Master
AHB-to-APBH Bridge
SSP0 ATA_NAND0
SSP1 ATA_NAND1
ATA_NAND2
SSP2
APBH
ATA_NAND3
SSP3
ATA_NAND0
LCDIF
ATA_NAND1
HSADC
ATA_NAND2
ATA_NAND3
Figure 6-1. AHB-to-APBH Bridge DMA Block Diagram
The DMA controller uses the APBH bus to transfer read and write data to and from each
peripheral. There is no separate DMA bus for these devices. Contention between the DMA's
use of the APBH bus and the AHB-to-APB bridge functions' use of the APBH is mediated
by an internal arbitration logic. For contention between these two units, the DMA is favored
and the AHB slave will report "not ready" through its HREADY output until the bridge
transfer can complete. The arbiter tracks repeated lockouts and inverts the priority,
guaranteeing the CPU every fourth transfer on the APB.

Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
6.2 APBH DMA

The DMA supports sixteen channels of DMA services, as shown in the following table.
The shared DMA resource allows each independent channel to follow a simple chained
command list. Command chains are built up using the general structure, as shown in Figure
6-2.
Table 6-1. APBH DMA Channel Assignments
APBH DMA CHANNEL # USAGE
0 SSP0
1 SSP1
2 SSP2
3 SSP3
4 GPMI0
5 GPMI1
6 GPMI2
7 GPMI3
8 GPMI4
9 GPMI5
10 GPMI6
11 GPMI7
12 HSADC
13 LCDIF
14 EMPTY
15 EMPTY
A single command structure or channel command word specifies a number of operations

to be performed by the DMA in support of a given device. Thus, the CPU can set up large
units of work, chaining together many DMA channel command words, pass them off to the
DMA, and have no further concern for the device until the DMA completion interrupt
occurs. The goal is to have enough intelligence in the DMA and the devices to keep the
interrupt frequency from any device below 1 KHz (arrival intervals longer than 1 ms).

APBH DMA
A single command structure can issue 32-bit PIO write operations to key registers in the
associated device using the same APB bus and the controls, it uses to write DMA data bytes
to the device. For example, this allows a chain of operations to be issued to the GPMI
controller to send NAND command bytes, address bytes, and data transfers where the
command and the address structure is completely under software control, but the
administration of that transfer is handled autonomously by the DMA. Each DMA structure
can have 0–15 PIO words appended to it. The #PIOWORDs field, if non-zero, instructs the
DMA engine to copy these words to the APB, beginning at PADDR = 0x0000 and
incrementing its PADDR for each cycle.
The DMA master generates only normal read/write transfers to the APBH. It does not
generate set, clear, or toggle (SCT) transfers.
After any requested PIO words have been transferred to the peripheral, the DMA examines
the two-bit command field in the channel command structure.
Command chains are built up using the general structure, as shown in the figure.
word 0 NEXTCMDADDR
CMDPIOWORDS
WAIT4ENDCMD
HALTONTERMINATE
NANDWAIT4READY
SEMAPHORE
IRQONCMPLT
NANDLOCK
COMMAND
CHAIN
XFER_COUNT
word 1
word 2 BUFFER ADDRESS
word 3-n PIOWORD
Figure 6-2. AHB-to-APBH Bridge DMA Channel Command Structure
The following table shows the four commands implemented by the DMA.
Table 6-2. APBH DMA Commands
DMA COMMAND USAGE
00 NO_DMA_XFER. Perform any requested PIO word transfers, but terminate the command before any DMA
transfer.
01 DMA_WRITE. Perform any requested PIO word transfers, then perform a DMA transfer from the peripheral
for the specified number of bytes.
10 DMA_READ. Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral

DMA COMMAND USAGE
11 DMA_SENSE. Perform any requested PIO word transfers, then perform a conditional branch to the next
chained device. Follow the NEXTCMD_ADDR pointer if the peripheral sense is false. Follow the BUFFER_AD-
DRESS as a chain pointer if the peripheral sense line is true. This command becomes a no-operation for
any channel other than a GPMI channel.
DMA_WRITE operations copy data bytes to the system memory (on-chip RAM or SDRAM)
from the associated peripheral. Each peripheral has a target PADDR value that it expects
to receive DMA bytes. This association is synthesized in the DMA. The DMA_WRITE
transfer uses the BUFFER_ADDRESS word in the command structure to point to the
beginning byte to write data from the peripheral.
DMA_READ operations copy data bytes to the APB peripheral from the system memory.
The DMA engine contains a shared byte aligner that aligns bytes from system memory to
or from the peripherals. Peripherals always assume little-endian-aligned data arrives or
departs on their 32-bit APB. The DMA_READ transfer uses the BUFFER_ADDRESS
word in the command structure to point to the DMA data buffer to be read by the
DMA_READ command.
The NO_DMA_XFER command is used to write PIO words to a device without performing
any DMA data byte transfers. This command is useful in such applications as activating
the NAND devices CHECKSTATUS operation. The check status command in the NAND
peripheral reads a status byte from the NAND device, performs an XOR and MASK against
an expected value supplied as part of the PIO transfer. Once the read check completes (see
NAND Read Status Polling Example), the NO_DMA_XFER command completes. The
result in the peripheral is that its PSENSE line is driven by the results of the comparison.
The sense flip-flop is only updated by CHECKSTATUS for the device that is executed. At
some future point, the chain contains a DMA command structure with the fourth and final
command value, that is, the DMA_SENSE command.
As each DMA command completes, it triggers the DMA to load the next DMA command
structure in the chain. The normal flow list of DMA commands is found by following the
NEXTCMD_ADDR pointer in the DMA command structure. The DMA_SENSE command
uses the DMA buffer pointer word of the command structure to point to an alternate DMA
command structure chain or list. The DMA_SENSE command examines the sense line of
the associated peripheral. If the sense line is false, then the DMA follows the standard list
found whose next command is found from the pointer in the NEXTCMD_ADDR word of
the command structure. If the sense line is true, then the DMA follows the alternate list
whose next command is found from the pointer in the DMA Buffer Pointer word of the
DMA_SENSE command structure (see Figure 6-2). The sense command ignores the CHAIN
bit, so that both pointers must be valid when the DMA comes to a sense command.

APBH DMA
If the wait-for-end-command bit (WAIT4ENDCMD) is set in a command structure, then

the DMA channel waits for the device to signal completion of a command by toggling the
endcmcd signal before proceeding to load and execute the next command structure. Then,
if DECREMENT_SEMAPHORE is set, the semaphore will be decremented after the end
command is seen.
A detailed bit-field view of the DMA command structure is shown in the following table,
which shows a field that specifies the number of bytes to be transferred by this DMA
command. The transfer-count mechanism is duplicated in the associated peripheral, either
as an implied or as a specified count in the peripheral.
Table 6-3. DMA Channel Command Word in System Memory
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
NEXT_COMMAND_ADDRESS
DECREMENT SEMAPHORE
HALTONTERMINATE
NANDwAIT4READY
IRQ_COMPLETE
WAIT4ENDCMD
NANDLOCK
COMMAND
Number PIO
CHAIN
Number DMA Bytes to Transfer Words to
Write
DMA Buffer or Alternate CCW
Zero or More PIO Words to Write to the Associated Peripheral Starting at its Base Address on the APBH Bus
Figure 6-2 also shows the CHAIN bit in bit 2 of the second word of the command structure.
This bit is set to 1, if the NEXT_COMMAND_ADDRESS contains a pointer to another
DMA command structure. If a null pointer (0) is loaded into the
NEXT_COMMAND_ADDRESS, it is not detected by the DMA hardware. Only the CHAIN
bit indicates whether a valid list exists beyond the current structure.
If the IRQ_COMPLETE bit is set in the command structure, then the last act of the DMA
before loading the next command is to set the interrupt-status bit corresponding to the current
channel. The sticky interrupt request bit in the DMA CSR remains set until cleared by the
software. It can be used to interrupt the CPU.
The NAND_LOCK bit is monitored by the DMA channel arbiter. After a NAND channel
(from channel 4 to channel 11) succeeds in the arbiter with its NAND_LOCK bit set, then
the arbiter ignores the other seven NAND channels until a command is completed in which
the NAND_LOCK is not set. Notice that the semantic here is that the NAND_LOCK state
is to limit scheduling of a non-locked DMA. A DMA channel can go from unlocked to
locked in the arbiter at the beginning of a command when the NAND_LOCK bit is set.
When the last DMA command of an atomic sequence is completed, the lock should be
removed. To accomplish this, the last command does not have the NAND_LOCK bit. It is
still locked in the atomic state within the arbiter when the command starts, so that it is the
only NAND command that can be executed. At the end, it drops from the atomic state within
the arbiter.
The NAND_WAIT4READY bit also has a special use for DMA channels (from channel 4
to channel 11), that is, the NAND device channels. The NAND device supplies a sample
of the ready line for the NAND device. This ready value is used to hold off of a command
with this bit set until the ready line is asserted to 1. Once the arbiter sees a command with
a wait-for-ready set, it holds off that channel until ready is asserted.
Receiving an IRQ for HALTONTERMINATE (HOT) is a new feature in the APBH/X
DMA descriptor that allows certain peripheral block (for example, GPMI, SSP, I2C) to
signal to the DMA engine that an error has occurred. In prior chips, if a block is stalled due
to an error, the only practical way to discover this in software was through a timer of some
sort, or to poll the block. Now, an HOT signal is sent from the peripheral to the DMA engine
and causes an IRQ after terminating the DMA descriptor being executed. Note not all
peripheral block support this termination feature.
Therefore, it is recommended that software use this signal as follows:
• Always set HALTONTERMINATE to 1 in a DMA descriptor. That way, if a peripheral
signals HOT, the transfer will end, leaving the peripheral block and the DMA engine
synchronized (but at the end of a command).
• When an IRQ from an APBH/X channel is received, and the IRQ is determined to be
due to an error (as opposed to an IRQONCOMPLETE interrupt) the software should:
• Reset the channel.
• Determine the error from error reporting in the peripheral block, then manage the
error in the peripheral that is attached to that channel in whatever appropriate way
exists for that device (software recovery, device reset, block reset, and so on).
Each channel has an eight-bit counting semaphore that controls whether it is in the run or
idle state. When the semaphore is non-zero, the channel is ready to run, process commands
and perform DMA transfers. Whenever a command finishes its DMA transfer, it checks
the DECREMENT_SEMAPHORE bit. If set, it decrements the counting semaphore. If the
semaphore goes to 0 as a result, then the channel enters the IDLE state and remains there
until the semaphore is incremented by the software. When the semaphore goes to non-zero
and the channel is in its IDLE state, then it uses the value in the
HW_APBH_CHn_NXTCMDAR register (next command address register) to fetch a pointer

Implementation Examples
to the next command to process. NOTE: This is a double indirect case. This method allows
the software to append to a running command list under the protection of the counting
semaphore.
To start processing the first time, software creates the command list to be processed. It
writes the address of the first command into the HW_APBH_CHn_NXTCMDAR register,
and then writes 1 to the counting semaphore in HW_APBH_CHn_SEMA. The DMA channel
loads HW_APBH_CHn_CURCMDAR register and then enters the normal state machine
processing for the next command. When the software writes a value to the counting
semaphore, it is added to the semaphore count by hardware, protecting the case where both
hardware and software are trying to change the semaphore on the same clock edge.
Software can examine the value of HW_APBH_CHn_CURCMDAR at any time to determine
the location of the command structure currently being processed.
6.3 Implementation Examples

6.3.1 NAND Read Status Polling Example
The following figure shows a more complicated scenario. This subset of a NAND device
workload shows that the first two command structures are used during the data-write phase
of an NAND device write operation (CLE and ALE transfers omitted for clarity).
• After writing the data, one must wait until the NAND device status register indicates
that the write charge has been transferred. This is built into the workload using a check
status command in the NAND in a loop created from the next two DMA command
structures.
• The NO_DMA_TRANSFER command is shown here performing the read check,
followed by a DMA_SENSE command to branch the DMA command structure list,
based on the status of a bit in the external NAND device.

1 PIO, chaining, no DMA, Check

1 PIO, chaining, DMA read NAND status & set sense line
NEXTCMD_ADDR NEXTCMD_ADDR
512 1 0 0 1 10 0 1 0 0 1 00
BUFFER ADDRESS BUFFER ADDRESS
NAND0=write mode NAND0= check status
No PIO, chaining, no DMA,
conditional branch based
No PIO, chaining
on sense line
DMA read
512-Byte NEXTCMD_ADDR
NEXTCMD_ADDR
Data
Block 16 0 0 0 1 10 0 0 0 0 1 11
16-Byte
Spare 1 PIO, chaining, DMA read
Area NEXTCMD_ADDR
512 1 0 0 1 10
BUFFER ADDRESS
NAND0=write mode
No PIO,IRQ,
no chaining,
DMA read
512-Byte
NEXTCMD_ADDR=0
Data
Block 16 0 0 1 0 10
BUFFER ADDRESS
16-Byte
Spare
Area
Figure 6-3. AHB-to-APBH Bridge DMA NAND Read Status Polling with DMA Sense Command
The example in the above figure shows the workload continuing immediately to the next
NAND page transfer. However, one could perform a second sense operation to see if an
error has occurred after the write. One could then point the sense command alternate branch
at a NO_DMA_XFER command with the interrupt bit set. If the CHAIN bit is not set on
this failure branch, then the CPU is interrupted immediately, and the channel process is also
immediately terminated in the presence of a workload-detected NAND error bit.

Behavior During Reset
Note that each word of the three-word DMA command structure corresponds to a PIO
register of the DMA that is accessible on the APBH bus. Normally, the DMA copies the
next command structure onto these registers for processing at the start of each command
by following the value of the pointer previously loaded into the NEXTCMD_ADDR register.
To start DMA processing for the first command, initialize the PIO registers of the desired
channel, as follows:
• First, load the next command address register with a pointer to the first command to
be loaded.
• Then, write 1 to the counting semaphore register. This causes the DMA to schedule the
targeted channel for the DMA command structure load, as if it just finished its previous
command.

Correct Way to Soft Reset a Block for additional information on using the SFTRST and
CLKGATE bit fields.

APBH Hardware Register Format Summary
HW_APBH memory map
Absolute
Width Section/
(in bits) page
(hex)
8000_4000 AHB to APBH Bridge Control and Status Register 0 32 R/W E000_0000h 6.5.1/358
(HW_APBH_CTRL0)
8000_4010 AHB to APBH Bridge Control and Status Register 1 32 R/W 0000_0000h 6.5.2/359
(HW_APBH_CTRL1)
8000_4020 AHB to APBH Bridge Control and Status Register 2 32 R/W 0000_0000h 6.5.3/363
(HW_APBH_CTRL2)
8000_4030 AHB to APBH Bridge Channel Register 32 R/W 0000_0000h 6.5.4/367
(HW_APBH_CHANNEL_CTRL)
8000_4040 AHB to APBH DMA Device Assignment Register 32 R 0000_0000h 6.5.5/369
(HW_APBH_DEVSEL)
8000_4050 AHB to APBH DMA burst size 32 R/W 0055_5555h 6.5.6/370
(HW_APBH_DMA_BURST_SIZE)
8000_4060 AHB to APBH DMA Debug Register (HW_APBH_DEBUG) 32 R/W 0000_0000h 6.5.7/371

HW_APBH memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
8000_4100 APBH DMA Channel 0 Current Command Address Register 32 R 0000_0000h 6.5.8/372
(HW_APBH_CH0_CURCMDAR)
8000_4110 APBH DMA Channel 0 Next Command Address Register 32 R/W 0000_0000h 6.5.9/373
(HW_APBH_CH0_NXTCMDAR)
8000_4120 APBH DMA Channel 0 Command Register 32 R 0000_0000h 6.5.10/373
(HW_APBH_CH0_CMD)
8000_4130 APBH DMA Channel 0 Buffer Address Register 32 R 0000_0000h 6.5.11/376
(HW_APBH_CH0_BAR)
8000_4140 APBH DMA Channel 0 Semaphore Register 32 R/W 0000_0000h 6.5.12/376
(HW_APBH_CH0_SEMA)
8000_4150 AHB to APBH DMA Channel 0 Debug Information 32 R 00A0_0000h 6.5.13/377
(HW_APBH_CH0_DEBUG1)
8000_4160 AHB to APBH DMA Channel 0 Debug Information 32 R 0000_0000h 6.5.14/380
8000_4170 APBH DMA Channel 1 Current Command Address Register 32 R/W 0000_0000h 6.5.15/380
(HW_APBH_CH1_CMD)
8000_41A0 APBH DMA Channel 1 Buffer Address Register 32 R 0000_0000h 6.5.18/384
(HW_APBH_CH1_BAR)
8000_41B0 APBH DMA Channel 1 Semaphore Register 32 R/W 0000_0000h 6.5.19/385
(HW_APBH_CH1_SEMA)
8000_41C0 AHB to APBH DMA Channel 1 Debug Information 32 R 00A0_0000h 6.5.20/386
8000_41D0 AHB to APBH DMA Channel 1 Debug Information 32 R 0000_0000h 6.5.21/388
8000_41E0 APBH DMA Channel 2 Current Command Address Register 32 R 0000_0000h 6.5.22/389
8000_41F0 APBH DMA Channel 2 Next Command Address Register 32 R/W 0000_0000h 6.5.23/389
(HW_APBH_CH2_CMD)
(HW_APBH_CH2_BAR)
(HW_APBH_CH2_SEMA)


Absolute
Width Section/
(in bits) page
(hex)
(HW_APBH_CH3_CMD)
(HW_APBH_CH3_BAR)
(HW_APBH_CH3_SEMA)
8000_42A0 AHB to APBH DMA Channel 3 Debug Information 32 R 00A0_0000h 6.5.34/401
8000_42B0 AHB to APBH DMA Channel 3 Debug Information 32 R 0000_0000h 6.5.35/403
8000_42C0 APBH DMA Channel 4 Current Command Address Register 32 R 0000_0000h 6.5.36/404
8000_42D0 APBH DMA Channel 4 Next Command Address Register 32 R/W 0000_0000h 6.5.37/405
8000_42E0 APBH DMA Channel 4 Command Register 32 R 0000_0000h 6.5.38/405
(HW_APBH_CH4_CMD)
8000_42F0 APBH DMA Channel 4 Buffer Address Register 32 R 0000_0000h 6.5.39/407
(HW_APBH_CH4_BAR)
(HW_APBH_CH4_SEMA)
(HW_APBH_CH5_CMD)
(HW_APBH_CH5_BAR)
(HW_APBH_CH5_SEMA)


Absolute
Width Section/
(in bits) page
(hex)
8000_43A0 APBH DMA Channel 6 Current Command Address Register 32 R 0000_0000h 6.5.50/420
8000_43B0 APBH DMA Channel 6 Next Command Address Register 32 R/W 0000_0000h 6.5.51/420
8000_43C0 APBH DMA Channel 6 Command Register 32 R 0000_0000h 6.5.52/421
(HW_APBH_CH6_CMD)
8000_43D0 APBH DMA Channel 6 Buffer Address Register 32 R 0000_0000h 6.5.53/423
(HW_APBH_CH6_BAR)
8000_43E0 APBH DMA Channel 6 Semaphore Register 32 R/W 0000_0000h 6.5.54/423
(HW_APBH_CH6_SEMA)
8000_43F0 AHB to APBH DMA Channel 6 Debug Information 32 R 00A0_0000h 6.5.55/424
(HW_APBH_CH7_CMD)
(HW_APBH_CH7_BAR)
(HW_APBH_CH7_SEMA)
8000_44A0 APBH DMA Channel 8 Command Register 32 R 0000_0000h 6.5.66/436
(HW_APBH_CH8_CMD)
8000_44B0 APBH DMA Channel 8 Buffer Address Register 32 R 0000_0000h 6.5.67/438
(HW_APBH_CH8_BAR)
8000_44C0 APBH DMA Channel 8 Semaphore Register 32 R/W 0000_0000h 6.5.68/439
(HW_APBH_CH8_SEMA)
8000_44D0 AHB to APBH DMA Channel 8 Debug Information 32 R 00A0_0000h 6.5.69/440
8000_44E0 AHB to APBH DMA Channel 8 Debug Information 32 R 0000_0000h 6.5.70/442


Absolute
Width Section/
(in bits) page
(hex)
8000_44F0 APBH DMA Channel 9 Current Command Address Register 32 R 0000_0000h 6.5.71/443
(HW_APBH_CH9_CMD)
(HW_APBH_CH9_BAR)
(HW_APBH_CH9_SEMA)
8000_4560 APBH DMA channel 10 Current Command Address Register 32 R 0000_0000h 6.5.78/450
8000_4570 APBH DMA channel 10 Next Command Address Register 32 R/W 0000_0000h 6.5.79/451
8000_4580 APBH DMA channel 10 Command Register 32 R 0000_0000h 6.5.80/451
(HW_APBH_CH10_CMD)
8000_4590 APBH DMA channel 10 Buffer Address Register 32 R 0000_0000h 6.5.81/454
(HW_APBH_CH10_BAR)
8000_45A0 APBH DMA channel 10 Semaphore Register 32 R/W 0000_0000h 6.5.82/454
(HW_APBH_CH10_SEMA)
8000_45B0 AHB to APBH DMA channel 10 Debug Information 32 R 00A0_0000h 6.5.83/455
8000_45C0 AHB to APBH DMA channel 10 Debug Information 32 R 0000_0000h 6.5.84/457
8000_45D0 APBH DMA Channel 11 Current Command Address Register 32 R 0000_0000h 6.5.85/458
8000_45E0 APBH DMA Channel 11 Next Command Address Register 32 R/W 0000_0000h 6.5.86/458
8000_45F0 APBH DMA Channel 11 Command Register 32 R 0000_0000h 6.5.87/459
(HW_APBH_CH11_CMD)
(HW_APBH_CH11_BAR)
(HW_APBH_CH11_SEMA)


Absolute
Width Section/
(in bits) page
(hex)
(HW_APBH_CH12_CMD)
(HW_APBH_CH12_BAR)
8000_4680 APBH DMA channel 12 Semaphore Register 32 R/W 0000_0000h 6.5.96/470
(HW_APBH_CH12_SEMA)
8000_4690 AHB to APBH DMA channel 12 Debug Information 32 R 00A0_0000h 6.5.97/470
8000_46A0 AHB to APBH DMA channel 12 Debug Information 32 R 0000_0000h 6.5.98/473
8000_46B0 APBH DMA Channel 13 Current Command Address Register 32 R 0000_0000h 6.5.99/473
8000_46C0 APBH DMA Channel 13 Next Command Address Register 32 R/W 0000_0000h 6.5.100/474
8000_46D0 APBH DMA Channel 13 Command Register 32 R 0000_0000h 6.5.101/474
(HW_APBH_CH13_CMD)
8000_46E0 APBH DMA Channel 13 Buffer Address Register 32 R 0000_0000h 6.5.102/477
(HW_APBH_CH13_BAR)
8000_46F0 APBH DMA Channel 13 Semaphore Register 32 R/W 0000_0000h 6.5.103/477
(HW_APBH_CH13_SEMA)
(HW_APBH_CH14_CMD)
(HW_APBH_CH14_BAR)
8000_4760 APBH DMA channel 14 Semaphore Register 32 R/W 0000_0000h 6.5.110/485
(HW_APBH_CH14_SEMA)
8000_4770 AHB to APBH DMA channel 14 Debug Information 32 R 0000_0000h 6.5.111/485
8000_4780 AHB to APBH DMA channel 14 Debug Information 32 R 0000_0000h 6.5.112/488


Absolute
Width Section/
(in bits) page
(hex)
8000_47A0 APBH DMA channel 15 Next Command Address Register 32 R/W 0000_0000h 6.5.114/489
8000_47B0 APBH DMA channel 15 Command Register 32 R 0000_0000h 6.5.115/490
(HW_APBH_CH15_CMD)
8000_47C0 APBH DMA channel 15 Buffer Address Register 32 R 0000_0000h 6.5.116/492
(HW_APBH_CH15_BAR)
8000_47D0 APBH DMA channel 15 Semaphore Register 32 R/W 0000_0000h 6.5.117/492
(HW_APBH_CH15_SEMA)
8000_47E0 AHB to APBH DMA channel 15 Debug Information 32 R 0000_0000h 6.5.118/493
8000_47F0 AHB to APBH DMA channel 15 Debug Information 32 R 0000_0000h 6.5.119/495
8000_4800 APBH Bridge Version Register (HW_APBH_VERSION) 32 R 0301_0000h 6.5.120/496
6.5.1 AHB to APBH Bridge Control and Status Register 0

(HW_APBH_CTRL0)
The APBH CTRL 0 provides overall control of the AHB to APBH bridge and DMA.
HW_APBH_CTRL0: 0x000
HW_APBH_CTRL0_SET: 0x004
HW_APBH_CTRL0_CLR: 0x008
HW_APBH_CTRL0_TOG: 0x00C
This register contains module softreset, clock gating, channel clock gating/freeze bits.
Address: HW_APBH_CTRL0 – 8000_4000h base + 0h offset = 8000_4000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BURST8_EN
BURST_EN
R RSVD0
CLKGATE
SFTRST
AHB_
APB_
Reset 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLKGATE_CHANNEL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_APBH_CTRL0 field descriptions

Field Description
31 Set this bit to zero to enable normal APBH DMA operation. Set this bit to one (default) to disable clocking
SFTRST with the APBH DMA and hold it in its reset (lowest power) state. This bit can be turned on and then off to
reset the APBH DMA block to its default state.
30 This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block.
CLKGATE
29 Set this bit to one (default) to enable AHB 8-beat burst. Set to zero to disable 8-beat burst on AHB interface.
AHB_BURST8_
EN
28 Set this bit to one to enable apb master do a continous transfers when a device request a burst dma. Set
APB_BURST_EN to zero will treat a burst dma request as 4/8 individual requests.
27–16 Reserved, always set to zero.

RSVD0
15–0 These bits must be set to zero for normal operation of each channel. When set to one they gate off the
CLKGATE_ individual clocks to the channels.
CHANNEL
0x0001 SSP0 —
0x0002 SSP1 —
0x0004 SSP2 —
0x0008 SSP3 —
0x0010 NAND0 —
0x0020 NAND1 —
0x0040 NAND2 —
0x0080 NAND3 —
0x0100 NAND4 —
0x0200 NAND5 —
0x0400 NAND6 —
0x0800 NAND7 —
0x1000 HSADC —
0x2000 LCDIF —

(HW_APBH_CTRL1)
The APBH CTRL one provides overall control of the interrupts generated by the AHB to
APBH DMA.
This register contains the per channel interrupt status bits and the per channel interrupt
enable bits. Each channel has a dedicated interrupt vector in the vectored interrupt controller.
EXAMPLE
BF_WR(APBH_CTRL1, CH5_CMDCMPLT_IRQ, 0); // use bitfield write macro

BF_APBH_CTRL1.CH5_CMDCMPLT_IRQ = 0; // or, assign to register struct's bitfield

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH15_CMDCMPLT_
CH14_CMDCMPLT_
CH13_CMDCMPLT_
CH12_CMDCMPLT_
CH11_CMDCMPLT_
CH10_CMDCMPLT_
CH9_CMDCMPLT_
CH8_CMDCMPLT_
CH7_CMDCMPLT_
CH6_CMDCMPLT_
CH5_CMDCMPLT_
CH4_CMDCMPLT_
CH3_CMDCMPLT_
CH2_CMDCMPLT_
CH1_CMDCMPLT_
CH0_CMDCMPLT_
R
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH15_CMDCMPLT_
CH14_CMDCMPLT_
CH13_CMDCMPLT_
CH12_CMDCMPLT_
CH11_CMDCMPLT_
CH10_CMDCMPLT_
CH9_CMDCMPLT_
CH8_CMDCMPLT_
CH7_CMDCMPLT_
CH6_CMDCMPLT_
CH5_CMDCMPLT_
CH4_CMDCMPLT_
CH3_CMDCMPLT_
CH2_CMDCMPLT_
CH1_CMDCMPLT_
CH0_CMDCMPLT_
R
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
31 Setting this bit enables the generation of an interrupt request for APBH DMA channel 15.
CH15_
CMDCMPLT_
IRQ_EN
CH14_
CMDCMPLT_
IRQ_EN
CH13_
CMDCMPLT_
IRQ_EN

HW_APBH_CTRL1 field descriptions (continued)

Field Description
CH12_
CMDCMPLT_
IRQ_EN
CH11_
CMDCMPLT_
IRQ_EN
CH10_
CMDCMPLT_
IRQ_EN
CH9_
CMDCMPLT_
IRQ_EN
CH8_
CMDCMPLT_
IRQ_EN
CH7_
CMDCMPLT_
IRQ_EN
CH6_
CMDCMPLT_
IRQ_EN
CH5_
CMDCMPLT_
IRQ_EN
CH4_
CMDCMPLT_
IRQ_EN
CH3_
CMDCMPLT_
IRQ_EN
CH2_
CMDCMPLT_
IRQ_EN
CH1_
CMDCMPLT_
IRQ_EN


Field Description
CH0_
CMDCMPLT_
IRQ_EN
15 Interrupt request status bit for APBH DMA Channel 15. This sticky bit is set by DMA hardware and reset by
CH15_ software. It is ANDed with its corresponding enable bit to generate an interrupt.
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
7 Interrupt request status bit for APBH DMA channel 7. This sticky bit is set by DMA hardware and reset by
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ


Field Description
CMDCMPLT_IRQ
CMDCMPLT_IRQ

(HW_APBH_CTRL2)
The APBH CTRL 2 provides channel error interrupts generated by the AHB to APBH
DMA.
This register contains the per channel interrupt status bits and the per channel interrupt
enable bits. Each channel has a dedicated interrupt vector in the vectored interrupt controller.
EXAMPLE
BF_WR(APBH_CTRL1, CH5_CMDCMPLT_IRQ, 0); // use bitfield write macro

BF_APBH_CTRL1.CH5_CMDCMPLT_IRQ = 0; // or, assign to register struct's bitfield

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERROR_
ERROR_
ERROR_
ERROR_
ERROR_
ERROR_
ERROR_
ERROR_
ERROR_
ERROR_
ERROR_
ERROR_
ERROR_
ERROR_
ERROR_
ERROR_
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
CH15_
CH14_
CH13_
CH12_
CH11_
CH10_
CH9_
CH8_
CH7_
CH6_
CH5_
CH4_
CH3_
CH2_
CH1_
CH0_
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH15_ERROR_IRQ
CH14_ERROR_IRQ
CH13_ERROR_IRQ
CH12_ERROR_IRQ
CH11_ERROR_IRQ
CH10_ERROR_IRQ
CH9_ERROR_IRQ
CH8_ERROR_IRQ
CH7_ERROR_IRQ
CH6_ERROR_IRQ
CH5_ERROR_IRQ
CH4_ERROR_IRQ
CH3_ERROR_IRQ
CH2_ERROR_IRQ
CH1_ERROR_IRQ
CH0_ERROR_IRQ
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
31 Error status bit for APBH DMA Channel 15. Valid when corresponding Error IRQ is set.
CH15_ERROR_
1 - AHB bus error
STATUS
0 - channel early termination.
0x0 TERMINATION — An early termination from the device causes error IRQ.
0x1 BUS_ERROR — An AHB bus error causes error IRQ.
CH14_ERROR_
1 - AHB bus error
STATUS
CH13_ERROR_
1 - AHB bus error
STATUS
CH12_ERROR_
1 - AHB bus error
STATUS
CH11_ERROR_
1 - AHB bus error
STATUS
CH10_ERROR_
1 - AHB bus error
STATUS


Field Description
CH9_ERROR_
1 - AHB bus error
STATUS
CH8_ERROR_
1 - AHB bus error
STATUS
23 Error status bit for APBX DMA Channel 7. Valid when corresponding Error IRQ is set.
CH7_ERROR_
1 - AHB bus error
STATUS
CH6_ERROR_
1 - AHB bus error
STATUS
CH5_ERROR_
1 - AHB bus error
STATUS
CH4_ERROR_
1 - AHB bus error
STATUS
CH3_ERROR_
1 - AHB bus error
STATUS
CH2_ERROR_
1 - AHB bus error
STATUS


Field Description
CH1_ERROR_
1 - AHB bus error
STATUS
CH0_ERROR_
1 - AHB bus error
STATUS
15 Error interrupt status bit for APBH DMA Channel 15. This sticky bit is set by DMA hardware and reset by
CH15_ERROR_ software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM.
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
7 Error interrupt status bit for APBX DMA Channel 7. This sticky bit is set by DMA hardware and reset by
IRQ
IRQ


Field Description
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
6.5.4 AHB to APBH Bridge Channel Register

(HW_APBH_CHANNEL_CTRL)
The APBH CHANNEL CTRL provides reset/freeze control of each DMA channel.
HW_APBH_CHANNEL_CTRL: 0x030
HW_APBH_CHANNEL_CTRL_SET: 0x034
HW_APBH_CHANNEL_CTRL_CLR: 0x038
HW_APBH_CHANNEL_CTRL_TOG: 0x03C
This register contains individual channel reset/freeze bits.
Address: HW_APBH_CHANNEL_CTRL – 8000_4000h base + 30h offset = 8000_4030h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RESET_CHANNEL FREEZE_CHANNEL
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

HW_APBH_CHANNEL_CTRL field descriptions

Field Description
31–16 Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state.
RESET_ The bit is reset after the channel resources are cleared.
CHANNEL
0x0001 SSP0 —
0x0002 SSP1 —
0x0004 SSP2 —
0x0008 SSP3 —
0x0010 NAND0 —
0x0020 NAND1 —
0x0040 NAND2 —
0x0080 NAND3 —
0x0100 NAND4 —
0x0200 NAND5 —
0x0400 NAND6 —
0x0800 NAND7 —
0x1000 HSADC —
0x2000 LCDIF —
15–0 Setting a bit in this field will freeze the DMA channel associated with it. This field is a direct input to the DMA
FREEZE_ channel arbiter. When frozen, the channel is denied access to the central DMA resources. Note: 1. DMA
CHANNEL PIO write to associated peripheral is not supported when Freeze bit is set, and use ARM instead to configure
peripheral. 2. After FREEZE bit is set, no more access, neither AHB access to memory nor APB access to
peripherals, will be allowed by arbiter. But, there might be on-going channel access exactly when FREEZE
bit is set, either INCR8/INCR4/SINGLE AHB access or APB peripheral access, this on-going access will not
be affected by FREEZE bit and will finish as normal. That is to say, setting FREEZE bit might not freeze
channel access immediately, it only freezes further channel access, and you have to wait a while to freeze
channel access completely. To make sure that there is no more access from freezed channel, channel state
machine should be checked by reading channel DEBUG1 register, wait till state stunk at any of IDLE,
READ_REQ, WRITE, or CHAIN_WAIT.
0x0001 SSP0 —
0x0002 SSP1 —
0x0004 SSP2 —
0x0008 SSP3 —
0x0010 NAND0 —
0x0020 NAND1 —
0x0040 NAND2 —
0x0080 NAND3 —
0x0100 NAND4 —
0x0200 NAND5 —
0x0400 NAND6 —
0x0800 NAND7 —
0x1000 HSADC —
0x2000 LCDIF —

6.5.5 AHB to APBH DMA Device Assignment Register

(HW_APBH_DEVSEL)
This register allows reassignment of the APBH device connected to the DMA Channels.
In this chip, apbhdma channel resource is enough for high speed peripherals, so this register
is of no use and reserved.
Address: HW_APBH_DEVSEL – 8000_4000h base + 40h offset = 8000_4040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_APBH_DEVSEL field descriptions

Field Description
31–30 Reserved.
CH15
29–28 Reserved.
CH14
27–26 Reserved.
CH13
25–24 Reserved.
CH12
23–22 Reserved.
CH11
21–20 Reserved.
CH10
19–18 Reserved.
CH9
17–16 Reserved.
CH8
15–14 Reserved.
CH7
13–12 Reserved.
CH6
11–10 Reserved.
CH5
9–8 Reserved.
CH4
7–6 Reserved.
CH3

HW_APBH_DEVSEL field descriptions (continued)

Field Description
5–4 Reserved.
CH2
3–2 Reserved.
CH1
1–0 Reserved.
CH0
6.5.6 AHB to APBH DMA burst size (HW_APBH_DMA_BURST_SIZE)

This register programs the apbh burst size of the APBH DMA devices when a DMA burst
request is issued.
It provides a mechanism for improving bandwidth between DMA and device if device's
FIFO is large enough.
Address: HW_APBH_DMA_BURST_SIZE – 8000_4000h base + 50h offset = 8000_4050h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CH15 CH14 CH13 CH12

CH11
CH10
CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
W
Re- 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
set
HW_APBH_DMA_BURST_SIZE field descriptions

Field Description
31–30 Reserved.
CH15
29–28 Reserved.
CH14
27–26 Reserved. HSADC not support DMA burst request.
CH13
25–24 Reserved.LCDIF not support DMA burst request.
CH12
23–22 DMA burst size for GPMI channel 7. Do not change. GPMI only support burst size 4.
CH11
CH10
CH9
CH8

HW_APBH_DMA_BURST_SIZE field descriptions (continued)

Field Description
CH7
CH6
CH5
CH4
7–6 DMA burst size for SSP3.
CH3
0x0 BURST0 —
0x1 BURST4 —
0x2 BURST8 —
CH2
0x0 BURST0 —
0x1 BURST4 —
0x2 BURST8 —
CH1
0x0 BURST0 —
0x1 BURST4 —
0x2 BURST8 —
CH0
0x0 BURST0 —
0x1 BURST4 —
0x2 BURST8 —
6.5.7 AHB to APBH DMA Debug Register (HW_APBH_DEBUG)

This register is for debug purpose.
It is for internal use only. Not recommend for customer usage.
Address: HW_APBH_DEBUG – 8000_4000h base + 60h offset = 8000_4060h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPMI_ONE_
R RSVD[15:1]
FIFO
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_APBH_DEBUG field descriptions

Field Description
RSVD
0 Set to one and the eight GPMI channels will share the DMA FIFO, and when set to zero, the eight GPMI
GPMI_ONE_ channels will use its own DMA FIFO.
FIFO
6.5.8 APBH DMA Channel 0 Current Command Address Register

The APBH DMA channel 0 current command address register points to the multiword
command that is currently being executed. Commands are threaded on the command address.
APBH DMA Channel 0 is controlled by a variable sized command structure. This register
points to the command structure currently being executed.
EXAMPLE
pCurCmd = (hw_apbh_chn_cmd_t *) HW_APBH_CHn_CURCMDAR_RD(0); // read the whole

register, since there is only one field
pCurCmd = (hw_apbh_chn_cmd_t *) BF_RDn(APBH_CHn_CURCMDAR, 0, CMD_ADDR); // or, use
multi-register bitfield read macro
pCurCmd = (hw_apbh_chn_cmd_t *) HW_APBH_CHn_CURCMDAR(0).CMD_ADDR; // or, assign from
bitfield of indexed register's struct
Address: HW_APBH_CH0_CURCMDAR – 8000_4000h base + 100h offset = 8000_4100h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_APBH_CH0_CURCMDAR field descriptions

Field Description
31–0 Pointer to command structure currently being processed for channel 0.
CMD_ADDR

6.5.9 APBH DMA Channel 0 Next Command Address Register

The APBH DMA Channel 0 Next Command Address register contains the address of the
next multiword command to be executed. Commands are threaded on the command address.
Set CHAIN to 1 in the DMA command word to process command lists.
APBH DMA Channel 0 is controlled by a variable sized command structure. Software loads
this register with the address of the first command structure to process and increments the
Channel 0 semaphore to start processing. This register points to the next command structure
to be executed when the current command is completed.
EXAMPLE
HW_APBH_CHn_NXTCMDAR_WR(0, (reg32_t) pCommandTwoStructure); // write the entire register,

since there is only one field
BF_WRn(APBH_CHn_NXTCMDAR, 0, (reg32_t) pCommandTwoStructure); // or, use multi-register
bitfield write macro
HW_APBH_CHn_NXTCMDAR(0).CMD_ADDR = (reg32_t) pCommandTwoStructure; // or, assign to bitfield
of indexed register's struct
Address: HW_APBH_CH0_NXTCMDAR – 8000_4000h base + 110h offset = 8000_4110h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_APBH_CH0_NXTCMDAR field descriptions

Field Description
31–0 Pointer to next command structure for channel 0.
CMD_ADDR
6.5.10 APBH DMA Channel 0 Command Register (HW_APBH_CH0_CMD)

The APBH DMA Channel 0 command register specifies the DMA transaction to perform
for the current command chain item.
The command register controls the overall operation of each DMA command for this channel.
It includes the number of bytes to transfer to or from the device, the number of APB PIO
command words included with this command structure, whether to interrupt at command
completion, whether to chain an additional command to the end of this one and whether
this transfer is a read or write DMA transfer.

EXAMPLE
hw_apbh_chn_cmd_t dma_cmd;
dma_cmd.XFER_COUNT = 512; // transfer 512 bytes
dma_cmd.COMMAND = BV_APBH_CHn_CMD_COMMAND__DMA_WRITE; // transfer to system memory from
peripheral device
dma_cmd.CHAIN = 1; // chain an additional command structure
on to the list
dma_cmd.IRQONCMPLT = 1; // generate an interrupt on completion
of this command structure
Address: HW_APBH_CH0_CMD – 8000_4000h base + 120h offset = 8000_4120h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HALTONTERMINATE
WAIT4ENDCMD
NANDWAIT4READY
IRQONCMPLT
SEMAPHORE
NANDLOCK
CHAIN
R CMDWORDS RSVD1 COMMAND
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_APBH_CH0_CMD field descriptions

Field Description
31–16 This field indicates the number of bytes to transfer to or from the appropriate PIO register in the SSP0
XFER_COUNT device. A value of 0 indicates a 64 KBytes transfer.

HW_APBH_CH0_CMD field descriptions (continued)

Field Description
15–12 This field indicates the number of command words to send to the SSP0, starting with the base PIO
CMDWORDS address of the SSP0 control register and incrementing from there. Zero means transfer NO command
words

RSVD1
8 A value of one indicates that the channel immediately terminates the current descriptor and halts the
HALTONTERMINATE DMA channel if a terminate signal is set. A value of 0 still causes an immediate terminate of the
channel if the terminate signal is set, but the channel continues as if the count had been exhausted,
meaning it honors IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD.
7 A value of one indicates that the channel waits for the end of command signal to be sent from the
WAIT4ENDCMD APBH device to the DMA before starting the next DMA command.
6 A value of one indicates that the channel decrements its semaphore at the completion of the current
SEMAPHORE command structure. If the semaphore decrements to zero, then this channel stalls until software
increments it again.
5 A value of one indicates that the NAND DMA channel waits until the NAND device reports \'ready\'
NANDWAIT4READY before executing the command. It is ignored for non-NAND DMA channels.
4 A value of one indicates that the NAND DMA channel remains locked in the arbiter at the expense of
NANDLOCK other NAND DMA channels. It is ignored for non-NAND DMA channels.
3 A value of one indicates that the channel will cause the interrupt status bit to be set upon completion
IRQONCMPLT of the current command, i.e. after the DMA transfer is complete.
2 A value of one indicates that another command is chained onto the end of the current command
CHAIN structure. At the completion of the current command, this channel will follow the pointer in
HW_APBH_CH0_CMDAR to find the next command.
1–0 This bitfield indicates the type of current command:

COMMAND
00- NO DMA TRANSFER
01- Write transfers, that is, data sent from the SSP0 (APB PIO Read) to the system memory (AHB
master write).
10- Read transfer
11- SENSE
0x0 NO_DMA_XFER — Perform any requested PIO word transfers but terminate command before
any DMA transfer.
0x1 DMA_WRITE — Perform any requested PIO word transfers and then perform a DMA transfer
from the peripheral for the specified number of bytes.
0x2 DMA_READ — Perform any requested PIO word transfers and then perform a DMA transfer
to the peripheral for the specified number of bytes.
0x3 DMA_SENSE — Perform any requested PIO word transfers and then perform a conditional
branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense
is false. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is true.

6.5.11 APBH DMA Channel 0 Buffer Address Register

(HW_APBH_CH0_BAR)
The APBH DMA Channel 0 buffer address register contains a pointer to the data buffer for
the transfer. For immediate forms, the data is taken from this register. This is a byte address
which means transfers can start on any byte boundary.
This register holds a pointer to the data buffer in system memory. After the command values
have been read into the DMA controller and the device controlled by this channel, then the
DMA transfer will begin, to or from the buffer pointed to by this register.
EXAMPLE
hw_apbh_chn_bar_t dma_data;
dma_data.ADDRESS = (reg32_t) pDataBuffer;
Address: HW_APBH_CH0_BAR – 8000_4000h base + 130h offset = 8000_4130h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_APBH_CH0_BAR field descriptions

Field Description
31–0 Address of system memory buffer to be read or written over the AHB bus.
ADDRESS
6.5.12 APBH DMA Channel 0 Semaphore Register

(HW_APBH_CH0_SEMA)
The APBH DMA Channel 0 semaphore register is used to synchronize the CPU instruction
stream and the DMA chain processing state.
Each DMA channel has an 8 bit counting semaphore that is used to synchronize between
the program stream and and the DMA chain processing. DMA processing continues until
the DMA attempts to decrement a semaphore that has already reached a value of zero. When
the attempt is made, the DMA channel is stalled until software increments the semaphore
count.
EXAMPLE

BF_WR(APBH_CHn_SEMA, 0, INCREMENT_SEMA, 2); // increment semaphore by two

current_sema = BF_RD(APBH_CHn_SEMA, 0, PHORE); // get instantaneous value
Address: HW_APBH_CH0_SEMA – 8000_4000h base + 140h offset = 8000_4140h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_APBH_CH0_SEMA field descriptions

Field Description
RSVD2
23–16 This read-only field shows the current (instantaneous) value of the semaphore counter.
PHORE
RSVD1
7–0 The value written to this field is added to the semaphore count in an atomic way such that simultaneous
INCREMENT_ software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads
SEMA back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA
channel decrements the count on the same clock, then the count is incremented by a net one.
6.5.13 AHB to APBH DMA Channel 0 Debug Information

This register gives debug visibility into the APBH DMA Channel 0 state machine and
controls.
This register allows debug visibility of the APBH DMA Channel 0.

Address: HW_APBH_CH0_DEBUG1 – 8000_4000h base + 150h offset = 8000_4150h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
SENSE
BURST
READY
LOCK
R REQ KICK END RSVD1[19:16]
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1[15:5] STATEMACHINE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_APBH_CH0_DEBUG1 field descriptions

Field Description
31 This bit reflects the current state of the DMA Request Signal from the APB device
REQ
30 This bit reflects the current state of the DMA Burst Signal from the APB device
BURST
29 This bit reflects the current state of the DMA Kick Signal sent to the APB Device
KICK
28 This bit reflects the current state of the DMA End Command Signal sent from the APB Device
END

HW_APBH_CH0_DEBUG1 field descriptions (continued)

Field Description
27 This bit is reserved for this DMA Channel and always reads 0. For Channels 4-11, this bit reflects
SENSE the current state of the GPMI Sense Signal sent from the APB GPMI Device
READY the current state of the GPMI Ready Signal sent from the APB GPMI Device
25 This bit is reserved for this Channel and always reads 0. For Channels 4-11, this bit reflects the
LOCK current state of the DMA Channel Lock for a GPMI Channel.
24 This bit reflects the internal bit which indicates whether the channel's next command address is
NEXTCMDADDRVALID valid.
23 This bit reflects the current state of the DMA Channel's Read FIFO Empty signal.
RD_FIFO_EMPTY
22 This bit reflects the current state of the DMA Channel's Read FIFO Full signal.
RD_FIFO_FULL
21 This bit reflects the current state of the DMA Channel's Write FIFO Empty signal.
WR_FIFO_EMPTY
20 This bit reflects the current state of the DMA Channel's Write FIFO Full signal.
WR_FIFO_FULL
19–5 Reserved
RSVD1
4–0 PIO Display of the DMA Channel 0 state machine state.
STATEMACHINE
0x00 IDLE — This is the idle state of the DMA state machine.
0x01 REQ_CMD1 — State in which the DMA is waiting to receive the first word of a command.
0x02 REQ_CMD3 — State in which the DMA is waiting to receive the third word of a command.
0x03 REQ_CMD2 — State in which the DMA is waiting to receive the second word of a command.
0x04 XFER_DECODE — The state machine processes the descriptor command field in this state
and branches accordingly.
0x05 REQ_WAIT — The state machine waits in this state for the PIO APB cycles to complete.
0x06 REQ_CMD4 — State in which the DMA is waiting to receive the fourth word of a command,
or waiting to receive the PIO words when PIO count is greater than 1.
0x07 PIO_REQ — This state determines whether another PIO cycle needs to occur before starting
DMA transfers.
0x08 READ_FLUSH — During a read transfers, the state machine enters this state waiting for the
last bytes to be pushed out on the APB.
0x09 READ_WAIT — When an AHB read request occurs, the state machine waits in this state
for the AHB transfer to complete.
0x0C WRITE — During DMA Write transfers, the state machine waits in this state until the AHB
master arbiter accepts the request from this channel.
0x0D READ_REQ — During DMA Read transfers, the state machine waits in this state until the
AHB master arbiter accepts the request from this channel.
0x0E CHECK_CHAIN — Upon completion of the DMA transfers, this state checks the value of
the Chain bit and branches accordingly.
0x0F XFER_COMPLETE — The state machine goes to this state after the DMA transfers are
complete, and determines what step to take next.
0x14 TERMINATE — When a terminate signal is set, the state machine enters this state until the
current AHB transfer is completed.


Field Description
0x15 WAIT_END — When the Wait for Command End bit is set, the state machine enters this
state until the DMA device indicates that the command is complete.
0x1C WRITE_WAIT — During DMA Write transfers, the state machine waits in this state until the
AHB master completes the write to the AHB memory space.
0x1D HALT_AFTER_TERM — If HALTONTERMINATE is set and a terminate signal is set, the
state machine enters this state and effectively halts. A channel reset is required to exit this
state
0x1E CHECK_WAIT — If the Chain bit is a 0, the state machine enters this state and effectively
halts.
0x1F WAIT_READY — When the NAND Wait for Ready bit is set, the state machine enters this
state until the GPMI device indicates that the external device is ready.

This register gives debug visibility for the APB and AHB byte counts for DMA Channel
0.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R APB_BYTES AHB_BYTES
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–16 This value reflects the current number of APB bytes remaining to be transfered in the current transfer.
APB_BYTES
15–0 This value reflects the current number of AHB bytes remaining to be transfered in the current transfer.
AHB_BYTES

The APBH DMA Channel 1 current command address register points to the multiword

EXAMPLE
pCurCmd = (hw_apbh_chn_cmd_t *) HW_APBH_CHn_CURCMDAR_RD(1); // read the whole

pCurCmd = (hw_apbh_chn_cmd_t *) BF_RDn(APBH_CHn_CURCMDAR, 1, CMD_ADDR); // or, use
pCurCmd = (hw_apbh_chn_cmd_t *) HW_APBH_CHn_CURCMDAR(1).CMD_ADDR; // or, assign from

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

The APBH DMA Channel 1 Next Command Address register contains the address of the
next multiword command to be executed. Commands are threaded on the command address.
Set CHAIN to 1 in the DMA command word to process command lists.
EXAMPLE
HW_APBH_CHn_NXTCMDAR_WR(1, (reg32_t) pCommandTwoStructure); // write the entire register,

BF_WRn(APBH_CHn_NXTCMDAR, 1, (reg32_t) pCommandTwoStructure); // or, use multi-register
HW_APBH_CHn_NXTCMDAR(1).CMD_ADDR = (reg32_t) pCommandTwoStructure; // or, assign to bitfield


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

The APBH DMA Channel 1 command register specifies the cycle to perform for the current
command chain item.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HALTONTERMINATE
WAIT4ENDCMD
NANDWAIT4READY
IRQONCMPLT
SEMAPHORE
NANDLOCK
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
XFER_COUNT device. A value of 0 indicates a 64 KBytes trasnfer size.
words

RSVD1


Field Description
COMMAND
00- NO DMA TRANSFER
master write).
10- Read transfer
11- SENSE
any DMA transfer.

(HW_APBH_CH1_BAR)
EXAMPLE
hw_apbh_chn_bar_t dma_data;
Address: HW_APBH_CH1_BAR – 8000_4000h base + 1A0h offset = 8000_41A0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
ADDRESS

(HW_APBH_CH1_SEMA)
The APBH DMA Channel 1 semaphore register is used to synchronize between the CPU
instruction stream and the DMA chain processing state.
count.
EXAMPLE

Address: HW_APBH_CH1_SEMA – 8000_4000h base + 1B0h offset = 8000_41B0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE
RSVD1


controls.
Address: HW_APBH_CH1_DEBUG1 – 8000_4000h base + 1C0h offset = 8000_41C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
SENSE
BURST
READY
REQ KICK END LOCK RSVD1[19:16]

R
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Field Description
REQ
BURST
KICK
END
24 This bit reflect the internal bit which indicates whether the channel's next command address is valid.
NEXTCMDADDRVALID
23 This bit reflect the current state of the DMA Channel's Read FIFO Empty signal.
RD_FIFO_EMPTY
22 This bit reflect the current state of the DMA Channel's Read FIFO Full signal.
RD_FIFO_FULL
21 This bit reflect the current state of the DMA Channel's Write FIFO Empty signal.
WR_FIFO_EMPTY
20 This bit reflect the current state of the DMA Channel's Write FIFO Full signal.
WR_FIFO_FULL
19–5 Reserved
RSVD1
STATEMACHINE
DMA transfers.


Field Description
state
halts.

1.
Address: HW_APBH_CH1_DEBUG2 – 8000_4000h base + 1D0h offset = 8000_41D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES


Address: HW_APBH_CH2_CURCMDAR – 8000_4000h base + 1E0h offset = 8000_41E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

The APBH DMA Channel 2 next command address register points to the next multiword
command to be executed. Commands are threaded on the command address. Set CHAIN
to one to process command lists.
Address: HW_APBH_CH2_NXTCMDAR – 8000_4000h base + 1F0h offset = 8000_41F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
CMD_ADDR

command chain item.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HALTONTERMINATE
WAIT4ENDCMD
NANDWAIT4READY
IRQONCMPLT
SEMAPHORE
NANDLOCK
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
words

RSVD1


Field Description
COMMAND
00- NO DMA TRANSFER
master write).
10- Read transfer
11- SENSE
any DMA transfer.

(HW_APBH_CH2_BAR)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDRESS


(HW_APBH_CH2_SEMA)
count.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE
RSVD1

controls.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
SENSE
BURST
READY
LOCK
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
REQ
BURST
KICK
END


Field Description
NEXTCMDADDRVALID
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1
STATEMACHINE
DMA transfers.


Field Description
state
halts.

2.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR


command chain item.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HALTONTERMINATE
WAIT4ENDCMD
NANDWAIT4READY
IRQONCMPLT
SEMAPHORE
NANDLOCK
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Field Description
words

RSVD1

COMMAND
00- NO DMA TRANSFER
master write).
10- Read transfer
11- SENSE
any DMA transfer.


(HW_APBH_CH3_BAR)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDRESS

(HW_APBH_CH3_SEMA)
count.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
RSVD2
PHORE
RSVD1

controls.
Address: HW_APBH_CH3_DEBUG1 – 8000_4000h base + 2A0h offset = 8000_42A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
SENSE
BURST
READY
LOCK
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
REQ
BURST
KICK
END
NEXTCMDADDRVALID
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL


Field Description
19–5 Reserved
RSVD1
STATEMACHINE
DMA transfers.
state
halts.

3.


Address: HW_APBH_CH3_DEBUG2 – 8000_4000h base + 2B0h offset = 8000_42B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES

Address: HW_APBH_CH4_CURCMDAR – 8000_4000h base + 2C0h offset = 8000_42C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR


Address: HW_APBH_CH4_NXTCMDAR – 8000_4000h base + 2D0h offset = 8000_42D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

command chain item.

Address: HW_APBH_CH4_CMD – 8000_4000h base + 2E0h offset = 8000_42E0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
HALTONTERMINATE 7 6 5 4 3 2 1 0
WAIT4ENDCMD
NANDWAIT4READY
IRQONCMPLT
SEMAPHORE
NANDLOCK
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
31–16 This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0
15–12 This field indicates the number of command words to send to the GPMI0, starting with the base PIO
CMDWORDS address of the GPMI0 control register and incrementing from there. Zero means transfer NO command
words

RSVD1


Field Description

COMMAND
00- NO DMA TRANSFER
01- Write transfers, that is, data sent from the NAND0(APB PIO Read) to the system memory (AHB
master write).
10- Read transfer
11- SENSE
any DMA transfer.

(HW_APBH_CH4_BAR)

Address: HW_APBH_CH4_BAR – 8000_4000h base + 2F0h offset = 8000_42F0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDRESS

(HW_APBH_CH4_SEMA)
The APBH DMA Channel 4 semaphore register is used to synchronize the CPU instruction
stream and the DMA chain processing state.
count.
EXAMPLE


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE

HW_APBH_CH4_SEMA field descriptions (continued)

Field Description
RSVD1

controls.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
SENSE
BURST
READY
LOCK
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
REQ
BURST
KICK
END
27 This bit reflects the current state of the GPMI Sense Signal sent from the APB GPMI Device
SENSE
26 This bit reflects the current state of the GPMI Ready Signal sent from the APB GPMI Device
READY
25 This bit reflects the current state of the DMA Channel Lock for a GPMI Channel.
LOCK
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1


Field Description
STATEMACHINE
DMA transfers.
state
halts.

4.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

command chain item.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
WAIT4ENDCMD
NANDWAIT4READY
IRQONCMPLT
SEMAPHORE
NANDLOCK
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
CMDWORDS address of the GPMI1 control register and incrementing from there. Zero means transfer NO command
words

RSVD1


Field Description

COMMAND
00- NO DMA TRANSFER
01- Write transfers, that is, data sent from the NAND1 (APB PIO Read) to the system memory (AHB
master write).
10- Read transfer
11- SENSE
any DMA transfer.

(HW_APBH_CH5_BAR)


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDRESS

(HW_APBH_CH5_SEMA)
count.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE
RSVD1


controls.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
SENSE
BURST
READY

R
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Field Description
REQ
BURST
KICK
END
SENSE
READY
LOCK
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1
STATEMACHINE
DMA transfers.


Field Description
state
halts.

5.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES


Address: HW_APBH_CH6_CURCMDAR – 8000_4000h base + 3A0h offset = 8000_43A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

Address: HW_APBH_CH6_NXTCMDAR – 8000_4000h base + 3B0h offset = 8000_43B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
CMD_ADDR

command chain item.
Address: HW_APBH_CH6_CMD – 8000_4000h base + 3C0h offset = 8000_43C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HALTONTERMINATE
WAIT4ENDCMD
IRQONCMPLT
SEMAPHORE
CHAIN
R CMDWORDS RSVD1 RSVD0 COMMAND
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
XFER_COUNT device. A value of 0 indicates a 64 Kbytes transfer.
15–12 This field indicates the number of command words to send to the GPMI2 starting with the base PIO
CMDWORDS address of the GPMI2 and increment from there. Zero means transfer NO command words

RSVD1
WAIT4ENDCMD APBX device to the DMA before starting the next DMA command.

RSVD0
3 A value of one indicates that the channel will cause its interrupt status bit to be set upon completion
IRQONCMPLT of the current command, that is, after the DMA transfer is complete.
HW_APBX_CH3_CMDAR to find the next command.

COMMAND
00- NO DMA TRANSFER
01- write transfers, that is, data sent from NAND2(APB PIO Read) to the system memory (AHB master
write).


Field Description
10- read transfer
11- SENSE
any DMA transfer.

(HW_APBH_CH6_BAR)
Address: HW_APBH_CH6_BAR – 8000_4000h base + 3D0h offset = 8000_43D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDRESS

(HW_APBH_CH6_SEMA)
count.
Address: HW_APBH_CH6_SEMA – 8000_4000h base + 3E0h offset = 8000_43E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE
RSVD1

controls.

Address: HW_APBH_CH6_DEBUG1 – 8000_4000h base + 3F0h offset = 8000_43F0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
SENSE
BURST
READY
LOCK
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
REQ
BURST
KICK
END


Field Description
SENSE
READY
LOCK
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1
STATEMACHINE
DMA transfers.


Field Description
state
halts.

6.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

command chain item.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HALTONTERMINATE
WAIT4ENDCMD
IRQONCMPLT
SEMAPHORE
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
XFER_COUNT device. A value of 0 indicates a 64 Kbytes transfer.
CMDWORDS address of the GPMI3 and increment from there. Zero means transfer NO command words


Field Description
RSVD1

RSVD0

COMMAND
00- NO DMA TRANSFER
01- write transfers, that is, data sent from NAND3 (APB PIO Read) to the system memory (AHB
master write).
10- read transfer
11- SENSE
any DMA transfer.

(HW_APBH_CH7_BAR)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDRESS

(HW_APBH_CH7_SEMA)
count.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE
RSVD1


Field Description

controls.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
SENSE
BURST
READY
LOCK
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
REQ
BURST
KICK
END
SENSE
READY
LOCK
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1


Field Description
STATEMACHINE
DMA transfers.
state
halts.

7.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

command chain item.

Address: HW_APBH_CH8_CMD – 8000_4000h base + 4A0h offset = 8000_44A0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
WAIT4ENDCMD
NANDWAIT4READY
IRQONCMPLT
SEMAPHORE
NANDLOCK
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
XFER_COUNT device HW_GPMI_DATA register. A value of 0 indicates a 64 Kbytes transfer.
CMDWORDS address of the GPMI4 (HW_GPMI_CTRL0) and increment from there. Zero means transfer NO
command words

RSVD1


Field Description

COMMAND
00- NO DMA TRANSFER
01- Write transfers, that is, data sent from NAND4 (APB PIO Read) to the system memory (AHB
master write).
10- Read transfer
11- SENSE
any DMA transfer.

(HW_APBH_CH8_BAR)

Address: HW_APBH_CH8_BAR – 8000_4000h base + 4B0h offset = 8000_44B0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDRESS

(HW_APBH_CH8_SEMA)
count.
Address: HW_APBH_CH8_SEMA – 8000_4000h base + 4C0h offset = 8000_44C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE
RSVD1


controls.
Address: HW_APBH_CH8_DEBUG1 – 8000_4000h base + 4D0h offset = 8000_44D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
SENSE
BURST
READY

R
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Field Description
REQ
BURST
KICK
END
SENSE
READY
LOCK
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1
STATEMACHINE
DMA transfers.


Field Description
state
halts.

8.
Address: HW_APBH_CH8_DEBUG2 – 8000_4000h base + 4E0h offset = 8000_44E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES


Address: HW_APBH_CH9_CURCMDAR – 8000_4000h base + 4F0h offset = 8000_44F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Pointer to command structure currently being processed for Channel 9.
CMD_ADDR

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
31–0 Pointer to next command structure for Channel 9.
CMD_ADDR

command chain item.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HALTONTERMINATE
WAIT4ENDCMD
NANDWAIT4READY
IRQONCMPLT
SEMAPHORE
NANDLOCK
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
command words

RSVD1


Field Description
COMMAND
00- NO DMA TRANSFER
master write).
10- Read transfer
11- SENSE
any DMA transfer.

(HW_APBH_CH9_BAR)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDRESS


(HW_APBH_CH9_SEMA)
count.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE
RSVD1

controls.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
SENSE
BURST
READY
LOCK
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
REQ
BURST
KICK
END


Field Description
SENSE
READY
LOCK
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1
STATEMACHINE
DMA transfers.


Field Description
state
halts.

9.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES
6.5.78 APBH DMA channel 10 Current Command Address Register

APBH DMA channel 10 is controlled by a variable sized command structure. This register


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR
6.5.79 APBH DMA channel 10 Next Command Address Register

The APBH DMA channel 10 next command address register points to the next multiword
APBH DMA channel 10 is controlled by a variable sized command structure. Software
loads this register with the address of the first command structure to process and increments
the channel 10 semaphore to start processing. This register points to the next command
structure to be executed when the current command is completed.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR
6.5.80 APBH DMA channel 10 Command Register

(HW_APBH_CH10_CMD)
The APBH DMA channel 10 command register specifies the cycle to perform for the current
command chain item.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HALTONTERMINATE
WAIT4ENDCMD
NANDWAIT4READY
IRQONCMPLT
SEMAPHORE
NANDLOCK
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
command words


Field Description
RSVD1

COMMAND
00- NO DMA TRANSFER
master write).
10- Read transfer
11- SENSE
any DMA transfer.

6.5.81 APBH DMA channel 10 Buffer Address Register

(HW_APBH_CH10_BAR)
The APBH DMA channel 10 buffer address register contains a pointer to the data buffer
for the transfer. For immediate forms, the data is taken from this register. This is a byte
address which means transfers can start on any byte boundary.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDRESS
6.5.82 APBH DMA channel 10 Semaphore Register

(HW_APBH_CH10_SEMA)
The APBH DMA channel 10 semaphore register is used to synchronize between the CPU
count.
Address: HW_APBH_CH10_SEMA – 8000_4000h base + 5A0h offset = 8000_45A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
RSVD2
PHORE
RSVD1
6.5.83 AHB to APBH DMA channel 10 Debug Information

This register gives debug visibility into the APBH DMA channel 10 state machine and
controls.
This register allows debug visibility of the APBH DMA channel 10.
Address: HW_APBH_CH10_DEBUG1 – 8000_4000h base + 5B0h offset = 8000_
45B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
SENSE
BURST
READY
LOCK
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
REQ
BURST
KICK
END
SENSE
READY
LOCK
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1


Field Description
4–0 PIO Display of the DMA channel 10 state machine state.
STATEMACHINE
DMA transfers.
state
halts.

This register gives debug visibility for the APB and AHB byte counts for DMA channel
10.

Address: HW_APBH_CH10_DEBUG2 – 8000_4000h base + 5C0h offset = 8000_45C0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES

Address: HW_APBH_CH11_CURCMDAR – 8000_4000h base + 5D0h offset = 8000_45D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR


APBH DMA Channel 11 is controlled by a variable sized command structure. Software

the Channel 11 semaphore to start processing. This register points to the next command
Address: HW_APBH_CH11_NXTCMDAR – 8000_4000h base + 5E0h offset = 8000_45E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR
6.5.87 APBH DMA Channel 11 Command Register

(HW_APBH_CH11_CMD)
command chain item.

Address: HW_APBH_CH11_CMD – 8000_4000h base + 5F0h offset = 8000_45F0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
WAIT4ENDCMD
NANDWAIT4READY
IRQONCMPLT
SEMAPHORE
NANDLOCK
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
command words

RSVD1


Field Description

COMMAND
00- NO DMA TRANSFER
master write).
10- Read transfer
11- SENSE
any DMA transfer.

(HW_APBH_CH11_BAR)
The APBH DMA Channel 11 buffer address register contains a pointer to the data buffer


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDRESS

(HW_APBH_CH11_SEMA)
count.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE
RSVD1


controls.
Address: HW_APBH_CH11_DEBUG1 – 8000_4000h base + 620h offset = 8000_
4620h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
SENSE
BURST
READY
LOCK
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Field Description
REQ
BURST
KICK
END
SENSE
READY
LOCK
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1
STATEMACHINE
DMA transfers.


Field Description
state
halts.

11.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES


APBH DMA channel 12 is controlled by a variable sized command structure. This register
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

APBH DMA channel 12 is controlled by a variable sized command structure. Software
the channel 12 semaphore to start processing. This register points to the next command
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
CMD_ADDR

(HW_APBH_CH12_CMD)
command chain item.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HALTONTERMINATE
WAIT4ENDCMD
NANDWAIT4READY
IRQONCMPLT
SEMAPHORE
NANDLOCK
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
31–16 This field indicates the number of bytes to transfer to or from the appropriate PIO register in the
XFER_COUNT HSADC device HW_HSADC_FIFO_DATA register. A value of 0 indicates a 64 Kbytes transfer.
15–12 This field indicates the number of command words to send to the HSADC, starting with the base PIO
CMDWORDS address of the HSADC (HW_HSADC_CTRL0) and increment from there. Zero means transfer NO
command words

RSVD1
NANDLOCK other NAND DMA channels. It is ignored for non-NAND DMA channels..


Field Description
COMMAND
00- NO DMA TRANSFER
01- Write transfers, that is, data sent from HSADC (APB PIO Read) to the system memory (AHB
master write).
10- Read transfer
11- SENSE
any DMA transfer.

(HW_APBH_CH12_BAR)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDRESS


(HW_APBH_CH12_SEMA)
count.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE
RSVD1

controls.


4690h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
SENSE
BURST
READY
LOCK
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
REQ
BURST
KICK
END


Field Description
SENSE
READY
LOCK
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1
STATEMACHINE
DMA transfers.


Field Description
state
halts.

12.
Address: HW_APBH_CH12_DEBUG2 – 8000_4000h base + 6A0h offset = 8000_46A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES


Address: HW_APBH_CH13_CURCMDAR – 8000_4000h base + 6B0h offset = 8000_46B0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

APBH DMA Channel 13 is controlled by a variable sized command structure. Software
Address: HW_APBH_CH13_NXTCMDAR – 8000_4000h base + 6C0h offset = 8000_46C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR
6.5.101 APBH DMA Channel 13 Command Register

(HW_APBH_CH13_CMD)
command chain item.

Address: HW_APBH_CH13_CMD – 8000_4000h base + 6D0h offset = 8000_46D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HALTONTERMINATE
WAIT4ENDCMD
NANDWAIT4READY
IRQONCMPLT
SEMAPHORE
NANDLOCK
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
31–16 This field indicates the number of bytes to transfer to or from the appropriate PIO register in the LCDIF
XFER_COUNT device HW_LCDIF_DATA register. A value of 0 indicates a 64 Kbytes transfer.
15–12 This field indicates the number of command words to send to the LCDIF, starting with the base PIO
CMDWORDS address of the LCDIF (HW_LCDIF_CTRL) and increment from there. Zero means transfer NO command
words


Field Description
RSVD1

COMMAND
00- NO DMA TRANSFER
01- Write transfers, that is, data sent from LCDIF (APB PIO Read) to the system memory (AHB master
write).
10- Read transfer
11- SENSE
any DMA transfer.


(HW_APBH_CH13_BAR)
The APBH DMA Channel 13 buffer address register contains a pointer to the data buffer
Address: HW_APBH_CH13_BAR – 8000_4000h base + 6E0h offset = 8000_46E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDRESS

(HW_APBH_CH13_SEMA)
count.
Address: HW_APBH_CH13_SEMA – 8000_4000h base + 6F0h offset = 8000_46F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
RSVD2
PHORE
RSVD1

controls.
4700h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
SENSE
BURST
READY
LOCK
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
REQ
BURST
KICK
END
SENSE
READY
LOCK
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1


Field Description
STATEMACHINE
DMA transfers.
state
halts.

13.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES

Because channel 14 is not assigned to any peripheral, this register is of no practical usage
and just reserved for compatibility.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

(HW_APBH_CH14_CMD)
command chain item.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HALTONTERMINATE
WAIT4ENDCMD
NANDWAIT4READY
IRQONCMPLT
SEMAPHORE
NANDLOCK
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
31–16 This field indicates the number of bytes to transfer to or from the appropriate PIO register in assigned
XFER_COUNT peripheral. A value of 0 indicates a 64 Kbytes transfer.
15–12 This field indicates the number of command words to send to assigned peripheral, starting with the
CMDWORDS base PIO address of assigned peripheral and increment from there. Zero means transfer NO command
words

RSVD1


Field Description
COMMAND
00- NO DMA TRANSFER
01- Write transfers, that is, data sent from assigned peripheral (APB PIO Read) to the system memory
(AHB master write).
10- Read transfer
11- SENSE
any DMA transfer.

(HW_APBH_CH14_BAR)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDRESS


(HW_APBH_CH14_SEMA)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE
RSVD1

controls.


4770h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
SENSE
BURST
READY
LOCK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
REQ
BURST
KICK
END


Field Description
27 This bit reflects the current state of the Sense Signal sent from assigned peripheral
SENSE
26 This bit reflects the current state of the Ready Signal sent from assigned peripheral
READY
LOCK
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1
STATEMACHINE
DMA transfers.


Field Description
state
halts.

14.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

Address: HW_APBH_CH15_NXTCMDAR – 8000_4000h base + 7A0h offset = 8000_47A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR


(HW_APBH_CH15_CMD)
command chain item.
Address: HW_APBH_CH15_CMD – 8000_4000h base + 7B0h offset = 8000_47B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HALTONTERMINATE
WAIT4ENDCMD
NANDWAIT4READY
IRQONCMPLT
SEMAPHORE
NANDLOCK
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Field Description
XFER_COUNT peripheral. A value of 0 indicates a 64 Kbytes transfer.
15–12 This field indicates the number of command words to send to assigned peripheral, starting with the
CMDWORDS base PIO address of assigned peripheral and increment from there. Zero means transfer NO command
words

RSVD1

COMMAND
00- NO DMA TRANSFER
01- Write transfers, i.e. data sent from assigned peripheral (APB PIO Read) to the system memory
(AHB master write).
10- Read transfer
11- SENSE
any DMA transfer.


(HW_APBH_CH15_BAR)
Address: HW_APBH_CH15_BAR – 8000_4000h base + 7C0h offset = 8000_47C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDRESS

(HW_APBH_CH15_SEMA)
Address: HW_APBH_CH15_SEMA – 8000_4000h base + 7D0h offset = 8000_47D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2


Field Description
PHORE
RSVD1

controls.
Address: HW_APBH_CH15_DEBUG1 – 8000_4000h base + 7E0h offset = 8000_
47E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
SENSE
BURST
READY
LOCK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
REQ
BURST
KICK
END
27 This bit reflects the current state of Sense Signal sent from assigned peripheral
SENSE
26 This bit reflects the current state of Ready Signal sent from assigned peripheral
READY
LOCK
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1


Field Description
STATEMACHINE
DMA transfers.
state
halts.

15.

Address: HW_APBH_CH15_DEBUG2 – 8000_4000h base + 7F0h offset = 8000_47F0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES
6.5.120 APBH Bridge Version Register (HW_APBH_VERSION)

of the block.
EXAMPLE
if (HW_APBH_VERSION.B.MAJOR != 3)
Error();
Address: HW_APBH_VERSION – 8000_4000h base + 800h offset = 8000_4800h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MAJOR MINOR STEP

W
Re- 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_APBH_VERSION field descriptions

Field Description
MAJOR
MINOR
STEP

Chapter 7
AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA)
7.1 AHB-to-APBX Bridge Overview

The AHB-to-APBX bridge provides the device with an inexpensive peripheral attachment
bus running on the AHB's XCLK. (The X in APBX denotes that the APBX runs on a
crystal-derived clock, as compared to APBH, which is synchronous to HCLK.)
As shown in the following figure, the AHB-to-APBX bridge includes the AHB-to-APB
PIO bridge for a memory-mapped I/O to the APB devices, as well a central DMA facility
for devices on this bus. Each one of the APB peripherals is documented in their own chapters
elsewhere in this document.

AHB-to-APBX Bridge Overview
AHB
AHB Slave AHB Master
AHB-to-APBX DMA
APBX MASTER
AHB-to-APBX Bridge
AUART3 RX I2C0
AUART3 TX I2C1
AUART0 RX
APBX
SPDIF Transmit AUART0 TX
AUART1 RX
SAIF1
SAIF2 AUART1 TX
SAIF1 AUART2 RX
SAIF2 AUART2 TX
Figure 7-1. AHB-to-APBX Bridge DMA Block Diagram
The DMA controller uses the APBX bus to transfer read and write data to and from each
peripheral. There is no separate DMA bus for these devices. Contention between the DMA's
use of the APBX bus and AHB-to-APB bridge functions' use of the APBX is mediated by
an internal arbitration logic. For contention between these two units, the DMA is favored
and the AHB slave will report not ready through its HREADY output until the bridge transfer
completes. The arbiter tracks repeated lockouts and inverts the priority, so that the CPU is
guaranteed every fourth transfer on the APB.

Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA)
7.2 APBX DMA

The DMA supports sixteen channels of DMA services, as shown in the following table.
The shared DMA resource allows each independent channel to follow a simple chained
command list. Command chains are built up using the DMA command structure, as shown
in Figure 7-2.
Table 7-1. APBX DMA Channel Assignments
APBX DMA Channel # USAGE
0 AUART4 RX
1 AUART4 TX
2 SPDIF TX
3 EMPTY
4 SAIF0
5 SAIF1
6 I2C0
7 I2C1
8 AUART0 RX
9 AUART0 TX
10 AUART1 RX
11 AUART1 TX
12 AUART2 RX
13 AUART2 TX
14 AUART3 RX
15 AUART3 TX
A single command structure or channel command word specifies a number of operations

to be performed by the DMA in support of a given device. Thus, the CPU can set up large
units of work, chaining together many DMA channel command words, pass them off to the
DMA and have no further concern for the device until the DMA completion interrupt occurs.
The i.MX28 is designed to have enough intelligence in the DMA and the devices to keep
the interrupt frequency from any device below 1 KHz (arrival intervals longer than 1 ms).

APBX DMA
Thus, a single command structure can issue 32-bit PIO write operations to key registers in
the associated device using the same APB bus and the controls, it uses to write DMA data
bytes to the device. For example, this allows a chain of operations to be issued to the serial
audio interface to send command bytes, address bytes, and data transfers, where the command
and the address structure is completely under software control, but the administration of
that transfer is handled autonomously by the DMA.
Each DMA structure can have from 0 to 15 PIO words appended to it. The #PIOWORDs
field, if non-zero, instructs the DMA engine to copy these words to the APB, beginning at
PADDR = 0x0000 and incrementing its PADDR for each cycle. (Note that for APBX DMA
Channel 8, which is the UART RX channel, the first PIO word in the DMA command is
CTRL0. However, for APBX DMA Channel 9, which is the UART TX, the first PIO word
in a DMA command is CTRL1.)
The DMA master generates only normal read/write transfers to the APBX. It does not
generate set, clear, or toggle SCT transfers.
word 0 NEXTCMDADDR
WAIT4ENDCMD
HALTONTERMINATE
TERMINATEFLUSH
IRQONCMPLT
SEMAPHORE
CMDWORDS
COMMAND
CHAIN
word 1 XFER_COUNT
word 2 BUFFER ADDRESS
word 3-n PIOWORD Value
Figure 7-2. AHB-to-APBX Bridge DMA Channel Command Structure
After any requested PIO words have been transferred to the peripheral, the DMA examines
the two-bit command field in the channel command structure. The following table shows
the four commands implemented by the DMA.
Table 7-2. APBX DMA Commands
DMA
Usage
COMMAND
NO_DMA_XFER. Perform any requested PIO word transfers, but terminate the command before any DMA
00
transfer.
01 DMA_WRITE. Perform any requested PIO word transfers, and then perform a DMA transfer from the peri-
pheral for the specified number of bytes.

DMA
Usage
COMMAND
DMA_READ. Perform any requested PIO word transfers, and then perform a DMA transfer to the peripheral
10
11 Reserved
DMA_WRITE operations copy data bytes to the system memory (on-chip RAM or SDRAM)
from the associated peripheral. Each peripheral has a target PADDR value that it expects
to receive DMA bytes. This association is synthesized in the DMA. The DMA_WRITE
transfer uses the BUFFER_ADDRESS word in the command structure to point to the
beginning byte to write data from the peripheral.
DMA_READ operations copy data bytes to the APB peripheral from the system memory.
The DMA engine contains a shared byte aligner that aligns bytes from system memory to
or from the peripherals. Peripherals always assume little-endian-aligned data arrives or
departs on their 32-bit APB. The DMA_READ transfer uses the BUFFER_ADDRESS
word in the command structure to point to the DMA data buffer to be read by the
DMA_READ command.
The NO_DMA_XFER command is used to write PIO words to a device without performing
any DMA data byte transfers.
As each DMA command completes, it triggers the DMA to load the next DMA command
structure in the chain. The normal flow list of DMA commands is found by following the
NEXTCMD_ADDR pointer in the DMA command structure. If the wait-for-end-command
bit (WAIT4ENDCMD) is set in a command structure, then the DMA channel waits for the
device to signal completion of a command by toggling the apx_endcmcd signal before
proceeding to load and execute the next command structure. Then, if
DECREMENT_SEMAPHORE is set, the semaphore is decremented after the end command
is seen.
A detailed bit-field view of the DMA command structure is shown in the following table,
which shows a field that specifies the number of bytes to be transferred by this DMA
command. The transfer count mechanism is duplicated in the associated peripheral, either
as an implied or as a specified count in the peripheral.
Table 7-3. DMA Channel Command Word in System Memory
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

APBX DMA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
DECREMENT SEMAPHORE
HALTONTERMINATE
TERMINATEFLUSH
WAIT4ENDCMD
IRQ_FINISH
COMMAND
Reserved
Number PIO
CHAIN
Number DMA Bytes to Transfer Words to
Write
DMA Buffer or Alternate CCW
Zero or More PIO Words to Write to the Associated Peripheral Starting at its Base Address on the APBX Bus
Figure 7-3 shows the CHAIN bit in bit 2 of the second word of the command structure. This
bit is set to 1, if the NEXT_COMMAND_ADDRESS contains a pointer to another DMA
command structure. If a null pointer (0) is loaded into the NEXT_COMMAND_ADDRESS,
it will not be detected by the DMA hardware. Only the CHAIN bit indicates whether a valid
list exists beyond the current structure.
If the IRQ_COMPLETE bit is set in the command structure, then the last act of the DMA
before loading the next command is to set the interrupt status bit corresponding to the current
channel. The sticky interrupt request bit in the DMA CSR remains set until cleared by the
software. It can be used to interrupt the CPU.
Each channel has an eight-bit counting semaphore that controls whether it is in the run or
idle state. When the semaphore is non-zero, the channel is ready to run and process
commands and DMA transfers. Whenever a command finishes its DMA transfer, it checks
the DECREMENT_SEMAPHORE bit. If set, it decrements the counting semaphore. If the
semaphore goes to 0 as a result, then the channel enters the IDLE state and remains there
until the semaphore is incremented by software. When the semaphore goes to non-zero and
the channel is in its IDLE state, then it uses the value in the HW_APBX_CHn_NXTCMDAR
(next command address register) to fetch a pointer to the next command to process. NOTE:
this is a double indirect case. This method allows software to append to a running command
list under the protection of the counting semaphore.
Receiving an IRQ for HALTONTERMINATE (HOT) is a new feature in the APBH/X
DMA descriptor that allows certain peripheral block (for example, GPMI, SSP, I2C) to
signal to the DMA engine that an error has occurred. In prior chips, if a block stalled due
to an error, the only practical way to discover this in software was through a timer of some
sort, or to poll the block. Now, an HOT signal is sent from the peripheral to the DMA engine
and causes an IRQ after terminating the DMA descriptor being executed. Note not all
peripheral block support this termination feature.

Under a normal operation mode, when termination occurs, DMA would stop the current
descriptor and discard any data remaining in the FIFO. By setting TERMINATEFLUSH
bit in the descriptor command word, DMA will flush out all the remainder data in the FIFO
to system memory for write DMA operation before issue HOT IRQ.
Therefore, it is recommended that software use this signal as follows:
• Always set HALTONTERMINATE to 1 in a DMA descriptor. That way, if a peripheral
signals HOT, the transfer will end, leaving the peripheral block and the DMA engine
synchronized (but at the end of a command).
• When an IRQ from an APBH/X channel is received, and the IRQ is determined to be
due to an error (as opposed to an IRQONCOMPLETE interrupt) the software should:
1. Reset the channel.

2. Determine the error from error reporting in the peripheral block, then manage the error
in the peripheral that is attached to that channel in whatever appropriate way exists for
that device (software recovery, device reset, block reset, and so on).
To start processing the first time, software creates the command list to be processed. It
writes the address of the first command into the HW_APBX_CHn_NXTCMDAR register,
and then writes a 1 to the counting semaphore in HW_APBX_CHn_SEMA. The DMA
channel loads HW_APBX_CHn_CURCMDAR register and then enters the normal state
machine processing for the next command. When the software writes a value to the counting
semaphore, it is added to the semaphore count by hardware, protecting the case where both
hardware and software are trying to change the semaphore on the same clock edge.
Software can examine the value of HW_APBX_CHn_CURCMDAR at any time to determine
the location of the command structure that is currently being processed.
7.3 DMA Chain Example

The example in the following figure shows how to bring the basic items together to make
a simple DMA chain to read PCM samples and send them out the Audio Output (DAC)
using one DMA channel. This example shows three command structures linked together
using their normal command list pointers. The first command writes a single PIO word to
the HW_AUDIOOUT_CTRL0 register with a new word count for the DAC. This first
command also performs a 512 byte DMA_READ operation to read the data block bytes
into the DAC. A second and a third DMA command structure also performs a DMA_READ
operation to handle circular buffer style outputs. The completion of each command structure
generates an interrupt request. In addition, each command structure decrements the

DMA Chain Example
semaphore. If the decompression software has not provided a buffer in a timely fashion,
then the DMA will stall. Without the decrement semaphore interlocking, then the DMA
will continue to output a stream of samples. In this mode, it is up to software to use the
interrupts to synchronize outputs so that underruns do not occur.
1 PIO, IRQ, DecSema 1 PIO,IRQ, DecSema,

chaining, DMA read chaining, DMA read
NEXTCMD_ADDR NEXTCMD_ADDR
512=0x200 0x104E 512=0x200 0x104E
HW_AUDIOOUT_CTRL0 HW_AUDIOOUT_CTRL0
1 PIO, IRQ,
DecSema,
chaining, DMA read
NEXTCMD_ADDR
512=0x200 0x104E 512-Byte
Data
BUFFER ADDRESS Block
512-Byte
Data HW_AUDIOOUT_CTRL0 (64 PCM
Block stereo
(64 PCM samples)
stereo 512-Byte (1.33 ms @
samples) Data 48 kHz)
(1.33 ms @ Block
48 kHz) (64 PCM
stereo
samples) Pointer to next ccw
(1.33 ms @
Pointer to DMA buffer
48 kHz)
Figure 7-3. AHB-to-APBX Bridge DMA AUDIOOUT (DAC) Example Command Chain
Note that each word of the three-word DMA command structure corresponds to a PIO
register of the DMA that is accessible on the APBX bus. Normally, the DMA copies the
next command structure onto these registers for processing at the start of each command
by following the value of the pointer previously loaded into the NEXTCMD_ADDR register.
To start DMA processing, for the first command, one must initialize the PIO registers of
the desired channel. First load the next command address register with a pointer to the first
command to be loaded. Then, write a one to the counting semaphore register. This causes
the DMA to schedule the targeted channel for DMA command structure load, as if it just
finished its previous command.


CLKGATE bit fields.

APBX Hardware Register Format Summary
HW_APBX memory map
Absolute
Width Section/
(in bits) page
(hex)
8002_4000 AHB to APBX Bridge Control Register 0 (HW_APBX_CTRL0) 32 R/W C000_0000h 7.5.1/511
8002_4010 AHB to APBX Bridge Control Register 1 (HW_APBX_CTRL1) 32 R/W 0000_0000h 7.5.2/511
8002_4020 AHB to APBX Bridge Control and Status Register 2 32 R/W 0000_0000h 7.5.3/515
(HW_APBX_CTRL2)
8002_4030 AHB to APBX Bridge Channel Register 32 R/W 0000_0000h 7.5.4/519
(HW_APBX_CHANNEL_CTRL)
8002_4040 AHB to APBX DMA Device Assignment Register 32 R 0000_0000h 7.5.5/521
(HW_APBX_DEVSEL)
8002_4100 APBX DMA Channel 0 Current Command Address Register 32 R 0000_0000h 7.5.6/522
(HW_APBX_CH0_CURCMDAR)
8002_4110 APBX DMA Channel 0 Next Command Address Register 32 R/W 0000_0000h 7.5.7/523
(HW_APBX_CH0_NXTCMDAR)
8002_4120 APBX DMA Channel 0 Command Register 32 R 0000_0000h 7.5.8/523
(HW_APBX_CH0_CMD)
8002_4130 APBX DMA Channel 0 Buffer Address Register 32 R 0000_0000h 7.5.9/525
(HW_APBX_CH0_BAR)
8002_4140 APBX DMA Channel 0 Semaphore Register 32 R/W 0000_0000h 7.5.10/526
(HW_APBX_CH0_SEMA)
8002_4150 AHB to APBX DMA Channel 0 Debug Information 32 R 00A0_0000h 7.5.11/527
(HW_APBX_CH0_DEBUG1)
8002_4160 AHB to APBX DMA Channel 0 Debug Information 32 R 0000_0000h 7.5.12/529
(HW_APBX_CH1_CMD)

HW_APBX memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
8002_41A0 APBX DMA Channel 1 Buffer Address Register 32 R 0000_0000h 7.5.16/533
(HW_APBX_CH1_BAR)
8002_41B0 APBX DMA Channel 1 Semaphore Register 32 R/W 0000_0000h 7.5.17/534
(HW_APBX_CH1_SEMA)
8002_41C0 AHB to APBX DMA Channel 1 Debug Information 32 R 00A0_0000h 7.5.18/535
8002_41D0 AHB to APBX DMA Channel 1 Debug Information 32 R 0000_0000h 7.5.19/537
8002_41E0 APBX DMA Channel 2 Current Command Address Register 32 R 0000_0000h 7.5.20/537
8002_41F0 APBX DMA Channel 2 Next Command Address Register 32 R/W 0000_0000h 7.5.21/538
(HW_APBX_CH2_CMD)
(HW_APBX_CH2_BAR)
(HW_APBX_CH2_SEMA)
(HW_APBX_CH3_CMD)
(HW_APBX_CH3_BAR)
(HW_APBX_CH3_SEMA)
8002_42A0 AHB to APBX DMA Channel 3 Debug Information 32 R 0000_0000h 7.5.32/548
8002_42B0 AHB to APBX DMA Channel 3 Debug Information 32 R 0000_0000h 7.5.33/551
8002_42C0 APBX DMA Channel 4 Current Command Address Register 32 R 0000_0000h 7.5.34/551
8002_42D0 APBX DMA Channel 4 Next Command Address Register 32 R/W 0000_0000h 7.5.35/552
8002_42E0 APBX DMA Channel 4 Command Register 32 R 0000_0000h 7.5.36/552
(HW_APBX_CH4_CMD)


Absolute
Width Section/
(in bits) page
(hex)
8002_42F0 APBX DMA Channel 4 Buffer Address Register 32 R 0000_0000h 7.5.37/554
(HW_APBX_CH4_BAR)
(HW_APBX_CH4_SEMA)
(HW_APBX_CH5_CMD)
(HW_APBX_CH5_BAR)
(HW_APBX_CH5_SEMA)
8002_43A0 APBX DMA Channel 6 Current Command Address Register 32 R 0000_0000h 7.5.48/565
8002_43B0 APBX DMA Channel 6 Next Command Address Register 32 R/W 0000_0000h 7.5.49/566
8002_43C0 APBX DMA Channel 6 Command Register 32 R 0000_0000h 7.5.50/566
(HW_APBX_CH6_CMD)
8002_43D0 APBX DMA Channel 6 Buffer Address Register 32 R 0000_0000h 7.5.51/568
(HW_APBX_CH6_BAR)
8002_43E0 APBX DMA Channel 6 Semaphore Register 32 R/W 0000_0000h 7.5.52/569
(HW_APBX_CH6_SEMA)
8002_43F0 AHB to APBX DMA Channel 6 Debug Information 32 R 00A0_0000h 7.5.53/570
(HW_APBX_CH7_CMD)


Absolute
Width Section/
(in bits) page
(hex)
(HW_APBX_CH7_BAR)
(HW_APBX_CH7_SEMA)
8002_44A0 APBX DMA Channel 8 Command Register 32 R 0000_0000h 7.5.64/581
(HW_APBX_CH8_CMD)
8002_44B0 APBX DMA Channel 8 Buffer Address Register 32 R 0000_0000h 7.5.65/583
(HW_APBX_CH8_BAR)
8002_44C0 APBX DMA Channel 8 Semaphore Register 32 R/W 0000_0000h 7.5.66/584
(HW_APBX_CH8_SEMA)
8002_44D0 AHB to APBX DMA Channel 8 Debug Information 32 R 00A0_0000h 7.5.67/584
8002_44E0 AHB to APBX DMA Channel 8 Debug Information 32 R 0000_0000h 7.5.68/587
8002_44F0 APBX DMA Channel 9 Current Command Address Register 32 R 0000_0000h 7.5.69/587
(HW_APBX_CH9_CMD)
(HW_APBX_CH9_BAR)
(HW_APBX_CH9_SEMA)
(HW_APBX_CH10_CMD)


Absolute
Width Section/
(in bits) page
(hex)
(HW_APBX_CH10_BAR)
8002_45A0 APBX DMA Channel 10 Semaphore Register 32 R/W 0000_0000h 7.5.80/598
(HW_APBX_CH10_SEMA)
8002_45B0 AHB to APBX DMA Channel 10 Debug Information 32 R 00A0_0000h 7.5.81/599
8002_45C0 AHB to APBX DMA Channel 10 Debug Information 32 R 0000_0000h 7.5.82/601
8002_45D0 APBX DMA Channel 11 Current Command Address Register 32 R 0000_0000h 7.5.83/602
8002_45E0 APBX DMA Channel 11 Next Command Address Register 32 R/W 0000_0000h 7.5.84/602
8002_45F0 APBX DMA Channel 11 Command Register 32 R 0000_0000h 7.5.85/603
(HW_APBX_CH11_CMD)
(HW_APBX_CH11_BAR)
(HW_APBX_CH11_SEMA)
(HW_APBX_CH12_CMD)
(HW_APBX_CH12_BAR)
(HW_APBX_CH12_SEMA)
8002_46A0 AHB to APBX DMA Channel 12 Debug Information 32 R 0000_0000h 7.5.96/616
8002_46B0 APBX DMA Channel 13 Current Command Address Register 32 R 0000_0000h 7.5.97/616
8002_46C0 APBX DMA Channel 13 Next Command Address Register 32 R/W 0000_0000h 7.5.98/617
8002_46D0 APBX DMA Channel 13 Command Register 32 R 0000_0000h 7.5.99/617
(HW_APBX_CH13_CMD)


Absolute
Width Section/
(in bits) page
(hex)
8002_46E0 APBX DMA Channel 13 Buffer Address Register 32 R 0000_0000h 7.5.100/619
(HW_APBX_CH13_BAR)
8002_46F0 APBX DMA Channel 13 Semaphore Register 32 R/W 0000_0000h 7.5.101/620
(HW_APBX_CH13_SEMA)
(HW_APBX_CH14_CMD)
(HW_APBX_CH14_BAR)
(HW_APBX_CH14_SEMA)
8002_47A0 APBX DMA Channel 15 Next Command Address Register 32 R/W 0000_0000h 7.5.112/631
8002_47B0 APBX DMA Channel 15 Command Register 32 R 0000_0000h 7.5.113/631
(HW_APBX_CH15_CMD)
8002_47C0 APBX DMA Channel 15 Buffer Address Register 32 R 0000_0000h 7.5.114/633
(HW_APBX_CH15_BAR)
8002_47D0 APBX DMA Channel 15 Semaphore Register 32 R/W 0000_0000h 7.5.115/634
(HW_APBX_CH15_SEMA)
8002_47E0 AHB to APBX DMA Channel 15 Debug Information 32 R 00A0_0000h 7.5.116/634
8002_47F0 AHB to APBX DMA Channel 15 Debug Information 32 R 0000_0000h 7.5.117/637
8002_4800 APBX Bridge Version Register (HW_APBX_VERSION) 32 R 0202_0000h 7.5.118/637

7.5.1 AHB to APBX Bridge Control Register 0 (HW_APBX_CTRL0)

The APBX CTRL 0 provides overall control and IRQ status of the AHB to APBX bridge
and DMA.
HW_APBX_CTRL0: 0x000
HW_APBX_CTRL0_SET: 0x004
HW_APBX_CTRL0_CLR: 0x008
HW_APBX_CTRL0_TOG: 0x00C
This register contains softreset, clock gating bits.
Address: HW_APBX_CTRL0 – 8002_4000h base + 0h offset = 8002_4000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD0[29:16]
CLKGATE
SFTRST
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD0[15:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_APBX_CTRL0 field descriptions

Field Description
31 Set this bit to zero to enable normal APBX DMA operation. Set this bit to one (default) to disable clocking
SFTRST with the APBX DMA and hold it in its reset (lowest power) state. This bit can be turned on and then off to
reset the APBX DMA block to its default state.
CLKGATE
RSVD0
7.5.2 AHB to APBX Bridge Control Register 1 (HW_APBX_CTRL1)

The APBX CTRL 1 provides channel complete IRQ status of the AHB to APBX bridge
and DMA.

This register contains the per channel interrupt status bits. Each channel has a dedicated
interrupt vector in the vectored interrupt controller.
EXAMPLE
BF_WR(APBX_CTRL1, CH5_CMDCMPLT_IRQ, 0); // use bitfield write macro

BF_APBX_CTRL1.CH5_CMDCMPLT_IRQ = 0; // or, assign to register struct's bitfield

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH15_CMDCMPLT_
CH14_CMDCMPLT_
CH13_CMDCMPLT_
CH12_CMDCMPLT_
CH11_CMDCMPLT_
CH10_CMDCMPLT_
CH9_CMDCMPLT_
CH8_CMDCMPLT_
CH7_CMDCMPLT_
CH6_CMDCMPLT_
CH5_CMDCMPLT_
CH4_CMDCMPLT_
CH3_CMDCMPLT_
CH2_CMDCMPLT_
CH1_CMDCMPLT_
CH0_CMDCMPLT_
R
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH15_CMDCMPLT_
CH14_CMDCMPLT_
CH13_CMDCMPLT_
CH12_CMDCMPLT_
CH11_CMDCMPLT_
CH10_CMDCMPLT_
CH9_CMDCMPLT_
CH8_CMDCMPLT_
CH7_CMDCMPLT_
CH6_CMDCMPLT_
CH5_CMDCMPLT_
CH4_CMDCMPLT_
CH3_CMDCMPLT_
CH2_CMDCMPLT_
CH1_CMDCMPLT_
CH0_CMDCMPLT_
R
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
31 Setting this bit enables the generation of an interrupt request for APBX DMA Channel 15.
CH15_
CMDCMPLT_
IRQ_EN
CH14_
CMDCMPLT_
IRQ_EN
CH13_
CMDCMPLT_
IRQ_EN

HW_APBX_CTRL1 field descriptions (continued)

Field Description
CH12_
CMDCMPLT_
IRQ_EN
CH11_
CMDCMPLT_
IRQ_EN
CH10_
CMDCMPLT_
IRQ_EN
CH9_
CMDCMPLT_
IRQ_EN
CH8_
CMDCMPLT_
IRQ_EN
CH7_
CMDCMPLT_
IRQ_EN
CH6_
CMDCMPLT_
IRQ_EN
CH5_
CMDCMPLT_
IRQ_EN
CH4_
CMDCMPLT_
IRQ_EN
CH3_
CMDCMPLT_
IRQ_EN
CH2_
CMDCMPLT_
IRQ_EN
CH1_
CMDCMPLT_
IRQ_EN


Field Description
CH0_
CMDCMPLT_
IRQ_EN
15 Interrupt request status bit for APBX DMA Channel 15. This sticky bit is set by DMA hardware and reset by
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ


Field Description
CMDCMPLT_IRQ
CMDCMPLT_IRQ
7.5.3 AHB to APBX Bridge Control and Status Register 2

(HW_APBX_CTRL2)
The APBX CTRL 2 provides channel error interrupts generated by the AHB to APBX
DMA.
This register contains the per channel bus error interrupt status bits and the per channel
completion interrupt enable bits. Each channel has a dedicated interrupt vector in the vectored
interrupt controller.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERROR_
ERROR_
ERROR_
ERROR_
ERROR_
ERROR_
ERROR_
ERROR_
ERROR_
ERROR_
ERROR_
ERROR_
ERROR_
ERROR_
ERROR_
ERROR_
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
CH15_
CH14_
CH13_
CH12_
CH11_
CH10_
CH9_
CH8_
CH7_
CH6_
CH5_
CH4_
CH3_
CH2_
CH1_
CH0_
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH15_ERROR_IRQ
CH14_ERROR_IRQ
CH13_ERROR_IRQ
CH12_ERROR_IRQ
CH11_ERROR_IRQ
CH10_ERROR_IRQ
CH9_ERROR_IRQ
CH8_ERROR_IRQ
CH7_ERROR_IRQ
CH6_ERROR_IRQ
CH5_ERROR_IRQ
CH4_ERROR_IRQ
CH3_ERROR_IRQ
CH2_ERROR_IRQ
CH1_ERROR_IRQ
CH0_ERROR_IRQ
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
CH15_ERROR_
1 - AHB bus error
STATUS
CH14_ERROR_
1 - AHB bus error
STATUS
CH13_ERROR_
1 - AHB bus error
STATUS
CH12_ERROR_
1 - AHB bus error
STATUS
CH11_ERROR_
1 - AHB bus error
STATUS
CH10_ERROR_
1 - AHB bus error
STATUS


Field Description
CH9_ERROR_
1 - AHB bus error
STATUS
CH8_ERROR_
1 - AHB bus error
STATUS
CH7_ERROR_
1 - AHB bus error
STATUS
CH6_ERROR_
1 - AHB bus error
STATUS
CH5_ERROR_
1 - AHB bus error
STATUS
CH4_ERROR_
1 - AHB bus error
STATUS
CH3_ERROR_
1 - AHB bus error
STATUS
CH2_ERROR_
1 - AHB bus error
STATUS


Field Description
CH1_ERROR_
1 - AHB bus error
STATUS
CH0_ERROR_
1 - AHB bus error
STATUS
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ


Field Description
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
7.5.4 AHB to APBX Bridge Channel Register

(HW_APBX_CHANNEL_CTRL)
The APBX CHANNEL CTRL provides reset/freeze control of each DMA channel.
HW_APBX_CHANNEL_CTRL: 0x030
HW_APBX_CHANNEL_CTRL_SET: 0x034
HW_APBX_CHANNEL_CTRL_CLR: 0x038
HW_APBX_CHANNEL_CTRL_TOG: 0x03C
This register contains individual channel reset/freeze bits.
Address: HW_APBX_CHANNEL_CTRL – 8002_4000h base + 30h offset = 8002_4030h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RESET_CHANNEL FREEZE_CHANNEL
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

HW_APBX_CHANNEL_CTRL field descriptions

Field Description
31–16 Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state.
RESET_ The bit is reset after the channel resources are cleared.
CHANNEL
0x0001 UART4_RX —
0x0002 UART4_TX —
0x0004 SPDIF_TX —
0x0010 SAIF0 —
0x0020 SAIF1 —
0x0040 I2C0 —
0x0080 I2C1 —
0x0100 UART0_RX —
0x0200 UART0_TX —
0x0400 UART1_RX —
0x0800 UART1_TX —
0x1000 UART2_RX —
0x2000 UART2_TX —
0x4000 UART3_RX —
0x8000 UART3_TX —
15–0 Setting a bit in this field will freeze the DMA channel associated with it. This field is a direct input to the DMA
FREEZE_ channel arbiter. When frozen, the channel is deined access to the central DMA resources. Note: 1. DMA
CHANNEL PIO write to associated peripheral is not supported when Freeze bit is to set, and use ARM instead to
configure peripheral. 2. After FREEZE bit is set, no more access, neither AHB access to memory nor APB
access to peripherals, will be allowed by arbiter. But, there might be on-going channel access exactly when
FREEZE bit is set, either INCR8/INCR4/SINGLE AHB access or APB peripheral access, this on-going access
will not be affected by FREEZE bit and will finish as normal. That is to say, setting FREEZE bit might not
freeze channel access immediately, it only freezes further channel access, and you have to wait a while to
freeze channel access completely. To make sure that there is no more access from freezed channel, channel
state machine should be checked by reading channel DEBUG1 register, wait till state stunk at any of IDLE,
READ_REQ, WRITE, or CHAIN_WAIT.
0x0001 UART4_RX —
0x0002 UART4_TX —
0x0004 SPDIF_TX —
0x0010 SAIF0 —
0x0020 SAIF1 —
0x0040 I2C0 —
0x0080 I2C1 —
0x0100 UART0_RX —
0x0200 UART0_TX —
0x0400 UART1_RX —
0x0800 UART1_TX —
0x1000 UART2_RX —
0x2000 UART2_TX —
0x4000 UART3_RX —
0x8000 UART3_TX —

7.5.5 AHB to APBX DMA Device Assignment Register

(HW_APBX_DEVSEL)
This register allows reassignment of the APBX device connected to the DMA Channels.
HW_APBX_DEVSEL: 0x040
HW_APBX_DEVSEL_SET: 0x044
HW_APBX_DEVSEL_CLR: 0x048
HW_APBX_DEVSEL_TOG: 0x04C
In this chip, apbxdma channel resource is enough for peripherals, so this register is of no
use and reserved.
Address: HW_APBX_DEVSEL – 8002_4000h base + 40h offset = 8002_4040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_APBX_DEVSEL field descriptions

Field Description
31–30 Reserved.
CH15
29–28 Reserved.
CH14
27–26 Reserved.
CH13
25–24 Reserved.
CH12
23–22 Reserved.
CH11
21–20 Reserved.
CH10
19–18 Reserved.
CH9
17–16 Reserved.
CH8
15–14 Reserved.
CH7
13–12 Reserved.
CH6

HW_APBX_DEVSEL field descriptions (continued)

Field Description
11–10 Reserved.
CH5
9–8 Reserved.
CH4
7–6 Reserved.
CH3
5–4 Reserved.
CH2
3–2 Reserved.
CH1
1–0 Reserved.
CH0
7.5.6 APBX DMA Channel 0 Current Command Address Register

The APBX DMA Channel 0 current command address register points to the multiword
APBX DMA Channel 0 is controlled by a variable sized command structure. This register
EXAMPLE
pCurCmd = (hw_apbx_chn_cmd_t *) HW_APBX_CHn_CURCMDAR_RD(0); // read the whole

pCurCmd = (hw_apbx_chn_cmd_t *) BF_RDn(APBX_CHn_CURCMDAR, 0, CMD_ADDR); // or, use
pCurCmd = (hw_apbx_chn_cmd_t *) HW_APBX_CHn_CURCMDAR(0).CMD_ADDR; // or, assign from
Address: HW_APBX_CH0_CURCMDAR – 8002_4000h base + 100h offset = 8002_4100h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_APBX_CH0_CURCMDAR field descriptions

Field Description
CMD_ADDR

7.5.7 APBX DMA Channel 0 Next Command Address Register

The APBX DMA Channel 0 next command address register points to the next multiword
APBX DMA Channel 0 is controlled by a variable sized command structure. Software loads
EXAMPLE
HW_APBX_CHn_NXTCMDAR_WR(0, (reg32_t) pCommandTwoStructure); // write the entire register,

BF_WRn(APBX_CHn_NXTCMDAR, 0, (reg32_t) pCommandTwoStructure); // or, use multi-register
HW_APBX_CHn_NXTCMDAR(0).CMD_ADDR = (reg32_t) pCommandTwoStructure; // or, assign to bitfield
Address: HW_APBX_CH0_NXTCMDAR – 8002_4000h base + 110h offset = 8002_4110h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_APBX_CH0_NXTCMDAR field descriptions

Field Description
CMD_ADDR
7.5.8 APBX DMA Channel 0 Command Register (HW_APBX_CH0_CMD)

The APBX DMA Channel 0 command register specifies the DMA transaction to perform
for the current command chain item.

EXAMPLE
hw_apbx_chn_cmd_t dma_cmd;
dma_cmd.XFER_COUNT = 512; // transfer 512 bytes
dma_cmd.COMMAND = BV_APBX_CHn_CMD_COMMAND__DMA_WRITE; // transfer to system memory from
peripheral device
dma_cmd.CHAIN = 1; // chain an additional command structure
on to the list
dma_cmd.IRQONCMPLT = 1; // generate an interrupt on completion
of this command structure
Address: HW_APBX_CH0_CMD – 8002_4000h base + 120h offset = 8002_4120h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEMAPHORE
IRQONCMPLT
WAIT4ENDCMD
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_APBX_CH0_CMD field descriptions

Field Description
31–16 This field indicates the number of bytes to transfer to or from the appropriate PIO register in the UART4
XFER_COUNT device HW_UARTAPP_DATA. A value of 0 indicates a 64 KBytes transfer.
15–12 This field indicates the number of command words to send to the UART, starting with the base PIO address
CMDWORDS of the UART4 (HW_UARTAPP_CTRL0) and increment from there. Zero means transfer NO command
words

HW_APBX_CH0_CMD field descriptions (continued)

Field Description
RSVD1
7 A value of one indicates that the channel will wait for the end of command signal to be sent from the ABPX
WAIT4ENDCMD device to the DMA before starting the next DMA command.
6 A value of one indicates that the channel will decrement its semaphore at the completion of the current
SEMAPHORE command structure. If the semaphore decrements to zero, then this channel stalls until software increments
it again.

RSVD0
3 A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the
IRQONCMPLT current command, i.e. after the DMA transfer is complete.
2 A value of one indicates that another command is chained onto the end of the current command structure.
CHAIN At the completion of the current command, this channel will follow the pointer in HW_APBX_CH0_CMDAR
to find the next command.

COMMAND
00- NO DMA TRANSFER
01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master
write).
10- read transfer
11- reserved
0x0 NO_DMA_XFER — Perform any requested PIO word transfers but terminate command before any
DMA transfer.
0x1 DMA_WRITE — Perform any requested PIO word transfers and then perform a DMA transfer from
the peripheral for the specified number of bytes.
0x2 DMA_READ — Perform any requested PIO word transfers and then perform a DMA transfer to the
peripheral for the specified number of bytes.
7.5.9 APBX DMA Channel 0 Buffer Address Register

(HW_APBX_CH0_BAR)
The APBX DMA Channel 0 buffer address register contains a pointer to the data buffer for
EXAMPLE

hw_apbx_chn_bar_t dma_data;
Address: HW_APBX_CH0_BAR – 8002_4000h base + 130h offset = 8002_4130h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_APBX_CH0_BAR field descriptions

Field Description
ADDRESS
7.5.10 APBX DMA Channel 0 Semaphore Register

(HW_APBX_CH0_SEMA)
The APBX DMA Channel 0 semaphore register is used to synchronize between the CPU
Each DMA channel has an 8 bit counting semaphore used to synchronize between the
program stream and the DMA chain processing. DMA processing continues until the DMA
attempts to decrement a semaphore which has already reached a value of zero. When the
attempt is made, the DMA channel is stalled until software increments the semaphore count.
EXAMPLE
BF_WR(APBX_CHn_SEMA, 0, INCREMENT_SEMA, 2); // increment semaphore by two

current_sema = BF_RD(APBX_CHn_SEMA, 0, PHORE); // get instantaneous value
Address: HW_APBX_CH0_SEMA – 8002_4000h base + 140h offset = 8002_4140h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_APBX_CH0_SEMA field descriptions

Field Description
RSVD2

HW_APBX_CH0_SEMA field descriptions (continued)

Field Description
PHORE
RSVD1
7.5.11 AHB to APBX DMA Channel 0 Debug Information

This register gives debug visibility into the APBX DMA Channel 0 state machine and
controls.
This register allows debug visibility of the APBX DMA Channel 0.
Address: HW_APBX_CH0_DEBUG1 – 8002_4000h base + 150h offset = 8002_4150h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
BURST
R REQ KICK END RSVD2 RSVD1[19:16]
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_APBX_CH0_DEBUG1 field descriptions

Field Description
REQ
BURST
KICK
END
27–25 Reserved
RSVD2
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1
STATEMACHINE

HW_APBX_CH0_DEBUG1 field descriptions (continued)

Field Description
DMA transfers.
halts.

0.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
APB_BYTES
AHB_BYTES

EXAMPLE
pCurCmd = (hw_apbx_chn_cmd_t *) HW_APBX_CHn_CURCMDAR_RD(1); // read the whole

pCurCmd = (hw_apbx_chn_cmd_t *) BF_RDn(APBX_CHn_CURCMDAR, 1, CMD_ADDR); // or, use
pCurCmd = (hw_apbx_chn_cmd_t *) HW_APBX_CHn_CURCMDAR(1).CMD_ADDR; // or, assign from

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR


EXAMPLE
HW_APBX_CHn_NXTCMDAR_WR(1, (reg32_t) pCommandTwoStructure); // write the entire register,

BF_WRn(APBX_CHn_NXTCMDAR, 1, (reg32_t) pCommandTwoStructure); // or, use multi-register
HW_APBX_CHn_NXTCMDAR(1).CMD_ADDR = (reg32_t) pCommandTwoStructure; // or, assign to bitfield

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

The APBX DMA Channel 1 command register specifies the cycle to perform for the current
command chain item.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEMAPHORE
IRQONCMPLT
WAIT4ENDCMD
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
15–12 This field indicates the number of command words to send to the DAC, starting with the base PIO address
words

RSVD1
7 A value of one indicates that the channel will wait for the end of command signal to be sent from the APBX
it again.

RSVD0


Field Description

COMMAND
00- NO DMA TRANSFER
write).
10- read transfer
11- reserved
DMA transfer.

(HW_APBX_CH1_BAR)
EXAMPLE
hw_apbx_chn_bar_t dma_data;
Address: HW_APBX_CH1_BAR – 8002_4000h base + 1A0h offset = 8002_41A0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
ADDRESS

(HW_APBX_CH1_SEMA)
EXAMPLE
BF_WR(APBX_CHn_SEMA, 1, INCREMENT_SEMA, 2); // increment semaphore by two

current_sema = BF_RD(APBX_CHn_SEMA, 1, PHORE); // get instantaneous value
Address: HW_APBX_CH1_SEMA – 8002_4000h base + 1B0h offset = 8002_41B0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE
RSVD1


controls.
Address: HW_APBX_CH1_DEBUG1 – 8002_4000h base + 1C0h offset = 8002_41C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
BURST
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Field Description
REQ
BURST
KICK
END
27–25 Reserved
RSVD2
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1
STATEMACHINE
DMA transfers.


Field Description
halts.

1.
Address: HW_APBX_CH1_DEBUG2 – 8002_4000h base + 1D0h offset = 8002_41D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES


Address: HW_APBX_CH2_CURCMDAR – 8002_4000h base + 1E0h offset = 8002_41E0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

Address: HW_APBX_CH2_NXTCMDAR – 8002_4000h base + 1F0h offset = 8002_41F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

command chain item.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEMAPHORE
IRQONCMPLT
WAIT4ENDCMD
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
31–16 This field indicates the number of bytes to transfer to or from the appropriate PIO register in the SPDIF
15–12 This field indicates the number of command words to send to the SPDIF, starting with the base PIO address
CMDWORDS of the SPDIF and incrementing from there. Zero means transfer NO command words

RSVD1


Field Description
it again.

RSVD0

COMMAND
00- NO DMA TRANSFER
write).
10- read transfer
11- reserved
DMA transfer.

(HW_APBX_CH2_BAR)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
ADDRESS

(HW_APBX_CH2_SEMA)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE
RSVD1

controls.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
BURST
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
REQ
BURST
KICK


Field Description
END
27–25 Reserved
RSVD2
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1
STATEMACHINE
DMA transfers.
halts.


2.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

command chain item.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEMAPHORE
IRQONCMPLT
WAIT4ENDCMD
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
XFER_COUNT peripheral. A value of 0 indicates a 64 KBytes transfer.
15–12 This field indicates the number of command words to send to assigned peripheral, starting with the base
CMDWORDS PIO address of the assigned peripheral and increment from there. Zero means transfer NO command words

RSVD1
it again.

RSVD0


Field Description

COMMAND
00- NO DMA TRANSFER
write).
10- read transfer
11- reserved
DMA transfer.

(HW_APBX_CH3_BAR)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDRESS


(HW_APBX_CH3_SEMA)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE
RSVD1

controls. Because channel 3 is not assigned to any peripheral, this register is of no practical
usage and just reserved for compatibility.

Address: HW_APBX_CH3_DEBUG1 – 8002_4000h base + 2A0h offset = 8002_42A0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
BURST
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
REQ
BURST
KICK
END


Field Description
27–25 Reserved
RSVD2
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1
STATEMACHINE
DMA transfers.
halts.


3.
Address: HW_APBX_CH3_DEBUG2 – 8002_4000h base + 2B0h offset = 8002_42B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES

Address: HW_APBX_CH4_CURCMDAR – 8002_4000h base + 2C0h offset = 8002_42C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
CMD_ADDR

Address: HW_APBX_CH4_NXTCMDAR – 8002_4000h base + 2D0h offset = 8002_42D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

command chain item.

Address: HW_APBX_CH4_CMD – 8002_4000h base + 2E0h offset = 8002_42E0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEMAPHORE
IRQONCMPLT
WAIT4ENDCMD
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
31–16 This field indicates the number of bytes to transfer to or from the SAIF0 device. A value of 0 indicates a 64
XFER_COUNT KBytes transfer.
15–12 This field indicates the number of command words to send to the SAIF0. Zero means transfer NO command
CMDWORDS words

RSVD1
it again.

RSVD0


Field Description

COMMAND
00- NO DMA TRANSFER
write).
10- read transfer
11- reserved
DMA transfer.

(HW_APBX_CH4_BAR)
have been read into the DMA controller and the device associate with this channel, then
the DMA transfer will begin, to or from the buffer pointed to by this register.
Address: HW_APBX_CH4_BAR – 8002_4000h base + 2F0h offset = 8002_42F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDRESS


(HW_APBX_CH4_SEMA)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE
RSVD1

controls.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
BURST
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
REQ
BURST
KICK
END


Field Description
27–25 Reserved
RSVD2
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1
STATEMACHINE
DMA transfers.
halts.


4.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

command chain item.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEMAPHORE
IRQONCMPLT
WAIT4ENDCMD
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
31–16 This field indicates the number of bytes to transfer to or from the appropriate PIO register in the SAIF1
XFER_COUNT register. A value of 0 indicates a 64 KBytes transfer.
15–12 This field indicates the number of command words to send to the SAIF1. Zero means transfer NO command
CMDWORDS words

RSVD1
it again.

RSVD0


Field Description

COMMAND
00- NO DMA TRANSFER
write).
10- read transfer
11- reserved
DMA transfer.

(HW_APBX_CH5_BAR)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDRESS


(HW_APBX_CH5_SEMA)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE
RSVD1

controls.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
BURST
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
REQ
BURST
KICK
END


Field Description
27–25 Reserved
RSVD2
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1
STATEMACHINE
DMA transfers.
halts.


5.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES

Address: HW_APBX_CH6_CURCMDAR – 8002_4000h base + 3A0h offset = 8002_43A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR


Address: HW_APBX_CH6_NXTCMDAR – 8002_4000h base + 3B0h offset = 8002_43B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

command chain item.

Address: HW_APBX_CH6_CMD – 8002_4000h base + 3C0h offset = 8002_43C0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TERMINATEFLUSH
HALTONTERMINATE
WAIT4ENDCMD
IRQONCMPLT
SEMAPHORE
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
31–16 This field indicates the number of bytes to transfer to or from the appropriate PIO register in the I2C0
15–12 This field indicates the number of command words to send to the I2C0 device. Zero means transfer
CMDWORDS NO command words

RSVD1
9 A value of one indicates that the channel will flush out any remainder data in DMA FIFO when
TERMINATEFLUSH termination occurs. Only appliese for write DMA operation.


Field Description
8 A value of one indicates that the channel will immeditately terminate the current descriptor and halt
HALTONTERMINATE the DMA channel if a terminate signal is set. A value of 0 will still cause an immediate terminate of
the channel if the terminate signal is set, but the channel will continue as if the count had been
exhausted, meaning it will honor IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD.
7 A value of one indicates that the channel will wait for the end of command signal to be sent from the

RSVD0

COMMAND
00- NO DMA TRANSFER
01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB
master write).
10- read transfer
11- reserved
any DMA transfer.

(HW_APBX_CH6_BAR)

Address: HW_APBX_CH6_BAR – 8002_4000h base + 3D0h offset = 8002_43D0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDRESS

(HW_APBX_CH6_SEMA)
Address: HW_APBX_CH6_SEMA – 8002_4000h base + 3E0h offset = 8002_43E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE
RSVD1


controls.
Address: HW_APBX_CH6_DEBUG1 – 8002_4000h base + 3F0h offset = 8002_43F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
BURST
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Field Description
REQ
BURST
KICK
END
27–25 Reserved
RSVD2
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1
STATEMACHINE
DMA transfers.


Field Description
halts.

6.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

command chain item.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TERMINATEFLUSH
HALTONTERMINATE
WAIT4ENDCMD
IRQONCMPLT
SEMAPHORE
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
31–16 This field indicates the number of bytes to transfer to or from the appropriate PIO register in I2C1
15–12 This field indicates the number of command words to send to the I2C1 device. Zero means transfer
CMDWORDS NO command words


Field Description
RSVD1

RSVD0

COMMAND
00- NO DMA TRANSFER
master write).
10- read transfer
11- reserved
any DMA transfer.

(HW_APBX_CH7_BAR)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDRESS

(HW_APBX_CH7_SEMA)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE
RSVD1


Field Description

controls.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
BURST
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
REQ
BURST
KICK
END
27–25 Reserved
RSVD2
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1
STATEMACHINE


Field Description
DMA transfers.
halts.

7.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
APB_BYTES
AHB_BYTES

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

command chain item.
Address: HW_APBX_CH8_CMD – 8002_4000h base + 4A0h offset = 8002_44A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TERMINATEFLUSH
HALTONTERMINATE
WAIT4ENDCMD
IRQONCMPLT
SEMAPHORE
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
15–12 This field indicates the number of command words to send to the UART0, starting with the base PIO
CMDWORDS address of the UART0 (HW_UARTAPP_CTRL0). Zero means transfer NO command words

RSVD1

RSVD0


Field Description
COMMAND
00- NO DMA TRANSFER
master write).
10- read transfer
11- reserved
any DMA transfer.

(HW_APBX_CH8_BAR)
Address: HW_APBX_CH8_BAR – 8002_4000h base + 4B0h offset = 8002_44B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDRESS


(HW_APBX_CH8_SEMA)
Address: HW_APBX_CH8_SEMA – 8002_4000h base + 4C0h offset = 8002_44C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE
RSVD1

controls.

Address: HW_APBX_CH8_DEBUG1 – 8002_4000h base + 4D0h offset = 8002_44D0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
BURST
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
REQ
BURST
KICK
END


Field Description
27–25 Reserved
RSVD2
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1
STATEMACHINE
DMA transfers.
halts.


8.
Address: HW_APBX_CH8_DEBUG2 – 8002_4000h base + 4E0h offset = 8002_44E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES

Address: HW_APBX_CH9_CURCMDAR – 8002_4000h base + 4F0h offset = 8002_44F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

command chain item.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TERMINATEFLUSH
HALTONTERMINATE
WAIT4ENDCMD
IRQONCMPLT
SEMAPHORE
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
CMDWORDS address of the UART0 (HW_UARTAPP_CTRL1). Zero means transfer NO command words

RSVD1


Field Description

RSVD0

COMMAND
00- NO DMA TRANSFER
master write).
10- read transfer
11- reserved
any DMA transfer.

(HW_APBX_CH9_BAR)


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDRESS

(HW_APBX_CH9_SEMA)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE
RSVD1


controls.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
BURST
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Field Description
REQ
BURST
KICK
END
27–25 Reserved
RSVD2
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1
STATEMACHINE
DMA transfers.


Field Description
halts.

9.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

APBX DMA Channel 10 is controlled by a variable sized command structure. Software
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR
7.5.78 APBX DMA Channel 10 Command Register

(HW_APBX_CH10_CMD)
command chain item.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TERMINATEFLUSH
HALTONTERMINATE
WAIT4ENDCMD
IRQONCMPLT
SEMAPHORE
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
XFER_COUNT device HW_UARTAPP_DATA register. A value of 0 indicates a 64 KBytes transfer.
CMDWORDS address of the UART1 (HW_UARTAPP_CTRL0) and increment from there. Zero means transfer NO
command words


Field Description
RSVD1

RSVD0

COMMAND
00- NO DMA TRANSFER
master write).
10- read transfer
11- reserved
any DMA transfer.

(HW_APBX_CH10_BAR)
The APBX DMA Channel 10 buffer address register contains a pointer to the data buffer

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDRESS

(HW_APBX_CH10_SEMA)
Address: HW_APBX_CH10_SEMA – 8002_4000h base + 5A0h offset = 8002_45A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE
RSVD1


Field Description

controls.
Address: HW_APBX_CH10_DEBUG1 – 8002_4000h base + 5B0h offset = 8002_
45B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
BURST
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
REQ
BURST
KICK
END
27–25 Reserved
RSVD2
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1
STATEMACHINE


Field Description
DMA transfers.
halts.

10.
Address: HW_APBX_CH10_DEBUG2 – 8002_4000h base + 5C0h offset = 8002_45C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
APB_BYTES
AHB_BYTES

Address: HW_APBX_CH11_CURCMDAR – 8002_4000h base + 5D0h offset = 8002_45D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR


Address: HW_APBX_CH11_NXTCMDAR – 8002_4000h base + 5E0h offset = 8002_45E0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

(HW_APBX_CH11_CMD)
command chain item.
Address: HW_APBX_CH11_CMD – 8002_4000h base + 5F0h offset = 8002_45F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEMAPHORE
IRQONCMPLT
WAIT4ENDCMD
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
15–12 This field indicates the number of command words to send to the UART1, starting with the base PIO address
words

RSVD1
it again.

RSVD0

COMMAND
00- NO DMA TRANSFER
write).
10- read transfer
11- reserved
DMA transfer.


Field Description

(HW_APBX_CH11_BAR)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDRESS

(HW_APBX_CH11_SEMA)


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE
RSVD1

controls.

Address: HW_APBX_CH11_DEBUG1 – 8002_4000h base + 620h offset = 8002_

4620h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
BURST
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
REQ
BURST
KICK
END


Field Description
27–25 Reserved
RSVD2
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1
STATEMACHINE
DMA transfers.
halts.


11.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

(HW_APBX_CH12_CMD)
command chain item.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TERMINATEFLUSH
HALTONTERMINATE
WAIT4ENDCMD
IRQONCMPLT
SEMAPHORE
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
command words

RSVD1


Field Description

RSVD0

COMMAND
00- NO DMA TRANSFER
master write).
10- read transfer
11- reserved
any DMA transfer.

(HW_APBX_CH12_BAR)


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDRESS

(HW_APBX_CH12_SEMA)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE
RSVD1


controls.
4690h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
BURST
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Field Description
REQ
BURST
KICK
END
27–25 Reserved
RSVD2
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1
STATEMACHINE
DMA transfers.


Field Description
halts.

12.
Address: HW_APBX_CH12_DEBUG2 – 8002_4000h base + 6A0h offset = 8002_46A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES


Address: HW_APBX_CH13_CURCMDAR – 8002_4000h base + 6B0h offset = 8002_46B0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

Address: HW_APBX_CH13_NXTCMDAR – 8002_4000h base + 6C0h offset = 8002_46C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

(HW_APBX_CH13_CMD)
command chain item.

Address: HW_APBX_CH13_CMD – 8002_4000h base + 6D0h offset = 8002_46D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEMAPHORE
IRQONCMPLT
WAIT4ENDCMD
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
words

RSVD1


Field Description
it again.

RSVD0

COMMAND
00- NO DMA TRANSFER
write).
10- read transfer
11- reserved
DMA transfer.

(HW_APBX_CH13_BAR)
Address: HW_APBX_CH13_BAR – 8002_4000h base + 6E0h offset = 8002_46E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
ADDRESS

(HW_APBX_CH13_SEMA)
Address: HW_APBX_CH13_SEMA – 8002_4000h base + 6F0h offset = 8002_46F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE
RSVD1

controls.

4700h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
BURST
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
REQ
BURST
KICK


Field Description
END
27–25 Reserved
RSVD2
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1
STATEMACHINE
DMA transfers.
halts.


13.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

(HW_APBX_CH14_CMD)
command chain item.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TERMINATEFLUSH
HALTONTERMINATE
WAIT4ENDCMD
IRQONCMPLT
SEMAPHORE
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
command words

RSVD1


Field Description

RSVD0

COMMAND
00- NO DMA TRANSFER
master write).
10- read transfer
11- reserved
any DMA transfer.

(HW_APBX_CH14_BAR)


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDRESS

(HW_APBX_CH14_SEMA)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE
RSVD1


controls.
4770h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
BURST
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Field Description
REQ
BURST
KICK
END
27–25 Reserved
RSVD2
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1
STATEMACHINE
DMA transfers.


Field Description
halts.

14.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

Address: HW_APBX_CH15_NXTCMDAR – 8002_4000h base + 7A0h offset = 8002_47A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
CMD_ADDR

(HW_APBX_CH15_CMD)
command chain item.

Address: HW_APBX_CH15_CMD – 8002_4000h base + 7B0h offset = 8002_47B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEMAPHORE
IRQONCMPLT
WAIT4ENDCMD
CHAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
words

RSVD1


Field Description
it again.

RSVD0

COMMAND
00- NO DMA TRANSFER
write).
10- read transfer
11- reserved
DMA transfer.

(HW_APBX_CH15_BAR)
Address: HW_APBX_CH15_BAR – 8002_4000h base + 7C0h offset = 8002_47C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
ADDRESS

(HW_APBX_CH15_SEMA)
Address: HW_APBX_CH15_SEMA – 8002_4000h base + 7D0h offset = 8002_47D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 PHORE RSVD1

INCREMENT_SEMA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
PHORE
RSVD1

controls.

Address: HW_APBX_CH15_DEBUG1 – 8002_4000h base + 7E0h offset = 8002_
47E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_FIFO_EMPTY
RD_FIFO_EMPTY
NEXTCMDADDRVALID
WR_FIFO_FULL
RD_FIFO_FULL
BURST
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
REQ
BURST
KICK


Field Description
END
27–25 Reserved
RSVD2
RD_FIFO_EMPTY
RD_FIFO_FULL
WR_FIFO_EMPTY
WR_FIFO_FULL
19–5 Reserved
RSVD1
STATEMACHINE
DMA transfers.
halts.


15.
Address: HW_APBX_CH15_DEBUG2 – 8002_4000h base + 7F0h offset = 8002_47F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
APB_BYTES
AHB_BYTES
7.5.118 APBX Bridge Version Register (HW_APBX_VERSION)

of the block.
This register indicates the RTL version in use.
EXAMPLE
if (HW_APBX_VERSION.B.MAJOR != 1)
Error();
Address: HW_APBX_VERSION – 8002_4000h base + 800h offset = 8002_4800h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MAJOR MINOR STEP

W
Re- 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

HW_APBX_VERSION field descriptions

Field Description
MAJOR
MINOR
STEP

Chapter 8
Pin Descriptions
8.1 Pin Descriptions Overview

This chapter provides various views of the pinout for the i.MX28.
• Pin definitions for the 289-pin BGA are in Pin Definitions for 289-pin BGA
• Pin sorted by functional groups are in Functional Pin Groups
The pin tables in this chapter include columns with the headings MUX0, MUX1, and MUX2.
These columns refer to the different functions that can be enabled for each individual pin
by programming the pin control registers (HW_PINCTRL_MUXSELx). For example:
• Enable the function listed in the "MUX0" column by programming the BANKx_PINx
bit field to 00.
bit field to 01.
bit field to 10.
See Pin Control and GPIO Overview for more information.

Table 8-1 lists the abbreviations used in the pin tables in this chapter.
Table 8-1. Nomenclature for Pin Tables
TYPE DESCRIPTION MODULE DESCRIPTION
A Analog pin ADC ADC analog pins
D Digital pin CLOCK Clock pins
E EMI pin DCDC DC-DC Converter pins
P Power pin EMI External Memory Interface pins
I Input pin ETM Embedded Trace Macrocell

Pin Definitions for 289-pin BGA
TYPE DESCRIPTION MODULE DESCRIPTION
O Output pin GPIO General-Purpose Input/Output pins
General-Purpose Media Interface

I/O Input/output pin GPMI
(NAND/ATA/CMOS) pins
HP Headphone pins
2 2
I C I C pins
LCDIF LCD Interface pins
LRADC Low-Resolution ADC/Touch-Screen pins
POWER Power pins
PWM Pulse Width Modulator pins
RTC Real-Time Clock pins
SSP Synchronous Serial Port pins
SYSTEM System pins
TIMER Timer/Rotary Encoder pins
UART Either debug or application UART pins
USB USB pins
Note
Almost all digital pins are powered down (that is, high-impedance)
or configured as GPIO input at reset, until reprogrammed. The
only exceptions are TEST PINS(TESTMODE, DEBUG, JTAG
pins). These pins are always active.
8.2 Pin Definitions for 289-pin BGA

This section includes the following pin information for the 289-pin BGA package:
• Table 8-2
• Figure 8-1
Table 8-2. Pin Definitions
PIN NAME PIN GROUP TYPE MUX0 MUX1 MUX2
AUART0_CTS J6 AUART D AUART0_CTS AUART4_RX DUART_RX
AUART0_RTS J7 AUART D AUART0_RTS AUART4_TX DUART_TX

Chapter 8 Pin Descriptions

AUART0_RX G5 AUART D AUART0_RX I2C0_SCL DUART_CTS
AUART0_TX H5 AUART D AUART0_TX I2C0_SDA DUART_RTS
AUART1_CTS K5 AUART D AUART1_CTS USB0_OVERCURRENT TIMROT_ROTARYA
AUART1_RTS J5 AUART D AUART1_RTS USB0_ID TIMROT_ROTARYB
AUART1_RX L4 AUART D AUART1_RX SSP2_CARD_DETECT PWM_0
AUART1_TX K4 AUART D AUART1_TX SSP3_CARD_DETECT PWM_1
AUART2_CTS H6 AUART D AUART2_CTS I2C1_SCL SAIF1_BITCLK
AUART2_RTS H7 AUART D AUART2_RTS I2C1_SDA SAIF1_LRCLK
AUART2_RX F6 AUART D AUART2_RX SSP3_D1 SSP3_D4
AUART2_TX F5 AUART D AUART2_TX SSP3_D2 SSP3_D5
EN-
AUART3_CTS L6 AUART D AUART3_CTS CAN1_TX
ET0_1588_EVENT1_OUT
EN-
AUART3_RTS K6 AUART D AUART3_RTS CAN1_RX
ET0_1588_EVENT1_IN
EN-
AUART3_RX M5 AUART D AUART3_RX CAN0_TX
ET0_1588_EVENT0_OUT
EN-
AUART3_TX L5 AUART D AUART3_TX CAN0_RX
ET0_1588_EVENT0_IN
BATTERY A15 DCDC A
DCDC_BATT B15 DCDC A
DCDC_GND A17 DCDC A
DCDC_LN1 B17 DCDC A
DCDC_LP A16 DCDC A
DCDC_VDDA B16 DCDC A
DCDC_VDDD D17 DCDC A
DCDC_VDDIO C17 DCDC A
SYS-
DEBUG B9 D
TEM
EMI_A00 U15 EMI E EMI_ADDR0
EMI_A03 T11 EMI E EMI_ADDR3
EMI_A05 R11 EMI E EMI_ADDR5
EMI_A06 R9 EMI E EMI_ADDR6
EMI_A07 N11 EMI E EMI_ADDR7
EMI_A09 P10 EMI E EMI_ADDR9


EMI_A14 N10 EMI E EMI_ADDR14
EMI_BA0 T16 EMI E EMI_BA0
EMI_BA1 T12 EMI E EMI_BA1
EMI_BA2 N12 EMI E EMI_BA2
EMI_CASN U16 EMI E EMI_CASN
EMI_CE0N P12 EMI E EMI_CE0N
EMI_CE1N P9 EMI E EMI_CE1N
EMI_CKE T13 EMI E EMI_CKE
EMI_CLK L17 EMI E EMI_CLK
EMI_CLKN L16 EMI E
EMI_D00 N16 EMI E EMI_DATA0
EMI_D01 M13 EMI E EMI_DATA1
EMI_D02 P15 EMI E EMI_DATA2
EMI_D03 N14 EMI E EMI_DATA3
EMI_D06 L14 EMI E EMI_DATA6
EMI_D07 M17 EMI E EMI_DATA7
EMI_D08 G16 EMI E EMI_DATA8
EMI_D09 H15 EMI E EMI_DATA9
EMI_D10 G14 EMI E EMI_DATA10
EMI_D11 J14 EMI E EMI_DATA11
EMI_D14 F13 EMI E EMI_DATA14
EMI_D15 F17 EMI E EMI_DATA15
EMI_DDR_OPEN K14 EMI E EMI_DDR_OPEN
EMI_DDR_OPEN_FEED-
EMI_DDR_OPEN_FB L15 EMI E
BACK
EMI_DQM0 M15 EMI E EMI_DQM0
EMI_DQM1 F15 EMI E EMI_DQM1
EMI_DQS0 K17 EMI E EMI_DQS0


EMI_DQS0N K16 EMI E
EMI_DQS1 J17 EMI E EMI_DQS1
EMI_DQS1N J16 EMI E
EMI_ODT0 R17 EMI E EMI_ODT0
EMI_ODT1 T17 EMI E EMI_ODT1
EMI_RASN R16 EMI E EMI_RASN
EMI_VREF0 R14 EMI E
EMI_VREF1 K13 EMI E
EMI_WEN T15 EMI E EMI_WEN
EN-
ENET0_COL J4 ENET D ENET0_COL ENET1_TX_EN
ET0_1588_EVENT3_OUT
EN-
ENET0_CRS J3 ENET D ENET0_CRS ENET1_RX_EN
ET0_1588_EVENT3_IN
ENET0_MDC G4 ENET D ENET0_MDC GPMI_CE4N SAIF0_SDATA1
ENET0_MDIO H4 ENET D ENET0_MDIO GPMI_CE5N SAIF0_SDATA2
ENET0_RXD0 H1 ENET D ENET0_RXD0 GPMI_CE7N SAIF1_SDATA2
ENET0_RXD1 H2 ENET D ENET0_RXD1 GPMI_READY4
EN-
ENET0_RXD2 J1 ENET D ENET0_RXD2 ENET1_RXD0
ET0_1588_EVENT0_OUT
EN-
ENET0_RXD3 J2 ENET D ENET0_RXD3 ENET1_RXD1
ET0_1588_EVENT0_IN
EN-
ENET0_RX_CLK F3 ENET D ENET0_RX_CLK ENET0_RX_ER
ET0_1588_EVENT2_IN
ENET0_RX_EN E4 ENET D ENET0_RX_EN GPMI_CE6N SAIF1_SDATA1
ENET0_TXD0 F1 ENET D ENET0_TXD0 GPMI_READY6
ENET0_TXD1 F2 ENET D ENET0_TXD1 GPMI_READY7
EN-
ENET0_TXD2 G1 ENET D ENET0_TXD2 ENET1_TXD0
ET0_1588_EVENT1_OUT
EN-
ENET0_TXD3 G2 ENET D ENET0_TXD3 ENET1_TXD1
ET0_1588_EVENT1_IN
EN-
ENET0_TX_CLK E3 ENET D ENET0_TX_CLK HSADC_TRIGGER
ET0_1588_EVENT2_OUT
ENET0_TX_EN F4 ENET D ENET0_TX_EN GPMI_READY5
ENET_CLK E2 ENET D CLKCTRL_ENET
GPMI_ALE P6 GPMI D GPMI_ALE SSP3_D1 SSP3_D4
GPMI_CE0N N7 GPMI D GPMI_CE0N SSP3_D0
GPMI_CE1N N9 GPMI D GPMI_CE1N SSP3_D3
GPMI_CE2N M7 GPMI D GPMI_CE2N CAN1_TX ENET0_RX_ER
GPMI_CE3N M9 GPMI D GPMI_CE3N CAN1_RX SAIF1_MCLK


GPMI_CLE P7 GPMI D GPMI_CLE SSP3_D2 SSP3_D5
GPMI_D00 U8 GPMI D GPMI_D0 SSP1_D0
GPMI_D01 T8 GPMI D GPMI_D1 SSP1_D1
GPMI_D02 R8 GPMI D GPMI_D2 SSP1_D2
GPMI_D05 R7 GPMI D GPMI_D5 SSP1_D5
GPMI_RDN R6 GPMI D GPMI_RDN SSP3_SCK
GPMI_RDY0 N6 GPMI D GPMI_READY0 SSP1_CARD_DETECT USB0_ID
GPMI_RDY1 N8 GPMI D GPMI_READY1 SSP1_CMD
GPMI_RDY2 M8 GPMI D GPMI_READY2 CAN0_TX ENET0_TX_ER
GPMI_RDY3 L8 GPMI D GPMI_READY3 CAN0_RX HSADC_TRIGGER
GPMI_RESETN L9 GPMI D GPMI_RESETN SSP3_CMD
GPMI_WRN P8 GPMI D GPMI_WRN SSP1_SCK
HSADC0 B14 HSADC A
I2C0_SCL C7 I2C D I2C0_SCL TIMROT_ROTARYA DUART_RX
I2C0_SDA D8 I2C D I2C0_SDA TIMROT_ROTARYB DUART_TX
SYS-
JTAG_RTCK E14 D JTAG_RTCK
TEM
SYS-
JTAG_TCK E11 D
TEM
SYS-
JTAG_TDI E12 D
TEM
SYS-
JTAG_TDO E13 D
TEM
SYS-
JTAG_TMS D12 D
TEM
SYS-
JTAG_TRST D14 D
TEM
LCD_CS P5 LCD D LCD_CS LCD_ENABLE
LCD_D00 K2 LCD D LCD_D0 ETM_DA0
LCD_D01 K3 LCD D LCD_D1 ETM_DA1
LCD_D02 L2 LCD D LCD_D2 ETM_DA2
LCD_D03 L3 LCD D LCD_D3 ETM_DA8 ETM_DA3
LCD_D04 M2 LCD D LCD_D4 ETM_DA9 ETM_DA4
LCD_D05 M3 LCD D LCD_D5 ETM_DA5


LCD_D06 N2 LCD D LCD_D6 ETM_DA6
LCD_D07 P1 LCD D LCD_D7 ETM_DA7
LCD_D08 P2 LCD D LCD_D8 ETM_DA3 ETM_DA8
LCD_D09 P3 LCD D LCD_D9 ETM_DA4 ETM_DA9
LCD_D10 R1 LCD D LCD_D10 ETM_DA10
LCD_D12 T1 LCD D LCD_D12 ETM_DA12
LCD_D14 U2 LCD D LCD_D14 ETM_DA14
EN-
ET1_1588_EVENT2_OUT
EN-
ET1_1588_EVENT2_IN
EN-
ET1_1588_EVENT3_OUT
EN-
ET1_1588_EVENT3_IN
LCD_DOTCLK N1 LCD D LCD_DOTCLK SAIF1_MCLK ETM_TCLK
LCD_ENABLE N5 LCD D LCD_ENABLE
LCD_HSYNC M1 LCD D LCD_HSYNC SAIF1_SDATA1 ETM_TCTL
LCD_RD_E P4 LCD D LCD_RD_E LCD_VSYNC ETM_TCTL
LCD_RESET M6 LCD D LCD_RESET LCD_VSYNC
LCD_RS M4 LCD D LCD_RS LCD_DOTCLK
LCD_VSYNC L1 LCD D LCD_VSYNC SAIF1_SDATA0
LCD_WR_RWN K1 LCD D LCD_WR_RWN LCD_HSYNC ETM_TCLK
LRADC0 C15 LRADC A
LRADC1 C9 LRADC A
LRADC2 C8 LRADC A
LRADC3 D9 LRADC A
LRADC4 D13 LRADC A
LRADC5 D15 LRADC A
LRADC6 C14 LRADC A
PSWITCH A11 DCDC A


PWM0 K7 PWM D PWM_0 I2C1_SCL DUART_RX
PWM1 L7 PWM D PWM_1 I2C1_SDA DUART_TX
PWM2 K8 PWM D PWM_2 USB0_ID USB1_OVERCURRENT
PWM3 E9 PWM D PWM_3
PWM4 E10 PWM D PWM_4
RESETN A14 DCDC A
RTC_XTALI D11 XTAL A
RTC_XTALO C11 XTAL A
SAIF0_BITCLK F7 SAIF D SAIF0_BITCLK PWM_5 AUART4_RX
SAIF0_LRCLK G6 SAIF D SAIF0_LRCLK PWM_4 AUART4_RTS
SAIF0_MCLK G7 SAIF D SAIF0_MCLK PWM_3 AUART4_CTS
SAIF0_SDATA0 E7 SAIF D SAIF0_SDATA0 PWM_6 AUART4_TX
SAIF1_SDATA0 E8 SAIF D SAIF1_SDATA0 PWM_7 SAIF0_SDATA1
SPDIF D7 SPDIF D SPDIF_TX ENET1_RX_ER
SSP0_CMD A4 SSP D SSP0_CMD
SSP0_DATA0 B6 SSP D SSP0_D0
SSP0_DATA1 C6 SSP D SSP0_D1
SSP0_DATA2 D6 SSP D SSP0_D2
SSP0_DATA3 A5 SSP D SSP0_D3
SSP0_DATA4 B5 SSP D SSP0_D4 SSP2_D0
SSP0_DATA5 C5 SSP D SSP0_D5 SSP2_D3
SSP0_DATA6 D5 SSP D SSP0_D6 SSP2_CMD
SSP0_DATA7 B4 SSP D SSP0_D7 SSP2_SCK
SSP0_CARD_DE-
SSP0_DETECT D10 SSP D
TECT
SSP0_SCK A6 SSP D SSP0_SCK
EN-
SSP1_CMD C1 SSP D SSP1_CMD SSP2_D2
ET0_1588_EVENT2_IN
EN-
SSP1_DATA0 D1 SSP D SSP1_D0 SSP2_D6
ET0_1588_EVENT3_OUT
EN-
SSP1_DATA3 E1 SSP D SSP1_D3 SSP2_D7
ET0_1588_EVENT3_IN
EN-
SSP1_SCK B1 SSP D SSP1_SCK SSP2_D1
ET0_1588_EVENT2_OUT
SSP2_MISO B3 SSP D SSP2_D0 AUART3_RX SAIF1_SDATA1
SSP2_MOSI C3 SSP D SSP2_CMD AUART2_TX SAIF0_SDATA2
SSP2_SCK A3 SSP D SSP2_SCK AUART2_RX SAIF0_SDATA1
SSP2_SS0 C4 SSP D SSP2_D3 AUART3_TX SAIF1_SDATA2


SSP2_SS1 D3 SSP D SSP2_D4 SSP2_D1 USB1_OVERCURRENT
SSP2_SS2 D4 SSP D SSP2_D5 SSP2_D2 USB0_OVERCURRENT
EN-
SSP3_MISO B2 SSP D SSP3_D0 AUART4_RTS
ET1_1588_EVENT1_OUT
EN-
SSP3_MOSI C2 SSP D SSP3_CMD AUART4_RX
ET1_1588_EVENT0_IN
EN-
SSP3_SCK A2 SSP D SSP3_SCK AUART4_TX
ET1_1588_EVENT0_OUT
EN-
SSP3_SS0 D2 SSP D SSP3_D3 AUART4_CTS
ET1_1588_EVENT1_IN
SYS-
TESTMODE C10 D
TEM
USB0DM A10 USB A
USB0DP B10 USB A
USB1DM B8 USB A
USB1DP A8 USB A
VDD1P5 D16 DCDC A
VDD4P2 A13 DCDC A
VDD5V E17 DCDC A
VDDA1 C13 POWER A
G12, G11,
F10, F11,
VDDD POWER P
K12, F12,
G10
G8, F9, F8,
VDDIO18 POWER P
G9
H8, J8, N3,
VDDIO33 G3, E6, J9, POWER P
J10, A7, E16
VDDIO33_EMI N17 POWER P
P11, R13,
N13, N15,
G17, M12,
VDDIO_EMI POWER P
M10, G13,
M11, L13,
G15
VDDIO_EMIQ K15, J13, R15 POWER P
VDDXTAL C12 POWER A


E15, L11, A1,
K10, K11,
J11, M14,
H11, U1, H9,
VSS H12, H3, K9, POWER P
C16, L10,
H16, J12,
H10, B7, E5,
J15, A9, N4
VSSA1 B13 POWER A
VSSA2 B11 POWER A
F16, R10,
H14, M16,
F14, L12,
VSSIO_EMI POWER P
P16, U17,
T14, P14,
R12
XTALI A12 XTAL A
XTALO B12 XTAL A

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SSP3_SC SSP2_SC SSP0_CM SSP0_DA SSP0_SC DCDC_G

A VSS
K K D TA3 K
VDDIO33 USB1DP VSS USB0DM PSWITCH XTALI VDD4P2 RESETN BATTERY DCDC_LP
ND
A
SSP1_SC SSP3_MI SSP2_MI SSP0_DA SSP0_DA SSP0_DA DCDC_B DCDC_V DCDC_L

B K SO SO TA7 TA4 TA0
VSS USB1DM DEBUG USB0DP VSSA2 XTALO VSSA1 HSADC0
ATT DDA N1
B
SSP1_CM SSP3_M SSP2_M SSP2_SS SSP0_DA SSP0_DA TESTMO RTC_XTA DCDC_V

C D OSI OSI 0 TA5 TA1
I2C0_SCL LRADC2 LRADC1
DE LO
VDDXTAL VDDA1 LRADC6 LRADC0 VSS
DDIO
C
SSP1_DA SSP3_SS SSP2_SS SSP2_SS SSP0_DA SSP0_DA SSP0_DE RTC_XTA JTAG_TM JTAG_TR DCDC_V
D TA0 0 1 2 TA6 TA2
SPDIF I2C0_SDA LRADC3
TECT LI S
LRADC4
ST
LRADC5 VDD1P5
DDD
D
SSP1_DA ENET_CL ENET0_T ENET0_R SAIF0_S SAIF1_S JTAG_TC JTAG_TD JTAG_RT

E TA3 K X_CLK X_EN
VSS VDDIO33
DATA0 DATA0
PWM3 PWM4
K
JTAG_TDI
O CK
VSS VDDIO33 VDD5V E
ENET0_T ENET0_T ENET0_R ENET0_T AUART2_ AUART2_ SAIF0_BI VSSIO_E EMI_DQM VSSIO_E
F XD0 XD1 X_CLK X_EN TX RX TCLK
VDDIO18 VDDIO18 VDDD VDDD VDDD EMI_D14
MI 1 MI
EMI_D15 F
ENET0_T ENET0_T ENET0_M AUART0_ SAIF0_L SAIF0_M VDDIO_E VDDIO_E VDDIO_E

G XD2 XD3
VDDIO33
DC RX RCLK CLK
VDDIO18 VDDIO18 VDDD VDDD VDDD
MI
EMI_D10
MI
EMI_D08
MI
G
ENET0_R ENET0_R ENET0_M AUART0_ AUART2_ AUART2_ VSSIO_E

H XD0 XD1
VSS
DIO TX CTS RTS
VDDIO33 VSS VSS VSS VSS EMI_D12
MI
EMI_D09 VSS EMI_D13 H
ENET0_R ENET0_R ENET0_C ENET0_C AUART1_ AUART0_ AUART0_ VDDIO_E EMI_DQS EMI_DQS
J XD2 XD3 RS OL RTS CTS RTS
VDDIO33 VDDIO33 VDDIO33 VSS VSS
MIQ
EMI_D11 VSS
1N 1
J
LCD_WR AUART1_ AUART1_ AUART3_ EMI_VRE EMI_DDR VDDIO_E EMI_DQS EMI_DQS

K _RWN
LCD_D00 LCD_D01
TX CTS RTS
PWM0 PWM2 VSS VSS VSS VDDD
F1 _OPEN MIQ 0N 0
K
EMI_DDR
LCD_VSY AUART1_ AUART3_ AUART3_ GPMI_RD GPMI_RE VSSIO_E VDDIO_E EMI_CLK
L NC
LCD_D02 LCD_D03
RX TX CTS
PWM1
Y3 SETN
VSS VSS
MI MI
EMI_D06 _OPEN_F
N
EMI_CLK L
B
LCD_HSY AUART3_ LCD_RES GPMI_CE GPMI_RD GPMI_CE VDDIO_E VDDIO_E VDDIO_E EMI_DQM VSSIO_E
M NC
LCD_D04 LCD_D05 LCD_RS
RX ET 2N Y2 3N MI MI MI
EMI_D01 VSS
0 MI
EMI_D07 M
LCD_DO LCD_EN GPMI_RD GPMI_CE GPMI_RD GPMI_CE VDDIO_E VDDIO_E VDDIO33

N TCLK
LCD_D06 VDDIO33 VSS
ABLE Y0 0N Y1 1N
EMI_A14 EMI_A07 EMI_BA2
MI
EMI_D03
MI
EMI_D00
_EMI
N
LCD_RD_ GPMI_AL GPMI_CL GPMI_W EMI_CE1 VDDIO_E EMI_CE0 VSSIO_E VSSIO_E

P LCD_D07 LCD_D08 LCD_D09
E
LCD_CS
E E RN N
EMI_A09
MI N
EMI_D04
MI
EMI_D02
MI
EMI_D05 P
GPMI_RD GPMI_D0 GPMI_D0 VSSIO_E VSSIO_E VDDIO_E EMI_VRE VDDIO_E EMI_RAS EMI_ODT
R LCD_D10 LCD_D11 LCD_D17 LCD_D20 LCD_D23
N 5 2
EMI_A06
MI
EMI_A05
MI MI F0 MIQ N 0
R
GPMI_D0 GPMI_D0 GPMI_D0 VSSIO_E EMI_ODT

T LCD_D12 LCD_D13 LCD_D16 LCD_D19 LCD_D22
7 4 1
EMI_A13 EMI_A11 EMI_A03 EMI_BA1 EMI_CKE
MI
EMI_WEN EMI_BA0
1
T
GPMI_D0 GPMI_D0 GPMI_D0 EMI_CAS VSSIO_E

U VSS LCD_D14 LCD_D15 LCD_D18 LCD_D21
6 3 0
EMI_A08 EMI_A04 EMI_A12 EMI_A01 EMI_A10 EMI_A02 EMI_A00
N MI
U
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Figure 8-1. Ball Map
8.3 Functional Pin Groups

This section includes the i.MX28 pins listed in tables by function.
Refer to the pin name tables in the previous sections for appropriate package pin numbers.
1. Table 8-3
2. Table 8-4

Functional Pin Groups
3. Table 8-5
4. Table 8-6
5. Table 8-7
6. Table 8-8
7. Table 8-9
8. Table 8-10
9. Table 8-11
10. Table 8-12
11. Table 8-13
12. Table 8-14
13. Table 8-15
14. Table 8-16
15. Table 8-17
16. Table 8-18
17. Table 8-19
18. Table 8-20
19. Table 8-21
Table 8-3. DCDC

PIN NAME GROUP TYPE DESCRIPTION
VDD1P5 DCDC A 1.5V regulator output for LVDDR2 power supply
DCDC_VDDD DCDC A DCDC output for Digital Core Power w/ typical value of 1.2V
DCDC_LN2 DCDC A DCDC Inductor N 2
DCDC_VDDIO DCDC A DCDC output for I/O Power w/ typical value of 3.3V
DCDC_VDDA DCDC A DCDC output for analog/DDR2/1.8V IO power w/ typical value of 1.8V
DCDC_LN1 DCDC A DCDC Inductor N 1
DCDC_GND DCDC A DCDC Ground
DCDC_LP DCDC A DCDC Inductor P

DCDC_BATT DCDC A DCDC Battery
VDD4P2_DCDC DCDC A DCDC 4.2V Input
VDD4P2 DCDC A DCDC 4.2V Regulated Output
VDD5V DCDC A 5V Power Input
BATTERY DCDC A Battery Input
RESETN DCDC A Chip-wide Reset In
PSWITCH DCDC A Power On / Recovery / Software Visible
Table 8-4. POWER

VDDA1 POWER A Analog Power 1
VDDD POWER P
VDDIO18 POWER P
VDDIO33 POWER P
VDDIO33_EMI POWER P Digital I/O Quiet Power 0 / EMI
VDDIO_EMI POWER P
VDDIO_EMIQ POWER P Digital I/O Quiet Power 0 / EMI
VDDXTAL POWER A Crystal Power Filter Capacitor
VSSA1 POWER A Analog Ground 1
VSSD POWER P
VSSIO18 POWER P
VSSIO33 POWER P
VSSIO_EMI POWER P
VSSIO_EMIQ POWER P

Table 8-5. Analog application pins

HSADC0 HSADC A HSADC
LRADC6 LRADC A LRADC6
USB0DP USB A USB0 Positive Data Line
USB0DM USB A USB0 Negative Data Line
RTC_XTALI XTAL A 32.768 or 32.0 KHz Xtal In
RTC_XTALO XTAL A 32.768 or 32.0 KHz Xtal Out
XTALO XTAL A 24MHz Crystal Out
XTALI XTAL A 24MHz Crystal In
Table 8-6. AUART

PIN NAME GROUP TYPE DESCRIPTION MUX0 MUX1 MUX2
SAIF0_SDATA0 SAIF D SAIF0 Serial Data0 (stereo) SAIF0_SDATA0 PWM_6 AUART4_TX
SSP2_SCK SSP D SSP Serial Clock SSP2_SCK AUART2_RX SAIF0_SDATA1
EN-
SSP3_SCK SSP D SSP Serial Clock SSP3_SCK AUART4_TX
ET1_1588_EVENT0_OUT
SSP2_MISO SSP D SD/MMC/Data0 / SPI MISO SSP2_D0 AUART3_RX SAIF1_SDATA1
SD/MMC/Data3 / SPI Slave

SSP2_SS0 SSP D SSP2_D3 AUART3_TX SAIF1_SDATA2
Select 0
SAIF0_BITCLK SAIF D SAIF0_BITCLK PWM_5 AUART4_RX

EN-
SSP3_MISO SSP D SD/MMC/Data0 / SPI MISO SSP3_D0 AUART4_RTS
ET1_1588_EVENT1_OUT
SSP2_MOSI SSP D SD/MMC CMD / SPI MOSI SSP2_CMD AUART2_TX SAIF0_SDATA2
AUART2_RX AUART D Application UART2 RX AUART2_RX SSP3_D1 SSP3_D4
EN-
SSP3_MOSI SSP D SD/MMC CMD / SPI MOSI SSP3_CMD AUART4_RX
ET1_1588_EVENT0_IN
SD/MMC/Data3 / SPI Slave EN-

SSP3_SS0 SSP D SSP3_D3 AUART4_CTS
Select 0 ET1_1588_EVENT1_IN
SAIF0_MCLK SAIF D SAIF0_MCLK PWM_3 AUART4_CTS
SAIF0_LRCLK SAIF D SAIF0 Left/Right Clock SAIF0_LRCLK PWM_4 AUART4_RTS
AUART2_TX AUART D Application UART2 TX AUART2_TX SSP3_D2 SSP3_D5
Application UART2 RTS Flow

AUART2_RTS AUART D AUART2_RTS I2C1_SDA SAIF1_LRCLK
Control
Application UART2 CTS Flow

AUART2_CTS AUART D AUART2_CTS I2C1_SCL SAIF1_BITCLK
Control
AUART0_RX AUART D Application UART0 RX AUART0_RX I2C0_SCL DUART_CTS

AUART0_RTS AUART D AUART0_RTS AUART4_TX DUART_TX
Control
AUART0_TX AUART D Application UART0 TX AUART0_TX I2C0_SDA DUART_RTS

AUART0_CTS AUART D AUART0_CTS AUART4_RX DUART_RX
Control

AUART1_RTS AUART D AUART1_RTS USB0_ID TIMROT_ROTARYB
Control
Application UART2 RTS Flow EN-

AUART3_RTS AUART D AUART3_RTS CAN1_RX
Control ET0_1588_EVENT1_IN
Application UART1 CTS Flow USB0_OVERCUR-

AUART1_CTS AUART D AUART1_CTS TIMROT_ROTARYA
Control RENT
SSP3_CARD_DE-
AUART1_TX AUART D Application UART1 TX AUART1_TX PWM_1
TECT
EN-
AUART3_TX AUART D Application UART2 TX AUART3_TX CAN0_RX
ET0_1588_EVENT0_IN
SSP2_CARD_DE-
AUART1_RX AUART D Application UART1 RX AUART1_RX PWM_0
TECT
Application UART2 CTS Flow EN-

AUART3_CTS AUART D AUART3_CTS CAN1_TX
Control ET0_1588_EVENT1_OUT

EN-
AUART3_RX AUART D Application UART2 RX AUART3_RX CAN0_TX
ET0_1588_EVENT0_OUT
Table 8-7. CAN


EN-
ET0_1588_EVENT0_IN

EN-
ET0_1588_EVENT0_OUT
GPMI_CE2N GPMI D NAND Chip Enable 2 GPMI_CE2N CAN1_TX ENET0_RX_ER
GPMI_RDY2 GPMI D NAND2 Ready/Busy# GPMI_READY2 CAN0_TX ENET0_TX_ER
GPMI_CE3N GPMI D NAND Chip Enable 3 GPMI_CE3N CAN1_RX SAIF1_MCLK
GPMI_RDY3 GPMI D NAND3 Ready/Busy# GPMI_READY3 CAN0_RX HSADC_TRIGGER
Table 8-8. DUART

I2C0_SDA I2C D I2C0 Serial Data I2C0_SDA TIMROT_ROTARYB DUART_TX
I2C0_SCL I2C D I2C0 Serial Clock I2C0_SCL TIMROT_ROTARYA DUART_RX

AUART0_RTS AUART D AUART0_RTS AUART4_TX DUART_TX
Control

AUART0_CTS AUART D AUART0_CTS AUART4_RX DUART_RX
Control
PWM0 PWM D PWM_0 I2C1_SCL DUART_RX
PWM1 PWM D PWM_1 I2C1_SDA DUART_TX

Table 8-9. EMI

EMI_A13 EMI E EMI Address 13
EMI_CE0N EMI E EMI CE0n
EMI_CE1N EMI E EMI CE1n
EMI_BA1 EMI E EMI Bank Address 1
EMI_ODT1 EMI E EMI DDR Byte1 ODT Enable
EMI_ODT0 EMI E EMI DDR Byte0 ODT Enable
EMI_RASN EMI E EMI RASn
EMI_CASN EMI E EMI CASn
EMI_WEN EMI E EMI WEn
EMI_CKE EMI E EMI Clock Enable

EMI_D05 EMI E EMI Data 5
EMI_DQM0 EMI E EMI DDR Data Mask 0 (Low Byte)
EMI_CLK EMI E EMI Clock
EMI_CLKN EMI E EMI Clock Invert
EMI_DQS0 EMI E EMI DDR Data Strobe 0 (Low Byte)
EMI_DQS0N EMI E EMI DDR Data Strobe 0 Invert (Low Byte)
EMI_DQS1 EMI E EMI DDR Data Strobe 1
EMI_DQS1N EMI E EMI DDR Data Strobe 1 Invert
EMI_DDR_OPEN_FB EMI E EMI DDR Echo Gating feedback
EMI_DDR_OPEN EMI E EMI DDR DDR Echo Gating
EMI_DQM1 EMI E EMI DDR Data Mask 1

Table 8-10. ENET

EN-
ENET D reference clock CLK_ENET ENET1_RX_ER
ET_CLK
SPDIF SPDIF D SPDIF_TX ENET1_RX_ER
EN-
ET1_1588_EVENT0_OUT
EN-
SSP3_MISO SSP D SD/MMC/Data0 / SPI MISO SSP3_D0 AUART4_RTS
ET1_1588_EVENT1_OUT
EN-
SSP1_SCK SSP D SSP Serial Clock SSP1_SCK SSP2_D1
ET0_1588_EVENT2_OUT
EN-
ET1_1588_EVENT0_IN
EN-
SSP1_CMD SSP D SD/MMC CMD / SPI MOSI SSP1_CMD SSP2_D2
ET0_1588_EVENT2_IN

EN-
SSP1_DATA0 SSP D SD/MMC/ Data0 / SPI MISO SSP1_D0 SSP2_D6
ET0_1588_EVENT3_OUT
SD/MMC/ Data3 / SPI Slave EN-

SSP1_DATA3 SSP D SSP1_D3 SSP2_D7
EN- DataValid/CRS_DV carrier

ENET D ENET0_RX_EN GPMI_CE6N SAIF1_SDATA1
ET0_RX_EN sense
EN- EN-
ENET D transmit clock ENET0_TX_CLK HSADC_TRIGGER
ET0_TX_CLK ET0_1588_EVENT2_OUT
EN-
ENET D Transmit data valid ENET0_TX_EN GPMI_READY5
ET0_TX_EN
EN- EN-
ENET D receive clock ENET0_RX_CLK ENET0_RX_ER
ET0_RX_CLK ET0_1588_EVENT2_IN
EN-
ENET D Transmit DATA1 ENET0_TXD1 GPMI_READY7
ET0_TXD1
EN-
ENET D Transmit DATA0 ENET0_TXD0 GPMI_READY6
ET0_TXD0
EN-
ENET D ENET0_MDC GPMI_CE4N SAIF0_SDATA1
ET0_MDC
EN- EN-
ENET D Transmit DATA3 ENET0_TXD3 ENET1_TXD1
ET0_TXD3 ET0_1588_EVENT1_IN

EN- EN-
ENET D Transmit DATA2 ENET0_TXD2 ENET1_TXD0
ET0_TXD2 ET0_1588_EVENT1_OUT
EN-
ENET D Management data ENET0_MDIO GPMI_CE5N SAIF0_SDATA2
ET0_MDIO
EN-
ENET D ENET0_RXD1 GPMI_READY4
ET0_RXD1
EN-
ENET D Receive DATA0 ENET0_RXD0 GPMI_CE7N SAIF1_SDATA2
ET0_RXD0
EN- EN-
ENET D collision detect ENET0_COL ENET1_TX_EN
ET0_COL ET0_1588_EVENT3_OUT
EN- EN-
ENET D carrier sense ENET0_CRS ENET1_RX_EN
ET0_CRS ET0_1588_EVENT3_IN
EN- EN-
ENET D Receive DATA3 ENET0_RXD3 ENET1_RXD1
ET0_RXD3 ET0_1588_EVENT0_IN
EN- EN-
ENET D ENET0_RXD2 ENET0_RXD2 ENET1_RXD0
ET0_RXD2 ET0_1588_EVENT0_OUT

EN-
ET0_1588_EVENT0_IN

EN-
ET0_1588_EVENT0_OUT
EN-
LCD_D20 LCD D LCD Interface Data 20 LCD_D20 ETM_DA3
ET1_1588_EVENT2_OUT
EN-
ET1_1588_EVENT3_IN
EN-
ET1_1588_EVENT3_OUT
EN-
ET1_1588_EVENT2_IN

Table 8-11. ETM

LCD Interface 6800 R/W_ /

LCD_WR_RWN LCD D LCD_WR_RWN LCD_HSYNC ETM_TCLK
8080 W
LCD_D03 LCD D LCD Interface Data 03 LCD_D3 ETM_DA8 ETM_DA3
LCD_HSYNC LCD D LCD0 Horizontal Sync LCD_HSYNC SAIF1_SDATA1 ETM_TCTL
LCD_DOTCLK LCD D LCD Interface DOT clock LCD_DOTCLK SAIF1_MCLK ETM_TCLK
LCD Interface 6800 Enable /

LCD_RD_E LCD D LCD_RD_E LCD_VSYNC ETM_TCTL
8080 RD
EN-
ET1_1588_EVENT2_OUT

EN-
ET1_1588_EVENT3_IN
EN-
ET1_1588_EVENT3_OUT
EN-
ET1_1588_EVENT2_IN
Table 8-12. GPMI

ENET0_RX_EN ENET D ENET0_RX_EN GPMI_CE6N SAIF1_SDATA1
ENET0_TX_EN ENET D RMII ENET0_TX_EN GPMI_READY5
ENET0_TXD1 ENET D ENET0_TXD1 GPMI_READY7
ENET0_TXD0 ENET D ENET0_TXD0 GPMI_READY6
ENET0_MDC ENET D ENET0_MDC ENET0_MDC GPMI_CE4N SAIF0_SDATA1
ENET0_MDIO ENET D ENET0_MDIO GPMI_CE5N SAIF0_SDATA2
ENET0_RXD1 ENET D Receive DATA1 ENET0_RXD1 GPMI_READY4
ENET0_RXD0 ENET D ENET0_RXD0 GPMI_CE7N SAIF1_SDATA2
SSP1_CARD_DE-
GPMI_RDY0 GPMI D NAND0 Ready/Busy# GPMI_READY0 USB0_ID
TECT
GPMI_ALE GPMI D NAND ALE GPMI_ALE SSP3_D1 SSP3_D4
GPMI_RDN GPMI D NAND Read Strobe GPMI_RDN SSP3_SCK
GPMI_D07 GPMI D NAND Data 7 GPMI_D7 SSP1_D7
GPMI_CE0N GPMI D NAND Chip Enable 0 GPMI_CE0N SSP3_D0
GPMI_CLE GPMI D NAND CLE GPMI_CLE SSP3_D2 SSP3_D5

GPMI_RDY1 GPMI D NAND1 Ready/Busy# GPMI_READY1 SSP1_CMD
GPMI_WRN GPMI D NAND Write Strobe GPMI_WRN SSP1_SCK
GPMI_RESETN GPMI D NAND Write Protect GPMI_RESETN SSP3_CMD
HSADC_TRIG-
GPMI_RDY3 GPMI D NAND3 Ready/Busy# GPMI_READY3 CAN0_RX
GER
Table 8-13. HSADC

HSADC_TRIG- EN-
ENET0_TX_CLK ENET D ENET0_TX_CLK
GER ET0_1588_EVENT2_OUT
NAND3
GPMI_RDY3 GPMI D GPMI_READY3 CAN0_RX HSADC_TRIGGER
Ready/Busy#
Table 8-14. I2C

TIM-
I2C0_SDA I2C D I2C0 Serial Data I2C0_SDA DUART_TX
ROT_ROTARYB
TIM-
I2C0_SCL I2C D I2C0 Serial Clock I2C0_SCL DUART_RX
ROT_ROTARYA
Application UART2 RTS

Flow Control
Application UART2 CTS

Flow Control

Table 8-15. JTAG

DEBUG SYSTEM D ARM jtag chain/Boundary scan chain selection
TESTMODE SYSTEM D Test Mode Pin
JTAG_RTCK SYSTEM D JTAG feedback clock (only for ARM ICE)
JTAG_TRST SYSTEM D JTAG Reset
JTAG_TDO SYSTEM D JTAG Serial Data Out
JTAG_TMS SYSTEM D JTAG Test Mode Select
JTAG_TDI SYSTEM D JTAG Serial Data In
JTAG_TCK SYSTEM D JTAG Clock
Table 8-16. LCD

LCD Interface Data

LCD_D01 LCD D LCD_D1 ETM_DA1
01
LCD Interface Data

00
LCD Interface 6800

LCD_WR_RWN LCD D LCD_WR_RWN LCD_HSYNC ETM_TCLK
R/W_ / 8080 W
LCD Interface Data

LCD_D03 LCD D LCD_D3 ETM_DA8 ETM_DA3
03
LCD Interface Data

02
LCD Interface Vertical

LCD_VSYNC LCD D LCD_VSYNC SAIF1_SDATA0
Sync
LCD Interface Re-

LCD_RS LCD D LCD_RS LCD_DOTCLK
gister Select
LCD Interface Data

05
LCD Interface Data

04
LCD0 Horizontal
LCD_HSYNC LCD D LCD_HSYNC SAIF1_SDATA1 ETM_TCTL
Sync
LCD_D06 LCD D LCD Interface Data LCD_D6 ETM_DA6

06

LCD Interface DOT

LCD_DOTCLK LCD D LCD_DOTCLK SAIF1_MCLK ETM_TCLK
clock
LCD_ENABLE LCD D LCD Interface Enable LCD_ENABLE
LCD Interface 6800

LCD_RD_E LCD D LCD_RD_E LCD_VSYNC ETM_TCTL
Enable / 8080 RD
LCD Interface Data

09
LCD Interface Data

08
LCD Interface Data

07
LCD Interface Data

17
LCD Interface Data

11
LCD Interface Data

10
LCD Interface Data

16
LCD Interface Data

13
LCD Interface Data

12
LCD Interface Data

14
LCD Interface Data

15
LCD Interface Data EN-

20 ET1_1588_EVENT2_OUT
LCD Interface Data

19
LCD Interface Data

18
LCD Interface Chip

LCD_CS LCD D LCD_CS LCD_ENABLE
Select

23 ET1_1588_EVENT3_IN


22 ET1_1588_EVENT3_OUT

21 ET1_1588_EVENT2_IN
LCD Interface Reset

LCD_RESET LCD D LCD_RESET LCD_VSYNC
Out
Table 8-17. PWM

SAIF1_SDATA0 SAIF D SAIF1 Serial Data0 (stereo) SAIF1_SDATA0 PWM_7 SAIF0_SDATA1
PWM3 PWM D PWM_3
PWM4 PWM D PWM_4
SAIF0_BITCLK SAIF D SAIF0 BIT clock SAIF0_BITCLK PWM_5 AUART4_RX
SAIF0_MCLK SAIF D SAIF0 Master Clock SAIF0_MCLK PWM_3 AUART4_CTS
SSP3_CARD_DE-
TECT
SSP2_CARD_DE-
TECT
USB1_OVER-
PWM2 PWM D PWM_2 USB0_ID
CURRENT
Table 8-18. AUDIO(SAIF/SPDIF)

SAIF1_SDATA0 SAIF D SAIF1 Serial Data0 (stereo) SAIF1_SDATA0 PWM_7 SAIF0_SDATA1


Select 0
SAIF0_BITCLK SAIF D SAIF0_BITCLK PWM_5 AUART4_RX
SD/MMC CMD / BS / SPI

SSP2_MOSI SSP D SSP2_CMD AUART2_TX SAIF0_SDATA2
MOSI
SAIF0_MCLK SAIF D SAIF0_MCLK PWM_3 AUART4_CTS
ENET0_RX_EN ENET D ENET0_RX_EN GPMI_CE6N SAIF1_SDATA1

Control

Control
ENET0_MDC ENET D ENET0_MDC GPMI_CE4N SAIF0_SDATA1
ENET0_MDIO ENET D ENET0_MDIO GPMI_CE5N SAIF0_SDATA2
ENET0_RXD0 ENET D ENET0_RXD0 GPMI_CE7N SAIF1_SDATA2
LCD_VSYNC LCD D LCD Interface Vertical Sync LCD_VSYNC SAIF1_SDATA0
LCD_HSYNC LCD D LCD0 Horizontal Sync LCD_HSYNC SAIF1_SDATA1 ETM_TCTL
LCD_DOTCLK LCD D LCD Interface DOT clock LCD_DOTCLK SAIF1_MCLK ETM_TCLK
SPDIF SPDIF D SPDIF_TX ENET1_RX_ER
Table 8-19. SSP

SSP0_DE- SSP0_CARD_DE-
SSP D Removable Card Detect
TECT TECT
SSP0_SCK SSP D SSP Serial Clock SSP0_SCK
SSP0_DATA0 SSP D SD/MMC/Data0 / SPI MISO SSP0_D0

SSP0_DATA3 SSP D SSP0_D3
Select 0
SSP0_DATA4 SSP D SD/MMC/Data4 / SPI Slave SSP0_D4 SSP2_D0

Select 1
SSP0_DATA1 SSP D SD/MMC/ Data1 / Winbond SSP0_D1

Write Protect_

SSP0_CMD SSP D SD/MMC CMD / SPI MOSI SSP0_CMD
SSP0_DATA7 SSP D SD/MMC/Data7 SSP0_D7 SSP2_SCK
SSP0_DATA5 SSP D SD/MMC/Data5 / SPI Slave SSP0_D5 SSP2_D3

Select 2
SD/MMC/Data2 / Winbond
SSP0_DATA2 SSP D SSP0_D2
Hold_
EN-
ET1_1588_EVENT0_OUT
SD/MMC/Memstick Data3 /
SPI Slave Select 0
SSP0_DATA6 SSP D SD/MMC/Memstick Data6 SSP0_D6 SSP2_CMD
SD/MMC/Memstick Data0 / EN-

SSP3_MISO SSP D SSP3_D0 AUART4_RTS
SPI MISO ET1_1588_EVENT1_OUT
SD/MMC CMD / Memstick BS

SSP2_MOSI SSP D SSP2_CMD AUART2_TX SAIF0_SDATA2
/ SPI MOSI
SD/MMC/Memstick Data0 / USB0_OVERCUR-

SSP2_SS2 SSP D SSP2_D5 SSP2_D2
SPI MISO RENT
AUART2_RX AUART D AUART2_RX SSP3_D1 SSP3_D4
EN-
SSP1_SCK SSP D SSP Serial Clock SSP1_SCK SSP2_D1
ET0_1588_EVENT2_OUT
EN-
ET1_1588_EVENT0_IN
SD/MMC/Data4 / SPI Slave USB1_OVERCUR-

Select 1 RENT
EN-
SSP1_CMD SSP D SD/MMC CMD / SPI MOSI SSP1_CMD SSP2_D2
ET0_1588_EVENT2_IN

EN-
SSP1_DATA0 SSP D SD/MMC/Data0 / SPI MISO SSP1_D0 SSP2_D6
ET0_1588_EVENT3_OUT

SSP1_DATA3 SSP D SSP1_D3 SSP2_D7
AUART2_TX AUART D Application UART2 TX AUART2_TX SSP3_D2 SSP3_D5

SSP3_CARD_DE-
TECT
SSP2_CARD_DE-
TECT
SSP1_CARD_DE-
TECT
GPMI_ALE GPMI D NAND ALE GPMI_ALE SSP3_D1 SSP3_D4
GPMI_RDN GPMI D NAND Read Strobe GPMI_RDN SSP3_SCK
GPMI_CLE GPMI D NAND CLE GPMI_CLE SSP3_D2 SSP3_D5
GPMI_RDY1 GPMI D NAND1 Ready/Busy# GPMI_READY1 SSP1_CMD
GPMI_WRN GPMI D NAND Write Strobe GPMI_WRN SSP1_SCK
GPMI_RE-
GPMI D NAND Write Protect GPMI_RESETN SSP3_CMD
SETN
Table 8-20. TIMROT

TIM-
I2C0_SDA I2C D I2C0 Serial Data I2C0_SDA DUART_TX
ROT_ROTARYB
TIM-
I2C0_SCL I2C D I2C0 Serial Clock I2C0_SCL DUART_RX
ROT_ROTARYA
Application UART1 RTS Flow TIM-

AUART1_RTS AUART D AUART1_RTS USB0_ID
Control ROT_ROTARYB

Application UART1 CTS Flow USB0_OVERCUR- TIM-

AUART1_CTS AUART D AUART1_CTS
Control RENT ROT_ROTARYA
Table 8-21. USB

SD/MMC/Data3 / SPI Slave USB0_OVERCUR-

Select 0 RENT
USB1_OVERCUR-
SSP2_SS1 SSP D SD/MMC/Data0 / SPI MISO SSP2_D4 SSP2_D1
RENT
Application UART1 RTS Flow TIM-

AUART1_RTS AUART D AUART1_RTS USB0_ID
Control ROT_ROTARYB
Application UART1 CTS Flow USB0_OVERCUR- TIM-

AUART1_CTS AUART D AUART1_CTS
Control RENT ROT_ROTARYA
USB1_OVERCUR-
PWM2 PWM D PWM_2 USB0_ID
RENT
SSP1_CARD_DE-
TECT

Chapter 9
Pin Control and GPIO (PinCtrl)
9.1 Pin Control and GPIO Overview

The i.MX28 digital interface pins have the following features: (In the context of this chapter,
"digital pin" means the standard digital interface pins. This does not include test pins used
for boundary scan control.)
• The device has seven banks of pins, Banks 0~4 serve as GPIOs. Banks 5 and 6 contain
the EMI sixteen data pins and EMI control/address signals, they are not multiplexed
with other functions since all the use cases require at least sixteen bit external memory.
• Each GPIO pin has separate control on voltage(1.8 V/3.3 V), Interrupt (trigger
type/polarity).
• All non-EMI digital pins have selectable output drive strengths as described in Pin
Drive Strength Selection.
• Each group of EMI data[7:0], data[15:8], control pins and address pins, dual pads
(clk/clkn/dqs#/dqs#n), have selectable output drive strengths.
• All digital pins have weak internal keepers to minimize power loss due to undriven
pins.
• All EMI pins' internal keepers can be disabled to allow them to change to a
high-impedance state (as required by some DRAM manufacturers).
• The following pin interfaces have selectable pull up resistors:
• SSP data - 47 kΩ
• SSP command/detect - 10 kΩ
• GPMI chip enable - 47 kΩ
• GPMI ready/busy - 10 kΩ
• The following pin interfaces are slow transitioning pins with internal Schmidt Triggers
for noise immunity:

Operation
• I2C SCL
• I2C SDA
9.2 Operation
Each individual digital pin supporting the GPIO operation may be dynamically programmed
at any time to be in one of the following states:
• High-impedance (for input, three-state, or open-drain applications)
• Low
• High
• Controlled by one to three selectable on-chip peripheral module interfaces, on a pin by
pin basis, as described in GPIO Interface.
All non-EMI digital pins can be programmed for 1.8 or 3.3 V operation. All EMI pads run
at 1.8 V/1.5 V.
Selected pins have pullups that can be configured using register settings. When pullups are
enabled, the pin's weak keeper devices are disabled.
Additionally, the state of each pin may be read at any time (no matter how it is configured),
and its drive strength may be configured as described in Pin Drive Strength Selection.
Each GPIO pin may also be used as an interrupt input and the interrupt trigger type may be
configured to be low level-sensitive, high level-sensitive, rising edge-sensitive, or falling
edge-sensitive.
The following sections show how to use all the features of each pin.

Chapter 9 Pin Control and GPIO (PinCtrl)
HARDWARE_FUNCTION_DOE0
OE#
Drive
HW_PINCTRL_DOEx Strength
GPIO Output Enable
HW_PINCTRL_DRIVEx
HW_PINCTRL_MUXSELx
HARDWARE_FUNCTION_DO0 OUTPUT Pad Power

HARDWARE_FUNCTION_DO1 Integrated Pull-up (available only on
10 K
HARDWARE_FUNCTION_DO2 EN or certain pins). Enabling the internal
47 K pull-up disables the Gate Keeper.
GPIO Output HW_PINCTRL_DOUTx HW_PINCTRL_PULLx
Pad Power
PAD
Gate Keeper.
Note external 47K ( or
HARDWARE_FUNCTION_DI0 stronger) pull-ups or
HARDWARE_FUNCTION_DI1
pull-downs are needed
EN to overdrive Gate Keepers
HARDWARE_FUNCTION_DI2
HW_PINCTRL_MUXSELx
INPUT
GPIO Input HW_PINCTRL_DINx
Figure 9-1. Pad Diagram
9.2.1 Reset Configuration

Out of reset (hardware/software reset), all the pins (except JTAG related) are configured
as GPIO inputs with gate keepers enabled.
Here are some exceptions on general reset behavior:
• Ethernet pins works differently, they will only reset when power is on. Software reset
will not affect them. This is to make sure that the enet switch can still work during
software reset.
• EMI pins do not mux with GPIO function. So after reset, configure as GPIO means it
is disabled.
.
9.2.2 Pin Interface Multiplexing

The device is designed for cost sensitive applications. It contains a rich set of specialized
hardware interfaces (mDDR, NAND Flash, LCD panels, many types of insertable media,
and so on), but does not have enough pins to allow use of all signals of all the interfaces
simultaneously. Consequently, a pin multiplexing scheme is used to allow customers to
choose which specialized interfaces to enable for their application. In addition to these
specialized hardware interfaces, the device allows many digital pins to be used as GPIOs.

Operation
This capability supports custom interfacing requirements, such as the ability to communicate
with LEDs, digital buttons, and other devices that are not directly supported by any of the
i.MX28 specialized hardware interfaces.
Each pin is connected to one, two, or three specialized hardware interfaces, in addition to
the GPIO function available on banks 0 through 4. The description of each pin in and
contains full details of which specialized hardware interfaces are attached to that pin. For
example, the package pin named PWM0 is shared between the PWM and debug UART
hardware interfaces.
Users define which of the available hardware interfaces controls each pin by writing a
two-bit field for that pin into one of the HW_PINCTRL_MUXSELx registers.
Table 9-1– Table 9-2 illustrate the pin multiplexing on the device.
Both 289 and 204 packages have same mux options, but some pins on 289 package are not
available on 204 package and caused those related mux unavailable too. These unavailable
pins for 204-pins package are marked gray on muxreg row in .
• Table 9-1 shows the color mapping used in the tables.
• Table 9-2 shows the multiplexing used in both the package.
Table 9-1. Color Mapping for Pin Control Bank Tables

EMI GPIO GPMI LCD SSP ENET USB
ETM DUART AUART I2C PWM SAIF SPDIF JTAG
Table 9-2. Pin Multiplexing for the 289-pin Package

Bank
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
Mux
Reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
gpmi_d6_gpmi_d7
se-
gpmi_d7
gpmi_d5
gpmi_d4
gpmi_d3
gpmi_d2
gpmi_d1
gpmi_d0
lect
=
00
se-
ssp1_d7
ssp1_d6
ssp1_d5
ssp1_d4
ssp1_d3
ssp1_d2
ssp1_d1
ssp1_d0
lect
=
01

se-
lect
=
10
se-
lect
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
=
11
Bank
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
Mux
Reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
gpmi_ready3
gpmi_ready2
gpmi_ready1
gpmi_ready0
gpmi_resetn
se-
gpmi_ce3n
gpmi_ce2n
gpmi_ce1n
gpmi_ce0n
gpmi_wrn
gpmi_rdn
gpmi_ale
gpmi_cle
lect
=
00
ssp1_card_detect
se-
ssp3_cmd
ssp1_cmd
ssp1_sck
ssp3_sck
ssp3_d2
ssp3_d1
ssp3_d3
ssp3_d0
can0_rx
can1_rx
can0_tx
can1_tx
lect
=
01
hsadc_trigger
enet0_rx_er
enet0_tx_er
se-
saif1_mclk
ssp3_d5
ssp3_d4
usb0_id
lect
=
10
se-
lect
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
=
11
Bank
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
Mux
Reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2
se-
lcd_d15
lcd_d14
lcd_d13
lcd_d12
lcd_d11
lcd_d10
lcd_d9
lcd_d8
lcd_d7
lcd_d6
lcd_d5
lcd_d4
lcd_d3
lcd_d2
lcd_d1
lcd_d0
lect
=
00

Operation
se-
lect
=
01
se-
etm_da15
etm_da14
etm_da13
etm_da12
etm_da11
etm_da10
etm_da9
etm_da8
etm_da7
etm_da5
etm_da6
etm_da4
etm_da3
etm_da2
etm_da1
etm_da0
lect
=
10
se-
lect
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
=
11
Bank
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
Mux
Reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
3
se-
lcd_wr_rwn
lcd_enable
lcd_dotclk
lcd_hsync
lcd_vsync
lcd_rd_e
lcd_d23
lcd_d22
lcd_d21
lcd_d20
lcd_d19
lcd_d18
lcd_d17
lcd_d16
lcd_cs
lect
lcd_rs
=
00
enet1_1588_event3_out
enet1_1588_event2_out
enet1_1588_event3_in
enet1_1588_event2_in
se-
lcd_enable
lcd_dotclk
lcd_hsync
lcd_vsync
lect
=
01
se-
etm_da0
etm_da1
etm_da2
etm_da3
etm_da4
etm_da5
etm_da6
etm_da7
etm_tclk
etm_tclk
etm_tclk
etm_tctl
lect
=
10
se-
lect
=
11
Bank
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2
Mux
Reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4

5
2
=
=
=
=
=
=
=
10
01
00
11
10
01
00
se-
se-
se-
se-
se-
se-
se-
lect
lect
lect
Mux
Bank
lect
lect
lect
lect
enet0_1588_event3_in ssp2_d7 ssp1_d3
31
enet0_1588_event3_out ssp2_d6 ssp1_d0
30
enet0_1588_event2_in ssp2_d2 ssp1_cmd
29
Freescale Semiconductor, Inc.

enet0_1588_event2_out ssp2_d1 ssp1_sck
28
GPIO GPIO GPIO GPIO
enet1_1588_event1_in auart4_cts ssp3_d3
27
enet1_1588_event1_out auart4_rts ssp3_d0 ssp0_sck
26
enet1_1588_event0_in auart4_rx ssp3_cmd ssp0_card_detect
25
enet1_1588_event0_out auart4_tx ssp3_sck ssp0_cmd
24
ssp2_sck ssp0_d7
23
ssp2_cmd ssp0_d6
22
usb0_overcurrent ssp2_d2 ssp2_d5 ssp2_d3 ssp0_d5
21
Reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
usb1_overcurrent ssp2_d1 ssp2_d4 ssp2_d0 ssp0_d4
20
8
7
saif1_sdata2 auart3_tx ssp2_d3 ssp0_d3

19
6
5
saif1_sdata1 auart3_rx ssp2_d0 ssp0_d2

18
4
3
saif0_sdata2 auart2_tx ssp2_cmd ssp0_d1

17
2
1
saif0_sdata1 auart2_rx ssp2_sck ssp0_d0

16
0
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
675
7
3
6
3
=
=
=
=
=
=
676
00
11
10
01
00
11
se-
se-
se-
se-
se-
se-
lect
Mux
Bank
lect
lect
lect
lect
Mux
Bank
lect
enet0_1588_event1_in can1_rx auart3_rts
31
15
Operation
lcd_reset enet0_1588_event1_out can1_tx auart3_cts
30
14
enet0_1588_event0_in can0_rx auart3_tx
29
13
enet0_1588_event0_out can0_tx auart3_rx
28
12
spdif_tx saif1_lrclk i2c1_sda auart2_rts
27
11
saif1_sdata0 saif1_bitclk i2c1_scl auart2_cts
26
10
i2c0_sda ssp3_d5 ssp3_d2 auart2_tx

9
25
i2c0_scl ssp3_d4 ssp3_d1 auart2_rx
8
24
GPIO GPIO GPIO GPIO
saif0_sdata0 timrot_rotaryb usb0_id auart1_rts

7
23
saif0_bitclk timrot_rotarya usb0_overcurrent auart1_cts
6
22
saif0_lrclk pwm_1 ssp3_card_detect auart1_tx
5
21
Reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
saif0_mclk pwm_0 ssp2_card_detect auart1_rx

4
20
8
8
7
7
duart_tx auart4_tx auart0_rts

3
19
6
6
5
5
pwm_2 duart_rx auart4_rx auart0_cts

2
18
4
4
3
3
pwm_1 duart_rts i2c0_sda auart0_tx

1
17
2
2
1
1
pwm_0 duart_cts i2c0_scl auart0_rx

0
16
0
0
GPIO GPIO GPIO GPIO GPIO GPIO

4
8
4
=
=
=
=
=
=
=
11
10
01
00
11
10
01
se-
se-
se-
se-
se-
se-
se-
Bank
lect
lect
lect
lect
Mux
Bank
lect
lect
lect
enet0_1588_event3_in enet1_rx_en enet0_crs
31
15
enet0_1588_event3_out enet1_tx_en enet0_col lcd_vsync
30
14
GPIO
enet0_1588_event2_in enet0_rx_er enet0_rx_clk
29
13

enet0_1588_event1_in enet1_txd1 enet0_txd3
28
12
enet0_1588_event1_out enet1_txd0 enet0_txd2 enet1_rx_er
27
11
enet0_1588_event0_in enet1_rxd1 enet0_rxd3 saif0_sdata1 pwm_7
26
10
enet0_1588_event0_out enet1_rxd0 enet0_rxd2 duart_tx timrot_rotaryb
25
gpmi_ready7 enet0_txd1 duart_rx timrot_rotarya
8
24
gpmi_ready6 enet0_txd0 auart4_tx pwm_6
7
23
gpmi_ready5 enet0_tx_en auart4_rx pwm_5
6
22
enet0_1588_event2_out hsadc_trigger enet0_tx_clk auart4_rts pwm_4
5
21
Reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
gpmi_ready4 enet0_rxd1 auart4_cts pwm_3

4
20
8
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
saif1_sdata2 gpmi_ce7n enet0_rxd0

3
19
6
5
saif1_sdata1 gpmi_ce6n enet0_rx_en usb1_overcurrent usb0_id

2
18
4
3
saif0_sdata2 gpmi_ce5n enet0_mdio duart_tx i2c1_sda

1
17
2
1
saif0_sdata1 gpmi_ce4n enet0_mdc duart_rx i2c1_scl

0
16
0
GPIO GPIO GPIO
677
Operation
Mux
Reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
9
se-
clkctrl_enet
jtag_rtck
lect
=
00
se-
lect
=
01
se-
lect
=
10
se-
lect
=
11
Bank
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
5
Mux
Reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
10
emi_data15
emi_data14
emi_data13
emi_data12
emi_data11
emi_data10
se-
emi_data9
emi_data8
emi_data7
emi_data6
emi_data5
emi_data4
emi_data3
emi_data2
emi_data1
emi_data0
lect
=
00
se-
lect
=
01
se-
lect
=
10
se-
lect dis- dis- dis- dis- dis- dis- dis- dis- dis- dis- dis- dis- dis- dis- dis- dis-
= abled abled abled abled abled abled abled abled abled abled abled abled abled abled abled abled
11
Bank
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
5

Mux
Reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
11
emi_ddr_open_feedback
emi_ddr_open
se-
emi_dqm1
emi_dqm0
emi_dqs1
emi_dqs0
emi_odt1
emi_odt0
emi_clk
lect
=
00
se-
lect
=
01
se-
lect
=
10
se-
lect dis- dis- dis- dis- dis- dis- dis- dis- dis-
= abled abled abled abled abled abled abled abled abled
11
Bank
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
6
Mux
Reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
12
emi_addr14
emi_addr13
emi_addr12
emi_addr11
emi_addr10
se-
emi_addr9
emi_addr8
emi_addr7
emi_addr6
emi_addr5
emi_addr4
emi_addr3
emi_addr2
emi_addr1
emi_addr0
lect
=
00
se-
lect
=
01
se-
lect
=
10
se-
lect dis- dis- dis- dis- dis- dis- dis- dis- dis- dis- dis- dis- dis- dis- dis-
= abled abled abled abled abled abled abled abled abled abled abled abled abled abled abled
11

Operation
Bank
31 30 29 28 26 25 24 23 22 21 20 19 18 17 16
6
Mux
Reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
13
se-
emi_ce1n
emi_ce0n
emi_casn
emi_rasn
emi_wen
emi_ba2
emi_ba1
emi_ba0
emi_cke
lect
=
00
se-
lect
=
01
se-
lect
=
10
se-
lect dis- dis- dis- dis- dis- dis- dis- dis- dis-
= abled abled abled abled abled abled abled abled abled
11
Readback registers are never affected by the operation of the HW_PINCTRL_MUXSELx

registers and always sense the actual value on the data pin.
For example, if a pin is programmed to be a GPIO output and then driven high, then any
specialized hardware interfaces that are actively monitoring that pin will read the high logic
value. Conversely, if the pin mux is programmed to give a specialized hardware interface
such as the GPMI block control of a particular pin, the current state of that pin can be read
through its GPIO read register at any time, even while active GPMI cycles are in progress.
This is not true for the EMI pads that are GPIO capable due to the pad design.
Because the pin mux configuration is independent for each individual pin, many pins which
are not required for a given active interface can be reused as GPIO pins. For example, the
LCD_RESET pin can be configured and controlled as a GPIO pin, while the other LCD
interface pins are still controlled by the LCDIF.
Banks 5 and 6 are for the EMI only and do not have GPIO capability.
9.2.2.1 Pin Drive Strength Selection

The drive strength for each digital pin can be programmed by setting the bit corresponding
to that pin in one of the HW_PINCTRL_DRIVEx registers. All digital pins have selectable
output drive strengths of 4, 8, and 12 mA, with the following exceptions:

• All clock pads have 8 and 16mA drive strength.

• All EMI pads have 5, 10 and 20 mA drive strengths.
Note
The HW_PINCTRL_DRIVEx registers must be configured prior
to the operation of the pins and cannot be changed mid-course
during active operation. Drive-strength options are provided to
optimize simultaneous switching output (SSO) noise. The majority
of GPIO pins must be programmed in 4-mA mode. For EMI pins,
the weakest mode should be used as long as the timing is met.
Note
It is recommended that the drive strength of GPMI_RDn and
GPMI_WRn output pins be set to 8 mA. This will reduce the
transition time under heavy loads. Low transition times will be
important when NAND interface read and write cycle times are
below 30 ns. The other GPMI pins may remain at 4 mA, since
their frequency is only up to half that of GPMI_RDn and
GPMI_WRn.
9.2.2.2 Pin Voltage Selection

Each GPIO (non-EMI) pin can be programmed to operate at either 1.8 V or 3.3 V by setting
the bit corresponding to that pin in one of the HW_PINCTRL_DRIVEx registers. The EMI
pins are capable of running at 1.5/1.8 V depending on the EMI_VDDIO voltage.
Note
The GPIO pad driver has two PMOS pullup drivers directly
connected to the 1.8 or 3.3-V power supply.
9.2.2.3 Pullup Selection

Several digital pins can be programmed to enable pullups by setting the appropriate bit in
one of the HW_PINCTRL_PULLx registers. Note that enabling the pullup will also disable
the internal gate keeper on that pin. The EMI pads do not have pullup selection, but do have
keeper disable capability.

Operation
The pullups are tied to the physical pin pad and not to the function. So, for example, if the
AUART1_TX pullup is enabled, that pullup will be present on the AUART1_TX pin
regardless of what function (AUART1_TX, IR_TX, or SSP1_DATA7) is pin multiplexed
out of that pin.
The table below lists which function (not which pin name), an internal pullup has been
implemented, to assist in the hardware interfaces' operation.
Table 9-3. i.MX28 Functions with Pullup Resistors
Present on Present on 204-
FUNCTION Type Value 289BGA pins
SSP0_DATA0 Pullup 47K Y Y
SSP0_CMD Pullup 10K Y Y
SSP0_DETECT Pullup 10K Y Y

Present on Present on 204-

FUNCTION Type Value 289BGA pins
SSP2_DATA6 Pullup 47K Y N
GPMI_CE0N Pullup 47K Y Y
GPMI_CE1N Pullup 47K Y Y
GPMI_CE2N Pullup 47K Y N
GPMI_CE3N Pullup 47K Y N
GPMI_RDY0 Pullup 10K Y Y
GPMI_RDY1 Pullup 10K Y Y
GPMI_RDY2 Pullup 10K Y N
GPMI_RDY3 Pullup 10K Y N

Operation
9.2.3 GPIO Interface

The registers discussed in the following sections exist within each of the three GPIO banks
to configure the chip's digital pins. Some pins exist in the 289-pin package only. The registers
that control those pins exist but do not perform any useful function when in a 204-pin
package.
9.2.3.1 Output Operation

Programming and controlling a digital pin as a GPIO output is accomplished by programming
the appropriate bits in four registers, as shown in the figure below.
• After setting the field in the HW_PINCTRL_MUXSELx to program for GPIO control,
the HW_PINCTRL_DRIVEx register bit is set for the desired drive strength and pin
voltage. Set bits in HW_PINCTRL_PULLx as required to enable pullups.
• The HW_PINCTRL_DOUTx register bit is then loaded with the level that will initially
be driven on the pin.
• Finally, the HW_PINCTRL_DOEx register bit is set.
• Once set, the logic value the HW_PINCTRL_DOUTx bit will be driven on the pin and
the value can be toggled with repeated writes.

Begin
Write to HW_PINCTRL_MUXSELx
register bit to select pin as GPIO.
Write to HW_PINCTRL_DRIVEx
register bit to set current drive
strength. Set bits in
HW_PINCTRL_PULLx as
required to enable pullups.
Write to HW_PINCTRL_DOUTx
register bit to set the output value to
drive on the pin.
Write to HW_PINCTRL_DOEx
register bit to enable the data value to
be driven on the pin.
Re-write the HW_PINCTRL_DOUTx

register bit to change the value driven
on the pin.
End
Figure 9-2. GPIO Output Setup Flowchart
9.2.3.2 Input Operation

Digital pins in Banks 0~4 may be used as a GPIO input by programming its
HW_PINCTRL_MUXSELx field to 3 to enable GPIO mode, programming its
HW_PINCTRL_DOEx field to 0 to disable output, and then reading from the
HW_PINCTRL_DINx register, as shown in the figure below. Note that because of clock
synchronization issues, the logic levels read from the HW_PINCTRL_DINx registers are
delayed from the pins by several APBX clock cycles.

Operation
Begin
Write zero to HW_PINCTRL_DOEx

register bit to ensure pin is selected
as an input.
If applicable, set bits in

HW_PINCTRL_PULLx to enable
internal pull-up resistors.
Read HW_PINCTRL_DINx register bit

to get the value on the pin.
End
Figure 9-3. GPIO Input Setup Flowchart
9.2.3.3 Input Interrupt Operation

Programming and controlling a digital pin as a GPIO interrupt input is accomplished by
programming the appropriate bits in six registers, as shown in the figure below.
• After setting the HW_PINCTRL_MUXSELx register for GPIO, the
HW_PINCTRL_IRQLEVELx and HW_PINCTRL_IRQPOLx registers set the interrupt
trigger mode. A GPIO interrupt pin can be programmed in one of four trigger detect
modes: positive edge, negative edge, positive level, and negative level triggered.
• The HW_PINCTRL_IRQSTATx register bit should then be cleared to ensure that there
are no interrupts pending when enabled.
• Setting the HW_PINCTRL_PIN2IRQx register bit will then set up the pin to be an
interrupt pin.
• At this point, if an interrupt event occurs on the pin, it will be sensed and recorded in
the appropriate HW_PINCTRL_IRQSTATx bit.
• However, the interrupt will not be communicated back to the interrupt collector until
the HW_PINCTRL_IRQENx register bit is enabled.

Begin
Write zero to HW_PINCTRL_DOEx

register bit to ensure pin is selected
as an input.
If applicable, set bits in

HW_PINCTRL_PULLx to enable
internal pull-up resistors.
Write to HW_PINCTRL_IRQLEVELx
register bit to set level or edge
assertion.
Write to HW_PINCTRL_IRQPOLx
register bit to set high or low logic
assertion.
Write zero to
HW_PINCTRL_IRQSTATx register bit
to clear interrupts.
Write to HW_PINCTRL_PIN2IRQx
register bit to enable as an interrupt
pin.
Write to HW_PINCTRL_IRQENx
register bit to enable the interrupt
signal back to the Interrupt collector.
End
Figure 9-4. GPIO Interrupt Flowchart
The figure below shows the logic diagram for the interrupt-generation circuit.

1
HW_PINCTRL_STATxb
edge
SCT Clear write to GPIOx & (apb_wdata[b]== 1)
level
HW_PINCTRL_IRQENxb
HW_PINCTRL_PIN2IRQxb
from other
31 bits
HW_PINCTRL_IRQLEVELxb
[hw_pinctrl_ctrl_irqoutb]
HW_PINCTRL_CTRL
HIGH
LOW
RISE
FALL
pin GPxBb
HW_PINCTRL_IRQPOLxb
PINCTRL_IRQx
to CPU
HW_PINCTRL_DINxb
Internal Register
sync
Figure 9-5. GPIO Interrupt Generation

CLKGATE when setting SFTRST. The reset process gates the clocks automatically.
ENET pins will not be affected by SFTRST, it only resets when power is on.

PINCTRL Hardware Register Format Summary
HW_PINCTRL memory map
Absolute
Width Section/
(in bits) page
(hex)
8001_8000 PINCTRL Block Control Register (HW_PINCTRL_CTRL) 32 R/W C1F0_0000h 9.4.1/692
8001_8100 PINCTRL Pin Mux Select Register 0 32 R/W 0000_FFFFh 9.4.2/694
(HW_PINCTRL_MUXSEL0)

HW_PINCTRL memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
8001_8110 PINCTRL Pin Mux Select Register 1 32 R/W 03FF_FFFFh 9.4.3/696
8001_8120 PINCTRL Pin Mux Select Register 2 32 R/W FFFF_FFFFh 9.4.4/699
8001_8140 PINCTRL Pin Mux Select Register 4 32 R/W FF3F_FFFFh 9.4.6/705
8001_8150 PINCTRL Pin Mux Select Register 5 32 R/W 00FF_0FFFh 9.4.7/708
8001_8170 PINCTRL Pin Mux Select Register 7 32 R/W 3FFF_FF3Fh 9.4.9/713
8001_8190 PINCTRL Pin Mux Select Register 9 32 R/W 0000_0003h 9.4.11/719
8001_81A0 PINCTRL Pin Mux Select Register 10 32 R/W FFFF_FFFFh 9.4.12/720
8001_81B0 PINCTRL Pin Mux Select Register 11 32 R/W 0030_FFFFh 9.4.13/723
8001_81C0 PINCTRL Pin Mux Select Register 12 32 R/W 3FFF_FFFFh 9.4.14/725
8001_81D0 PINCTRL Pin Mux Select Register 13 32 R/W 0003_FFFFh 9.4.15/728
8001_8300 PINCTRL Drive Strength and Voltage Register 0 32 R/W 4444_4444h 9.4.16/730
(HW_PINCTRL_DRIVE0)
(HW_PINCTRL_DRIVE1)
(HW_PINCTRL_DRIVE2)
(HW_PINCTRL_DRIVE3)
(HW_PINCTRL_DRIVE4)
(HW_PINCTRL_DRIVE5)
(HW_PINCTRL_DRIVE6)
(HW_PINCTRL_DRIVE7)


Absolute
Width Section/
(in bits) page
(hex)
(HW_PINCTRL_DRIVE8)
(HW_PINCTRL_DRIVE9)
8001_83A0 PINCTRL Drive Strength and Voltage Register 10 32 R/W 0044_4444h 9.4.26/759
(HW_PINCTRL_DRIVE10)
8001_83B0 PINCTRL Drive Strength and Voltage Register 11 32 R/W 0000_4444h 9.4.27/762
8001_83C0 PINCTRL Drive Strength and Voltage Register 12 32 R/W 4444_4444h 9.4.28/764
8001_83D0 PINCTRL Drive Strength and Voltage Register 13 32 R/W 4444_4444h 9.4.29/767
8001_83E0 PINCTRL Drive Strength and Voltage Register 14 32 R/W 4444_0444h 9.4.30/770
8001_83F0 PINCTRL Drive Strength and Voltage Register 15 32 R/W 0444_4444h 9.4.31/773
8001_8430 PINCTRL Drive Strength and Voltage Register 19 32 R 0000_0000h 9.4.35/784
8001_8600 PINCTRL Bank 0 Pull Up Resistor Enable Register 32 R/W 0000_0000h 9.4.36/785
(HW_PINCTRL_PULL0)
(HW_PINCTRL_PULL1)
(HW_PINCTRL_PULL2)
(HW_PINCTRL_PULL3)
(HW_PINCTRL_PULL4)
8001_8650 PINCTRL Bank 5 Pad Keeper Disable Register 32 R/W 0000_0000h 9.4.41/796
(HW_PINCTRL_PULL5)
8001_8660 PINCTRL Bank 6 Pad Keeper Disable Register 32 R/W 0000_0000h 9.4.42/798
(HW_PINCTRL_PULL6)
8001_8700 PINCTRL Bank 0 Data Output Register 32 R/W 0000_0000h 9.4.43/800
(HW_PINCTRL_DOUT0)
(HW_PINCTRL_DOUT1)


Absolute
Width Section/
(in bits) page
(hex)
(HW_PINCTRL_DOUT2)
(HW_PINCTRL_DOUT3)
(HW_PINCTRL_DOUT4)
8001_8900 PINCTRL Bank 0 Data Input Register (HW_PINCTRL_DIN0) 32 R 0000_0000h 9.4.48/804
8001_8B00 PINCTRL Bank 0 Data Output Enable Register 32 R/W 0000_0000h 9.4.53/808
(HW_PINCTRL_DOE0)
(HW_PINCTRL_DOE1)
(HW_PINCTRL_DOE2)
(HW_PINCTRL_DOE3)
(HW_PINCTRL_DOE4)
8001_9000 PINCTRL Bank 0 Interrupt Select Register 32 R/W 0000_0000h 9.4.58/812
(HW_PINCTRL_PIN2IRQ0)
8001_9100 PINCTRL Bank 0 Interrupt Mask Register 32 R/W 0000_0000h 9.4.63/817
(HW_PINCTRL_IRQEN0)
(HW_PINCTRL_IRQEN1)
(HW_PINCTRL_IRQEN2)
(HW_PINCTRL_IRQEN3)


Absolute
Width Section/
(in bits) page
(hex)
(HW_PINCTRL_IRQEN4)
8001_9200 PINCTRL Bank 0 Interrupt Level/Edge Register 32 R/W 0000_0000h 9.4.68/822
(HW_PINCTRL_IRQLEVEL0)
8001_9300 PINCTRL Bank 0 Interrupt Polarity Register 32 R/W 0000_0000h 9.4.73/826
(HW_PINCTRL_IRQPOL0)
8001_9400 PINCTRL Bank 0 Interrupt Status Register 32 R/W 0000_0000h 9.4.78/831
(HW_PINCTRL_IRQSTAT0)
8001_9A40 PINCTRL EMI Slice ODT Control 32 R/W 0888_8888h 9.4.83/836
(HW_PINCTRL_EMI_ODT_CTRL)
8001_9B80 PINCTRL EMI Slice DS Control 32 R/W 0003_0000h 9.4.84/840
(HW_PINCTRL_EMI_DS_CTRL)
9.4.1 PINCTRL Block Control Register (HW_PINCTRL_CTRL)

The PINCTRL Block Control Register contains the block control bits and combined interrupt
output status for each PINCTRL bank.
HW_PINCTRL_CTRL: 0x000
HW_PINCTRL_CTRL_SET: 0x004
HW_PINCTRL_CTRL_CLR: 0x008
HW_PINCTRL_CTRL_TOG: 0x00C
This register contains block-wide control bits and combined bank interrupt status bits. For
normal operation, write a 0x0 into this register.
Address: HW_PINCTRL_CTRL – 8001_8000h base + 0h offset = 8001_8000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESENT4
PRESENT3
PRESENT2
PRESENT1
PRESENT0
R RSRVD2 RSRVD1[19:16]
CLKGATE
SFTRST
Reset 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRQOUT4
IRQOUT3
IRQOUT2
IRQOUT1
IRQOUT0
R RSRVD1[15:5]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_PINCTRL_CTRL field descriptions

Field Description
31 This bit must be set to zero to enable operation of any of the PINCTRL banks. When set to one, it forces a
SFTRST block-level reset.
30 This bit must be set to zero for normal operation. When set to one, it disables the block clock.
CLKGATE
RSRVD2
24 GPIO Functionality Present. 0: GPIO functionality for Pin Control Bank 4 is not present in this product. 1:
PRESENT4 GPIO functionality for Bank 4 is present.

HW_PINCTRL_CTRL field descriptions (continued)

Field Description

RSRVD1
4 Read-only view of the interrupt collector GPIO4 signal, sourced from the combined IRQ outputs from bank
IRQOUT4 4.
IRQOUT3 3.
IRQOUT2 2.
IRQOUT1 1.
IRQOUT0 0.
9.4.2 PINCTRL Pin Mux Select Register 0 (HW_PINCTRL_MUXSEL0)

The PINCTRL Pin Mux Select Register provides pin function selection for 8 pins in bank0.
HW_PINCTRL_MUXSEL0: 0x100
HW_PINCTRL_MUXSEL0_SET: 0x104
HW_PINCTRL_MUXSEL0_CLR: 0x108
HW_PINCTRL_MUXSEL0_TOG: 0x10C
This register allows the programmer to select which hardware interface blocks drive the 8
pins shown above.
Address: HW_PINCTRL_MUXSEL0 – 8001_8000h base + 100h offset = 8001_8100h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BANK0_ BANK0_ BANK0_ BANK0_ BANK0_ BANK0_ BANK0_ BANK0_
PIN07 PIN06 PIN05 PIN04 PIN03 PIN02 PIN01 PIN00
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
HW_PINCTRL_MUXSEL0 field descriptions

Field Description
RSRVD0
15–14 Pin 124, GPMI_D07 pin function selection:
BANK0_PIN07
00= gpmi_d7;
01= ssp1_d7;
10= reserved;
11= GPIO.

BANK0_PIN06
00= gpmi_d6;
01= ssp1_d6;
10= reserved;
11= GPIO.

BANK0_PIN05
00= gpmi_d5;
01= ssp1_d5;
10= reserved;
11= GPIO.

BANK0_PIN04
00= gpmi_d4;
01= ssp1_d4;
10= reserved;
11= GPIO.

BANK0_PIN03
00= gpmi_d3;
01= ssp1_d3;
10= reserved;
11= GPIO.

BANK0_PIN02
00= gpmi_d2;
01= ssp1_d2;

HW_PINCTRL_MUXSEL0 field descriptions (continued)

Field Description
10= reserved;
11= GPIO.

BANK0_PIN01
00= gpmi_d1;
01= ssp1_d1;
10= reserved;
11= GPIO.

BANK0_PIN00
00= gpmi_d0;
01= ssp1_d0;
10= reserved;
11= GPIO.

pins shown above.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD0
BANK0_ BANK0_ BANK0_ BANK0_ BANK0_
PIN28 PIN27 PIN26 PIN25 PIN24
W
Reset 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Field Description
RSRVD0
25–24 Pin 129, GPMI_RESETN pin function selection:
BANK0_PIN28
00= gpmi_resetn;
01= ssp3_cmd;
10= reserved;
11= GPIO.
23–22 Pin 123, GPMI_CLE pin function selection:

BANK0_PIN27
00= gpmi_cle;
01= ssp3_d2;
10= ssp3_d5;
11= GPIO.
21–20 Pin 117, GPMI_ALE pin function selection:

BANK0_PIN26
00= gpmi_ale;
01= ssp3_d1;
10= ssp3_d4;
11= GPIO.
19–18 Pin 127, GPMI_WRN pin function selection:

BANK0_PIN25
00= gpmi_wrn;
01= ssp1_sck;
10= reserved;
11= GPIO.
17–16 Pin 110, GPMI_RDN pin function selection:

BANK0_PIN24
00= gpmi_rdn;
01= ssp3_sck;
10= reserved;
11= GPIO.
15–14 Pin 80, GPMI_RDY3 pin function selection:

BANK0_PIN23
00= gpmi_ready3;
01= can0_rx;


Field Description
10= hsadc_trigger;
11= GPIO.

BANK0_PIN22
00= gpmi_ready2;
01= can0_tx;
10= enet0_tx_er;
11= GPIO.

BANK0_PIN21
00= gpmi_ready1;
01= ssp1_cmd;
10= reserved;
11= GPIO.

BANK0_PIN20
00= gpmi_ready0;
01= ssp1_card_detect;
10= usb0_id;
11= GPIO.
7–6 Pin 135, GPMI_CE3N pin function selection:

BANK0_PIN19
00= gpmi_ce3n;
01= can1_rx;
10= saif1_mclk;
11= GPIO.

BANK0_PIN18
00= gpmi_ce2n;
01= can1_tx;
10= enet0_rx_er;
11= GPIO.

BANK0_PIN17
00= gpmi_ce1n;
01= ssp3_d3;
10= reserved;
11= GPIO.

BANK0_PIN16
00= gpmi_ce0n;
01= ssp3_d0;


Field Description
10= reserved;
11= GPIO.

pins shown above.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Field Description
31–30 Pin 114, LCD_D15 pin function selection:
BANK1_PIN15
00= lcd_d15;
01= reserved;
10= etm_da15;
11= GPIO.

BANK1_PIN14


Field Description
00= lcd_d14;
01= reserved;
10= etm_da14;
11= GPIO.

BANK1_PIN13
00= lcd_d13;
01= reserved;
10= etm_da13;
11= GPIO.

BANK1_PIN12
00= lcd_d12;
01= reserved;
10= etm_da12;
11= GPIO.

BANK1_PIN11
00= lcd_d11;
01= reserved;
10= etm_da11;
11= GPIO.

BANK1_PIN10
00= lcd_d10;
01= reserved;
10= etm_da10;
11= GPIO.

BANK1_PIN09
00= lcd_d9;
01= etm_da4;
10= etm_da9;
11= GPIO.

BANK1_PIN08
00= lcd_d8;
01= etm_da3;
10= etm_da8;
11= GPIO.


Field Description
BANK1_PIN07
00= lcd_d7;
01= reserved;
10= etm_da7;
11= GPIO.

BANK1_PIN06
00= lcd_d6;
01= reserved;
10= etm_da6;
11= GPIO.

BANK1_PIN05
00= lcd_d5;
01= reserved;
10= etm_da5;
11= GPIO.

BANK1_PIN04
00= lcd_d4;
01= etm_da9;
10= etm_da4;
11= GPIO.

BANK1_PIN03
00= lcd_d3;
01= etm_da8;
10= etm_da3;
11= GPIO.

BANK1_PIN02
00= lcd_d2;
01= reserved;
10= etm_da2;
11= GPIO.

BANK1_PIN01
00= lcd_d1;
01= reserved;
10= etm_da1;
11= GPIO.


Field Description
BANK1_PIN00
00= lcd_d0;
01= reserved;
10= etm_da0;
11= GPIO.

pins shown above.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Field Description
31–30 Pin 111, LCD_ENABLE pin function selection:
BANK1_PIN31
00= lcd_enable;
01= reserved;
10= reserved;


Field Description
11= GPIO.
29–28 Pin 73, LCD_DOTCLK pin function selection:

BANK1_PIN30
00= lcd_dotclk;
01= saif1_mclk;
10= etm_tclk;
11= GPIO.
27–26 Pin 71, LCD_HSYNC pin function selection:

BANK1_PIN29
00= lcd_hsync;
01= saif1_sdata1;
10= etm_tctl;
11= GPIO.
25–24 Pin 59, LCD_VSYNC pin function selection:

BANK1_PIN28
00= lcd_vsync;
01= saif1_sdata0;
10= reserved;
11= GPIO.
23–22 Pin 113, LCD_CS pin function selection:

BANK1_PIN27
00= lcd_cs;
01= lcd_enable;
10= reserved;
11= GPIO.
21–20 Pin 94, LCD_RS pin function selection:

BANK1_PIN26
00= lcd_rs;
01= lcd_dotclk;
10= reserved;
11= GPIO.
19–18 Pin 55, LCD_WR_RWN pin function selection:

BANK1_PIN25
00= lcd_wr_rwn;
01= lcd_hsync;
10= etm_tclk;
11= GPIO.
17–16 Pin 96, LCD_RD_E pin function selection:

BANK1_PIN24
00= lcd_rd_e;
01= lcd_vsync;
10= etm_tctl;


Field Description
11= GPIO.

BANK1_PIN23
00= lcd_d23;
01= enet1_1588_event3_in;
10= etm_da0;
11= GPIO.

BANK1_PIN22
00= lcd_d22;
01= enet1_1588_event3_out;
10= etm_da1;
11= GPIO.

BANK1_PIN21
00= lcd_d21;
10= etm_da2;
11= GPIO.

BANK1_PIN20
00= lcd_d20;
10= etm_da3;
11= GPIO.

BANK1_PIN19
00= lcd_d19;
01= reserved;
10= etm_da4;
11= GPIO.

BANK1_PIN18
00= lcd_d18;
01= reserved;
10= etm_da5;
11= GPIO.

BANK1_PIN17
00= lcd_d17;
01= reserved;
10= etm_da6;


Field Description
11= GPIO.

BANK1_PIN16
00= lcd_d16;
01= reserved;
10= etm_da7;
11= GPIO.

pins shown above.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD0
BANK2_ BANK2_ BANK2_ BANK2_ BANK2_ BANK2_ BANK2_
PIN15 PIN14 PIN13 PIN12 PIN10 PIN09 PIN08
W
Reset 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Field Description
31–30 Pin 23, SSP1_DATA3 pin function selection:
BANK2_PIN15
00= ssp1_d3;


Field Description
01= ssp2_d7;
11= GPIO.

BANK2_PIN14
00= ssp1_d0;
01= ssp2_d6;
11= GPIO.
27–26 Pin 17, SSP1_CMD pin function selection:

BANK2_PIN13
00= ssp1_cmd;
01= ssp2_d2;
11= GPIO.
25–24 Pin 11, SSP1_SCK pin function selection:

BANK2_PIN12
00= ssp1_sck;
01= ssp2_d1;
11= GPIO.

RSRVD0
BANK2_PIN10
00= ssp0_sck;
01= reserved;
10= reserved;
11= GPIO.
19–18 Pin 275, SSP0_DETECT pin function selection:

BANK2_PIN09
01= reserved;
10= reserved;
11= GPIO.
17–16 Pin 276, SSP0_CMD pin function selection:

BANK2_PIN08
00= ssp0_cmd;
01= reserved;
10= reserved;
11= GPIO.


Field Description
BANK2_PIN07
00= ssp0_d7;
01= ssp2_sck;
10= reserved;
11= GPIO.

BANK2_PIN06
00= ssp0_d6;
01= ssp2_cmd;
10= reserved;
11= GPIO.

BANK2_PIN05
00= ssp0_d5;
01= ssp2_d3;
10= reserved;
11= GPIO.

BANK2_PIN04
00= ssp0_d4;
01= ssp2_d0;
10= reserved;
11= GPIO.

BANK2_PIN03
00= ssp0_d3;
01= reserved;
10= reserved;
11= GPIO.

BANK2_PIN02
00= ssp0_d2;
01= reserved;
10= reserved;
11= GPIO.

BANK2_PIN01
00= ssp0_d1;
01= reserved;
10= reserved;
11= GPIO.


Field Description
BANK2_PIN00
00= ssp0_d0;
01= reserved;
10= reserved;
11= GPIO.

pins shown above.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1
BANK2_ BANK2_ BANK2_ BANK2_
PIN27 PIN26 PIN25 PIN24
W
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD0
BANK2_ BANK2_ BANK2_ BANK2_ BANK2_ BANK2_
PIN21 PIN20 PIN19 PIN18 PIN17 PIN16
W
Reset 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

Field Description
RSRVD1
23–22 Pin 15, SSP3_SS0 pin function selection:
BANK2_PIN27
00= ssp3_d3;


Field Description
01= auart4_cts;
11= GPIO.
21–20 Pin 3, SSP3_MISO pin function selection:

BANK2_PIN26
00= ssp3_d0;
01= auart4_rts;
11= GPIO.
19–18 Pin 9, SSP3_MOSI pin function selection:

BANK2_PIN25
00= ssp3_cmd;
01= auart4_rx;
11= GPIO.

BANK2_PIN24
00= ssp3_sck;
01= auart4_tx;
11= GPIO.

RSRVD0
BANK2_PIN21
00= ssp2_d5;
01= ssp2_d2;
10= usb0_overcurrent;
11= GPIO.

BANK2_PIN20
00= ssp2_d4;
01= ssp2_d1;
11= GPIO.

BANK2_PIN19
00= ssp2_d3;
01= auart3_tx;
10= saif1_sdata2;
11= GPIO.


Field Description
5–4 Pin 288, SSP2_MISO pin function selection:
BANK2_PIN18
00= ssp2_d0;
01= auart3_rx;
10= saif1_sdata1;
11= GPIO.
3–2 Pin 1, SSP2_MOSI pin function selection:

BANK2_PIN17
00= ssp2_cmd;
01= auart2_tx;
10= saif0_sdata2;
11= GPIO.

BANK2_PIN16
00= ssp2_sck;
01= auart2_rx;
10= saif0_sdata1;
11= GPIO.

pins shown above.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Field Description
31–30 Pin 82, AUART3_RTS pin function selection:
BANK3_PIN15
00= auart3_rts;
01= can1_rx;
11= GPIO.
29–28 Pin 90, AUART3_CTS pin function selection:

BANK3_PIN14
00= auart3_cts;
01= can1_tx;
11= GPIO.
27–26 Pin 86, AUART3_TX pin function selection:

BANK3_PIN13
00= auart3_tx;
01= can0_rx;
11= GPIO.
25–24 Pin 98, AUART3_RX pin function selection:

BANK3_PIN12
00= auart3_rx;
01= can0_tx;
11= GPIO.

BANK3_PIN11
00= auart2_rts;
01= i2c1_sda;
10= saif1_lrclk;
11= GPIO.

BANK3_PIN10
00= auart2_cts;
01= i2c1_scl;
10= saif1_bitclk;
11= GPIO.


Field Description
BANK3_PIN09
00= auart2_tx;
01= ssp3_d2;
10= ssp3_d5;
11= GPIO.

BANK3_PIN08
00= auart2_rx;
01= ssp3_d1;
10= ssp3_d4;
11= GPIO.

BANK3_PIN07
00= auart1_rts;
01= usb0_id;
10= timrot_rotaryb;
11= GPIO.

BANK3_PIN06
00= auart1_cts;
10= timrot_rotarya;
11= GPIO.

BANK3_PIN05
00= auart1_tx;
10= pwm_1;
11= GPIO.

BANK3_PIN04
00= auart1_rx;
10= pwm_0;
11= GPIO.

BANK3_PIN03
00= auart0_rts;
01= auart4_tx;
10= duart_tx;
11= GPIO.


Field Description
BANK3_PIN02
00= auart0_cts;
01= auart4_rx;
10= duart_rx;
11= GPIO.

BANK3_PIN01
00= auart0_tx;
01= i2c0_sda;
10= duart_rts;
11= GPIO.

BANK3_PIN00
00= auart0_rx;
01= i2c0_scl;
10= duart_cts;
11= GPIO.

pins shown above.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1
W
Reset 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD0
W
Reset 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1

Field Description
RSRVD1
29–28 Pin 101, LCD_RESET pin function selection:
BANK3_PIN30
00= lcd_reset;
01= lcd_vsync;
10= reserved;
11= GPIO.
27–26 Pin 279, PWM4 pin function selection:

BANK3_PIN29
00= pwm_4;
01= reserved;
10= reserved;
11= GPIO.

BANK3_PIN28
00= pwm_3;
01= reserved;
10= reserved;
11= GPIO.
23–22 Pin 285, SPDIF pin function selection:

BANK3_PIN27
00= spdif_tx;
01= reserved;
10= enet1_rx_er;
11= GPIO.
21–20 Pin 8, SAIF1_SDATA0 pin function selection:

BANK3_PIN26
00= saif1_sdata0;
01= pwm_7;
10= saif0_sdata1;
11= GPIO.
19–18 Pin 281, I2C0_SDA pin function selection:

BANK3_PIN25
00= i2c0_sda;
01= timrot_rotaryb;


Field Description
10= duart_tx;
11= GPIO.
17–16 Pin 272, I2C0_SCL pin function selection:

BANK3_PIN24
00= i2c0_scl;
01= timrot_rotarya;
10= duart_rx;
11= GPIO.
15–14 Pin 12, SAIF0_SDATA0 pin function selection:

BANK3_PIN23
00= saif0_sdata0;
01= pwm_6;
10= auart4_tx;
11= GPIO.
13–12 Pin 16, SAIF0_BITCLK pin function selection:

BANK3_PIN22
00= saif0_bitclk;
01= pwm_5;
10= auart4_rx;
11= GPIO.
11–10 Pin 34, SAIF0_LRCLK pin function selection:

BANK3_PIN21
00= saif0_lrclk;
01= pwm_4;
10= auart4_rts;
11= GPIO.
9–8 Pin 28, SAIF0_MCLK pin function selection:

BANK3_PIN20
00= saif0_mclk;
01= pwm_3;
10= auart4_cts;
11= GPIO.

RSRVD0
BANK3_PIN18
00= pwm_2;
01= usb0_id;
11= GPIO.


Field Description
BANK3_PIN17
00= pwm_1;
01= i2c1_sda;
10= duart_tx;
11= GPIO.

BANK3_PIN16
00= pwm_0;
01= i2c1_scl;
10= duart_rx;
11= GPIO.

pins shown above.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1


Field Description
31–30 Pin 61, ENET0_CRS pin function selection:
BANK4_PIN15
00= enet0_crs;
01= enet1_rx_en;
11= GPIO.
29–28 Pin 57, ENET0_COL pin function selection:

BANK4_PIN14
00= enet0_col;
01= enet1_tx_en;
11= GPIO.
27–26 Pin 31, ENET0_RX_CLK pin function selection:

BANK4_PIN13
00= enet0_rx_clk;
01= enet0_rx_er;
11= GPIO.
25–24 Pin 41, ENET0_TXD3 pin function selection:

BANK4_PIN12
00= enet0_txd3;
01= enet1_txd1;
11= GPIO.

BANK4_PIN11
00= enet0_txd2;
01= enet1_txd0;
11= GPIO.
21–20 Pin 53, ENET0_RXD3 pin function selection:

BANK4_PIN10
00= enet0_rxd3;
01= enet1_rxd1;
11= GPIO.

BANK4_PIN09
00= enet0_rxd2;
01= enet1_rxd0;
11= GPIO.


Field Description
BANK4_PIN08
00= enet0_txd1;
01= gpmi_ready7;
10= reserved;
11= GPIO.

BANK4_PIN07
00= enet0_txd0;
01= gpmi_ready6;
10= reserved;
11= GPIO.
13–12 Pin 29, ENET0_TX_EN pin function selection:

BANK4_PIN06
00= enet0_tx_en;
01= gpmi_ready5;
10= reserved;
11= GPIO.
11–10 Pin 13, ENET0_TX_CLK pin function selection:

BANK4_PIN05
00= enet0_tx_clk;
01= hsadc_trigger;
11= GPIO.

BANK4_PIN04
00= enet0_rxd1;
01= gpmi_ready4;
10= reserved;
11= GPIO.

BANK4_PIN03
00= enet0_rxd0;
01= gpmi_ce7n;
10= saif1_sdata2;
11= GPIO.
5–4 Pin 27, ENET0_RX_EN pin function selection:

BANK4_PIN02
00= enet0_rx_en;
01= gpmi_ce6n;
10= saif1_sdata1;
11= GPIO.


Field Description
3–2 Pin 39, ENET0_MDIO pin function selection:
BANK4_PIN01
00= enet0_mdio;
01= gpmi_ce5n;
10= saif0_sdata2;
11= GPIO.
1–0 Pin 54, ENET0_MDC pin function selection:

BANK4_PIN00
00= enet0_mdc;
01= gpmi_ce4n;
10= saif0_sdata1;
11= GPIO.

pins shown above.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1[15:10] RSRVD0
BANK4_ BANK4_
PIN20 PIN16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1


Field Description
RSRVD1
9–8 Pin 230, JTAG_RTCK pin function selection:
BANK4_PIN20
00= jtag_rtck;
01= reserved;
10= reserved;
11= GPIO.

RSRVD0
1–0 Pin 19, ENET_CLK pin function selection:
BANK4_PIN16
00= clkctrl_enet;
01= reserved;
10= reserved;
11= GPIO.

HW_PINCTRL_MUXSEL10: 0x1a0
HW_PINCTRL_MUXSEL10_SET: 0x1a4
HW_PINCTRL_MUXSEL10_CLR: 0x1a8
HW_PINCTRL_MUXSEL10_TOG: 0x1aC
pins shown above.
Address: HW_PINCTRL_MUXSEL10 – 8001_8000h base + 1A0h offset = 8001_
81A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Field Description
31–30 Pin 218, EMI_D15 pin function selection:
BANK5_PIN15
00= emi_data15;
01= reserved;
10= reserved;
11= disabled.

BANK5_PIN14
00= emi_data14;
01= reserved;
10= reserved;
11= disabled.

BANK5_PIN13
00= emi_data13;
01= reserved;
10= reserved;
11= disabled.

BANK5_PIN12
00= emi_data12;
01= reserved;
10= reserved;
11= disabled.

BANK5_PIN11
00= emi_data11;
01= reserved;
10= reserved;
11= disabled.

BANK5_PIN10
00= emi_data10;
01= reserved;
10= reserved;
11= disabled.


Field Description
BANK5_PIN09
00= emi_data9;
01= reserved;
10= reserved;
11= disabled.

BANK5_PIN08
00= emi_data8;
01= reserved;
10= reserved;
11= disabled.

BANK5_PIN07
00= emi_data7;
01= reserved;
10= reserved;
11= disabled.

BANK5_PIN06
00= emi_data6;
01= reserved;
10= reserved;
11= disabled.

BANK5_PIN05
00= emi_data5;
01= reserved;
10= reserved;
11= disabled.

BANK5_PIN04
00= emi_data4;
01= reserved;
10= reserved;
11= disabled.

BANK5_PIN03
00= emi_data3;
01= reserved;
10= reserved;
11= disabled.


Field Description
BANK5_PIN02
00= emi_data2;
01= reserved;
10= reserved;
11= disabled.

BANK5_PIN01
00= emi_data1;
01= reserved;
10= reserved;
11= disabled.

BANK5_PIN00
00= emi_data0;
01= reserved;
10= reserved;
11= disabled.

HW_PINCTRL_MUXSEL11: 0x1b0
HW_PINCTRL_MUXSEL11_SET: 0x1b4
HW_PINCTRL_MUXSEL11_CLR: 0x1b8
HW_PINCTRL_MUXSEL11_TOG: 0x1bC
pins shown above.
Address: HW_PINCTRL_MUXSEL11 – 8001_8000h base + 1B0h offset = 8001_
81B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1 RSRVD0
BANK5_
PIN26
W
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Field Description
RSRVD1
21–20 Pin 196, EMI_DDR_OPEN pin function selection:
BANK5_PIN26
00= emi_ddr_open;
01= reserved;
10= reserved;
11= disabled.

RSRVD0
15–14 Pin 204, EMI_DQS1 pin function selection:
BANK5_PIN23
00= emi_dqs1;
01= reserved;
10= reserved;
11= disabled.
13–12 Pin 202, EMI_DQS0 pin function selection:

BANK5_PIN22
00= emi_dqs0;
01= reserved;
10= reserved;
11= disabled.
11–10 Pin 200, EMI_CLK pin function selection:

BANK5_PIN21
00= emi_clk;
01= reserved;
10= reserved;
11= disabled.
9–8 Pin 195, EMI_DDR_OPEN_FB pin function selection:

BANK5_PIN20
00= emi_ddr_open_feedback;
01= reserved;
10= reserved;
11= disabled.
7–6 Pin 222, EMI_DQM1 pin function selection:

BANK5_PIN19


Field Description
00= emi_dqm1;
01= reserved;
10= reserved;
11= disabled.
5–4 Pin 171, EMI_ODT1 pin function selection:

BANK5_PIN18
00= emi_odt1;
01= reserved;
10= reserved;
11= disabled.
3–2 Pin 183, EMI_DQM0 pin function selection:

BANK5_PIN17
00= emi_dqm0;
01= reserved;
10= reserved;
11= disabled.
1–0 Pin 173, EMI_ODT0 pin function selection:

BANK5_PIN16
00= emi_odt0;
01= reserved;
10= reserved;
11= disabled.

HW_PINCTRL_MUXSEL12: 0x1c0
HW_PINCTRL_MUXSEL12_SET: 0x1c4
HW_PINCTRL_MUXSEL12_CLR: 0x1c8
HW_PINCTRL_MUXSEL12_TOG: 0x1cC
pins shown above.

Address: HW_PINCTRL_MUXSEL12 – 8001_8000h base + 1C0h offset = 8001_

81C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD0
W
Reset 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Field Description
RSRVD0
29–28 Pin 147, EMI_A14 pin function selection:
BANK6_PIN14
00= emi_addr14;
01= reserved;
10= reserved;
11= disabled.

BANK6_PIN13
00= emi_addr13;
01= reserved;
10= reserved;
11= disabled.

BANK6_PIN12
00= emi_addr12;
01= reserved;
10= reserved;
11= disabled.

BANK6_PIN11
00= emi_addr11;
01= reserved;
10= reserved;
11= disabled.

BANK6_PIN10


Field Description
00= emi_addr10;
01= reserved;
10= reserved;
11= disabled.

BANK6_PIN09
00= emi_addr9;
01= reserved;
10= reserved;
11= disabled.

BANK6_PIN08
00= emi_addr8;
01= reserved;
10= reserved;
11= disabled.

BANK6_PIN07
00= emi_addr7;
01= reserved;
10= reserved;
11= disabled.

BANK6_PIN06
00= emi_addr6;
01= reserved;
10= reserved;
11= disabled.

BANK6_PIN05
00= emi_addr5;
01= reserved;
10= reserved;
11= disabled.

BANK6_PIN04
00= emi_addr4;
01= reserved;
10= reserved;
11= disabled.


Field Description
BANK6_PIN03
00= emi_addr3;
01= reserved;
10= reserved;
11= disabled.

BANK6_PIN02
00= emi_addr2;
01= reserved;
10= reserved;
11= disabled.

BANK6_PIN01
00= emi_addr1;
01= reserved;
10= reserved;
11= disabled.

BANK6_PIN00
00= emi_addr0;
01= reserved;
10= reserved;
11= disabled.

HW_PINCTRL_MUXSEL13: 0x1d0
HW_PINCTRL_MUXSEL13_SET: 0x1d4
HW_PINCTRL_MUXSEL13_CLR: 0x1d8
HW_PINCTRL_MUXSEL13_TOG: 0x1dC
pins shown above.

Address: HW_PINCTRL_MUXSEL13 – 8001_8000h base + 1D0h offset = 8001_

81D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD0
BANK6_
PIN24
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Field Description
RSRVD0
17–16 Pin 166, EMI_CKE pin function selection:
BANK6_PIN24
00= emi_cke;
01= reserved;
10= reserved;
11= disabled.
15–14 Pin 139, EMI_CE1N pin function selection:

BANK6_PIN23
00= emi_ce1n;
01= reserved;
10= reserved;
11= disabled.
13–12 Pin 151, EMI_CE0N pin function selection:

BANK6_PIN22
00= emi_ce0n;
01= reserved;
10= reserved;
11= disabled.
11–10 Pin 176, EMI_WEN pin function selection:

BANK6_PIN21
00= emi_wen;
01= reserved;
10= reserved;
11= disabled.
9–8 Pin 167, EMI_RASN pin function selection:

BANK6_PIN20


Field Description
00= emi_rasn;
01= reserved;
10= reserved;
11= disabled.
7–6 Pin 172, EMI_CASN pin function selection:

BANK6_PIN19
00= emi_casn;
01= reserved;
10= reserved;
11= disabled.
5–4 Pin 165, EMI_BA2 pin function selection:

BANK6_PIN18
00= emi_ba2;
01= reserved;
10= reserved;
11= disabled.

BANK6_PIN17
00= emi_ba1;
01= reserved;
10= reserved;
11= disabled.

BANK6_PIN16
00= emi_ba0;
01= reserved;
10= reserved;
11= disabled.
9.4.16 PINCTRL Drive Strength and Voltage Register 0

(HW_PINCTRL_DRIVE0)
The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 8
pins of bank 0.
HW_PINCTRL_DRIVE0: 0x300
HW_PINCTRL_DRIVE0_SET: 0x304
HW_PINCTRL_DRIVE0_CLR: 0x308

HW_PINCTRL_DRIVE0_TOG: 0x30C
The Drive Strength and Voltage Register selects the drive strength and voltage for pins that
are configured for output.
Address: HW_PINCTRL_DRIVE0 – 8001_8000h base + 300h offset = 8001_8300h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD7
RSRVD6
RSRVD5
RSRVD4
BANK0_PIN07_V
BANK0_PIN06_V
BANK0_PIN05_V
BANK0_PIN04_V
R

PIN07_MA PIN06_MA PIN05_MA PIN04_MA
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD3
RSRVD2
RSRVD1
RSRVD0
BANK0_PIN03_V
BANK0_PIN02_V
BANK0_PIN01_V
BANK0_PIN00_V
R

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
HW_PINCTRL_DRIVE0 field descriptions

Field Description
31 Always write zeroes to this field.
RSRVD7
30 Pin 124, GPMI_D07 pin voltage selection:
BANK0_PIN07_V
0= 1.8V;
1= 3.3V.
29–28 Pin 124, GPMI_D07 pin output drive strength selection:

BANK0_PIN07_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD6
BANK0_PIN06_V
0= 1.8V;
1= 3.3V.

HW_PINCTRL_DRIVE0 field descriptions (continued)

Field Description
BANK0_PIN06_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD5
BANK0_PIN05_V
0= 1.8V;
1= 3.3V.

BANK0_PIN05_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD4
BANK0_PIN04_V
0= 1.8V;
1= 3.3V.

BANK0_PIN04_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD3
BANK0_PIN03_V
0= 1.8V;
1= 3.3V.

BANK0_PIN03_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;


Field Description
RSRVD2
BANK0_PIN02_V
0= 1.8V;
1= 3.3V.

BANK0_PIN02_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD1
BANK0_PIN01_V
0= 1.8V;
1= 3.3V.

BANK0_PIN01_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD0
BANK0_PIN00_V
0= 1.8V;
1= 3.3V.

BANK0_PIN00_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;


(HW_PINCTRL_DRIVE1)
pins of bank 0.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSRVD0

(HW_PINCTRL_DRIVE2)
pins of bank 0.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD7
RSRVD6
RSRVD5
RSRVD4
BANK0_PIN23_V
BANK0_PIN22_V
BANK0_PIN21_V
BANK0_PIN20_V
R

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD3
RSRVD2
RSRVD1
RSRVD0
BANK0_PIN19_V
BANK0_PIN18_V
BANK0_PIN17_V
BANK0_PIN16_V
R

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Field Description
RSRVD7
30 Pin 80, GPMI_RDY3 pin voltage selection:
BANK0_PIN23_V
0= 1.8V;
1= 3.3V.
29–28 Pin 80, GPMI_RDY3 pin output drive strength selection:

BANK0_PIN23_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD6
BANK0_PIN22_V
0= 1.8V;
1= 3.3V.

BANK0_PIN22_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;


Field Description
RSRVD5
BANK0_PIN21_V
0= 1.8V;
1= 3.3V.

BANK0_PIN21_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD4
BANK0_PIN20_V
0= 1.8V;
1= 3.3V.

BANK0_PIN20_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD3
14 Pin 135, GPMI_CE3N pin voltage selection:
BANK0_PIN19_V
0= 1.8V;
1= 3.3V.
13–12 Pin 135, GPMI_CE3N pin output drive strength selection:

BANK0_PIN19_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD2
BANK0_PIN18_V
0= 1.8V;
1= 3.3V.


Field Description
BANK0_PIN18_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD1
BANK0_PIN17_V
0= 1.8V;
1= 3.3V.

BANK0_PIN17_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD0
BANK0_PIN16_V
0= 1.8V;
1= 3.3V.

BANK0_PIN16_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

(HW_PINCTRL_DRIVE3)
pins of bank 0.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD4
BANK0_PIN28_V
R RSRVD5
BANK0_
PIN28_MA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD3
RSRVD2
RSRVD1
RSRVD0
BANK0_PIN27_V
BANK0_PIN26_V
BANK0_PIN25_V
BANK0_PIN24_V
R

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Field Description
RSRVD5
RSRVD4
18 Pin 129, GPMI_RESETN pin voltage selection:
BANK0_PIN28_V
0= 1.8V;
1= 3.3V.
17–16 Pin 129, GPMI_RESETN pin output drive strength selection:

BANK0_PIN28_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD3


Field Description
14 Pin 123, GPMI_CLE pin voltage selection:
BANK0_PIN27_V
0= 1.8V;
1= 3.3V.
13–12 Pin 123, GPMI_CLE pin output drive strength selection:

BANK0_PIN27_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD2
10 Pin 117, GPMI_ALE pin voltage selection:
BANK0_PIN26_V
0= 1.8V;
1= 3.3V.
9–8 Pin 117, GPMI_ALE pin output drive strength selection:

BANK0_PIN26_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD1
6 Pin 127, GPMI_WRN pin voltage selection:
BANK0_PIN25_V
0= 1.8V;
1= 3.3V.
5–4 Pin 127, GPMI_WRN pin output drive strength selection:

BANK0_PIN25_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD0
2 Pin 110, GPMI_RDN pin voltage selection:
BANK0_PIN24_V
0= 1.8V;
1= 3.3V.
1–0 Pin 110, GPMI_RDN pin output drive strength selection:

BANK0_PIN24_
00= 4 mA;
MA


Field Description
01= 8 mA;
10= 12 mA;
11= Reserved;

(HW_PINCTRL_DRIVE4)
pins of bank 1.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD7
RSRVD6
RSRVD5
RSRVD4
BANK1_PIN07_V
BANK1_PIN06_V
BANK1_PIN05_V
BANK1_PIN04_V
R

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD3
RSRVD2
RSRVD1
RSRVD0
BANK1_PIN03_V
BANK1_PIN02_V
BANK1_PIN01_V
BANK1_PIN00_V

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0


Field Description
RSRVD7
30 Pin 75, LCD_D07 pin voltage selection:
BANK1_PIN07_V
0= 1.8V;
1= 3.3V.
29–28 Pin 75, LCD_D07 pin output drive strength selection:

BANK1_PIN07_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD6
BANK1_PIN06_V
0= 1.8V;
1= 3.3V.

BANK1_PIN06_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD5
BANK1_PIN05_V
0= 1.8V;
1= 3.3V.

BANK1_PIN05_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD4
BANK1_PIN04_V
0= 1.8V;
1= 3.3V.


Field Description
BANK1_PIN04_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD3
BANK1_PIN03_V
0= 1.8V;
1= 3.3V.

BANK1_PIN03_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD2
BANK1_PIN02_V
0= 1.8V;
1= 3.3V.

BANK1_PIN02_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD1
BANK1_PIN01_V
0= 1.8V;
1= 3.3V.

BANK1_PIN01_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;


Field Description
RSRVD0
BANK1_PIN00_V
0= 1.8V;
1= 3.3V.

BANK1_PIN00_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

(HW_PINCTRL_DRIVE5)
pins of bank 1.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD7
RSRVD6
RSRVD5
RSRVD4
BANK1_PIN15_V
BANK1_PIN14_V
BANK1_PIN13_V
BANK1_PIN12_V

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD3
RSRVD2
RSRVD1
RSRVD0
BANK1_PIN11_V
BANK1_PIN10_V
BANK1_PIN09_V
BANK1_PIN08_V
R

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Field Description
RSRVD7
BANK1_PIN15_V
0= 1.8V;
1= 3.3V.

BANK1_PIN15_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD6
BANK1_PIN14_V
0= 1.8V;
1= 3.3V.

BANK1_PIN14_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD5
BANK1_PIN13_V
0= 1.8V;
1= 3.3V.

BANK1_PIN13_
00= 4 mA;
MA
01= 8 mA;


Field Description
10= 12 mA;
11= Reserved;

RSRVD4
BANK1_PIN12_V
0= 1.8V;
1= 3.3V.

BANK1_PIN12_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD3
BANK1_PIN11_V
0= 1.8V;
1= 3.3V.

BANK1_PIN11_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD2
BANK1_PIN10_V
0= 1.8V;
1= 3.3V.

BANK1_PIN10_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD1
BANK1_PIN09_V
0= 1.8V;


Field Description
1= 3.3V.

BANK1_PIN09_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD0
BANK1_PIN08_V
0= 1.8V;
1= 3.3V.

BANK1_PIN08_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

(HW_PINCTRL_DRIVE6)
pins of bank 1.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD7
RSRVD6
RSRVD5
RSRVD4
BANK1_PIN23_V
BANK1_PIN22_V
BANK1_PIN21_V
BANK1_PIN20_V
R

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD3
RSRVD2
RSRVD1
RSRVD0
BANK1_PIN19_V
BANK1_PIN18_V
BANK1_PIN17_V
BANK1_PIN16_V
R

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Field Description
RSRVD7
BANK1_PIN23_V
0= 1.8V;
1= 3.3V.

BANK1_PIN23_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD6
BANK1_PIN22_V
0= 1.8V;
1= 3.3V.

BANK1_PIN22_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;


Field Description
RSRVD5
BANK1_PIN21_V
0= 1.8V;
1= 3.3V.

BANK1_PIN21_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD4
BANK1_PIN20_V
0= 1.8V;
1= 3.3V.

BANK1_PIN20_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD3
BANK1_PIN19_V
0= 1.8V;
1= 3.3V.

BANK1_PIN19_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD2
BANK1_PIN18_V
0= 1.8V;
1= 3.3V.


Field Description
BANK1_PIN18_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD1
BANK1_PIN17_V
0= 1.8V;
1= 3.3V.

BANK1_PIN17_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD0
BANK1_PIN16_V
0= 1.8V;
1= 3.3V.

BANK1_PIN16_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

(HW_PINCTRL_DRIVE7)
pins of bank 1.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD7
RSRVD6
RSRVD5
RSRVD4
BANK1_PIN31_V
BANK1_PIN30_V
BANK1_PIN29_V
BANK1_PIN28_V
R

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD3
RSRVD2
RSRVD1
RSRVD0
BANK1_PIN27_V
BANK1_PIN26_V
BANK1_PIN25_V
BANK1_PIN24_V
R

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Field Description
RSRVD7
30 Pin 111, LCD_ENABLE pin voltage selection:
BANK1_PIN31_V
0= 1.8V;
1= 3.3V.
29–28 Pin 111, LCD_ENABLE pin output drive strength selection:

BANK1_PIN31_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD6
26 Pin 73, LCD_DOTCLK pin voltage selection:
BANK1_PIN30_V
0= 1.8V;


Field Description
1= 3.3V.
25–24 Pin 73, LCD_DOTCLK pin output drive strength selection:

BANK1_PIN30_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD5
22 Pin 71, LCD_HSYNC pin voltage selection:
BANK1_PIN29_V
0= 1.8V;
1= 3.3V.
21–20 Pin 71, LCD_HSYNC pin output drive strength selection:

BANK1_PIN29_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD4
18 Pin 59, LCD_VSYNC pin voltage selection:
BANK1_PIN28_V
0= 1.8V;
1= 3.3V.
17–16 Pin 59, LCD_VSYNC pin output drive strength selection:

BANK1_PIN28_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD3
14 Pin 113, LCD_CS pin voltage selection:
BANK1_PIN27_V
0= 1.8V;
1= 3.3V.
13–12 Pin 113, LCD_CS pin output drive strength selection:

BANK1_PIN27_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;


Field Description
11= Reserved;

RSRVD2
10 Pin 94, LCD_RS pin voltage selection:
BANK1_PIN26_V
0= 1.8V;
1= 3.3V.
9–8 Pin 94, LCD_RS pin output drive strength selection:

BANK1_PIN26_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD1
6 Pin 55, LCD_WR_RWN pin voltage selection:
BANK1_PIN25_V
0= 1.8V;
1= 3.3V.
5–4 Pin 55, LCD_WR_RWN pin output drive strength selection:

BANK1_PIN25_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD0
2 Pin 96, LCD_RD_E pin voltage selection:
BANK1_PIN24_V
0= 1.8V;
1= 3.3V.
1–0 Pin 96, LCD_RD_E pin output drive strength selection:

BANK1_PIN24_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;


(HW_PINCTRL_DRIVE8)
pins of bank 2.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD7
RSRVD6
RSRVD5
RSRVD4
BANK2_PIN07_V
BANK2_PIN06_V
BANK2_PIN05_V
BANK2_PIN04_V
R

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD3
RSRVD2
RSRVD1
RSRVD0
BANK2_PIN03_V
BANK2_PIN02_V
BANK2_PIN01_V
BANK2_PIN00_V
R

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Field Description
RSRVD7
30 Pin 282, SSP0_DATA7 pin voltage selection:
BANK2_PIN07_V
0= 1.8V;
1= 3.3V.


Field Description
29–28 Pin 282, SSP0_DATA7 pin output drive strength selection:
BANK2_PIN07_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD6
BANK2_PIN06_V
0= 1.8V;
1= 3.3V.

BANK2_PIN06_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD5
BANK2_PIN05_V
0= 1.8V;
1= 3.3V.

BANK2_PIN05_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD4
BANK2_PIN04_V
0= 1.8V;
1= 3.3V.

BANK2_PIN04_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;


Field Description
RSRVD3
BANK2_PIN03_V
0= 1.8V;
1= 3.3V.

BANK2_PIN03_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD2
BANK2_PIN02_V
0= 1.8V;
1= 3.3V.

BANK2_PIN02_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD1
BANK2_PIN01_V
0= 1.8V;
1= 3.3V.

BANK2_PIN01_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD0
BANK2_PIN00_V
0= 1.8V;
1= 3.3V.


Field Description
BANK2_PIN00_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

(HW_PINCTRL_DRIVE9)
pins of bank 2.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD7
RSRVD6
RSRVD5
RSRVD4
BANK2_PIN15_V
BANK2_PIN14_V
BANK2_PIN13_V
BANK2_PIN12_V

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD2
RSRVD1
RSRVD0
BANK2_PIN10_V
BANK2_PIN09_V
BANK2_PIN08_V
R RSRVD3
BANK2_ BANK2_ BANK2_
PIN10_MA PIN09_MA PIN08_MA
Reset 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Field Description
RSRVD7
BANK2_PIN15_V
0= 1.8V;
1= 3.3V.

BANK2_PIN15_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD6
BANK2_PIN14_V
0= 1.8V;
1= 3.3V.

BANK2_PIN14_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD5
22 Pin 17, SSP1_CMD pin voltage selection:
BANK2_PIN13_V
0= 1.8V;
1= 3.3V.
21–20 Pin 17, SSP1_CMD pin output drive strength selection:

BANK2_PIN13_
00= 4 mA;
MA
01= 8 mA;


Field Description
10= 12 mA;
11= Reserved;

RSRVD4
18 Pin 11, SSP1_SCK pin voltage selection:
BANK2_PIN12_V
0= 1.8V;
1= 3.3V.
17–16 Pin 11, SSP1_SCK pin output drive strength selection:

BANK2_PIN12_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD3
RSRVD2
BANK2_PIN10_V
0= 1.8V;
1= 3.3V.

BANK2_PIN10_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD1
6 Pin 275, SSP0_DETECT pin voltage selection:
BANK2_PIN09_V
0= 1.8V;
1= 3.3V.
5–4 Pin 275, SSP0_DETECT pin output drive strength selection:

BANK2_PIN09_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD0


Field Description
2 Pin 276, SSP0_CMD pin voltage selection:
BANK2_PIN08_V
0= 1.8V;
1= 3.3V.
1–0 Pin 276, SSP0_CMD pin output drive strength selection:

BANK2_PIN08_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

pins of bank 2.
HW_PINCTRL_DRIVE10: 0x3a0
HW_PINCTRL_DRIVE10_SET: 0x3a4
HW_PINCTRL_DRIVE10_CLR: 0x3a8
HW_PINCTRL_DRIVE10_TOG: 0x3aC
Address: HW_PINCTRL_DRIVE10 – 8001_8000h base + 3A0h offset = 8001_83A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD5
RSRVD4
BANK2_PIN21_V
BANK2_PIN20_V
R RSRVD6
BANK2_ BANK2_
PIN21_MA PIN20_MA
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD3
RSRVD2
RSRVD1
RSRVD0
BANK2_PIN19_V
BANK2_PIN18_V
BANK2_PIN17_V
BANK2_PIN16_V
R

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Field Description
RSRVD6
RSRVD5
22 Pin 18, SSP2_SS2 pin voltage selection:
BANK2_PIN21_V
0= 1.8V;
1= 3.3V.
21–20 Pin 18, SSP2_SS2 pin output drive strength selection:

BANK2_PIN21_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD4
BANK2_PIN20_V
0= 1.8V;
1= 3.3V.

BANK2_PIN20_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD3
BANK2_PIN19_V
0= 1.8V;
1= 3.3V.


Field Description
BANK2_PIN19_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD2
10 Pin 288, SSP2_MISO pin voltage selection:
BANK2_PIN18_V
0= 1.8V;
1= 3.3V.
9–8 Pin 288, SSP2_MISO pin output drive strength selection:

BANK2_PIN18_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD1
6 Pin 1, SSP2_MOSI pin voltage selection:
BANK2_PIN17_V
0= 1.8V;
1= 3.3V.
5–4 Pin 1, SSP2_MOSI pin output drive strength selection:

BANK2_PIN17_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD0
BANK2_PIN16_V
0= 1.8V;
1= 3.3V.

BANK2_PIN16_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;


pins of bank 2.
HW_PINCTRL_DRIVE11: 0x3b0
HW_PINCTRL_DRIVE11_SET: 0x3b4
HW_PINCTRL_DRIVE11_CLR: 0x3b8
HW_PINCTRL_DRIVE11_TOG: 0x3bC
Address: HW_PINCTRL_DRIVE11 – 8001_8000h base + 3B0h offset = 8001_83B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD4
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD3
RSRVD2
RSRVD1
RSRVD0
BANK2_PIN27_V
BANK2_PIN26_V
BANK2_PIN25_V
R BANK2_PIN24_V

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Field Description
RSRVD4
RSRVD3
BANK2_PIN27_V
0= 1.8V;
1= 3.3V.


Field Description
BANK2_PIN27_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD2
10 Pin 3, SSP3_MISO pin voltage selection:
BANK2_PIN26_V
0= 1.8V;
1= 3.3V.
9–8 Pin 3, SSP3_MISO pin output drive strength selection:

BANK2_PIN26_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD1
6 Pin 9, SSP3_MOSI pin voltage selection:
BANK2_PIN25_V
0= 1.8V;
1= 3.3V.
5–4 Pin 9, SSP3_MOSI pin output drive strength selection:

BANK2_PIN25_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD0
BANK2_PIN24_V
0= 1.8V;
1= 3.3V.

BANK2_PIN24_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;


pins of bank 3.
HW_PINCTRL_DRIVE12: 0x3c0
HW_PINCTRL_DRIVE12_SET: 0x3c4
HW_PINCTRL_DRIVE12_CLR: 0x3c8
HW_PINCTRL_DRIVE12_TOG: 0x3cC
Address: HW_PINCTRL_DRIVE12 – 8001_8000h base + 3C0h offset = 8001_83C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD7
RSRVD6
RSRVD5
RSRVD4
BANK3_PIN07_V
BANK3_PIN06_V
BANK3_PIN05_V
BANK3_PIN04_V
R

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD3
RSRVD2
RSRVD1
RSRVD0
BANK3_PIN03_V
BANK3_PIN02_V
BANK3_PIN01_V
BANK3_PIN00_V
R

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Field Description
RSRVD7
30 Pin 74, AUART1_RTS pin voltage selection:
BANK3_PIN07_V
0= 1.8V;
1= 3.3V.


Field Description
29–28 Pin 74, AUART1_RTS pin output drive strength selection:
BANK3_PIN07_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD6
26 Pin 78, AUART1_CTS pin voltage selection:
BANK3_PIN06_V
0= 1.8V;
1= 3.3V.
25–24 Pin 78, AUART1_CTS pin output drive strength selection:

BANK3_PIN06_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD5
22 Pin 65, AUART1_TX pin voltage selection:
BANK3_PIN05_V
0= 1.8V;
1= 3.3V.
21–20 Pin 65, AUART1_TX pin output drive strength selection:

BANK3_PIN05_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD4
18 Pin 81, AUART1_RX pin voltage selection:
BANK3_PIN04_V
0= 1.8V;
1= 3.3V.
17–16 Pin 81, AUART1_RX pin output drive strength selection:

BANK3_PIN04_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;


Field Description
RSRVD3
BANK3_PIN03_V
0= 1.8V;
1= 3.3V.

BANK3_PIN03_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD2
BANK3_PIN02_V
0= 1.8V;
1= 3.3V.

BANK3_PIN02_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD1
BANK3_PIN01_V
0= 1.8V;
1= 3.3V.

BANK3_PIN01_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD0
BANK3_PIN00_V
0= 1.8V;
1= 3.3V.


Field Description
BANK3_PIN00_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

pins of bank 3.
HW_PINCTRL_DRIVE13: 0x3d0
HW_PINCTRL_DRIVE13_SET: 0x3d4
HW_PINCTRL_DRIVE13_CLR: 0x3d8
HW_PINCTRL_DRIVE13_TOG: 0x3dC
Address: HW_PINCTRL_DRIVE13 – 8001_8000h base + 3D0h offset = 8001_83D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD7
RSRVD6
RSRVD5
RSRVD4
BANK3_PIN15_V
BANK3_PIN14_V
BANK3_PIN13_V
BANK3_PIN12_V

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD3
RSRVD2
RSRVD1
RSRVD0
BANK3_PIN11_V
BANK3_PIN10_V
BANK3_PIN09_V
BANK3_PIN08_V
R

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Field Description
RSRVD7
BANK3_PIN15_V
0= 1.8V;
1= 3.3V.

BANK3_PIN15_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD6
BANK3_PIN14_V
0= 1.8V;
1= 3.3V.

BANK3_PIN14_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD5
BANK3_PIN13_V
0= 1.8V;
1= 3.3V.

BANK3_PIN13_
00= 4 mA;
MA
01= 8 mA;


Field Description
10= 12 mA;
11= Reserved;

RSRVD4
BANK3_PIN12_V
0= 1.8V;
1= 3.3V.

BANK3_PIN12_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD3
BANK3_PIN11_V
0= 1.8V;
1= 3.3V.

BANK3_PIN11_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD2
BANK3_PIN10_V
0= 1.8V;
1= 3.3V.

BANK3_PIN10_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD1
BANK3_PIN09_V
0= 1.8V;


Field Description
1= 3.3V.

BANK3_PIN09_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD0
BANK3_PIN08_V
0= 1.8V;
1= 3.3V.

BANK3_PIN08_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

pins of bank 3.
HW_PINCTRL_DRIVE14: 0x3e0
HW_PINCTRL_DRIVE14_SET: 0x3e4
HW_PINCTRL_DRIVE14_CLR: 0x3e8
HW_PINCTRL_DRIVE14_TOG: 0x3eC

Address: HW_PINCTRL_DRIVE14 – 8001_8000h base + 3E0h offset = 8001_83E0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD7
RSRVD6
RSRVD5
RSRVD4
BANK3_PIN23_V
BANK3_PIN22_V
BANK3_PIN21_V
BANK3_PIN20_V
R

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Bit 15 14 13 12 11
RSRVD2 10 9 8 7 6 5 4 3 2 1 0
RSRVD1
RSRVD0
BANK3_PIN18_V
BANK3_PIN17_V
BANK3_PIN16_V
R RSRVD3
Reset 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Field Description
RSRVD7
30 Pin 12, SAIF0_SDATA0 pin voltage selection:
BANK3_PIN23_V
0= 1.8V;
1= 3.3V.
29–28 Pin 12, SAIF0_SDATA0 pin output drive strength selection:

BANK3_PIN23_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD6
26 Pin 16, SAIF0_BITCLK pin voltage selection:
BANK3_PIN22_V
0= 1.8V;
1= 3.3V.
25–24 Pin 16, SAIF0_BITCLK pin output drive strength selection:

BANK3_PIN22_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;


Field Description
RSRVD5
22 Pin 34, SAIF0_LRCLK pin voltage selection:
BANK3_PIN21_V
0= 1.8V;
1= 3.3V.
21–20 Pin 34, SAIF0_LRCLK pin output drive strength selection:

BANK3_PIN21_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD4
18 Pin 28, SAIF0_MCLK pin voltage selection:
BANK3_PIN20_V
0= 1.8V;
1= 3.3V.
17–16 Pin 28, SAIF0_MCLK pin output drive strength selection:

BANK3_PIN20_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD3
RSRVD2
10 Pin 68, PWM2 pin voltage selection:
BANK3_PIN18_V
0= 1.8V;
1= 3.3V.
9–8 Pin 68, PWM2 pin output drive strength selection:

BANK3_PIN18_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD1
BANK3_PIN17_V
0= 1.8V;


Field Description
1= 3.3V.

BANK3_PIN17_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD0
BANK3_PIN16_V
0= 1.8V;
1= 3.3V.

BANK3_PIN16_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

pins of bank 3.
HW_PINCTRL_DRIVE15: 0x3f0
HW_PINCTRL_DRIVE15_SET: 0x3f4
HW_PINCTRL_DRIVE15_CLR: 0x3f8
HW_PINCTRL_DRIVE15_TOG: 0x3fC

Address: HW_PINCTRL_DRIVE15 – 8001_8000h base + 3F0h offset = 8001_83F0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD6
RSRVD5
RSRVD4
BANK3_PIN30_V
BANK3_PIN29_V
BANK3_PIN28_V
R RSRVD7
Reset 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD3
RSRVD2
RSRVD1
RSRVD0
BANK3_PIN27_V
BANK3_PIN26_V
BANK3_PIN25_V
BANK3_PIN24_V
R

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Field Description
RSRVD7
RSRVD6
26 Pin 101, LCD_RESET pin voltage selection:
BANK3_PIN30_V
0= 1.8V;
1= 3.3V.
25–24 Pin 101, LCD_RESET pin output drive strength selection:

BANK3_PIN30_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD5
BANK3_PIN29_V
0= 1.8V;
1= 3.3V.

BANK3_PIN29_
00= 4 mA;
MA
01= 8 mA;


Field Description
10= 12 mA;
11= Reserved;

RSRVD4
BANK3_PIN28_V
0= 1.8V;
1= 3.3V.

BANK3_PIN28_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD3
14 Pin 285, SPDIF pin voltage selection:
BANK3_PIN27_V
0= 1.8V;
1= 3.3V.
13–12 Pin 285, SPDIF pin output drive strength selection:

BANK3_PIN27_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD2
10 Pin 8, SAIF1_SDATA0 pin voltage selection:
BANK3_PIN26_V
0= 1.8V;
1= 3.3V.
9–8 Pin 8, SAIF1_SDATA0 pin output drive strength selection:

BANK3_PIN26_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD1
6 Pin 281, I2C0_SDA pin voltage selection:
BANK3_PIN25_V
0= 1.8V;


Field Description
1= 3.3V.
5–4 Pin 281, I2C0_SDA pin output drive strength selection:

BANK3_PIN25_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD0
2 Pin 272, I2C0_SCL pin voltage selection:
BANK3_PIN24_V
0= 1.8V;
1= 3.3V.
1–0 Pin 272, I2C0_SCL pin output drive strength selection:

BANK3_PIN24_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

pins of bank 4.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD7
RSRVD6
RSRVD5
RSRVD4
BANK4_PIN07_V
BANK4_PIN06_V
BANK4_PIN05_V
BANK4_PIN04_V
R

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD3
RSRVD2
RSRVD1
RSRVD0
BANK4_PIN03_V
BANK4_PIN02_V
BANK4_PIN01_V
BANK4_PIN00_V
R

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Field Description
RSRVD7
30 Pin 37, ENET0_TXD0 pin voltage selection:
BANK4_PIN07_V
0= 1.8V;
1= 3.3V.
29–28 Pin 37, ENET0_TXD0 pin output drive strength selection:

BANK4_PIN07_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD6
26 Pin 29, ENET0_TX_EN pin voltage selection:
BANK4_PIN06_V
0= 1.8V;
1= 3.3V.
25–24 Pin 29, ENET0_TX_EN pin output drive strength selection:

BANK4_PIN06_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;


Field Description
RSRVD5
22 Pin 13, ENET0_TX_CLK pin voltage selection:
BANK4_PIN05_V
0= 1.8V;
1= 3.3V.
21–20 Pin 13, ENET0_TX_CLK pin output drive strength selection:

BANK4_PIN05_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD4
18 Pin 47, ENET0_RXD1 pin voltage selection:
BANK4_PIN04_V
0= 1.8V;
1= 3.3V.
17–16 Pin 47, ENET0_RXD1 pin output drive strength selection:

BANK4_PIN04_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD3
BANK4_PIN03_V
0= 1.8V;
1= 3.3V.

BANK4_PIN03_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD2
10 Pin 27, ENET0_RX_EN pin voltage selection:
BANK4_PIN02_V
0= 1.8V;
1= 3.3V.


Field Description
9–8 Pin 27, ENET0_RX_EN pin output drive strength selection:
BANK4_PIN02_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD1
6 Pin 39, ENET0_MDIO pin voltage selection:
BANK4_PIN01_V
0= 1.8V;
1= 3.3V.
5–4 Pin 39, ENET0_MDIO pin output drive strength selection:

BANK4_PIN01_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD0
2 Pin 54, ENET0_MDC pin voltage selection:
BANK4_PIN00_V
0= 1.8V;
1= 3.3V.
1–0 Pin 54, ENET0_MDC pin output drive strength selection:

BANK4_PIN00_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

pins of bank 4.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD7
RSRVD6
RSRVD5
RSRVD4
BANK4_PIN15_V
BANK4_PIN14_V
BANK4_PIN13_V
BANK4_PIN12_V
R

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD3
RSRVD2
RSRVD1
RSRVD0
BANK4_PIN11_V
BANK4_PIN10_V
BANK4_PIN09_V
BANK4_PIN08_V
R

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Field Description
RSRVD7
30 Pin 61, ENET0_CRS pin voltage selection:
BANK4_PIN15_V
0= 1.8V;
1= 3.3V.
29–28 Pin 61, ENET0_CRS pin output drive strength selection:

BANK4_PIN15_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD6
26 Pin 57, ENET0_COL pin voltage selection:
BANK4_PIN14_V
0= 1.8V;


Field Description
1= 3.3V.
25–24 Pin 57, ENET0_COL pin output drive strength selection:

BANK4_PIN14_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD5
22 Pin 31, ENET0_RX_CLK pin voltage selection:
BANK4_PIN13_V
0= 1.8V;
1= 3.3V.
21–20 Pin 31, ENET0_RX_CLK pin output drive strength selection:

BANK4_PIN13_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD4
BANK4_PIN12_V
0= 1.8V;
1= 3.3V.

BANK4_PIN12_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD3
BANK4_PIN11_V
0= 1.8V;
1= 3.3V.

BANK4_PIN11_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;


Field Description
11= Reserved;

RSRVD2
BANK4_PIN10_V
0= 1.8V;
1= 3.3V.

BANK4_PIN10_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD1
BANK4_PIN09_V
0= 1.8V;
1= 3.3V.

BANK4_PIN09_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD0
BANK4_PIN08_V
0= 1.8V;
1= 3.3V.

BANK4_PIN08_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;


pins of bank 4.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD2
BANK4_PIN20_V
R RSRVD3
BANK4_
PIN20_MA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD0
BANK4_PIN16_V
R RSRVD1
BANK4_
PIN16_MA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

Field Description
RSRVD3
RSRVD2
18 Pin 230, JTAG_RTCK pin voltage selection:
BANK4_PIN20_V
0= 1.8V;


Field Description
1= 3.3V.
17–16 Pin 230, JTAG_RTCK pin output drive strength selection:

BANK4_PIN20_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

RSRVD1
RSRVD0
2 Pin 19, ENET_CLK pin voltage selection:
BANK4_PIN16_V
0= 1.8V;
1= 3.3V.
1–0 Pin 19, ENET_CLK pin output drive strength selection:

BANK4_PIN16_
00= 4 mA;
MA
01= 8 mA;
10= 12 mA;
11= Reserved;

pins of bank 4.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSRVD0
9.4.36 PINCTRL Bank 0 Pull Up Resistor Enable Register

(HW_PINCTRL_PULL0)
The PINCTRL Bank 0 PULL Register enables/disables the internal pull up resistors for
those pins in bank 0 which support this operation.
HW_PINCTRL_PULL0: 0x600
HW_PINCTRL_PULL0_SET: 0x604
HW_PINCTRL_PULL0_CLR: 0x608
HW_PINCTRL_PULL0_TOG: 0x60C
The Pull register enables/disables integrated on-chip pull up resistors or pad keepers for the
pins.
Address: HW_PINCTRL_PULL0 – 8001_8000h base + 600h offset = 8001_8600h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1
BANK0_
BANK0_
BANK0_
BANK0_
BANK0_
BANK0_
BANK0_
BANK0_
BANK0_
BANK0_
BANK0_
BANK0_
BANK0_
PIN28
PIN27
PIN26
PIN25
PIN24
PIN23
PIN22
PIN21
PIN20
PIN19
PIN18
PIN17
PIN16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD0
BANK0_
BANK0_
BANK0_
BANK0_
BANK0_
BANK0_
BANK0_
BANK0_
PIN07
PIN06
PIN05
PIN04
PIN03
PIN02
PIN01
PIN00
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

HW_PINCTRL_PULL0 field descriptions

Field Description
RSRVD1
28 Set this bit to one to enable the internal pullup on pin 129, GPMI_RESETN.
BANK0_PIN28
27 Set this bit to one to enable the internal pullup on pin 123, GPMI_CLE.
BANK0_PIN27
26 Set this bit to one to enable the internal pullup on pin 117, GPMI_ALE.
BANK0_PIN26
25 Set this bit to one to disable the internal keeper on pin 127, GPMI_WRN.
BANK0_PIN25
24 Set this bit to one to enable the internal pullup on pin 110, GPMI_RDN.
BANK0_PIN24
23 Set this bit to one to enable the internal pullup on pin 80, GPMI_RDY3.
BANK0_PIN23
BANK0_PIN22
BANK0_PIN21
BANK0_PIN20
19 Set this bit to one to enable the internal pullup on pin 135, GPMI_CE3N.
BANK0_PIN19
BANK0_PIN18
BANK0_PIN17
BANK0_PIN16
RSRVD0
7 Set this bit to one to enable the internal pullup on pin 124, GPMI_D07.
BANK0_PIN07
BANK0_PIN06
BANK0_PIN05
BANK0_PIN04
BANK0_PIN03
BANK0_PIN02

HW_PINCTRL_PULL0 field descriptions (continued)

Field Description
BANK0_PIN01
BANK0_PIN00

(HW_PINCTRL_PULL1)
pins.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BANK1_
BANK1_
BANK1_
BANK1_
BANK1_
BANK1_
BANK1_
BANK1_
BANK1_
BANK1_
BANK1_
BANK1_
BANK1_
BANK1_
BANK1_
BANK1_
PIN31
PIN30
PIN29
PIN28
PIN27
PIN26
PIN25
PIN24
PIN23
PIN22
PIN21
PIN20
PIN19
PIN18
PIN17
PIN16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BANK1_
BANK1_
BANK1_
BANK1_
BANK1_
BANK1_
BANK1_
BANK1_
BANK1_
BANK1_
BANK1_
BANK1_
BANK1_
BANK1_
BANK1_
BANK1_
PIN15
PIN14
PIN13
PIN12
PIN11
PIN10
PIN09
PIN08
PIN07
PIN06
PIN05
PIN04
PIN03
PIN02
PIN01
PIN00
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
31 Set this bit to one to disable the internal keeper on pin 111, LCD_ENABLE.
BANK1_PIN31
30 Set this bit to one to disable the internal keeper on pin 73, LCD_DOTCLK.
BANK1_PIN30


Field Description
29 Set this bit to one to disable the internal keeper on pin 71, LCD_HSYNC.
BANK1_PIN29
28 Set this bit to one to disable the internal keeper on pin 59, LCD_VSYNC.
BANK1_PIN28
27 Set this bit to one to disable the internal keeper on pin 113, LCD_CS.
BANK1_PIN27
26 Set this bit to one to disable the internal keeper on pin 94, LCD_RS.
BANK1_PIN26
25 Set this bit to one to disable the internal keeper on pin 55, LCD_WR_RWN.
BANK1_PIN25
24 Set this bit to one to disable the internal keeper on pin 96, LCD_RD_E.
BANK1_PIN24
23 Set this bit to one to disable the internal keeper on pin 108, LCD_D23.
BANK1_PIN23
BANK1_PIN22
BANK1_PIN21
BANK1_PIN20
BANK1_PIN19
BANK1_PIN18
BANK1_PIN17
BANK1_PIN16
BANK1_PIN15
BANK1_PIN14
BANK1_PIN13
BANK1_PIN12
BANK1_PIN11
BANK1_PIN10
BANK1_PIN09


Field Description
BANK1_PIN08
BANK1_PIN07
BANK1_PIN06
BANK1_PIN05
BANK1_PIN04
BANK1_PIN03
BANK1_PIN02
BANK1_PIN01
BANK1_PIN00

(HW_PINCTRL_PULL2)
pins.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BANK2_PIN27
BANK2_PIN26
BANK2_PIN25
BANK2_PIN24
BANK2_PIN21
BANK2_PIN20
BANK2_PIN19
BANK2_PIN18
BANK2_PIN17
BANK2_PIN16
R RSRVD2 RSRVD1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11
RSRVD0 10 9 8 7 6 5 4 3 2 1 0
BANK2_PIN15
BANK2_PIN14
BANK2_PIN13
BANK2_PIN12
BANK2_PIN10
BANK2_PIN09
BANK2_PIN08
BANK2_PIN07
BANK2_PIN06
BANK2_PIN05
BANK2_PIN04
BANK2_PIN03
BANK2_PIN02
BANK2_PIN01
BANK2_PIN00
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD2
27 Set this bit to one to enable the internal pullup on pin 15, SSP3_SS0.
BANK2_PIN27
26 Set this bit to one to enable the internal pullup on pin 3, SSP3_MISO.
BANK2_PIN26
25 Set this bit to one to enable the internal pullup on pin 9, SSP3_MOSI.
BANK2_PIN25
24 Set this bit to one to disable the internal keeper on pin 286, SSP3_SCK.
BANK2_PIN24
RSRVD1
BANK2_PIN21
BANK2_PIN20
BANK2_PIN19
18 Set this bit to one to enable the internal pullup on pin 288, SSP2_MISO.
BANK2_PIN18
17 Set this bit to one to enable the internal pullup on pin 1, SSP2_MOSI.
BANK2_PIN17
BANK2_PIN16


Field Description
15 Set this bit to one to enable the internal pullup on pin 23, SSP1_DATA3.
BANK2_PIN15
BANK2_PIN14
13 Set this bit to one to enable the internal pullup on pin 17, SSP1_CMD.
BANK2_PIN13
12 Set this bit to one to enable the internal pullup on pin 11, SSP1_SCK.
BANK2_PIN12
RSRVD0
BANK2_PIN10
9 Set this bit to one to enable the internal pullup on pin 275, SSP0_DETECT.
BANK2_PIN09
8 Set this bit to one to enable the internal pullup on pin 276, SSP0_CMD.
BANK2_PIN08
BANK2_PIN07
BANK2_PIN06
BANK2_PIN05
BANK2_PIN04
BANK2_PIN03
BANK2_PIN02
BANK2_PIN01
BANK2_PIN00

(HW_PINCTRL_PULL3)
pins.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD1
RSRVD0
BANK3_PIN30
BANK3_PIN29
BANK3_PIN28
BANK3_PIN27
BANK3_PIN26
BANK3_PIN25
BANK3_PIN24
BANK3_PIN23
BANK3_PIN22
BANK3_PIN21
BANK3_PIN20
BANK3_PIN18
BANK3_PIN17
BANK3_PIN16
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BANK3_PIN15
BANK3_PIN14
BANK3_PIN13
BANK3_PIN12
BANK3_PIN11
BANK3_PIN10
BANK3_PIN09
BANK3_PIN08
BANK3_PIN07
BANK3_PIN06
BANK3_PIN05
BANK3_PIN04
BANK3_PIN03
BANK3_PIN02
BANK3_PIN01
BANK3_PIN00
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
30 Set this bit to one to disable the internal keeper on pin 101, LCD_RESET.
BANK3_PIN30
29 Set this bit to one to disable the internal keeper on pin 279, PWM4.
BANK3_PIN29
BANK3_PIN28
27 Set this bit to one to disable the internal keeper on pin 285, SPDIF.
BANK3_PIN27
26 Set this bit to one to disable the internal keeper on pin 8, SAIF1_SDATA0.
BANK3_PIN26
25 Set this bit to one to disable the internal keeper on pin 281, I2C0_SDA.
BANK3_PIN25
24 Set this bit to one to disable the internal keeper on pin 272, I2C0_SCL.
BANK3_PIN24


Field Description
23 Set this bit to one to disable the internal keeper on pin 12, SAIF0_SDATA0.
BANK3_PIN23
22 Set this bit to one to disable the internal keeper on pin 16, SAIF0_BITCLK.
BANK3_PIN22
21 Set this bit to one to disable the internal keeper on pin 34, SAIF0_LRCLK.
BANK3_PIN21
20 Set this bit to one to disable the internal keeper on pin 28, SAIF0_MCLK.
BANK3_PIN20
RSRVD0
18 Set this bit to one to enable the internal pullup on pin 68, PWM2.
BANK3_PIN18
BANK3_PIN17
BANK3_PIN16
15 Set this bit to one to disable the internal keeper on pin 82, AUART3_RTS.
BANK3_PIN15
14 Set this bit to one to disable the internal keeper on pin 90, AUART3_CTS.
BANK3_PIN14
13 Set this bit to one to disable the internal keeper on pin 86, AUART3_TX.
BANK3_PIN13
12 Set this bit to one to disable the internal keeper on pin 98, AUART3_RX.
BANK3_PIN12
BANK3_PIN11
BANK3_PIN10
9 Set this bit to one to enable the internal pullup on pin 26, AUART2_TX.
BANK3_PIN09
8 Set this bit to one to enable the internal pullup on pin 22, AUART2_RX.
BANK3_PIN08
7 Set this bit to one to enable the internal pullup on pin 74, AUART1_RTS.
BANK3_PIN07
6 Set this bit to one to enable the internal pullup on pin 78, AUART1_CTS.
BANK3_PIN06
BANK3_PIN05
BANK3_PIN04
BANK3_PIN03


Field Description
BANK3_PIN02
BANK3_PIN01
BANK3_PIN00

(HW_PINCTRL_PULL4)
pins.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1 RSRVD0
BANK4_
BANK4_
PIN20
PIN16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BANK4_
BANK4_
BANK4_
BANK4_
BANK4_
BANK4_
BANK4_
BANK4_
BANK4_
BANK4_
BANK4_
BANK4_
BANK4_
BANK4_
BANK4_
BANK4_
PIN15
PIN14
PIN13
PIN12
PIN11
PIN10
PIN09
PIN08
PIN07
PIN06
PIN05
PIN04
PIN03
PIN02
PIN01
PIN00
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1


Field Description
20 Set this bit to one to disable the internal keeper on pin 230, JTAG_RTCK.
BANK4_PIN20
RSRVD0
16 Set this bit to one to disable the internal keeper on pin 19, ENET_CLK.
BANK4_PIN16
15 Set this bit to one to disable the internal keeper on pin 61, ENET0_CRS.
BANK4_PIN15
14 Set this bit to one to disable the internal keeper on pin 57, ENET0_COL.
BANK4_PIN14
13 Set this bit to one to disable the internal keeper on pin 31, ENET0_RX_CLK.
BANK4_PIN13
12 Set this bit to one to disable the internal keeper on pin 41, ENET0_TXD3.
BANK4_PIN12
11 Set this bit to one to disable the internal keeper on pin 43, ENET0_TXD2.
BANK4_PIN11
10 Set this bit to one to disable the internal keeper on pin 53, ENET0_RXD3.
BANK4_PIN10
9 Set this bit to one to disable the internal keeper on pin 51, ENET0_RXD2.
BANK4_PIN09
8 Set this bit to one to enable the internal pullup on pin 35, ENET0_TXD1.
BANK4_PIN08
7 Set this bit to one to enable the internal pullup on pin 37, ENET0_TXD0.
BANK4_PIN07
6 Set this bit to one to enable the internal pullup on pin 29, ENET0_TX_EN.
BANK4_PIN06
5 Set this bit to one to disable the internal keeper on pin 13, ENET0_TX_CLK.
BANK4_PIN05
4 Set this bit to one to enable the internal pullup on pin 47, ENET0_RXD1.
BANK4_PIN04
3 Set this bit to one to enable the internal pullup on pin 45, ENET0_RXD0.
BANK4_PIN03
2 Set this bit to one to enable the internal pullup on pin 27, ENET0_RX_EN.
BANK4_PIN02
1 Set this bit to one to enable the internal pullup on pin 39, ENET0_MDIO.
BANK4_PIN01
0 Set this bit to one to enable the internal pullup on pin 54, ENET0_MDC.
BANK4_PIN00

9.4.41 PINCTRL Bank 5 Pad Keeper Disable Register

(HW_PINCTRL_PULL5)
The PINCTRL Bank 5 PULL Register enables/disables the pad keepers for those pins in
bank 5 which support this operation.
pins.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1 RSRVD0
BANK5_
BANK5_
BANK5_
BANK5_
BANK5_
BANK5_
BANK5_
BANK5_
BANK5_
PIN26
PIN23
PIN22
PIN21
PIN20
PIN19
PIN18
PIN17
PIN16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BANK5_
BANK5_
BANK5_
BANK5_
BANK5_
BANK5_
BANK5_
BANK5_
BANK5_
BANK5_
BANK5_
BANK5_
BANK5_
BANK5_
BANK5_
BANK5_
PIN15
PIN14
PIN13
PIN12
PIN11
PIN10
PIN09
PIN08
PIN07
PIN06
PIN05
PIN04
PIN03
PIN02
PIN01
PIN00
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
26 Set this bit to one to disable the internal keeper on pin 196, EMI_DDR_OPEN.
BANK5_PIN26
RSRVD0
23 Set this bit to one to disable the internal keeper on pin 204, EMI_DQS1.
BANK5_PIN23
22 Set this bit to one to disable the internal keeper on pin 202, EMI_DQS0.
BANK5_PIN22
21 Set this bit to one to disable the internal keeper on pin 200, EMI_CLK.
BANK5_PIN21


Field Description
20 Set this bit to one to disable the internal keeper on pin 195, EMI_DDR_OPEN_FB.
BANK5_PIN20
19 Set this bit to one to disable the internal keeper on pin 222, EMI_DQM1.
BANK5_PIN19
18 Set this bit to one to disable the internal keeper on pin 171, EMI_ODT1.
BANK5_PIN18
17 Set this bit to one to disable the internal keeper on pin 183, EMI_DQM0.
BANK5_PIN17
16 Set this bit to one to disable the internal keeper on pin 173, EMI_ODT0.
BANK5_PIN16
15 Set this bit to one to disable the internal keeper on pin 218, EMI_D15.
BANK5_PIN15
BANK5_PIN14
BANK5_PIN13
BANK5_PIN12
BANK5_PIN11
BANK5_PIN10
BANK5_PIN09
BANK5_PIN08
BANK5_PIN07
BANK5_PIN06
BANK5_PIN05
BANK5_PIN04
BANK5_PIN03
BANK5_PIN02
BANK5_PIN01
BANK5_PIN00

9.4.42 PINCTRL Bank 6 Pad Keeper Disable Register

(HW_PINCTRL_PULL6)
The PINCTRL Bank 6 PULL Register enables/disables the pad keepers for those pins in
bank 6 which support this operation.
pins.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BANK6_PIN24
BANK6_PIN23
BANK6_PIN22
BANK6_PIN21
BANK6_PIN20
BANK6_PIN19
BANK6_PIN18
BANK6_PIN17
BANK6_PIN16
R RSRVD1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD0
BANK6_PIN14
BANK6_PIN13
BANK6_PIN12
BANK6_PIN11
BANK6_PIN10
BANK6_PIN09
BANK6_PIN08
BANK6_PIN07
BANK6_PIN06
BANK6_PIN05
BANK6_PIN04
BANK6_PIN03
BANK6_PIN02
BANK6_PIN01
BANK6_PIN00
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
24 Set this bit to one to disable the internal keeper on pin 166, EMI_CKE.
BANK6_PIN24
23 Set this bit to one to disable the internal keeper on pin 139, EMI_CE1N.
BANK6_PIN23


Field Description
22 Set this bit to one to disable the internal keeper on pin 151, EMI_CE0N.
BANK6_PIN22
21 Set this bit to one to disable the internal keeper on pin 176, EMI_WEN.
BANK6_PIN21
20 Set this bit to one to disable the internal keeper on pin 167, EMI_RASN.
BANK6_PIN20
19 Set this bit to one to disable the internal keeper on pin 172, EMI_CASN.
BANK6_PIN19
18 Set this bit to one to disable the internal keeper on pin 165, EMI_BA2.
BANK6_PIN18
BANK6_PIN17
BANK6_PIN16
RSRVD0
14 Set this bit to one to disable the internal keeper on pin 147, EMI_A14.
BANK6_PIN14
BANK6_PIN13
BANK6_PIN12
BANK6_PIN11
BANK6_PIN10
BANK6_PIN09
BANK6_PIN08
BANK6_PIN07
BANK6_PIN06
BANK6_PIN05
BANK6_PIN04
BANK6_PIN03
BANK6_PIN02


Field Description
BANK6_PIN01
BANK6_PIN00
9.4.43 PINCTRL Bank 0 Data Output Register (HW_PINCTRL_DOUT0)

The Bank 0 Data Output register provides data for all pins in bank 0 that are configured for
GPIO output mode.
HW_PINCTRL_DOUT0: 0x700
HW_PINCTRL_DOUT0_SET: 0x704
HW_PINCTRL_DOUT0_CLR: 0x708
HW_PINCTRL_DOUT0_TOG: 0x70C
This register contains the data that will be driven out all bank 0 pins which are configured
for GPIO output mode. For example, if HW_PINCTRL_MUXSEL0 contains 0x0000000F
and HW_PINCTRL_DOE0 contains 0x00000001, then GPIO0[0] will be driven with the
value from bit 0 of this register, GPIO0[1] will not be driven, and GPIO0[2:15] will be
controlled by the associated primary interfaces.
Address: HW_PINCTRL_DOUT0 – 8001_8000h base + 700h offset = 8001_8700h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
DOUT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_PINCTRL_DOUT0 field descriptions

Field Description
31–29 Empty Description.
RSRVD1
28–0 This field selects the output value (0 or 1) for pins configured as GPIO outputs. Each bit in this register
DOUT corresponds to one of the 29 pins in bank 0.


GPIO output mode.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DOUT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description

GPIO output mode.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
DOUT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSRVD1

GPIO output mode.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD1
DOUT[30:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT[15:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
31 Empty Description.
RSRVD1

GPIO output mode.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
DOUT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSRVD1
9.4.48 PINCTRL Bank 0 Data Input Register (HW_PINCTRL_DIN0)

The current value of all bank 0 pins may be read from the PINCTRL Bank 0 Data Input
Register.
HW_PINCTRL_DIN0: 0x900
HW_PINCTRL_DIN0_SET: 0x904
HW_PINCTRL_DIN0_CLR: 0x908
HW_PINCTRL_DIN0_TOG: 0x90C
This register reflects the current values of all the bank 0 pins. The register accurately reflects
the state of the pin regardless of the setting of the HW_PINCTRL_MUXSELx or
HW_PINCTRL_DOEx registers, but generally, if it is desired to use a pin as a general
purpose input, the pin's two bits in the HW_PINCTRL_MUXSELx register should be set
to 3 (GPIO mode) and the pin's bit in the HW_PINCTRL_DOEx register should be set to
0 (disabled) to insure that the chip is not driving the pin.
Address: HW_PINCTRL_DIN0 – 8001_8000h base + 900h offset = 8001_8900h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1 DIN
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

HW_PINCTRL_DIN0 field descriptions

Field Description
RSRVD1
28–0 Each bit in this read-only register corresponds to one of the 29 pins in bank 0. The current state of each pin
DIN in bank 0, synchronized to HCLK, may be read here.

Register.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DIN
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description


Register.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1 DIN
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSRVD1

Register.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD1
R DIN[30:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DIN[15:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1

Register.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1 DIN
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSRVD1
9.4.53 PINCTRL Bank 0 Data Output Enable Register

(HW_PINCTRL_DOE0)
The PINCTRL Bank 0 Output Enable Register controls the output enable signal for all pins
in bank 0 that are configured for GPIO mode.
HW_PINCTRL_DOE0: 0xb00
HW_PINCTRL_DOE0_SET: 0xb04
HW_PINCTRL_DOE0_CLR: 0xb08
HW_PINCTRL_DOE0_TOG: 0xb0C
For pins in bank 0 that are configured as GPIOs, a 1 in this register will enable the
corresponding bit value from HW_PINCTRL_DOUTxx register to be driven out the pin,
and a 0 in this register will disable the corresponding driver.

Address: HW_PINCTRL_DOE0 – 8001_8000h base + B00h offset = 8001_8B00h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
DOE
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_PINCTRL_DOE0 field descriptions

Field Description
RSRVD1
28–0 Each bit in this register corresponds to one of the 29 pins in bank 0. Setting a bit in this register to one allows
DOE the chip to drive the corresponding pin in GPIO mode.

(HW_PINCTRL_DOE1)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DOE
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description


(HW_PINCTRL_DOE2)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
DOE
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSRVD1

(HW_PINCTRL_DOE3)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD1
DOE[30:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOE[15:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1

(HW_PINCTRL_DOE4)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
DOE
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSRVD1
9.4.58 PINCTRL Bank 0 Interrupt Select Register

The Bank 0 Interrupt Select register selects which of the bank 0 pins may be used as interrupt
sources.
HW_PINCTRL_PIN2IRQ0: 0x1000
HW_PINCTRL_PIN2IRQ0_SET: 0x1004
HW_PINCTRL_PIN2IRQ0_CLR: 0x1008
HW_PINCTRL_PIN2IRQ0_TOG: 0x100C
As described earlier in this chapter, any digital I/O pin can be used as an interrupt source.
This register selects which pins in bank 0 can be used to generate interrupts. If the pin is
selected in this register by setting its bit to 1, then detection of the correct level or edge on
the pin (as chosen by the HW_PINCTRL_IRQLEVEL0 and HW_PINCTRL_IRQPOL0
registers) will set the corresponding bit in the HW_PINCTRL_IRQSTAT0 register. If the
pin is additionally enabled in the HW_PINCTRL_IRQEN0 register, then the interrupt will
be propagated to the interrupt collector as interrupt GPIO0. For example, if this register
contains 0x00000014, then pins GPIO0[2] and GPIO0[4] can be used as interrupt pins, and
no other pins in bank 0 will cause bits to be set in the HW_PINCTRL_IRQSTAT0 register.

Address: HW_PINCTRL_PIN2IRQ0 – 8001_8000h base + 1000h offset = 8001_9000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
PIN2IRQ
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_PINCTRL_PIN2IRQ0 field descriptions

Field Description
RSRVD1
28–0 Each bit in this register corresponds to one of the 29 pins in bank 0:
PIN2IRQ
0= Deselect the pin's interrupt functionality.
1= Select the pin to be used as an interrupt source.

sources.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PIN2IRQ
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
PIN2IRQ

sources.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
PIN2IRQ
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSRVD1
PIN2IRQ

sources.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD1
PIN2IRQ[30:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIN2IRQ[15:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
PIN2IRQ

sources.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
PIN2IRQ
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSRVD1
PIN2IRQ
9.4.63 PINCTRL Bank 0 Interrupt Mask Register (HW_PINCTRL_IRQEN0)

The PINCTRL Bank 0 Interrupt Mask Register contains interrupt enable masks for the pins
in bank 0.
HW_PINCTRL_IRQEN0: 0x1100
HW_PINCTRL_IRQEN0_SET: 0x1104
HW_PINCTRL_IRQEN0_CLR: 0x1108
HW_PINCTRL_IRQEN0_TOG: 0x110C
This register masks the interrupt sources from the pins in bank 0. If a bit is set in this register
and the same bit is set in HW_PINCTRL_IRQSTAT0, an interrupt will be propagated to

the interrupt collector as interrupt GPIO0. For example, if this register contains 0x00000014,
then only bits 2 and 4 in HW_PINCTRL_IRQSTAT0 (corresponding to pins GPIO0[2] and
GPIO0[4]) will cause interrupts from bank 0.
Address: HW_PINCTRL_IRQEN0 – 8001_8000h base + 1100h offset = 8001_9100h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
IRQEN
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_PINCTRL_IRQEN0 field descriptions

Field Description
RSRVD1
IRQEN
1= Enable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT0.
0= Disable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT0.

in bank 1.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
IRQEN
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
IRQEN

in bank 2.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
IRQEN
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
RSRVD1
IRQEN

in bank 3.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD1
IRQEN[30:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRQEN[15:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
IRQEN

in bank 4.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
IRQEN
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
RSRVD1
IRQEN
9.4.68 PINCTRL Bank 0 Interrupt Level/Edge Register

The PINCTRL Bank 0 Interrupt Level/Edge Register selects level or edge sensitivity for
interrupt requests for the pins in bank 0.
HW_PINCTRL_IRQLEVEL0: 0x1200
HW_PINCTRL_IRQLEVEL0_SET: 0x1204
HW_PINCTRL_IRQLEVEL0_CLR: 0x1208
HW_PINCTRL_IRQLEVEL0_TOG: 0x120C
This register selects level or edge detection for interrupt generation. Each pin in bank 0 that
is configured for interrupt generation can be independently set to interrupt on low level,
high level, rising edge, or falling edge by setting bits in this register and
HW_PINCTRL_IRQPOL0 (see below) appropriately.
Address: HW_PINCTRL_IRQLEVEL0 – 8001_8000h base + 1200h offset = 8001_9200h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
IRQLEVEL
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_PINCTRL_IRQLEVEL0 field descriptions

Field Description
RSRVD1
IRQLEVEL
1= Level detection;
0= Edge detection.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
IRQLEVEL
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
IRQLEVEL
1= Level detection;
0= Edge detection.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
IRQLEVEL
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSRVD1
IRQLEVEL
1= Level detection;
0= Edge detection.


Address: HW_PINCTRL_IRQLEVEL3 – 8001_8000h base + 1230h offset = 8001_

9230h
Bit 31
RSRVD1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IRQLEVEL[30:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRQLEVEL[15:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
IRQLEVEL
1= Level detection;
0= Edge detection.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
IRQLEVEL
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSRVD1
IRQLEVEL
1= Level detection;
0= Edge detection.
9.4.73 PINCTRL Bank 0 Interrupt Polarity Register

The PINCTRL Bank 0 Interrupt Polarity Register selects the polarity for interrupt requests
for the pins in bank 0.
HW_PINCTRL_IRQPOL0: 0x1300
HW_PINCTRL_IRQPOL0_SET: 0x1304
HW_PINCTRL_IRQPOL0_CLR: 0x1308
HW_PINCTRL_IRQPOL0_TOG: 0x130C
This register selects the polarity for interrupt generation. Each pin in bank 0 which is
configured for interrupt generation can be independently set to interrupt on low level, high
level, rising edge, or falling edge by setting this register and HW_PINCTRL_IRQLEVEL0
(see above) appropriately.

Address: HW_PINCTRL_IRQPOL0 – 8001_8000h base + 1300h offset = 8001_9300h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
IRQPOL
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_PINCTRL_IRQPOL0 field descriptions

Field Description
RSRVD1
IRQPOL
0= Low or falling edge;
1= High or rising edge.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
IRQPOL
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
IRQPOL

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
IRQPOL
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSRVD1
IRQPOL


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD1
IRQPOL[30:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRQPOL[15:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
IRQPOL

HW_PINCTRL_IRQPOL3 field descriptions (continued)

Field Description

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
IRQPOL
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSRVD1
IRQPOL

9.4.78 PINCTRL Bank 0 Interrupt Status Register

The PINCTRL Bank 0 Interrupt Status Register reflects pending interrupt status for the pins
in bank 0.
HW_PINCTRL_IRQSTAT0: 0x1400
HW_PINCTRL_IRQSTAT0_SET: 0x1404
HW_PINCTRL_IRQSTAT0_CLR: 0x1408
HW_PINCTRL_IRQSTAT0_TOG: 0x140C
This register reflects the pending interrupt status for pins in bank 0. Bits in this register are
automatically set by hardware when an interrupt condition (level high, level low, rising
edge, or falling edge) occurs on a bank 0 pin which has been enabled as an interrupts source
in the HW_PINCTRL_PIN2IRQ0 register. Software may clear any bit in this register by
writing a 1 to the bit at the SCT clear address, for example,
HW_PINCTRL_IRQSTAT0_CLR. Status bits for pins configured as level sensitive interrupts
cannot be cleared unless either the actual pin is in the non-interrupting state, or the pin has
been disabled as an interrupt source by clearing its bit in HW_PINCTRL_PIN2IRQ0. If a
bit is set in this register, and the corresponding bit is also set in the
HW_PINCNTRL_IRQEN0 mask register, then the GPIO0 interrupt will be asserted to the
interrupt collector.
Address: HW_PINCTRL_IRQSTAT0 – 8001_8000h base + 1400h offset = 8001_9400h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
IRQSTAT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_PINCTRL_IRQSTAT0 field descriptions

Field Description
RSRVD1
IRQSTAT
0= No interrupt pending;
1= Interrupt pending.


in bank 1.
writing a 1 to the bit at the SCT clear address, e.g., HW_PINCTRL_IRQSTAT1_CLR.
Status bits for pins configured as level sensitive interrupts cannot be cleared unless either
the actual pin is in the non-interrupting state, or the pin has been disabled as an interrupt
source by clearing its bit in HW_PINCTRL_PIN2IRQ1. If a bit is set in this register, and
the corresponding bit is also set in the HW_PINCNTRL_IRQEN1 mask register, then the
GPIO1 interrupt will be asserted to the interrupt collector.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
IRQSTAT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
IRQSTAT


in bank 2.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
IRQSTAT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSRVD1
IRQSTAT


in bank 3.
Address: HW_PINCTRL_IRQSTAT3 – 8001_8000h base + 1430h offset = 8001_
9430h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD1
IRQSTAT[30:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRQSTAT[15:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Field Description
RSRVD1
IRQSTAT

in bank 4.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
IRQSTAT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
RSRVD1
IRQSTAT
9.4.83 PINCTRL EMI Slice ODT Control (HW_PINCTRL_EMI_ODT_CTRL)

The PINCTRL EMI On Die Termination (ODT) Control Register Controls the load and
calibration of each EMI slice.
HW_PINCTRL_EMI_ODT_CTRL: 0x1a40
HW_PINCTRL_EMI_ODT_CTRL_SET: 0x1a44
HW_PINCTRL_EMI_ODT_CTRL_CLR: 0x1a48
HW_PINCTRL_EMI_ODT_CTRL_TOG: 0x1a4C
This register controls On Die Termination for the EMI SLices 0-3.
Address: HW_PINCTRL_EMI_ODT_CTRL – 8001_8000h base + 1A40h offset =
8001_9A40h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1
ADDRESS_ ADDRESS_ CONTROL_ CONTROL_ DUALPAD_ DUALPAD_
CALIB TLOAD CALIB TLOAD CALIB TLOAD
W
Reset 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SLICE3_ SLICE3_ SLICE2_ SLICE2_ SLICE1_ SLICE1_ SLICE0_ SLICE0_
CALIB TLOAD CALIB TLOAD CALIB TLOAD CALIB TLOAD
W
Reset 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0
HW_PINCTRL_EMI_ODT_CTRL field descriptions

Field Description
RSRVD1

HW_PINCTRL_EMI_ODT_CTRL field descriptions (continued)

Field Description
27–26 ODT Calibration for EMI ADDRESS:
ADDRESS_
With On Die Termination set (through the emi controller):
CALIB
0= Disabled;
1= 1 Res Adj;
2= 2 Res Adj;
3= 3 Res Adj;
With ODT disabled:
Disabled;
25–24 Termination Resistince for On-Die-Termination on chip for EMI ADDRESS:

ADDRESS_
TLOAD
0= Disabled
1= 75 ohm
2= 150 ohm
3= 50 ohm
With ODT disabled:
Disabled;
23–22 ODT Calibration for EMI CONTROL signals:

CONTROL_
CALIB
0= Disabled;
1= 1 Res Adj;
2= 2 Res Adj;
3= 3 Res Adj;
With ODT disabled:
Disabled;
21–20 Termination Resistince for On-Die-Termination on chip for EMI CONTROL:

CONTROL_
TLOAD
0= Disabled
1= 75 ohm
2= 150 ohm
3= 50 ohm
With ODT disabled:
Disabled;
19–18 ODT Calibration for EMI DUALPAD:

DUALPAD_
CALIB
0= Disabled;
1= 1 Res Adj;


Field Description
2= 2 Res Adj;
3= 3 Res Adj;
With ODT disabled:
Disabled;
17–16 Termination Resistince for On-Die-Termination on chip for EMI DUALPAD:

DUALPAD_
TLOAD
0= Disabled
1= 75 ohm
2= 150 ohm
3= 50 ohm
With ODT disabled:
Disabled;
15–14 ODT Calibration for EMI SLICE3:

SLICE3_CALIB
0= Disabled;
1= 1 Res Adj;
2= 2 Res Adj;
3= 3 Res Adj;
With ODT disabled:
Disabled;
13–12 Termination Resistince for On-Die-Termination on chip for EMI SLICE3:

SLICE3_TLOAD
0= Disabled
1= 75 ohm
2= 150 ohm
3= 50 ohm
With ODT disabled:
Disabled;

SLICE2_CALIB
0= Disabled;
1= 1 Res Adj;
2= 2 Res Adj;
3= 3 Res Adj;
With ODT disabled:
Disabled;


Field Description
SLICE2_TLOAD
0= Disabled
1= 75 ohm
2= 150 ohm
3= 50 ohm
With ODT disabled:
Disabled;

SLICE1_CALIB
0= Disabled;
1= 1 Res Adj;
2= 2 Res Adj;
3= 3 Res Adj;
With ODT disabled:
Disabled;

SLICE1_TLOAD
0= Disabled
1= 75 ohm
2= 150 ohm
3= 50 ohm
With ODT disabled:
Disabled;

SLICE0_CALIB
0= Disabled;
1= 1 Res Adj;
2= 2 Res Adj;
3= 3 Res Adj;
With ODT disabled:
Disabled;

SLICE0_TLOAD
0= Disabled
1= 75 ohm


Field Description
2= 150 ohm
3= 50 ohm
With ODT disabled:
Disabled;
9.4.84 PINCTRL EMI Slice DS Control (HW_PINCTRL_EMI_DS_CTRL)

The PINCTRL EMI On Die Termination (DS) Control Register Controls the load and
calibration of each EMI slice.
HW_PINCTRL_EMI_DS_CTRL: 0x1b80
HW_PINCTRL_EMI_DS_CTRL_SET: 0x1b84
HW_PINCTRL_EMI_DS_CTRL_CLR: 0x1b88
HW_PINCTRL_EMI_DS_CTRL_TOG: 0x1b8C
This register controls Pad Drive Strength for the EMI SLices 0-3.
Address: HW_PINCTRL_EMI_DS_CTRL – 8001_8000h base + 1B80h offset = 8001_
9B80h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1
DDR_MODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD0
ADDRESS_ CONTROL_ DUALPAD_
SLICE3_MA SLICE2_MA SLICE1_MA SLICE0_MA
MA MA MA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_PINCTRL_EMI_DS_CTRL field descriptions

Field Description
RSRVD1
17–16 set working mode for EMI pads, default is DDR2 mode:
DDR_MODE
bit 1 controls DDR2_EN

HW_PINCTRL_EMI_DS_CTRL field descriptions (continued)

Field Description
bit 0 controls LVDDR2_ENB
00 mDDR — mDDR(LPDDR1) mode
01 DISABLED — low power suspend mode, in which EMI pads are disabled
10 LVDDR2 — LVDDR2 mode
11 DDR2 — DDR2 mode
RSRVD0
13–12 Pin output drive strength selection for the EMI address signals:
ADDRESS_MA
00= 5 mA;
01= 10 mA;
10= 20 mA;
11= Reserved;
11–10 Pin output drive strength selection for the EMI control signals:
CONTROL_MA
00= 5 mA;
01= 10 mA;
10= 20 mA;
11= Reserved;
9–8 Pin output drive strength selection for the dual pads (CLK/CLKN and DQS/DQSN):
DUALPAD_MA
00= 5 mA;
01= 10 mA;
10= 20 mA;
11= Reserved;
7–6 Pin output drive strength selection for SLICE 3:

SLICE3_MA
00= 5 mA;
01= 10 mA;
10= 20 mA;
11= Reserved;

SLICE2_MA
00= 5 mA;
01= 10 mA;
10= 20 mA;
11= Reserved;

SLICE1_MA
00= 5 mA;
01= 10 mA;
10= 20 mA;

HW_PINCTRL_EMI_DS_CTRL field descriptions (continued)

Field Description
11= Reserved;

SLICE0_MA
00= 5 mA;
01= 10 mA;
10= 20 mA;
11= Reserved;

Chapter 10
Clock Generation and Control (CLKCTRL)
10.1 Clock Generation and Control (CLKCTRL) Overview

The clock control module, or CLKCTRL, generates the clock domains for all components
in the i.MX28 system. The crystal clock or PLL clock are the two fundamental sources used
to produce all the clock domains. For lower performance and reduced power consumption,
the crystal clock is selected. The PLL is selected for higher performance requirements but
requires increased power consumption. In most cases, when the PLL is used as the source,
a phase fractional divider (PFD) can be programmed to reduce the PLL clock frequency by
up to a factor of 2.
The PLL and PFD clocks are used as reference clock sources to drive digital clock dividers
in the clock control module. These reference clocks, or ref_<clock>, drive the digital clock
dividers in CLKCTRL. The digital clock dividers have three modes of operation, integer
divide mode, fractional divide mode, and gated clock mode. The details of these three modes
will be described to understand which mode should be selected to achieve the desired
frequency.
All programming control for system clocks are contained in the CLKCTRL module. All
clock domains have a programmable clock frequency to meet application requirements.
Also, all analog clock control programming is done indirectly through the CLKCTRL
module. This contains the complexity of overall system clock selection to a single device.
Also, the hardware used to generate all clock domains is replicated. Following is a description
of all clock domains in the i.MX28 system.
10.2 Clock Structure

The reference clocks are used in CLKCTRL as fundamental clock sources to produce clock
domains throughout the system. A reference clock can be either the crystal clock, 480 MHz
PLL, or PFD output from the analog module. The selected reference clock is used by a
digital clock divider to produce the desired clock domain. The table below summarizes all
available reference clocks used within the CLKCTRL and all clock domains used in the

Clock Structure
system. The diagram that follows depicts all clock domains and how they are connected
within the CLKCTRL module. This should provide a reference for how clocks are generated
within the i.MX28 system.
10.2.1 Table of System Clocks

The following table summarizes the clocks produced by the clock control module.
Table 10-1. System Clocks
NAME REFERENCE DI- DESCRIPTION
VIDE/FREQ
Reference Clocks.
ref_xtal xtal_24m/ 1 This is the muxed select between the internal ring oscillator and the external
crystal.
ring_24m
ref_cpu PLL0 9 phase The 9 phase fractional divider output used as the reference for the CPU clock
divider.
ref_emi PLL0 9 phase The 9 phase fractional divider output used as the reference for the EMI clock di-
vider.
ref_io0 PLL0 9 phase The 9 phase fractional divider output used as the reference for the SSP0/SSP1
clock dividers.
ref_io1 PLL0 9 phase The 9 phase fractional divider output used as the reference for the SSP2/SSP3
clock divider.
ref_pix PLL0 9 phase The 9 phase fractional divider output used as the reference for the LCDIF clock
divider.
ref_hsadc PLL0 9 phase The 9 phase fractional divider output used as the reference for the HSADC clock
divider.
ref_gpmi PLL0 9 phase The 9 phase fractional divider output used as the reference for the GPMI clock
divider.
ref_pll PLL0 1 This is the raw PLL output used as the reference for the SAIF0 and SAIF1 clock
divider.
ref_enet_pll PLL2 1 This is the raw PLL output used as the reference for the ENET clock divider.
Divided clock domains referenced from PLL or Xtal clock.
clk_p ref_xtal 10/6 bits ARM core clock.

/ref_cpu
clk_h clk_p 5 bits AHB/APBH clock domain. clk_h is a gated branch of the clk_p domain.
clk_h_flex- clk_h 1 Flexcan0 Message Buffer Management (MBM) clock whose clock gating is con-
can0_ipg trolled by hw_clkctrl_flexcan register.

Chapter 10 Clock Generation and Control (CLKCTRL)

VIDE/FREQ
clk_h_flex- clk_h 1 Flexcan1 Message Buffer Management (MBM) clock whose clock gating is con-
can1_ipg trolled by hw_clkctrl_flexcan register.
clk_h_flex- clk_h 1 Flexcan0 bus clock which is gated off when no access to flexcan0 module.
can0
clk_h_flex- clk_h 1 Flexcan1 bus clock which is gated off when no access to flexcan1 module.
can1
clk_h_en- clk_h 1 Ethernet Switch bus clock whose clock gating is controlled by hw_clkctrl_enet
et_swi register.
clk_h_mac0 clk_h 1 Ethernet MAC0 bus clock whose clock gating is controlled by hw_clkctrl_enet
register.
clk_h_mac1 clk_h 1 Ethernet MAC1 bus clock whose clock gating is controlled by hw_clkctrl_enet
register.
clk_ocrom clk_h 1 OCROM bus clock whose clock gating is controlled by OCROM controller H/W.
clk_etm ref_xtal 6/6 bits ARM etm clock.

/ref_cpu
clk_emi ref_xtal 4/6 bits External DDR interface clock.

/ref_emi
/ref_cpu
clk_ssp0 ref_xtal/ref_io0 9 bits SSP0 interface clock.
clk_gpmi ref_xtal 8 bits General purpose memory interface clock domain.

/ref_gpmi
clk_sp- ref_xtal Clk_spdif is an intermediate clock that drives the clk_pcmspdif fractional clock
dif/clk_pcmsp- divider.
/ref_pll
dif
clk_saif0 ref_xtal/ref_pll DDA Serial Audio Interface clock domain. Its reference is the PLL clock output which
drives a DDA (Digital Differential Analyzer) fractional divider.
clk_saif1 ref_xtal/ref_pll DDA Serial Audio Interface clock domain. Its reference is the PLL clock output which
drives a DDA (Digital Differential Analyzer) fractional divider.
clk_dis_lcdif ref_xtal/ref_pix 13 bits LCD interface clock.
clk_hsadc ref_hsadc 9/18/36/ 72 High-Speed ADC clock.

Clock Structure

VIDE/FREQ
clk_enet_time ref_pll 6 bits Ethernet 1588 timer clock

/ref_xtal
/ref_net_pll
Divided clock domains referenced from Xtal clock.
clk_x ref_xtal 10 bits APBX clock domain.
clk_uart ref_xtal 2 bits UART clock domain.
Fixed clock domains.
clk_xtal24m ref_xtal 24Mhz Used for the PWM and analog 24 MHz clock domains.
clk_32k ref_xtal 32khz Fixed 32 KHz clock domain. The reference is the 24 MHz crystal and divides by
768 to produce 32 KHz.
clk_flex- ref_xtal 24MHz Flexcan0 CAN Protocol Interface(CPI) clock without gating.
can0_nogate
clk_flex- ref_xtal 24MHz Flexcan1 CAN Protocol Interface(CPI) clock without gating.
can1_nogate
clk_flexcan0 ref_xtal 24MHz Flexcan0 CAN Protocol Interface (CPI) clock with gating which is controlled by
FLEXCAN H/W.
clk_flexcan1 ref_xtal 24MHz Flexcan1 CAN Protocol Interface (CPI) clock with gating which is controlled by
FLEXCAN H/W.
clk_lradc2k ref_xtal 2khz Fixed 2 KHz clock domain.

10.2.2 Logical Diagram of Clock Domains

System PLL1, USB1
-------------------------------------
HW_CLKCTRL_PLL1CTRL
PLL1 PLL 480M UTMI1_CLK480M
HW_CLKCTRL_PLL0CTRL
UTMI0_CLK480M
7 bit
ICG Int/Frac CLK_ETM
ref_xtal
HW_CLKCTRL_ETM
ICG CLK_H_FLEXCAN_IPG(x2)
ICG CLK_H_ENET_SWI
Dynamic Power CLK_H
EN1 ICG
Adjust EN2 ICG CLK_OCROM
HW_CLKCTRL_HBUS
5 bit ICG CLK_H_MAC(x2)
System PLL0, Multi-Output PLL HW_CLKCTRL_HBUS 1 to 31
Each output configurable for ICG CLK_H_FLEXCAN0(x2)
frequency and bypass. HW_CLKCTRL_CPU 6 bit
------------------------------------- HW_CLKCTRL_EMI 6 bit
ref_cpu CLK_P_NG
ICG Phase Div
ref_emi
Int
ICG Phase Div
ref_io0 ref_xtal ICG Int/Frac ICG CLK_P
ICG Phase Div
ref_io1 HW_CLKCTRL_CPU 10 bit HW_CLKCTRL_CPU & INTERRUPT WAIT circuit
PLL0 ICG Phase Div
ref_pix HW_CLKCTRL_EMI 4 bit
ICG Phase Div
ref_hsadc ICG CLK_EMI
ICG Phase Div
ref_gpmi ref_emi 6 bit
ICG Phase Div Int
ref_pll
ref_xtal ICG Int HW_CLKCTRL_EMI_SYNC_MODE_EN
PLL 480M HW_CLKCTRL_EMI 4 bit
ref_io0 9 bit
ref_xtal ICG Int/Frac CLK_SSP (X2)
HW_CLKCTRL_SSP0(1)
ref_io1 9 bit
ref_xtal ICG Int/Frac CLK_SSP (X2)
HW_CLKCTRL_SSP2(3)
ref_pix 13 bit
ref_xtal ICG Int/Frac ICG CLK_DIS_LCDIF
HW_CLKCTRL_DIS_LCDIF0
ref_hsadc
HSADC
CLK_HSADC
HW_CLKCTRL_HSADC DIV
ref_gpmi
10 bit
ref_xtal
ICG Int/Frac CLK_GPMI
HW_CLKCTRL_GPMI
ref_pll
16 bit
ref_xtal
ICG Frac CLK_SAIF (X2)
HW_CLKCTRL_SAIF
HW_CLKCTRL_SPDIF 9 bit
ICG 4 Frac CLK_PCMSPDIF
Fixed Divider via HW_SPDIF_SRR
ref_pll
6 bit
Crystal Clock
ref_xtal Int ICG CLK_ENET_TIME
XTAL _CLK24M
enet_rmii_clk_in HW_CLKCTRL_ENET
24.000 MHz 0
ICG CLK_UART
gl
ref_xtal HW_CLKCTRL_ENET_TIME_SEL
Ring Oscillator 1 HW_CLKCTRL_XTAL
RING_CLK24M (2 Clock Gate control bits)
ICG CLK_PWM24M
24.000 MHz
HW_POWER_MINPWR
HW_CLKCTRL_XTAL
ICG 750 CLK_32K
Fixed Divider
16 CLK_LRADC2k
Fixed Divider
10 bit
ICG Int/Frac CLK_X
HW_CLKCTRL_XBUS
CLK_ANA24M
HW_CLKCTRL_XTAL
Crystal Clock ICG 768

CLK_RTC32K
XTAL _CLK32K
32.768 kHz /
HW_RTC_PERSISTENT0_CLKSOURCE CLK_FLEXCAN_NOGATE (x2)
32.0 kHz
ICG CLK_FLEXCAN (x2)
ref_enet_pll via ENET Controller H/W via FLEXCAN Controller H/W
PLL2 50M Int CLK_ENET_OUT
ENET_CLK
enet_rmii_clk_in
ICG CLK_ENET_RMII
PAD
CLK_ENET_OUT HW_CLKCTRL_ENET
HW_CLKCTRL_ENET_CLK_OUT_EN
ICG CLK_MAC0_RX
ENET_MII_PHY0 HW_CLKCTRL_ENET
ICG CLK_MAC0_TX
Others Legend
Analog Unless otherwise shown, all
Digital – Xtal Only multiplexers are controlled via
Digital – Xtal or PLL HW_CLKCTRL_CLKSEQ
Digital – PLL Only Within CLKCTRL
Figure 10-1. Logical Diagram of Clock Domains

Clock Structure
10.2.3 Clock Domain Description

All major functional clock domains/branches have trunk level clock gating for power
management. The intent is to gate clock domains off when modules of certain applications
are not necessary. This clock gating is instantiated using an ICG element from the standard
cell library. Software will have to enable the clock domain that drives on chip devices where
trunk level clock gating is implemented.
The location of ICG elements to gate clock domains is not systematic. Since most of the
clock structures throughout the system are unique, the location of ICGs for clock tree power
reduction differs from one domain to the other. The location of these ICGs to gate off clock
domains is apparent in the clock structure diagram.
All clock domains are asynchronous unless noted otherwise.
10.2.3.1 CLK_P, CLK_H

The clk_p domain is used to drive the integrated ARM9 core. The reference for clk_p can
be either ref_xtal or ref_cpu. The reference ref_cpu drives a 6-bit clock divider to provide
a maximum divide down of the reference clock by 2^6. The reference ref_xtal drives a
10-bit clock divider to provide a maximum divide down of the selected reference clock by
2^10. All of the ARM core and SoC components on the clk_h branch are considered to be
on the clk_p domain. The clk_h is actually a branch of the clk_p domain. So, clk_h runs
synchronous to clk_p.
The clk_h domain can be programmed to any divided ratio with respect to the clk_p domain
depending on performance and power requirements. A dynamic clock frequency management
controller monitors the system performance requirements and scales the clk_h frequency
to meet the performance needs. When the CPU or support components require data transfer
to/from the system memory, the frequency manager scales the clk_h domain to meet the
system performance requirements. Also, when the system is quiesced, the clk_h frequency
is reduced to save power.
The clk_h has a 5-bit divider that divides the clk_p domain to produce the clk_h domain.
The frequency for clk_h can be clk_p/32 <= clk_h <= clk_p. Two divide modes exist for
the clk_h branch:
• Integer divide: In this mode, the value programmed in the hw_clkctrl_hbus.div field
represents an integer divide value.
• Fractional divide: In this mode, the value programmed in the hw_clkctrl_hbus.div field
represents a binary fraction. When the accumulation of the current count and the
programmed divide value carry out of the most significant bit, a clk_h pulse is generated.
For example, to achieve a 8:3 clk_p:clk_h clock ratio, set the div field to 0.01100 which
represents (0*1/2) + (1*1/4) + (1*1/8) + (0*1/16) + (0*1/32). Note, fractional divide
can not be used when clk_emi is synchronous with clk_h.
The clk_h branch can be further divided by the dynamic clock frequency adjustment logic,
(hw_clkctrl_emi_sync_mode_en = 0 only). When all the system clk_h components are not
busy and their respective busy signals are inactive, the clk_h branch is further divided down
by the value in the hw_clkctrl_hbus register. The frequency reduction of the clk_h branch
saves overall power consumption. Note, the dynamic clock frequency adjustment logic
should not be enabled when clk_emi is synchronous with clk_h.
10.2.3.2 CLK_EMI
The external memory interface domain is called clk_emi. This clock can be asynchronous
to clk_h to achieve the highest possible clock rate for the EMI interface, or synchronously
to minimize the incurred latency for CPU access to external DRAM. This option is provided
to tradeoff the optimization of performace for systems that are dependent on memory access
latency or throughput.
When the hw_clkctrl_emi_sync_mode_en bit is set to 1, clk_h is synchronous and edge
aligned with the emi clock and clk_p. The emi clock dividers will set the frequency of clk_h
and clk_emi domains when synchronous mode is selected. In synchronous mode, the dynamic
clock frequency adjust logic should be disabled. This is required since DRAM devices
cannot operate correctly with changing clock frequencies.
10.2.3.3 System Clocks

All reference clock domains used in the CLKCTRL are driven by replicated instances of
the PFD pre dividers in the analog module. These PFD reference clocks drive replicated
instances of a single digital clock divider design to create all system clocks. The following
sections describe the features of the digital clock dividers and how these drives can be used
to create clocks throughout the system. The CLKCTRL structural diagram should be used
with the digital clock divider description to understand how clocks are generated in the
i.MX28 system.
10.3 CLKCTRL Digital Clock Divider

The digital clock divider that is used to drive all the functional clock domains has three
modes of operation. These include:
• Integer divide mode

CLKCTRL Digital Clock Divider
• Fractional divide mode

• Gated clock divide mode
These modes are described in the following three sections.
10.3.1 Integer Clock Divide Mode

Each divider has the capability to divide an input reference frequency by a fixed integer
value. This is the most common mode that will be used to select a particular clock frequency.
For a desired clock frequency, first try to select a PFD reference clock frequency AND an
integer clock divide value to achieve the desired clock domain frequency. This mode is
selected when the respective frac_en field in the clock control register is logic 0. The divide
value will be in the range of 1 to 2^N. When programming the DIV field to 1, the reference
clock for the domain is passed and the clock domain assumes the same frequency as the
reference domain. When a value of 2 is programmed, the clock domain frequency will be
half the reference clock frequency. The maximum divide value depends on the number of
bits each digital clock divider implements. This is different for each digital clock divider.
The number of bits implemented for each divider is indicated by each DIV field that controls
each clock domain. Divide by zero is NOT a valid programming value for the DIV field of
any clock control PIO register.
10.3.2 Fractional Clock Divide Mode

This mode is used to divide a reference clock in the range of 2 < div < 2^N. The fractional
clock divider in the CLKCTRL module implements a fractional counter to approximate a
divided clock with respect to the selected reference frequency. The accuracy of the output
clock is dependent on the extent of the bits used to implement the fractional counter. The
reference clock frequency and the fractional divide value must both be selected to achieve
the desired output frequency.
This mode is enabled when setting the FRAC_EN field of the respective clock domain
control register to logic 1 AND the most significant bit of the DIV field is logic 0. Do NOT
use this mode to divide the reference clock domain by an integer value (such as 4, 8, and
so on). Use the integer divide mode to achieve the best results to divide by an integer.

Note
It is important to note that the nearest rising or falling edge of the
input reference clock frequency is used to approximate the rising
edge of the output clock domain. So, the output clock frequency
will jitter based on the input reference clock frequency and the
programmed fractional divide value.
10.3.2.1 Fractional Clock Divide Example, Divide by 3.5

As an example, if the desired divide value is 3.5, the digital approximation of 1/3.5 is
0.01001001 using a 8 bit fractional approximation. The most significant bit of the div field
in this case is logic 0, so the fractional divide mode is selected. The following sequence
indicates the first eight values of the fractional clock divider. The accumulated count is
simply the current value incremented by the value programmed in the div field on each
cycle.
1. 0.01001001
2. 0.10010010
3. 0.11011011
4. 1.00100100 (carry out of MSB initiates an output clock edge)
5. 0.01101101
6. 0.10110110
7. 0.11111111
8. 1.01001000 (output edge initiated)
When the carry out of the fractional count is one, a rising edge output pulse is initiated and
the remainder of the accumulator is preserved. The sub-fractional accumulated value is
considered to determine if the output edge should occur on the falling edge of the reference
clock or the rising edge of the reference clock to minimize the output clock jitter.
10.3.2.1.1 Fractional ClockDivide Example, Divide by 3/8
This example uses a 3-bit fractional accumulator to divide the reference clock input by 3/8.
There are 3 output clock edges produced for every eight input reference clock edges. An
output edge is generated on every cycle that the fractional accumulator carries out of the
most significant bit. Notice when the fractional component is .01, the output edge is shifted
and generated off the falling edge of the input reference clock. This is done to produce the
best output duty cycle that can be achieved based on the input reference clock frequency.
Clock Frequency Management
3 output clocks repeats

every 8 reference clocks
CLK_REF
3 bit divider 0.000 0.011 0.110 1.001 0.100 0.111 1.010 0.101 1.000 0.011
CLK_OUT
2nd cycle on falling clk_ref

½ cycle shift
Figure 10-2. Fractional Clock divide; 3/8 example
10.3.3 Gated Clock Divide Mode

This mode is selected when the reference clock frequency is divided by a range of 1 < div
< 2. To select this mode, program the FRAC_EN field to logic 1 and progarm the DIV field
with the most significant bit set to logic 1. In this case, the reference clock is enabled/disabled
on a cycle by cycle basis to pass to the output clock domain. Essentially, the reference clock
is gated on or off depending on the carry out bit of the fractional count accumulator. This
option is useful to divide the 24 MHz clock to a range between 12 to 24 MHz. The effective
period is equal to the reference period since the output clock is a gated version of the
reference clock. For example, a divide value of 4/3 will allow three consecutive pulses of
the reference clock to propagate and will then gate off a single reference clock cycle. The
edge to edge timing is effectively equal to the reference clock.
Output clock period
equal to reference clock.
CLK_REF
CLK_OUT
3 output clocks for every

4 reference clocks.
Figure 10-3. Divide Range 1 < div < 2
10.4 Clock Frequency Management

Clock frequency selection for some domains can be a function of multiple reference clock
sources and divide parameters that are set in the CLKCTRL PIO control registers. The most
extreme case is using a programmable fractional PLL clock divider, a multiplexer that
selects either the xtal clock or fractional PLL clock as a source to drive the CLKCTRL
divider, and the divide value for the CLKCTRL divider itself. When programming a selected
frequency, the sequence of events to achieve a given frequency must maintain the integrity

of the system as a whole. During a clock system context switch, intermediate clock
frequencies for the selected domains cannot be faster than the sub system or the I/O interface
which is designed to support.
It is expected that the sequence of events when a clock domain is tuned to a desired frequency
be managed by a software using a hardware status polling mechanism. Each parameter has
an associated enable bit so that all the divide parameters can be programmed in advance of
the parameters taking effect. A single register, hw_clkctrl_clkseq, contains all the enable
bits that cause the divide parameters to take effect. The enable bits can be set, the busy bits
can be polled for each parameter, and thus the enable/busy sequencing through software
control can manage the tuning of clock frequencies throughout the system.
10.5 Analog Clock Control

Analog clock control is performed indirectly through PIO accessable registers in the
CLKCTRL module. The analog circuits that are controlled through CLKCTRL PIO access
are the PLL and all instances of the phase fractional dividers, or PFDs.
10.6 CPU and EMI Clock Programming

A defined protocol is necessary for selecting clock frequencies and root sources for driving
the clk_p and clk_emi domains. These two clock structures are unique in that each implement
a separate divider, one referenced by xtal clock and the other referenced by a PLL/PFD
structure. The roots of these clocks must be programmed in order of the sources furthest
from the trunk first. Elements in the clock roots should subsequently be configured along
the root path up to the desired clock trunk. The programming sequence to go from a clock
that is referenced from the xtal clock to the PLL is outlined below. This is the case when
the device is in low power operation and there exists the need for higher clock rates to meet
the demands of a more compute-intensive application.
1. The crystal is the current source for the CPU or the EMI clock domain.
2. Enable the PLL.
3. Wait for PLL lock.
4. Program and enable the PFD with the desired configuration.
5. Clear the PFD clock gate to establish the desired reference clock frequency.
6. Program the CLKCTRL clock divider register (EMI or CPU) that uses the PLL/PFD
as its reference clock.

Chip Reset
7. Switch the bypass to off (select PLL, not crystal).
The requirement is that the roots of the clock are configured and stable before the elements
higher up in the tree are programmed. This will allow the roots to stabilize before selected
as a valid source to drive a clock trunk/tree. If this sequence is not honored, unpredictable
frequencies can occur which may violate the maximum operating frequency of components
on the respective clock trees. Be sure to gate off the clock paths directly downstream from
the PLL before powering off the PLL.
When clk_emi is operating in synchronous mode, the following requirements must be
maintained:
• The clk_p divide value is less than or equal to the clk_emi divide value.
• The clk_emi divide value must be divisable by the clk_p divide value. An example of
possible clk_p:clk_emi divide values would be, but not limited, to 1:1, 1:2, 1:3, 2:2,
2:4, 2:6, 3:3, 3:6, 3:9.
10.7 Chip Reset

Two PIO accessible soft reset bits exists to establish the initial state of the device. These
bits are called HW_CLKCTRL_RESET_CHIP and HW_CLKCTRL_RESET_DIG. Setting
these bits will result in a chip wide reset cycle. When setting the DIG software reset bit, the
digital logic is reset with the exception of the power module and the DCDC converter control
logic. The CHIP software reset bit also initiates the full reset cycle and the power and the
DCDC converter logic are also reset. These two soft reset bits themselves reset during a
soft reset sequence.
Ethernet module is a special case. To avoid network traffic blocking, Ethernet Switch need
to maintain working as long as possible. So when the Ethernet module is in Switch mode,
it can be configured to only POR resettable by setting both
HW_CLKCTRL_ENET_RESET_BY_SW_CHIP and
HW_CLKCTRL_ENET_RESET_BY_SW to 0. If Ethernet module is not in Switch mode,
it will be reset by both DIG software reset bit and CHIP reset bit regardless of the value of
HW_CLKCTRL_ENET_RESET_BY_SW_CHIP and
HW_CLKCTRL_ENET_RESET_BY_SW.
The following figure shows the functionality of these two reset bits.

Chip
Chip_reset_n
Digital Domain
HW_CLKCTRL_RESET_DIG ENET_swi_reset_n
FSM ENET
HW_CLKCTRL_RESET_CHIP
Power
Reset sequence DCDC
Power_reset_n
clock control
signals
Figure 10-4. Reset Logic Functional Diagram

CLKCTRL Hardware Register Format Summary
HW_CLKCTRL memory map
Absolute
Width Section/
(in bits) page
(hex)
8004_0000 System PLL0, System/USB0 PLL Control Register 0 32 R/W 0000_0000h 10.8.1/856
(HW_CLKCTRL_PLL0CTRL0)
8004_0010 System PLL0, System/USB0 PLL Control Register 1 32 R/W 0000_0000h 10.8.2/858
8004_0020 System PLL1, USB1 PLL Control Register 0 32 R/W 8000_0000h 10.8.3/859
8004_0030 System PLL1, USB1 PLL Control Register 1 32 R/W 0000_0000h 10.8.4/861
8004_0040 System PLL2, Ethernet PLL Control Register 0 32 R/W 8000_0000h 10.8.5/862
8004_0050 CPU Clock Control Register (HW_CLKCTRL_CPU) 32 R/W 0001_0001h 10.8.6/863
8004_0060 AHB, APBH Bus Clock Control Register 32 R/W 0000_0001h 10.8.7/865
(HW_CLKCTRL_HBUS)
8004_0070 APBX Clock Control Register (HW_CLKCTRL_XBUS) 32 R/W 0000_0100h 10.8.8/867
8004_0080 XTAL Clock Control Register (HW_CLKCTRL_XTAL) 32 R/W 6000_0001h 10.8.9/868
8004_0090 Synchronous Serial Port0 Clock Control Register 32 R/W 8000_0001h 10.8.10/869
(HW_CLKCTRL_SSP0)
8004_00A0 Synchronous Serial Port1 Clock Control Register 32 R/W 8000_0001h 10.8.11/870
(HW_CLKCTRL_SSP1)
8004_00B0 Synchronous Serial Port2 Clock Control Register 32 R/W 8000_0001h 10.8.12/871
(HW_CLKCTRL_SSP2)
8004_00C0 Synchronous Serial Port3 Clock Control Register 32 R/W 8000_0001h 10.8.13/873
(HW_CLKCTRL_SSP3)
8004_00D0 General-Purpose Media Interface Clock Control Register 32 R/W 8000_0001h 10.8.14/874
(HW_CLKCTRL_GPMI)

HW_CLKCTRL memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
8004_00E0 SPDIF Clock Control Register (HW_CLKCTRL_SPDIF) 32 R/W 8000_0000h 10.8.15/875
8004_00F0 EMI Clock Control Register (HW_CLKCTRL_EMI) 32 R/W 8000_0101h 10.8.16/876
8004_0100 SAIF0 Clock Control Register (HW_CLKCTRL_SAIF0) 32 R/W 8000_0001h 10.8.17/877
8004_0110 SAIF1 Clock Control Register (HW_CLKCTRL_SAIF1) 32 R/W 8000_0001h 10.8.18/878
8004_0120 CLK_DIS_LCDIF Clock Control Register 32 R/W 8000_0001h 10.8.19/880
(HW_CLKCTRL_DIS_LCDIF)
8004_0130 ETM Clock Control Register (HW_CLKCTRL_ETM) 32 R/W 8000_0001h 10.8.20/881
8004_0140 ENET Clock Control Register (HW_CLKCTRL_ENET) 32 R/W E010_0000h 10.8.21/882
8004_0150 HSADC Clock Control Register (HW_CLKCTRL_HSADC) 32 R/W 0000_0000h 10.8.22/883
8004_0160 FLEXCAN Clock Control Register (HW_CLKCTRL_FLEXCAN) 32 R/W 7800_0000h 10.8.23/884
8004_01B0 Fractional Clock Control Register 0 (HW_CLKCTRL_FRAC0) 32 R/W 9292_9292h 10.8.24/885
8004_01C0 Fractional Clock Control Register 1 (HW_CLKCTRL_FRAC1) 32 R/W 0092_9292h 10.8.25/887
8004_01D0 Clock Frequency Sequence Control Register 32 R/W 0044_83FFh 10.8.26/889
(HW_CLKCTRL_CLKSEQ)
8004_01E0 System Reset Control Register (HW_CLKCTRL_RESET) 32 R/W 0000_0012h 10.8.27/891
8004_01F0 ClkCtrl Status (HW_CLKCTRL_STATUS) 32 R 0000_0000h 10.8.28/892
8004_0200 ClkCtrl Version (HW_CLKCTRL_VERSION) 32 R 0C02_0000h 10.8.29/893
10.8.1 System PLL0, System/USB0 PLL Control Register 0

HW_CLKCTRL_PLL0CTRL0: 0x000
HW_CLKCTRL_PLL0CTRL0_SET: 0x004
HW_CLKCTRL_PLL0CTRL0_CLR: 0x008
HW_CLKCTRL_PLL0CTRL0_TOG: 0x00C
The PLL0 Control Register 0 programs the 480 MHz PLL0 and the USB0-clock enables.
EXAMPLE
HW_CLKCTRL_PLL0CTRL0_WR(BF_CLKCTRL_PLL0CTRL0_POWER(1)); // enable PLL and wait 10 us to let

PLL0 lock before using it

Address: HW_CLKCTRL_PLL0CTRL0 – 8004_0000h base + 0h offset = 8004_0000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD3
RSRVD1
R RSRVD6 RSRVD5 RSRVD4
[16:16]
POWER
EN_
LFR_SEL CP_SEL DIV_SEL USB_
CLKS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1[15:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_CLKCTRL_PLL0CTRL0 field descriptions

Field Description
31–30 Always set to zero (0).
RSRVD6
29–28 TEST MODE FOR FREESCALE USE ONLY. Adjusts loop filter resistor.
LFR_SEL
0x0 DEFAULT — Default loop filter resistor
0x1 TIMES_2 — Doubles the loop filter resistor
0x2 TIMES_05 — Halves the loop filter resistor
0x3 UNDEFINED — Undefined
RSRVD5
25–24 TEST MODE FOR FREESCALE USE ONLY. Adjusts charge pump current
CP_SEL
0x0 DEFAULT — Default charge pump current
0x1 TIMES_2 — Doubles charge pump current
0x2 TIMES_05 — Halves the charge pump current
RSRVD4
21–20 TEST MODE FOR FREESCALE USE ONLY. This field is currently NOT supported.
DIV_SEL
0x0 DEFAULT — PLL0 frequency is 480 Mhz
0x1 LOWER — Lower the PLL0 fequency from 480MHz to 384Mhz
0x2 LOWEST — Lower the PLL0 fequency from 480MHz to 288MHz
19 Always set to zero (0).
RSRVD3

HW_CLKCTRL_PLL0CTRL0 field descriptions (continued)

Field Description
18 0: 8-phase PLL outputs for USB0 PHY are powered down. If set to 1, 8-phase PLL outputs for USB0 PHY
EN_USB_CLKS are powered up. Additionally, the utmi clock gate must be deasserted in the UTMI0 phy to enable USB0
operation. If HW_USBPHY_CTRL.ENAUTOSET_USBCLKS of USB0 is set, this bit will be set automatically
when USB0 remote wakeup event happens.
17 PLL Power On (0 = PLL off; 1 = PLL On). Allow 10 us after turning the PLL0 on before using the PLL0 as a
POWER clock source. This is the time the PLL0 takes to lock to 480 MHz. If
HW_USB_PHY_CTRL_ENAUTO_PWRON_PLL of UTM0 is set, this bit will be set to one (1'b1) automatically
when either USB0 or USB1 remote wakeup event happens. Note: The POWER bit must be set to on to
ungate the reference xtal to all of the PLLs.

RSRVD1
10.8.2 System PLL0, System/USB0 PLL Control Register 1

PLL0 Lock Control Register
The lock count is driven off of xtal. So after the PLL0 is powered on, the PLL0 Lock should
be asserted after 50 us.
EXAMPLE
HW_CLKCTRL_PLL0CTRL1_WR(BF_CLKCTRL_PLL0CTRL1_FORCE_LOCK(1)); // force pll lock sequence
HW_CLKCTRL_PLL0CTRL1_WR(BF_CLKCTRL_PLL0CTRL1_FORCE_LOCK(0)); // clear
force pll lock

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R LOCK RSRVD1
FORCE_
LOCK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R LOCK_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Field Description
31 PLL0 Lock bit. 1=PLL0 Locked. 0=PLL0 Unlocked.
LOCK
30 Force the PLL0 Lock sequence to start. 1=Enable Force Lock. This bit is not self clearing.
FORCE_LOCK
29–16 Reserved - Always set to zero (0).
RSRVD1
15–0 Status of the PLL0 lock count. The PLL0 lock bit will assert when the count reaches 0x4B0. The lock count
LOCK_COUNT is driven off of xtal, so it should be asserted after 50 us.
10.8.3 System PLL1, USB1 PLL Control Register 0

The PLL1 Control Register 0 programs the 480 MHz PLL1 and the USB1-clock enables.
EXAMPLE

PLL1 lock before using it

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD6
RSRVD3
RSRVD1
CLKGATEEMI
R RSRVD5 RSRVD4
[16:16]
POWER
EN_
LFR_SEL CP_SEL DIV_SEL USB_
CLKS
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1[15:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
31 TEST MODE FOR FREESCALE USE ONLY.
CLKGATEEMI
RSRVD6
LFR_SEL
0x0 DEFAULT — Default loop filter resistor
0x1 TIMES_2 — Doubles the loop filter resistor
0x2 TIMES_05 — Halves the loop filter resistor
RSRVD5
25–24 TEST MODE FOR FREESCALE USE ONLY. Adjusts charge pump current
CP_SEL
0x0 DEFAULT — Default charge pump current
0x1 TIMES_2 — Doubles charge pump current
0x2 TIMES_05 — Halves the charge pump current
RSRVD4
21–20 TEST MODE FOR FREESCALE USE ONLY. This field is currently NOT supported.
DIV_SEL
0x0 DEFAULT — PLL1 frequency is 480 Mhz
0x1 LOWER — Lower the PLL1 fequency from 480MHz to 384Mhz
0x2 LOWEST — Lower the PLL1 fequency from 480MHz to 288MHz
RSRVD3
18 0: 8-phase PLL outputs for USB1 PHY are powered down. If set to 1, 8-phase PLL outputs for USB1 PHY
EN_USB_CLKS are powered up. Additionally, the utmi clock gate must be deasserted in the UTMI1 phy to enable USB1
operation. If HW_USBPHY_CTRL.ENAUTOSET_USBCLKS of USB1 is set, this bit will be set automatically
when USB0 remote wakeup event happens.
17 PLL Power On (0 = PLL off; 1 = PLL On). Allow 10 us after turning the PLL1 on before using the PLL1 as a
POWER clock source. This is the time the PLL1 takes to lock to 480 MHz. If
HW_USB_PHY_CTRL_ENAUTO_PWRON_PLL of UTM1 is set, this bit will be set to one (1'b1) automatically
when USB1 remote wakeup event happens. Note: The HW_CLKCTRL_PLL0CTRL0_POWER bit must be
set to on to ungate the reference xtal to all of the PLLs.


Field Description
RSRVD1
10.8.4 System PLL1, USB1 PLL Control Register 1

PLL1 Lock Control Register
The lock count is driven off of xtal. So after the PLL1 is powered on, the PLL1 Lock should
be asserted after 50 us.
EXAMPLE
HW_CLKCTRL_PLL1CTRL1_WR(BF_CLKCTRL_PLL1CTRL1_FORCE_LOCK(1)); // force pll lock sequence
HW_CLKCTRL_PLL1CTRL1_WR(BF_CLKCTRL_PLL1CTRL1_FORCE_LOCK(0)); // clear
force pll lock

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R LOCK RSRVD1
FORCE_
LOCK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R LOCK_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
31 PLL1 Lock bit. 1=PLL1 Locked. 0=PLL1 Unlocked.
LOCK
30 Force the PLL1 Lock sequence to start. 1=Enable Force Lock. This bit is not self clearing.
FORCE_LOCK
29–16 Reserved - Always set to zero (0).
RSRVD1
15–0 Status of the PLL1 lock count. The PLL1 lock bit will assert when the count reaches 0x4B0. The lock count
LOCK_COUNT is driven off of xtal, so it should be asserted after 50 us.

10.8.5 System PLL2, Ethernet PLL Control Register 0

The System PLL2 Control Register 0 programs the Ethernet PLL.
EXAMPLE

PLL lock before using it

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HOLD_RING_OFF_B
RSRVD3
RSRVD2
R RSRVD1[22:16]
CLKGATE
POWER
LFR_SEL CP_SEL
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1[15:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
31 PLL Clock Gate. If set to 1, the ENET PLL clock is off (power savings). 0: ENET PLL clock is enabled.
CLKGATE
RSRVD3
LFR_SEL


Field Description
RSRVD2
26 TEST MODE FOR FREESCALE USE ONLY. Adjust VCO phase.
HOLD_RING_
OFF_B
25–24 TEST MODE FOR FREESCALE USE ONLY. Adjusts charge pump current.
CP_SEL
23 PLL Power On (0 = PLL off; 1 = PLL On). Allow 10 us after turning the PLL on before ungating the PLL and
POWER using it as a clock source. This is the time the PLL takes to lock.

RSRVD1
10.8.6 CPU Clock Control Register (HW_CLKCTRL_CPU)

The CPUCLK Clock Control Register provides controls for generating the ARM CPUCLK.
HW_CLKCTRL_CPU: 0x050
HW_CLKCTRL_CPU_SET: 0x054
HW_CLKCTRL_CPU_CLR: 0x058
HW_CLKCTRL_CPU_TOG: 0x05c
Note: Do not write register space when busy bit(s) are high.
EXAMPLE
HW_CLKCTRL_CPU_WR(BF_CLKCTRL_DIV_CPU(12)); // 480 MHz / 12 = 40 MHz
Address: HW_CLKCTRL_CPU – 8004_0000h base + 50h offset = 8004_0050h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REF_XTAL
DIV_XTAL_FRAC_EN
REF_CPU
RSRVD4
BUSY_
BUSY_
R RSRVD5
DIV_XTAL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_CPU_FRAC_EN
INTERRUPT_WAIT
RSRVD2
R RSRVD3 RSRVD1
DIV_CPU
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
HW_CLKCTRL_CPU field descriptions

Field Description
RSRVD5
29 This read-only bit field returns a one when the clock divider is busy transfering a new divider value across
BUSY_REF_ clock domains.
XTAL
BUSY_REF_CPU clock domains.

RSRVD4
26 1 = Enable fractional divide. 0 = Enable integer divide.
DIV_XTAL_
FRAC_EN
25–16 This field controls the divider connected to the crystal reference clock that drives the CLK_P domain when
DIV_XTAL bypass is selected.
NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0.

RSRVD3
12 Gate off CLK_P while waiting for an interrupt.
INTERRUPT_
WAIT
RSRVD2
10 Reserved - Always set to zero (0).
DIV_CPU_
FRAC_EN
RSRVD1
5–0 This field controls the divider connected to the ref_cpu reference clock that drives the CLK_P domain when
DIV_CPU bypass is NOT selected. For changes to this field to take effect, the ref_cpu reference clock must be running.

10.8.7 AHB, APBH Bus Clock Control Register (HW_CLKCTRL_HBUS)

HW_CLKCTRL_HBUS: 0x060
HW_CLKCTRL_HBUS_SET: 0x064
HW_CLKCTRL_HBUS_CLR: 0x068
HW_CLKCTRL_HBUS_TOG: 0x06c
This register controls the clock divider that generates the CLK_H, the clock used by the
AHB and APBH buses, when HW_CLKCTRL_EMI_SYNC_MODE_EN = 0. Note: Do
not write register space when busy bit(s) are high.
EXAMPLE
HW_CLKCTRL_HBUS_WR(BF_CLKCTRL_HBUS_DIV(2)); // set CLK_H to half the ARM clock (CLK_P) frequency
Address: HW_CLKCTRL_HBUS – 8004_0000h base + 60h offset = 8004_0060h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ASM_EMIPORT_AS_
AUTO_CLEAR_DIV_
TRAFFIC_JAM_AS_
RSRVD2
DCP_AS_ENABLE
PXP_AS_ENABLE
CPU_INSTR_AS_
ASM_
BUSY
CPU_DATA_AS_
APBHDMA_AS_
APBXDMA_AS_
TRAFFIC_AS_
ASM_ENABLE
R
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
SLOW_DIV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_FRAC_EN
R RSRVD1
DIV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
HW_CLKCTRL_HBUS field descriptions

Field Description
ASM_BUSY clock domains.

HW_CLKCTRL_HBUS field descriptions (continued)

Field Description
30 Enable auto-slow mode based on DCP activity. 0 = Run at the programmed CLK_H frequency.
DCP_AS_
ENABLE
29 Enable auto-slow mode based on PXP activity. 0 = Run at the programmed CLK_H frequency.
PXP_AS_
ENABLE
28 Reserved
RSRVD2
27 Enable auto-slow mode based on EMI axi0 port activity. 0 = Run at the programmed CLK_HS frequency.
ASM_EMIPORT_
AS_ENABLE
26 Enable auto-slow mode based on APBH DMA activity. 0 = Run at the programmed CLK_H frequency.
APBHDMA_AS_
ENABLE
25 Enable auto-slow mode based on APBX DMA activity. 0 = Run at the programmed CLK_H frequency.
APBXDMA_AS_
ENABLE
24 Enable auto-slow mode when less than three masters are trying to use the AHB. More than three active
TRAFFIC_JAM_ masters will engage the default mode. 0 = Run at the programmed CLK_H frequency.
AS_ENABLE
23 Enable auto-slow mode based on AHB master activity. 0 = Run at the programmed CLK_H frequency.
TRAFFIC_AS_
ENABLE
22 Enable auto-slow mode based on with CPU Data access to AHB. 0 = Run at the programmed CLK_H
CPU_DATA_AS_ frequency.
ENABLE
21 Enable auto-slow mode based on with CPU Instruction access to AHB. 0 = Run at the programmed CLK_H
CPU_INSTR_ frequency.
AS_ENABLE
20 Enable CLK_H auto-slow mode. When this is set, then CLK_H will run at the slow rate until one of the fast
ASM_ENABLE mode events has occurred.
19 If this bit is set to one (1'b1), HW_CLKCTRL_HBUS_DIV is cleared to 1 automatically without S/W interaction
AUTO_CLEAR_ when wakeup interrupt event happens. This feature is to accelerate the waking up from Wait-For-Interrupt
DIV_ENABLE Mode.
Note: This bit is not self-cleared. This feature is supposed to used when the clk_h is reduced to very low
frequency, for example, 24KHz.
18–16 Slow mode divide ratio. Sets the ratio of CLK_H fast rate to the slow rate.
SLOW_DIV
0x0 BY1 — Slow mode divide ratio = 1
15–6 Reserved
RSRVD1

HW_CLKCTRL_HBUS field descriptions (continued)

Field Description
DIV_FRAC_EN
4–0 CLK_P-to-CLK_H divide ratio.
DIV
10.8.8 APBX Clock Control Register (HW_CLKCTRL_XBUS)

This register controls the clock divider that generates the CLK_X, the clock used by the
APBX bus. Note: Do not write register space when busy bit(s) are high.
EXAMPLE
HW_CLKCTRL_XBUS_WR(BF_CLKCTRL_XBUS_DIV(4)); // set apbx xbus clock to 1/4 the 24.0MHz crystal

clock frequency
Address: HW_CLKCTRL_XBUS – 8004_0000h base + 70h offset = 8004_0070h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R BUSY RSRVD1[30:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTO_CLEAR_
DIV_FRAC_
DIV_ENABLE
R RSRVD1[15:12]
EN
DIV
W
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
HW_CLKCTRL_XBUS field descriptions

Field Description
BUSY clock domains.

RSRVD1
11 If this bit is set to one (1'b1), HW_CLKCTRL_XBUS_DIV is cleared to 1 automaticlly without S/W interaction
AUTO_CLEAR_ when wakeup interrupt event happens. This feature is to accelerate the waking up from Wait-For-Interrupt
DIV_ENABLE Mode.
Note: This bit is not self-cleared. This feature is supposed to used when the clk_x is reduced to very low
frequency, for example, 24KHz.

HW_CLKCTRL_XBUS field descriptions (continued)

Field Description
DIV_FRAC_EN
9–0 This field controls the CLK_X divide ratio. CLK_X is sourced from the 24-MHz XTAL through this divider.
DIV Do NOT divide by 0.
10.8.9 XTAL Clock Control Register (HW_CLKCTRL_XTAL)

The XTAL control register provides gating control for clocks sourced from the 24-MHz
XTAL clock domain.
HW_CLKCTRL_XTAL: 0x080
HW_CLKCTRL_XTAL_SET: 0x084
HW_CLKCTRL_XTAL_CLR: 0x088
HW_CLKCTRL_XTAL_TOG: 0x08C
This register controls various fixed-rate divider clocks working off the 24.0-MHz crystal
clock.
EXAMPLE
HW_CLKCTRL_XTAL_WR(BF_CLKCTRL_XTAL_UART_CLK_GATE(0)|BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(1));
Address: HW_CLKCTRL_XTAL – 8004_0000h base + 80h offset = 8004_0080h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLK32K_GATE
UART_CLK_
R RSRVD2 RSRVD1[25:16]
RSRVD3
CLK24M_
TIMROT_
PWM_
GATE
GATE
Reset 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1[15:2]
DIV_UART
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

HW_CLKCTRL_XTAL field descriptions

Field Description
31 If set to 1, fixed 24-MHz clock for the UART, CLK_UART, is gated off.
UART_CLK_
GATE
RSRVD3
29 If set to 1, fixed 24-MHz clock for the PWM, CLK_PWM24M, is gated off.
PWM_CLK24M_
GATE
RSRVD2
26 If set to 1, fixed 32-kHz clock for the TIMROT block, CLK_32K, is gated off.
TIMROT_
CLK32K_GATE
RSRVD1
1–0 Reserved - Always set to one (1)
DIV_UART
10.8.10 Synchronous Serial Port0 Clock Control Register

(HW_CLKCTRL_SSP0)
This register controls the clock divider that generates the clock for the synchronous serial
port (SSP0), CLK_SSP0. Note: Do not write register space when busy bit(s) are high.
EXAMPLE
HW_CLKCTRL_SSP0_WR(BF_CLKCTRL_SSP0_DIV(40));
Address: HW_CLKCTRL_SSP0 – 8004_0000h base + 90h offset = 8004_0090h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD2
CLKGATE
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_FRAC_EN
R RSRVD1[15:10]
DIV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
HW_CLKCTRL_SSP0 field descriptions

Field Description
31 CLK_SSP0 Gate. If set to 1, CLK_SSP0 is gated off. 0: CLK_SSP0 is not gated. When this bit is modified,
CLKGATE or when it is high, the DIV field should not change its value. The DIV field can change ONLY when this clock
gate bit field is low.

RSRVD2
BUSY clock domains.

RSRVD1
DIV_FRAC_EN
8–0 The synchronous serial port clock frequency is determined by dividing the selected reference clock (ref_xtal
DIV or ref_io) by the value in this bit field. This field can be programmed with a new value only when CLKGATE
= 0.

(HW_CLKCTRL_SSP1)
EXAMPLE

Address: HW_CLKCTRL_SSP1 – 8004_0000h base + A0h offset = 8004_00A0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD2
CLKGATE
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_FRAC_EN
R RSRVD1[15:10]
DIV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Field Description

RSRVD2
BUSY clock domains.

RSRVD1
DIV_FRAC_EN
= 0.

(HW_CLKCTRL_SSP2)

EXAMPLE
Address: HW_CLKCTRL_SSP2 – 8004_0000h base + B0h offset = 8004_00B0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD2
CLKGATE
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_FRAC_EN
R RSRVD1[15:10]
DIV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Field Description

RSRVD2
BUSY clock domains.

RSRVD1
DIV_FRAC_EN
= 0.


(HW_CLKCTRL_SSP3)
EXAMPLE
Address: HW_CLKCTRL_SSP3 – 8004_0000h base + C0h offset = 8004_00C0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD2
CLKGATE
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_FRAC_EN
R RSRVD1[15:10]
DIV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Field Description

RSRVD2
BUSY clock domains.

RSRVD1
DIV_FRAC_EN

HW_CLKCTRL_SSP3 field descriptions (continued)

Field Description
= 0.
10.8.14 General-Purpose Media Interface Clock Control Register

(HW_CLKCTRL_GPMI)
This register controls the divider that generates the General-Purpose Media Interface (GPMI)
clock, CLK_GPMI. Note: Do not write register space when busy bit(s) are high.
EXAMPLE
HW_CLKCTRL_GPMI_WR(BF_CLKCTRL_GPMI_DIV(40));
Address: HW_CLKCTRL_GPMI – 8004_0000h base + D0h offset = 8004_00D0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD2
CLKGATE
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_FRAC_EN
R RSRVD1[15:11]
DIV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
HW_CLKCTRL_GPMI field descriptions

Field Description
31 CLK_GPMI Gate. If set to 1, CLK_GPMI is gated off. 0: CLK_GPMI is not gated. When this bit is modified,

HW_CLKCTRL_GPMI field descriptions (continued)

Field Description
RSRVD2
BUSY clock domains.

RSRVD1
DIV_FRAC_EN
9–0 The GPMI clock frequency is determined by dividing the selected reference clock (ref_xtal or ref_io) by the
DIV value in this bit field. This field can be programmed with a new value only when CLKGATE = 0.
10.8.15 SPDIF Clock Control Register (HW_CLKCTRL_SPDIF)

This register controls the clock gate on the SPDIF clock, CLK_PCMSPDIF.
EXAMPLE
HW_CLKCTRL_SPDIF_WR(BF_CLKCTRL_SPDIF_CLKGATE(1));
Address: HW_CLKCTRL_SPDIF – 8004_0000h base + E0h offset = 8004_00E0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD[30:16]
CLKGATE
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD[15:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_CLKCTRL_SPDIF field descriptions

Field Description
31 CLK_PCMSPDIF Gate. If set to 1, CLK_PCMSPDIF is gated off. 0: CLK_PCMSPDIF is not gated. When
CLKGATE this bit is modified, or when it is high, the SPDIF rate change field should not change its value. The SPDIF
rate change field can change ONLY when this clock gate bit field is low.

HW_CLKCTRL_SPDIF field descriptions (continued)

Field Description
RSRVD
10.8.16 EMI Clock Control Register (HW_CLKCTRL_EMI)

This register controls the clock dividers that generate the External Memory Interface (EMI)
clock. Note: Do not write register space when busy bit(s) are high.
EXAMPLE
HW_CLKCTRL_EMI_WR(BF_CLKCTRL_EMI_DIV_XTAL(1));
Address: HW_CLKCTRL_EMI – 8004_0000h base + F0h offset = 8004_00F0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REF_XTAL
REF_CPU
REF_EMI
RESYNC
SYNC_
SYNC_MODE_EN
BUSY_
BUSY_
BUSY_
BUSY_
MODE
BUSY_
DCC_RESYNC_
DCC_
R RSRVD3
CLKGATE
ENABLE
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD2 RSRVD1
DIV_XTAL DIV_EMI
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
HW_CLKCTRL_EMI field descriptions

Field Description
31 CLK_EMI crystal divider Gate. If set to 1, the EMI_CLK divider that is sourced by the crystal reference clock,
CLKGATE ref_xtal, is gated off. 0: CLK_EMI crystal divider is not gated
30 If set to 1, EMI_CLK is synchronous with the APBH clock. If set to 0, EMI_CLK is aysnchronous. In
SYNC_MODE_ synchronous operation, the EMI clock dividers control both EMI_CLK and APBH clock. Both xtal and ref_cpu
EN must be active to switch between asynchronous/synchronous operation.

HW_CLKCTRL_EMI field descriptions (continued)

Field Description
BUSY_REF_ clock domains. This bit is valid when HW_CLKCTRL_EMI_SYNC_MODE_EN = 0.
XTAL
BUSY_REF_EMI clock domains.
BUSY_REF_CPU clock domains. This bit is valid when HW_CLKCTRL_EMI_SYNC_MODE_EN = 1.
26 This read-only bit field returns a one when there is a change in HW_CLKCTRL_EMI_SYNCE_MODE_EN
BUSY_SYNC_ or when there is a change in HW_CLKCTRL_CLKSEQ_BYPASS_CPU and
MODE HW_CLKCTRL_EMI_SYNCE_MODE_EN is set. When this bit returns a one, do not change the CPU or
EMI divider values.

RSRVD3
17 Reserved.
BUSY_DCC_
RESYNC
16 Reserved.
DCC_RESYNC_
ENABLE
RSRVD2
11–8 This field controls the divider connected to the crystal reference clock, ref_xtal, that drives the CLK_EMI
DIV_XTAL domain when bypass IS selected.

RSRVD1
5–0 This field controls the divider connected to the ref_emi reference clock that drives the CLK_EMI domain
DIV_EMI when bypass IS NOT selected. For changes to this field to take effect, the ref_emi reference clock must be
running.
10.8.17 SAIF0 Clock Control Register (HW_CLKCTRL_SAIF0)

This register controls the divider that generates the Serial Audio Interface (SAIF0) clock.
EXAMPLE
HW_CLKCTRL_SAIF0_WR(BF_CLKCTRL_SAIF0_DIV(40));

Address: HW_CLKCTRL_SAIF0 – 8004_0000h base + 100h offset = 8004_0100h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD2
DIV_FRAC_EN
R BUSY RSRVD1
CLKGATE
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
HW_CLKCTRL_SAIF0 field descriptions

Field Description
31 CLK_SAIF0 Gate. If set to 1, CLK_SAIF0 is gated off. 0: CLK_SAIF0 is not gated. When this bit is modified,

RSRVD2
BUSY clock domains.

RSRVD1
16 Always set to one (1) for functional operation. - Notice this is not the reset value.
DIV_FRAC_EN
15–0 The SAIF0 clock frequency is determined by dividing the selected reference clock (ref_xtal or ref_pll) by the
NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. ref_pll should be selected
for functional operation.
10.8.18 SAIF1 Clock Control Register (HW_CLKCTRL_SAIF1)

This register controls the divider that generates the Serial Audio Interface (SAIF1) clock.
EXAMPLE
HW_CLKCTRL_SAIF1_WR(BF_CLKCTRL_SAIF1_DIV(40));
Address: HW_CLKCTRL_SAIF1 – 8004_0000h base + 110h offset = 8004_0110h

Bit 31 30
RSRVD2 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIV_FRAC_EN
R BUSY RSRVD1
CLKGATE
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
HW_CLKCTRL_SAIF1 field descriptions

Field Description
31 CLK_SAIF1 Gate. If set to 1, CLK_SAIF1 is gated off. 0: CLK_SAIF1 is not gated. When this bit is modified,

RSRVD2
BUSY clock domains.

RSRVD1
16 Always set to one (1) for functional operation - Notice this is not the reset value.
DIV_FRAC_EN
15–0 The SAIF1 clock frequency is determined by dividing the selected reference clock (ref_xtal or ref_pll) by the
NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. ref_pll should be selected
for functional operation.

10.8.19 CLK_DIS_LCDIF Clock Control Register

(HW_CLKCTRL_DIS_LCDIF)
This register controls the divider that generates the CLK_DIS_LCDIF clock. Note: Do not
write register space when busy bit(s) are high.
EXAMPLE
HW_CLKCTRL_DIS_LCDIF_WR(BF_CLKCTRL_DIS_LCDIF_DIV(40));
Address: HW_CLKCTRL_DIS_LCDIF – 8004_0000h base + 120h offset = 8004_

0120h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD2
CLKGATE
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD1
DIV_FRAC_EN
R
[15:14]
DIV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
HW_CLKCTRL_DIS_LCDIF field descriptions

Field Description
31 CLK_DIS_LCDIF Gate. If set to 1, CLK_DIS_LCDIF is gated off. 0: CLK_DIS_LCDIF is not gated. When
CLKGATE this bit is modified, or when it is high, the DIV field should not change its value. The DIV field can change
ONLY when this clock gate bit field is low.

RSRVD2
BUSY clock domains.

RSRVD1
DIV_FRAC_EN

HW_CLKCTRL_DIS_LCDIF field descriptions (continued)

Field Description
12–0 The DIS_LCDIF clock frequency is determined by dividing the reference clock, ref_xtal or ref_pix, by the
NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. Do not divide by more than
255.
10.8.20 ETM Clock Control Register (HW_CLKCTRL_ETM)

This register controls the clock divider that generates the clock for the ETM, CLK_ETM.
EXAMPLE
HW_CLKCTRL_ETM_WR(BF_CLKCTRL_ETM_DIV(4));
Address: HW_CLKCTRL_ETM – 8004_0000h base + 130h offset = 8004_0130h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD2
CLKGATE
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_FRAC_EN
R RSRVD1[15:8]
DIV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
HW_CLKCTRL_ETM field descriptions

Field Description
31 CLK_ETM Gate. If set to 1, CLK_ETM is gated off. 0: CLK_ETM is not gated. When this bit is modified, or
CLKGATE when it is high, the DIV field should not change its value. The DIV field can change ONLY when this clock

RSRVD2

HW_CLKCTRL_ETM field descriptions (continued)

Field Description
BUSY clock domains.

RSRVD1
DIV_FRAC_EN
6–0 The ETM clock frequency is determined by dividing the selected reference clock (ref_xtal or ref_cpu) by the
10.8.21 ENET Clock Control Register (HW_CLKCTRL_ENET)

This register provides control for ETHERNET clock generation
EXAMPLE
HW_CLKCTRL_ENET_WR(BF_CLKCTRL_ENET_SLEEP(1));
Address: HW_CLKCTRL_ENET – 8004_0000h base + 140h offset = 8004_0140h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET_BY_SW_CHIP
RSRVD1
STATUS
BUSY_
TIME
RESET_BY_SW
CLK_OUT_EN
R
DISABLE
SLEEP
DIV_TIME TIME_SEL
Reset 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

HW_CLKCTRL_ENET field descriptions

Field Description
31 CLOCK Gate. If set to 1, put Ethernet block in sleep mode. CLK_H_MAC0(1), CLK_H_MAC0(1)_S, and
SLEEP CLK_ENET0(1)_TX are gated off. Ethernet can be wakeup remotely in sleep mode 0: Resume Ethernet
block to normal operation. CLK_H_MAC0(1), CLK_H_MAC0(1)_S, and CLK_ENET_TX are not gated. .
30 This bit is used to gate off all Ethernet clocks when Ethernet is disabled in some use case. If set to 1, gate
DISABLE off all of the Ethernet clocks. Ethernet can not be wakeup remotely when Ethernet is disabled. 0: Do not
gate off Ethernet's clocks.
29 This read-only bit indicates the status of Ehternet module. 1'b1: Ethernet is in SLEEP or DISABLE mode.
STATUS 1'b0: Ethernet is in NORMAL mode.

RSRVD1
BUSY_TIME clock domains.
26–21 This field controls the divider that drives the CLK_ENET_TIME (1588 timer) domain. For changes to this
DIV_TIME field to take effect, the reference clock must be running.
20–19 This field selects clock that drives the Ethernet 1588 timer between the xtal, ref_pll and enet_rmii_clk_in
TIME_SEL sources.
0x0 XTAL — select xtal source
0x1 PLL — select ref_pll source
0x2 RMII_CLK — select enet_rmii_clk_in source which is from PAD
18 This bit controls the ENET_CLK PAD direction. 1: Enable the output; 0: Disable the output. NOTE: This bit
CLK_OUT_EN must be configured before ENET PLL is enabled.
17 Setting this bit to a logic one will enable the function that ENET SWITCH can be reset by SW chip reset
RESET_BY_SW_ (HW_CLKCTRL_RESET.CHIP, or watchdog_reset when HW_CLKCTRL_RESET.WDOG_POR_DISABLE
CHIP is set to 1'b1). This bit's reset value reflects OTP fuse ENET_SWITCH_RESET_BY_SW_CHIP.
16 Setting this bit to a logic one will enable the function that ENET SWITCH can be reset by all software reset
RESET_BY_SW (Either HW_CLKCTRL_RESET.CHIP or HW_CLKCTRL_RESET.DIG). This bit's reset value reflects OTP
fuse ENET_SWITCH_RESET_BY_SW.

RSRVD0
10.8.22 HSADC Clock Control Register (HW_CLKCTRL_HSADC)

This register controls the clock dividers that generate the High Speed ADC (HSADC) clock.
EXAMPLE

HW_CLKCTRL_HSADC_WR(BF_CLKCTRL_HSADC_CLKGATE(1));
Address: HW_CLKCTRL_HSADC – 8004_0000h base + 150h offset = 8004_0150h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD2
R RSRVD1[27:16]
RESETB
FREQDIV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1[15:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_CLKCTRL_HSADC field descriptions

Field Description
RSRVD2
30 0: Reset the HSADC Divider. 1: Divider normal work.
RESETB
29–28 This field selects HSADC Divider's divide factor.
FREQDIV
00: Divide by 9; 01: Divide by 18; 10: Divide by 36; 11: Divide by 72

RSRVD1
10.8.23 FLEXCAN Clock Control Register (HW_CLKCTRL_FLEXCAN)

The FLEXCAN control register provides control for Flexcan0 and Flexcan1 clock generation.
EXAMPLE
HW_CLKCTRL_FLEXCAN_WR(BF_CLKCTRL_FLEXCAN_STOP_CAN0(1));

Address: HW_CLKCTRL_FLEXCAN – 8004_0000h base + 160h offset = 8004_0160h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD2
STATUS
STATUS
CAN0_
CAN1_
RSRVD1[26:16]
STOP_CAN0
STOP_CAN1
R
Reset 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1[15:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_CLKCTRL_FLEXCAN field descriptions

Field Description
RSRVD2
30 If this bit is set to one (1'b1), the FLEXCAN0 will be stopped and all the clocks to FLEXCAN0 are gated off.
STOP_CAN0
29 This read-only bit indicates FLEXCAN0 status. 1'b1: FLEXCAN0 is in STOP mode. 1'b0: FLEXCAN0 is in
CAN0_STATUS NORMAL Mode.
28 If this bit is set to one (1'b1), the FLEXCAN1 will be stopped and all the clocks to FLEXCAN1 are gated off.
STOP_CAN1
27 This read-only bit indicates FLEXCAN1 status. 1'b1: FLEXCAN1 is in STOP mode. 1'b0: FLEXCAN1 is in
CAN1_STATUS NORMAL Mode.

RSRVD1
10.8.24 Fractional Clock Control Register 0 (HW_CLKCTRL_FRAC0)

The FRAC0 control register provides control for PFD clock generation.
HW_CLKCTRL_FRAC0: 0x1B0
HW_CLKCTRL_FRAC0_SET: 0x1B4
HW_CLKCTRL_FRAC0_CLR: 0x1B8

HW_CLKCTRL_FRAC0_TOG: 0x1BC
This register controls the 9-phase fractional clock dividers. The fractional clock frequencies
are a product of the values in these registers. NOTE: This register can only be addressed
by byte instructions. Addressing word or half-word are not allowed.
EXAMPLE
*((u8 *)(HW_CLKCTRL_FRAC0_ADDR + 1)) = 30;
Address: HW_CLKCTRL_FRAC0 – 8004_0000h base + 1B0h offset = 8004_01B0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STABLE
STABLE
IO0_
IO1_
CLKGATEIO0
CLKGATEIO1
R
IO0FRAC IO1FRAC
Reset 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STABLE
STABLE
CPU_
CLKGATECPU
EMI_
CLKGATEEMI
EMIFRAC CPUFRAC
Reset 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0
HW_CLKCTRL_FRAC0 field descriptions

Field Description
31 IO0 Clock Gate. If set to 1, the IO0 fractional divider clock (reference PLL0 ref_io0) is off (power savings).
CLKGATEIO0 0: IO0 fractional divider clock is enabled.
30 This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become
IO0_STABLE stable quickly enough that this field will never need to be used by either device driver or application code.
The value inverts when the new programmed fractional divide value has taken effect. Read this bit, program
the new value, and when this bit inverts, the phase divider clock output is stable. Note that the value will not
invert when the fractional divider is taken out of or placed into clock-gated state.
29–24 This field controls the IO0 clocks fractional divider. The resulting frequency shall be 480 * (18/IO0FRAC)
IO0FRAC where IO0FRAC = 18-35.
23 IO1 Clock Gate. If set to 1, the IO1 fractional divider clock (reference PLL0 ref_io1) is off (power savings).
CLKGATEIO1 0: IO1 fractional divider clock is enabled.
IO1_STABLE stable quickly enough that this field will never need to be used by either device driver or application code.

HW_CLKCTRL_FRAC0 field descriptions (continued)

Field Description
21–16 This field controls the IO1 clocks fractional divider. The resulting frequency shall be 480 * (18/IO1FRAC)
IO1FRAC where IO1FRAC = 18-35.
15 EMI Clock Gate. If set to 1, the EMI fractional divider clock (reference PLL0 ref_emi) is off (power savings).
CLKGATEEMI 0: EMI fractional divider clock is enabled.
14 This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divide should become
EMI_STABLE stable quickly enough that this field will never need to be used by either device driver or application code.
This value inverts when the new programmed fractional divide value has taken effect. Read this bit, program
13–8 This field controls the EMI clock fractional divider. The resulting frequency shall be 480 * (18/EMIFRAC)
EMIFRAC where EMIFRAC = 18-35.
7 CPU Clock Gate. If set to 1, the CPU fractional divider clock (reference PLL0 ref_cpu) is off (power savings).
CLKGATECPU 0: CPU fractional divider clock is enabled.
6 This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divide should become
CPU_STABLE stable quickly enough that this field will never need to be used by either device driver or application code.
5–0 This field controls the CPU clock fractional divider. The resulting frequency shall be 480 * (18/CPUFRAC)
CPUFRAC where CPUFRAC = 18-35.
10.8.25 Fractional Clock Control Register 1 (HW_CLKCTRL_FRAC1)

The FRAC1 control register provides control for PFD clock generation.
HW_CLKCTRL_FRAC1: 0x1C0
HW_CLKCTRL_FRAC1_SET: 0x1C4
HW_CLKCTRL_FRAC1_CLR: 0x1C8
HW_CLKCTRL_FRAC1_TOG: 0x1CC
This register controls the 9-phase fractional clock dividers. The fractional clock frequencies
are a product of the values in these registers. NOTE: This register can only be addressed
by byte instructions. Addressing word or half-word are not allowed.
EXAMPLE
*((u8 *)(HW_CLKCTRL_FRAC1_ADDR + 1)) = 30;

Address: HW_CLKCTRL_FRAC1 – 8004_0000h base + 1C0h offset = 8004_01C0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STABLE
GPMI_
CLKGATEGPMI
R RSRVD2
GPMIFRAC
Reset 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STABLE
HSADC_
STABLE
PIX_
CLKGATEHSADC
CLKGATEPIX
R
HSADCFRAC PIXFRAC
Reset 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0
HW_CLKCTRL_FRAC1 field descriptions

Field Description
RSRVD2
23 GPMI Clock Gate. If set to 1, the GPMI fractional divider clock (reference PLL0 ref_gpmi) is off (power
CLKGATEGPMI savings). 0: GPMI fractional divider clock is enabled.
GPMI_STABLE stable quickly enough that this field will never need to be used by either device driver or application code.
the new value, and when this bit inverts, the phase divider clock output is stable. Note that the value will
not invert when the fractional divider is taken out of or placed into clock-gated state.
21–16 This field controls the GPMI clock fractional divider. The resulting frequency shall be 480 * (18/GPMIFRAC)
GPMIFRAC where GPMIFRAC = 18-35.
15 HSADC Clock Gate. If set to 1, the HSADC fractional divider clock (reference PLL0 ref_adc) is off (power
CLKGATEHSADC savings). 0: HSADC fractional divider clock is enabled.
HSADC_STABLE stable quickly enough that this field will never need to be used by either device driver or application code.
13–8 This field controls the HSADC clock fractional divider. The resulting frequency shall be 480 *
HSADCFRAC (18/HSADCFRAC) where HSADCFRAC = 18-35.
7 PIX Clock Gate. If set to 1, the PIX fractional divider clock (reference PLL0 ref_pix) is off (power savings).
CLKGATEPIX 0: PIX fractional divider clock is enabled.

HW_CLKCTRL_FRAC1 field descriptions (continued)

Field Description
PIX_STABLE stable quickly enough that this field will never need to be used by either device driver or application code.
5–0 This field controls the PIX clock fractional divider. The resulting frequency shall be 480 * (18/PIXFRAC)
PIXFRAC where PIXFRAC = 18-35.
10.8.26 Clock Frequency Sequence Control Register

(HW_CLKCTRL_CLKSEQ)
The CLKSEQ control register provides control for switching between XTAL and PLL clock
generation.
HW_CLKCTRL_CLKSEQ: 0x1D0
HW_CLKCTRL_CLKSEQ_SET: 0x1D4
HW_CLKCTRL_CLKSEQ_CLR: 0x1D8
HW_CLKCTRL_CLKSEQ_TOG: 0x1DC
This register controls the selection of clock sources (ref_xtal or ref_*) for various clock
dividers.
EXAMPLE
HW_CLKCTRL_CLKSEQ_WR(BF_CLKCTRL_CLKSEQ_BYPASS_SAIF0(1));
Address: HW_CLKCTRL_CLKSEQ – 8004_0000h base + 1D0h offset = 8004_01D0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD1
BYPASS_
R RSRVD0
[17:16]
CPU
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD1
DIS_LCDIF
BYPASS_
BYPASS_
BYPASS_
BYPASS_
BYPASS_
BYPASS_
BYPASS_
BYPASS_
BYPASS_
BYPASS_
R RSRVD2
[15:15]
SAIF1
SAIF0
SSP3
SSP2
SSP1
SSP0
GPMI
ETM
EMI
W
Reset 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
HW_CLKCTRL_CLKSEQ field descriptions

Field Description
RSRVD0
18 CPU bypsss select. 1 = Select ref_xtal path to generate the CPU clock domain. 0 = Select ref_cpu path to
BYPASS_CPU generate the CPU clock domain. PLL0 and 9-phase fractional divider must already be configured when
changing from bypass mode.

RSRVD1
14 LCDIF bypsss select. 1 = Select ref_xtal path to generate the LCDIF clock domain. 0 = Select ref_pix path
BYPASS_DIS_ to generate the LCDIF clock domain. PLL0 and 9-phase fractional divider must already be configured when
LCDIF changing from bypass mode.
0x1 BYPASS — select xtal source, bypass mode
0x0 PFD — select PFD, ref_pix
RSRVD2
8 ETM bypass select. 1 = Select ref_xtal path to generate the ETM clock domain. 0 = Select ref_cpu path to
BYPASS_ETM generate the ETM clock domain. PLL0 and 9-phase fractional divider must already be configured when this
bit is cleared.
7 EMI bypass select. 1 = Select ref_xtal path to generate the EMI clock domain. 0 = Select ref_emi path to
BYPASS_EMI generate the EMI clock domain. PLL0 and 9-phase fractional divider must already be configured when this
bit is cleared.
6 SSP3 bypass select. 1 = Select ref_xtal path to generate the SSP3 clock domain. 0 = Select ref_io1 path
BYPASS_SSP3 to generate the SSP3 clock domain. PLL0 and 9-phase fractional divider must already be configured when
this bit is cleared.
2 GPMI bypass select. 1 = Select ref_xtal path to generate the GPMI clock domain. 0 = Select ref_gpmi path
BYPASS_GPMI to generate the GPMI clock domain. PLL0 and 9-phase fractional divider must already be configured when

HW_CLKCTRL_CLKSEQ field descriptions (continued)

Field Description
1 Always set to zero (0) for functional operation. Bypass is only used for POR and SAIF1 divider configuration.
BYPASS_SAIF1
0 Always set to zero (0) for functional operation Bypass is only used for POR and SAIF0 divider configuration.
BYPASS_SAIF0
10.8.27 System Reset Control Register (HW_CLKCTRL_RESET)

The RESET control register provides control for software reset and enable/disable reset
control in analog.
EXAMPLE
HW_CLKCTRL_RESET_WR(BF_CLKCTRL_RESET_ALL(1));
Address: HW_CLKCTRL_RESET – 8004_0000h base + 1E0h offset = 8004_01E0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET_ENABLE
RESET_ENABLE
EXTERNAL_
RSRVD[15:6]
DISABLE
R
THERMAL_
THERMAL_
WDOG_
DEFAULT
RESET_
POR_
CHIP DIG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
HW_CLKCTRL_RESET field descriptions

Field Description
RSRVD
5 Analog Reset Control. Setting this bit to a logic one will disable the function that watchdog perform a POR.
WDOG_POR_ Then watchdog will function same with software reset HW_CLKCTRL_RESET.CHIP. Setting this bit to a
DISABLE logic zero, watchdog_reset will trigger a POR. This bit's reset value reflects OTP fuse
WDOG_PERFORM_POR.
4 Analog Reset Control. Setting this bit to a logic one will enable the external pin reset control logic.
EXTERNAL_
RESET_ENABLE

HW_CLKCTRL_RESET field descriptions (continued)

Field Description
3 Analog Reset Control. Setting this bit to a logic one will enable the thermal reset control logic.
THERMAL_
RESET_ENABLE
2 Reserved.
THERMAL_
RESET_
DEFAULT
1 Software reset. Setting this bit to a logic one will reset the ENTIRE chip, no exceptions. This bit will also be
CHIP reset after the full chip reset cycle completes.
0 Software reset. Setting this bit to a logic one will reset the digital sections of the chip. The DCDC and power
DIG module will not be reset. This bit will also be reset after the reset cycle completes.
10.8.28 ClkCtrl Status (HW_CLKCTRL_STATUS)

The STATUS control register provides read only status of the CPU frequecy limits.
EXAMPLE
HW_CLKCTRL_STATUS_RD(BF_CLKCTRL_STATUS_CPU_LIMIT());
Address: HW_CLKCTRL_STATUS – 8004_0000h base + 1F0h offset = 8004_01F0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CPU_LIMIT RSRVD[29:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD[15:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_CLKCTRL_STATUS field descriptions

Field Description
31–30 CPU Limiting. 00: full cpu frequency, 01: limit cpu frequency to 455 MHz, 10: limit cpu frequency to 411
CPU_LIMIT MHz, 11: limit cpu frequency to 360 MHz

RSRVD

10.8.29 ClkCtrl Version (HW_CLKCTRL_VERSION)

EXAMPLE
HW_CLKCTRL_VERSION_RD(BF_CLKCTRL_VERSION_MAJOR());
Address: HW_CLKCTRL_VERSION – 8004_0000h base + 200h offset = 8004_0200h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MAJOR MINOR STEP

W
Re- 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_CLKCTRL_VERSION field descriptions

Field Description
MAJOR
MINOR
STEP


Chapter 11
Power Supply
11.1 Overview
This chapter describes the power supply subsystem provided on the i.MX28. It includes
sections on the DC-DC converter, linear regulators, PSWITCH pin functions, battery monitor
and charger, silicon speed sensor, thermal-overload protection circuit, bandgap reference
and programmable registers.
The i.MX28 integrates a comprehensive power supply subsystem, including the following
features:
• One integrated DC-DC converter that supports Li-Ion batteries.
• Four linear regulators directly power the supply rails from 5 V.
• Linear battery charger for Li-Ion cells.
• Battery voltage and brownout detection monitoring for VDDD, VDDA, VDDIO,
VDDMEM, VDD4P2 and 5V supplies.
• Integrated current limiter from 5 V power source.
• Reset controller.
• System monitors for temperature and speed.
• Generates USB-Host 5V from Li-Ion battery (using PWM).
• Support for on-the-fly transitioning between 5V and battery power.
• VDD4P2, a nominal 4.2 V supply, is available when the i.MX28 is connected to a 5 V
source and allows the DCDC to run from a 5 V source with a depleted battery-integrated
current limiter from 5 V power source.
• The 4.2 V regulated output also allows for programmable current limits:
a. Battery Charge current + DCDC input current < the 5 V current limit.

Overview
b. DCDC input current (which ultimately provides current to the on-chip and off-chip
loads) as the priority and battery charge current will be automatically reduced if
the 5 V current limit is reached.
The i.MX28 power supply is designed to offer maximum flexibility and performance, while
minimizing external component requirements. Figure 11-1 shows a functional block diagram
of the power supply components including switching converters, five regulators, battery
charge support, as well as battery monitoring, supply brownout detection, and silicon
process/temperature sensors. This figure can be used to understand which register and status
bits relate to which subsystems, but it is not intended to be a complete architecture
description.
X VDD5V
Current VDDIO
Limiter HW_POWER_STS_VDDIO_BO
VDD4P2 VBG
HW_POWER_STS_VDD4P2_BO
Battery IOFB
Charge
X VDDIO
VBG
X VDD4P2
Battery VDDA
X
HW_POWER_STS_VDDA_BO
VBG
AFB
X VDDA
VDDMEM
DCDC
VDDD VBG
IOFB, AFB, DFB HW_POWER_STS_VDDD_BO
VDDMEM X
VBG
HW_POWER_CTRL_DC_OK_IRQ DFB
X VDDD
Notes:
Status Bits are in Italic
Figure 11-1. Power Supply Block Diagram

Chapter 11 Power Supply
11.2 DC-DC Converters

The DC-DC converters efficiently scale battery voltage (or a regulated 4.2 V derived from
a 5 V source) to the required supply voltages. The DC-DC converters include several
advanced features:
• Single inductor architecture
• Programmable output voltages
• Programmable brownout detection thresholds
• Pulse frequency modulation (PFM) mode for low-current load operation
11.2.1 DC-DC Operation

The i.MX28 DC-DC converter enables a low-power system and features programmable
output voltages and control modes. Most products adjust VDDD dynamically to provide
the minimum voltage required for proper system operation. VDDIO and VDDA are typically
set once during system initialization and not changed during operation.
11.2.1.1 Brownout/Error Detection

The power subsystem has several mechanisms active by default that safely return the device
to off state if any one of the following errors or brownouts occur:
• The crystal oscillator frequency is detected below a certain threshold—This threshold
is process-and voltage-sensitive, but will always be between 100 KHz and 2 MHz. This
feature can be disabled in DISABLE_XTALOK field in HW_RTC_PERSISTENT0
register.
• The battery voltage falls below the battery brownout level (field BRWNOUT_LVL in
HW_POWER_BATTMONITOR)—This feature is disabled by clearing
PWDN_BATTBRNOUT in the same register.
• 5 V is detected, then removed—This feature is disabled by clearing
HW_POWER_5VCTRL_PWDN_5VBRNOUT.
All three mechanisms are active by default to ensure that the device always has a valid
transition to a known state in case the power source is unexpectedly removed before the
software has completed the system configuration. Software will typically disable the
functionality of PWDN_5VBRNOUT and PWDN_BATTBRNOUT after system

DC-DC Converters
configuration is complete, as shown in Figure 11-2. System configuration generally includes

setting up brownout detection thresholds on the supply voltages, battery, and so on to obtain
the desired system operation as the battery or power source is depleted or removed.
Typically, each output target voltage is set to some voltage margin above the minimum
operating level through the TRG field in HW_POWER_VDDDCTRL,
HW_POWER_VDDACTRL, HW_POWER_VDDIOCTRL, and
HW_POWER_VDDMEMCTRL registers. The brownout detection threshold is also set
through the BO_OFFSET field in same three registers. The BO_OFFSET field determines
how far the brownout voltage is below the output target voltage for each supply and might
typically be set 75–100 mV below the target voltage. If the voltage drops to the brownout
detector's level, then it optionally triggers a CPU Fast Interrupt (FIQ). The CPU can then
alleviate the problem and/or shut down the system elegantly. See i.MX28 Datasheet for
suggested voltage settings for the supply and brownout targets for different operating
frequencies.
To eliminate false detection, the brownout circuit filters transient noise above 1 MHz. Any
system with an i.MX28 should include at least 33 μF of decoupling capacitance on VDDIO,
VDDA and VDDD power rails. The capacitors should be arranged to filter supply noise in
1 MHz and higher frequencies.

Base State Defaults:

HW_POWER_5VCTRL_PWDN_5VBRNOUT=1
HW_POWER_BATTMONITOR_PWDN_BATTBRNOUT=1
Brownout =
Unplug =
Unplug=1 Brownout=1 (HW_POWER_STS_VDD5V_GT_VDDIO=0) &
(On falling edge of
(HW_POWER_BATTMONITOR_PWDN
HW_POWER_STS_VDD5V_GT_VDDIO) &
_BATTBRNOUT=1) &
(HW_POWER_5VCTRL_PWDN_5VBRNOUT=1)
(HW_POWER_STS_BATT_BO=1)
Off
(PSWITCH or RTC wakeup or HW_POWER_STS_VDD5V_GT_VDDIO=1)
ROM
Bist
Enable LRADC to measure battery

and put value into
HW_POWER_BATTMONITOR_BATT_VAL. HW_POWER_STS_VDD5V_GT_VDDIO=1
Set up battery brownout code.
HW_POWER_BATTMONITOR_EN
HW_POWER_STS_VDD5V_GT_VDDIO=0 _BATADJ=1
5V Device Plugin
HW_POWER_STS_
VDD5V_GT_VDDIO=1 (interrupt-driven event)
(any instance)
Do you want to
Reset reset or continue
on a future
plugin?
Do you want to
reset or continue Reset
Continue on a future
unplug?
Set up IRQ for VDDIO5V plug in.

HW_POWER_CTRL_POLARITY HW_POWER_5VCTRL Continue
_VDD5V_GT_VDDIO=1 _ENABLE_DCDC=1
HW_POWER_CTRL_ENIRQ HW_POWER_5VCTRL
_VDD5V_GT_VDDIO=1 _PWDN_5VBRNOUT=0
Configure* 5V unplug detection.
HW_POWER_5VCTRL_PWDN HW_POWER_5VCTRL_DCDC_XFER=1
_5VBRNOUT=1 HW_POWER_5VCTRL_PWDN_5VBRNOUT=0
HW_POWER_BATTMONITOR_PWDN
_BATTBRNOUT=1
HW_POWER_CTRL_ENIRQBATT_BO=1
HW_POWER_BATTMONITOR_PWDN
_BATTBRNOUT=0
HW_POWER_5VCTRL
_PWDN_5VBRNOUT=1
Application
Figure 11-2. Brownout Detection Flowchart
11.2.1.2 DC-DC Extended Battery Life Features

The DC-DC converter has several other power-reducing programmable modes that are
useful for maximizing battery life:
• Li-Ion Buck/Boost—The Li-Ion battery configuration supports buck/boost operation,
which means that a VDDIO voltage can be supported which is higher than the input
Li-Ion battery voltage. This is important to maximize the battery life in all applications,
but is crucial in hard drives that have large transient current requirements.

Linear Regulators
• Transient Loading Optimizations—Several new incremental improvements have

been made to the control architecture of the switching converters. At this time, Freescale
recommends setting the following bits through software in HW_POWER_LOOPCTRL
to obtain maximum efficiency and minimum supply ripple: TOGGLE_DIF,
EN_CM_HYST and EN_RCSCALE=0x1. Also, set
HW_POWER_BATTMONITOR_EN_BATADJ. The complete settings to optimize
transient loading will be dependent on the application, component selection and board
layout.
• Pulse Frequency Modulation (PFM)—PFM, also known as pulse-skipping mode, is
used to reduce power consumed by the DC-DC converter when the voltage outputs are
lightly-loaded at a cost of higher transient noise. The DC-DC converter can be separately
placed in PFM mode through the EN_DC_PFM bit in HW_POWER_MINPWR.
• DC-DC Switching Frequency—The standard DC-DC switching frequency is 1.5 MHz,
which provides a good mix of efficiency and power output. The frequency can be
reduced to 750 KHz to reduce operating current in some light load situations through
DC_HALFCLK in HW_POWER_MINPWR. The DC-DC converter can also be
programmed to a frequency that is based on PLL using the SEL_PLLCLK and
FREQSEL fields in the HW_POWER_MISC register.
• DC-DC Converter Power Down—If the system is to operate from linear regulators
or an external power supply, then the internal DC-DC converters can be powered down
through DC_STOPCLK in HW_POWER_MINPWR. This bit is not intended to power
down the whole system. Use the HW_POWER_RESET bits to power the system off.
The DC-DC converter can be programmed to run off of the battery or the 4.2 V regulated
voltage supply. It can be set up to opportunistically draw power from either source. This
allows the system to draw up to the USB current limit from the 5 V supply and take the
balance of the required power from the battery.
11.3 Linear Regulators

The i.MX28 integrates four linear regulators that can be used to directly power the supply
rails when 5 V is present. All of these regulators have an output impedance of approximately
one-quarter ohm. This means that the measured output voltage will be slightly dependent
on the current consumed on each supply. Architecturally, one regulator generates VDDIO
from the VDD5V pin, one generates VDDA from VDDIO, one generates VDDMEM from
VDDA, and the other generates VDDD from the VDDA supply. Therefore, all of the current
is supplied by the VDD5V->VDDIO regulator.

In addition, the i.MX28 integrates a 4.2 V regulator which enables the DC-DC converter
to run off the power supplied by 5 V. This allows the DC-DC converter operation when 5
V is present and the battery is exhausted. In addition, the path can provide better power
consumption as compared to the other linear regulator generated supplies. A current limiter
is implemented in a series with the 4.2 V regulator and the battery supply. The intent is to
limit the Ibattery plus I4P2 to be less than Ilimit. The 4.2 V regulator has priority on the
current and will dynamically reduce the battery charge current in order to preserve the Ilimit
and the regulated 4.2 V.
It should also be noted that the VDD5V voltage can dynamically change as the product is
plugged into a USB port or other 5-V supply. The i.MX28 is programmable to provide a
variety of behaviors when the VDD5V supply becomes valid or invalid, as well as to support
operation through USB or external power.
11.3.1 USB Compliance Features

Upon connection of 5 V to the powered-down device, the linear regulators will automatically
power up the device. To meet USB inrush specifications, linear regulators have a current
limit which is <100 mA, nominally 50 mA, and is active by default. This current limit is
disabled in hardware after power-up, but can be re-enabled through the
HW_POWER_5VCTRL_ENABLE_ILIMIT by software. System designers must understand
that the current inrush limit during 5 V power-up places restrictions on application current
consumption until it is disabled. Specifically, after connection to 5V, if the system draws
more current than the current limit allows, the startup sequence does not complete and the
ROM code does not execute.
Further, USB Host implies that B-devices must draw very little current from 5 V. This
requirement can be met by setting HW_POWER_5VCTRL_ILIMIT_EQ_ZERO when the
Host application is active. The comparators required for Host capability can be enabled by
HW_POWER_5VCTRL_PWRUP_VBUS_CMPS. It is also possible to change the threshold
of the Vbus valid comparator using HW_POWER_5VCTRL_VBUSVALID_TRSH.
If very low power operation is required, as in USB suspend, then the circuits required to
elegantly switch to the DC-DC converter may have to be powered off. In those cases, the
system must fully power down after VDD5V becomes invalid. It can auto restart with the
DC-DC converter, if HW_RTC_PERSISTENT0_AUTO_RESTART is set.

Linear Regulators
11.3.2 5V to Battery Power Interaction

The i.MX28 supports several different options related to the interaction of the switching
converters with the linear regulators. The two primary options are a reset on 5V
insertion/removal or a handoff to the DC-DC converters that is invisible to the end-user of
the application. Figure 11-3 includes these two options as the two system architecture
decision boxes.
11.3.2.1 Battery Power to 5-V Power

By default, the DC-DC converter turns off when VDD5V becomes valid and the system
does not reset. If the system is operating from the DC-DC converter and is using more
current than the linear regulators can supply, then the VDDD, VDDA, and VDDIO rails
will droop when 5V is attached and the system may brownout and shut down. To avoid this
issue, set the ENABLE_DCDC bit and set the LINREG_OFFSET fields to 0b2 in anticipation
of VDD5V becoming present. The ENABLE_DCDC bit will cause the DC-DC converter
to remain on even after 5V is connected and, thus, guarantee a stable supply voltage until
the system is configured for removal of 5V. The LINREG_OFFSET fields = 0b2 cause the
linear regulators to regulate to a lower target voltage than the switching converter and
prevent unwanted interaction between the two power supplies. After the system is configured
for removal of 5V, ENABLE_DCDC can be set low and ENABLE_ILIMIT set low in
register HW_POWER_5VCTRL to allow the linear regulators to supply the system power,
if desired.
11.3.2.2 5-V Power to Battery Power

Configuring the system for a 5-V-to-battery power handoff requires setup code to monitor
the battery voltage as well as detect the removal of 5V.
Monitoring the battery voltage is performed by LRADC. Typically, this involves
programming the LRADC registers to periodically monitor the battery voltage as described
in LRADC Overview. The measured battery voltage should be written into the
HW_POWER_BATTMONITOR register field BATT_VAL using the AUTOMATIC field
in the HW_LRADC_CONVERSION register. Also, configuring battery brownout should
be performed so that the system behaves as desired when 5V is no longer present and the
battery is low.
The recommended method to detect removal of 5V requires setting
VBUSVALID_5VDETECT and programming the detection threshold VBUSVALID_TRSH
to 0x1 in HW_POWER_5VCTRL. Next, in order to minimize linear regulator and DC-DC
converter interaction, it is necessary to set the LINREG_OFFSET = 0b2 in the

HW_POWER_VDDIOCTRL, HW_POWER_VDDACTRL, and

HW_POWER_VDDDCTRL registers. Finally, set DCDC_XFER and clear
PWDN_5VBRNOUT in the HW_POWER_5VCTRL register. This sequence is important
because it is safe to disable the powerdown-on-unplug functionality of the device only after
the system is completely ready for a transition to battery power.
11.3.2.3 5-V Power and Battery Power

Battery charge can also be enabled to provide additional power efficiency when connected
to 5V. If the DC-DC switching converter is also enabled, the buck switching converters
will efficiently convert the battery voltage to the desired VDDA, VDDD, and VDDIO
voltages (instead of using the less efficient internal linear regulators).
11.3.3 Power-Up Sequence

The DC-DC converter controls the power-up and reset of the i.MX28. The power-up sequence
begins when the battery is connected to the BATT pin of the device (or a 5V source is
connected to the VDD5V pin). Either the BATT pin or VDD5V provides power to the
DC-DC startup circuitry, the crystal oscillator, and the real-time clock. This means that the
crystal oscillator can be running, if desired, whenever a battery is connected to BATT pin.
This feature allows the real-time clock to operate when the chip is in the off state. The
crystal oscillator/RTC is the only power drain on the battery in this state and consumes only
a very small amount of power. During this time, the VDDIO, VDDD and VDDA supplies
are held at ground. This is the off state that continues until the system power up begins.
Power-up can be started with one of several events:
• PSWITCH pin >= minimum MID level PSWITCH for 100 ms
• VDD5V power pin > 4.25 V for 100 ms
• Real-time clock alarm wakeup
When a power-up event has occurred, if VDD5V is valid, then the on-chip linear regulators
charge the VDDD, VDDA and VDDIO rails to their default voltages. If VDD5V is not
valid, then the DC-DC supplies the VDDD, VDDA, and VDDIO rails. When the voltage
rails have reached their target values, the digital logic reset is deasserted and the CPU begins
executing code. If the power supplies do not reach the target values by the time PSWITCH
is deasserted or 5V is removed, the system returns to the off state.

Linear Regulators
The power-up time is dependent on the VDDD/VDDA/VDDIO load and battery or VDD5V
voltage, but should be less than 100 ms. The VDDD//VDDAVDDIO load should be minimal
during power up to ensure proper startup of the DC-DC converter.
There is an integrated 5-KΩ resistor that can be switched in between the VDDXTAL pin
and PSWITCH. If enabled using HW_RTC_PERSISTENT0_AUTO_RESTART, then the
device immediately begins the power-up sequence after power-down.
11.3.4 Power-Down Sequence

Power-down is also controlled by the DC-DC converters. When the DC-DC converter
detects a power-down event, it returns the device to the off state described above. The
power-down sequence is started when one of these events occur:
• HW_POWER_RESET_PWD bit set while the register is unlocked.
• Error condition occurs, as described in Brownout/Error Detection.
• The watchdog timer expires while enabled.
• Fast falling edge (<10 ns) on PSWITCH pin.
The HW_POWER_RESET_PWD_OFF bit disables all the power-down paths except for
the watchdog timer when it is set.
The lower 16 bits of the HW_POWER_RESET register can only be written, if the value
0x3E77 is placed in the unlock field.
An external capacitor on the PSWITCH can be used to prevent an unwanted power down
due to falling edges. This can also be disabled in HW_POWER_RESET_PWD_OFF register.
11.3.4.1 Powered-Down State

While the chip is powered down, the VDDIO, VDDD and VDDA rail are pulled down to
ground. The VDDIO rail is shorted to ground. The crystal oscillator and the RTC can
continue to operate by drawing power from the BATT pin. See RTC Overview for more
information about operating a crystal and the RTC in the powered-down state.
11.3.5 Reset Sequence

Figure 11-3 shows a flowchart for the power-up, power-down and reset sequences. A reset
event can be triggered by unlocking the HW_POWER_RESET register and setting the
HW_CLKCTRL_RESET_DIG bit. This reset affects the digital logic only, although the

digital logic also includes most of the registers that control the analog portions of the chip.
The persistent bits within the RTC block and the power module control bits are not reset
using this method. To reset the analog as well as the digital logic, set the
HW_CLKCTRL_RESET_CHIP bit. The DC-DC converter and/or linear regulators continue
to maintain the power supply rails during the reset.
11.4 PSWITCH Pin Functions

The PSWITCH pin has several functions whose operation is determined by the i.MX28-based
product's hardware and software design.
11.4.1 Power On
When the PSWITCH pin voltage is higher than approximately the minimum MID level (as
specified in Table 11-1) for >100 ms, the DC-DC converter begins its startup routine. This
is the primary method of starting the system through PSWITCH. All products based on the
i.MX28 must have a mechanism of bringing PSWITCH high to power up through an
always-present supply (for example, battery or VDDXTAL).
Table 11-1. PSWITCH Input Characteristics
Parameter HW_PWR_STS_PSWITCH Min Max Units
1
PSWITCH LOW LEVEL 0x00 0.00 0.30 V
12
PSWITCH MID LEVEL & STARTUP 0x01 0.65 1.50 V
13
PSWITCH HIGH LEVEL 0x11 (1.1* VDDX- 2.45 V
TAL)+ 0.58
1. Consult the reference schematics for recommended PSWITCH button circuitry.
2. A MID LEVEL PSWITCH state can be generated by connecting the VDDXTAL output of the SOC to PSWITCH through a
switch.
3. PSWITCH acts like a high impedance input (>300 kΩ) when the voltage applied to it is less than 1.5 V. However, above 1.5
V it becomes lower impedance. To simplify design, it is recommended that a 10 kΩ resistor to VDDIO be applied to PSWITCH
to set the HIGH LEVEL state (the PSWITCH input can tolerate voltages greater than 2.45 V as long as there is a 10 kΩ resistor
in series to limit the current).
11.4.2 Power Down

If the PSWITCH pin voltage has a falling edge faster than 15 ns, then this sends a
power-down request to the DC-DC converter. The fast-falling-edge power-down may be
blocked by the HW_POWER_RESET_PWD_OFF function. The fast-falling edge can also
be prevented by placing a RC filter on the PSWITCH pin. Most i.MX28-based systems do
not use the PSWITCH fast-falling-edge power-down and include the RC filter to prevent
it from occurring accidentally.

PSWITCH Pin Functions
11.4.3 Software Functions/Recovery Mode

When the PSWITCH pin voltage is pulled up to the minimum MID level (as specified in
Table 11-1) the lower HW_POWER_STS_PSWITCH bit is set. Software can poll this bit
and perform a function as desired by the product designer. Example functions include a
play/pause/power-down button, delay for startup, and so on.
When the PSWITCH pin is connected to VDDIO through a current limiting resistor, the
upper HW_POWER_STS_PSWITCH bit is also set. If this bit is set for more than five
seconds during ROM boot, the system executes the Freescale USB Firmware Recovery
function, as described in Boot Modes. If the product designer does not wish to use Freescale
USB Firmware Recovery, the product can be designed to not assert a voltage higher than
the maximum MID level (as specified in Table 11-1) on the PSWITCH pin.
Refer to the Freescale i.MX28 reference schematics for example configurations of the
PSWITCH pin.

Software-Controlled Resets Normal Power-Up Flow
No Power
No Battery, no 5V.
Battery Insert or
5V_Detect=1
Power-On Reset
(Clock and Persistent Bits Reset)
To Power Down:
Set HW_POWER_RESET_PWD
State Zero
(Persistent bits retain state, XTAL
and clock active if enabled)
For Cold Reboot: PSWITCH=1 or

RTC Alarm or
HW_RTC_PERSISTENT0_AUTO_RESTART AUTO_RESTART=1 or
then HW_POWER_RESET_PWD 5V_DETECT=1
Power Up
(Start XTAL if it’s off ,
Start 5V Linear Regs if 5V
Detect, else start DCDC
converter)
Power is Stable
Start Digital Clocks

(Digital Reset Asserted.
Digital clocks all = 1 MHz)
To Reset DCDC and Digital:
Set HW_CLKCTRL_RESET_CHIP
Reset DCDC PIO Registers

(All non-persistent flop resets
asserted, Note that the DCDC
continues to operate even if the
PIO registers are reset. Digital
clocks all = 1 MHz)
To Reset Digital but not DCDC
(warm boot):
Set HW_CLKCTRL_RESET_DIG
Reset Non-DCDC Digital

Registers
(Non persistent and non-POWER
flop resets asserted. Digital
clocks all = 1 MHz)
Wait 16 cycles for all

resets to propogate
Release Reset
(Digital clock domains at default
frequency and gating, boot CPU )
Figure 11-3. Power-Up, Power-Down, and Reset Flow Chart
11.5 Battery Monitor

The power control system includes a battery monitor. The battery monitor has two functions:
battery brownout detection and battery voltage feedback to the DC-DC converter.
If the battery voltage drops below the programmable brownout, then a fast interrupt (FIQ)
can be generated for the CPU. Software typically uses the LRADC to monitor the battery
voltage and shut down elegantly while there is a minimal operating margin. But, if an
unexpected event (such as a battery removal) occurs, then the system needs to be placed
immediately in the off state to ensure that it can restart properly. The brownout is controlled
in the HW_POWER_BATTMONITOR register. The IRQ must also be enabled in the
interrupt collector.

Battery Charger
To enable optimum performance over the battery range, the DC-DC converter needs to be
provided with the battery voltage, which is measured by the battery pin LRADC. Normally,
LRADC channel 7 is dedicated to periodically measuring the battery voltage with a period
in the millisecond range for most applications. The voltage is automatically placed into the
BATT_VAL field of the HW_POWER_BATTMONITOR register through the
HW_LRADC_CONVERSION register. If necessary, software can turn off the automatic
battery voltage update and set the BATT_VAL field manually.
11.6 Battery Charger

The battery charger is essentially a linear regulator that has current and voltage limits.
Charge current is software-programmable within the HW_POWER_CHARGE register.
Li-Ion batteries can be charged at the lower of 1C, 785 mA, or the VDD5V current limit.
USB charging is typically limited to 500 mA or less to meet compliance requirements. Also,
battery charge current will be automatically reduced if the current demands from VDD4P2
and the battery charger exceed the CHARGE_4P2_ILIMIT. Full battery charge current will
be restored once the VDD4P2 + battery charge current falls below the
CHARGE_4P2_ILIMIT value.
Typical charge times for a Li-Ion battery are 1.5 to 3 hours with >70% of the charge delivered
in the first hour.
The battery charge voltage limit is 4.2 V for the Li-Ion batteries.
The Li-Ion charge is typically stopped after a certain time limit OR when the charging
current drops below 10% of the charge current setting. The HW_POWER_CHARGE register
includes controls for the maximum charge current and for the stop charge current. While
the charger is delivering current greater than the stop charge limit, the
HW_POWER_STS_CHRGSTS bit will be high. This bit should be polled (a low rate of 1
second or greater is fine) during charge. When the bit goes low, the charging is complete.
It would be good practice to check that this bit is low for two consecutive checks, as the
DC-DC switching might cause a spurious low result. Once this bit goes low, the charger
can either be stopped immediately or stopped after a top-off time limit. Although the charger
will avoid exceeding the charge voltage limit on the battery, it is NOT recommended to
leave the charger active indefinitely. It should be turned off when the charge is complete.
One can programatically monitor the battery voltage using the LRADC. The charger has
its own (very robust) voltage limiting that operates independently of the LRADC. But
monitoring the battery voltage during the charge might be helpful for reporting the charge
progress.

The battery charger is capable of generating a large amount of heat within the i.MX28,
especially at currents above 400 mA. The dissipated power can be estimated as: (5V –
battery_volt) * current. At max current (785 mA) and a 3-V battery, the charger can dissipate
1.57 W, raising the die temp as much as 80 C°. To ensure that the system operates correctly,
the die temperature sensor should be monitored every 100 ms. If the die temperature exceeds
115 C° (the max value for the chip temp sensor), then the battery charge current must be
reduced. The LRADC can also be used to monitor the battery temperature or chip
temperature. There is an integrated current source for the external temperature sensor that
can be configured and enabled through HW_LRADC_CTRL2 register.
11.7 11.5.1 Battery Detection

The battery is detected by checking the battery brownout status or measuring the battery
pin voltage. If either indicates the battery voltage is below an application-defined low-voltage
threshold, the battery is not attached. When the battery voltage is measured in the expected
operational range, the FASTSETTLING bitfield in the HW_POWER_REFCTRL register
should be set to enable an internal load on the battery. If no battery is connected, the internal
load will discharge the capacitor on the battery pin to bring the voltage below the
application-defined low-voltage threshold. If a battery is connected, the voltage should
remain in the expected operational range. After battery detection is complete, the
FASTSETTLING bitfield should be cleared to disable the internal load.
The internal load is automatically disabled when a battery brownout is detected. In this
case, the FASTSETTLING bitfield must be cycled to re-enabled the load. This is important
for situations where the load is enabled at a battery voltage just above the battery brownout
threshold and then the battery voltage drops below the threshold causing the brownout status
to change. Software must account for this situation by re-enabling the load when the battery
voltage is below the brownout threshold. The length of time for the battery capacitor to
discharge is variable between designs and is dependent on the amount of capacitance on
the board.
11.8 Silicon Speed Sensor

The i.MX28 integrates three silicon speed sensors to measure the performance characteristics
of an individual die at its ambient temperature and process parametrics. One is inside ARM9
to measure ARM9 performance, one is in core logic which including system bus and
peripherals to measure core logic performance and another one is inside DC-DC block. A
silicon speed sensor consists of a ring oscillator and a frequency counter. The ring oscillator
runs on the VDDD power rail. Therefore, its frequency tracks the silicon performance as it
changes in response to changes in operating voltage and temperature. The crystal oscillator

Thermal-Overload Protection Circuit
is directly used as the precision time base for measuring the frequency of a ring oscillator.
The ring oscillator is normally disabled. There is a 8-bit/16-bit counter connected to the
ring oscillator that performs the frequency measurement. See HW_POWER_SPEED register.
Thus, the counter holds the number of cycles the ring oscillator was able to generate during
one crystal clock period. The natural frequency of the ring oscillator strongly tracks the
silicon process parametrics, that is, faster silicon processes yield ring oscillators that run
faster and thereby yield larger count values. The natural frequency tracks junction temperature
effects on silicon speed as well.
The information given by the speed sensors can be used with the silicon temperature and
process parameters, which can also be monitored by system software. Freescale can provide
a power management application note and firmware that takes full advantage of the on-chip
monitoring functions to enable minimum-voltage operation.
11.9 Thermal-Overload Protection Circuit

The i.MX28 integrates a thermal-overload protection circuit to shut down the device when
the on-die temperature exceeds a programmed target value. It consists of a bipolar based
voltage generator whose characteristics track the on-die temperature. This
temperature-dependent voltage is compared to a fixed voltage level that does not vary with
the temperature to trigger a shut down of the device. The thermal-overload protection circuit
is disabled by default, but can be enabled after the system is up. Its default thermal trip-point
is set to 115degC and can be programmed up to 150degC in 5degC steps. See
HW_POWER_THERMAL register.
11.10 Bandgap Reference Generator

The i.MX28 integrates a bandgap generator which creates supply and temperature stable
voltage and current references for the on-chip blocks. Several bits are provided to adjust
the reference voltages and currents. See HW_POWER_REFCTRL register.
11.11 Interrupts
The power system supports nine CPU interrupt events that are programmable within the
HW_POWER_CTRL register. The interrupts are listed in Table 11-2.
Table 11-2. Power System Interrupts
HW_POWER_CTRL INTERRUPT BIT Description
VDDA_BO_IRQ VDDA Brownout

HW_POWER_CTRL INTERRUPT BIT Description
VDDD_BO_IRQ VDDD Brownout
VDDIO_BO_IRQ VDDIO Brownout
BATT_BO_IRQ Battery Brownout
VDD5V_GT_VDDIO_IRQ VDD5V > (VDDIO + 0.6)
DC_OK_IRQ Voltage Supplies Ok after target voltage change
VBUSVALID_IRQ VDD5V > Vbusvalid Threshold
LINREG_OK_IRQ Debug use only
PSWITCH_IRQ PSWITCH Status
The VDDA_BO_IRQ, VDDD_BO_IRQ, VDDIO_BO_IRQ, and BATT_BO_IRQ each

have their own interrupt line back to the interrupt collector. However, the remaining five
interrupts—VDD5V_GT_VDDIO_IRQ, DC_OK_IRQ, VBUSVALID_IRQ,
LINREG_OK_IRQ and PSWITCH_IRQ—all share a single interrupt line. In this case,
software must read the interrupt status bits to discover which event caused the interrupt.

iMX28 POWER Hardware Register Format Summary
HW_POWER memory map
Absolute
Width Section/
(in bits) page
(hex)
8004_4000 Power Control Register (HW_POWER_CTRL) 32 R/W 0001_0024h 11.12.1/912
8004_4010 DC-DC 5V Control Register (HW_POWER_5VCTRL) 32 R/W 2010_0490h 11.12.2/915
8004_4020 DC-DC Minimum Power and Miscellaneous Control Register 32 R/W 0000_0000h 11.12.3/917
(HW_POWER_MINPWR)
8004_4030 Battery Charge Control Register (HW_POWER_CHARGE) 32 R/W 0001_0000h 11.12.4/919
8004_4040 VDDD Supply Targets and Brownouts Control Register 32 R/W 0032_0710h 11.12.5/921
(HW_POWER_VDDDCTRL)
8004_4050 VDDA Supply Targets and Brownouts Control Register 32 R/W 0000_270Ch 11.12.6/923
(HW_POWER_VDDACTRL)
8004_4060 VDDIO Supply Targets and Brownouts Control Register 32 R/W 0000_2406h 11.12.7/924
(HW_POWER_VDDIOCTRL)
8004_4070 VDDMEM Supply Targets Control Register 32 R/W 0000_0230h 11.12.8/926
(HW_POWER_VDDMEMCTRL)

HW_POWER memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
8004_4080 DC-DC Converter 4.2V Control Register 32 R/W 0000_0018h 11.12.9/927
(HW_POWER_DCDC4P2)
8004_4090 DC-DC Miscellaneous Register (HW_POWER_MISC) 32 R/W 0000_0000h 11.12.10/929
8004_40A0 DC-DC Duty Cycle Limits Control Register 32 R/W 0000_0C5Fh 11.12.11/930
(HW_POWER_DCLIMITS)
8004_40B0 Converter Loop Behavior Control Register 32 R/W 0000_0021h 11.12.12/931
(HW_POWER_LOOPCTRL)
8004_40C0 Power Subsystem Status Register (HW_POWER_STS) 32 R 0000_0200h 11.12.13/933
8004_40D0 Transistor Speed Control and Status Register 32 R/W 0000_0000h 11.12.14/936
(HW_POWER_SPEED)
8004_40E0 Battery Level Monitor Register 32 R/W 0000_0A00h 11.12.15/937
(HW_POWER_BATTMONITOR)
8004_4100 Power Module Reset Register (HW_POWER_RESET) 32 R/W 0000_0000h 11.12.16/938
8004_4110 Power Module Debug Register (HW_POWER_DEBUG) 32 R/W 0000_0000h 11.12.17/939
8004_4120 Power Module Thermal Reset Register 32 R/W 0000_0080h 11.12.18/940
(HW_POWER_THERMAL)
8004_4130 Power Module USB1 Manual Controls Register 32 R/W 0000_000Eh 11.12.19/941
(HW_POWER_USB1CTRL)
8004_4140 Power Module Special Register (HW_POWER_SPECIAL) 32 R/W 0000_0000h 11.12.20/942
8004_4150 Power Module Version Register (HW_POWER_VERSION) 32 R 0400_0000h 11.12.21/943
8004_4160 Analog Clock Control Register (HW_POWER_ANACLKCTRL) 32 R/W 8400_0400h 11.12.22/943
8004_4170 POWER Reference Control Register 32 R/W 0000_0000h 11.12.23/945
(HW_POWER_REFCTRL)
11.12.1 Power Control Register (HW_POWER_CTRL)

The Power Control Register contains control bits specific to the digital section.
HW_POWER_CTRL: 0x000
HW_POWER_CTRL_SET: 0x004
HW_POWER_CTRL_CLR: 0x008
HW_POWER_CTRL_TOG: 0x00C

Address: HW_POWER_CTRL – 8004_4000h base + 0h offset = 8004_4000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENIRQ_PSWITCH
VDD5V_DROOP_
ENIRQ_DCDC4P2_BO
POLARITY_PSWITCH
ENIRQ_VDD5V_
DCDC4P2_BO_IRQ
POLARITY_DC_OK
PSWITCH_MID_
PSWITCH_IRQ_
PSWITCH_IRQ
R RSRVD2 RSRVD1
DROOP
TRAN
SRC
IRQ
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VBUSVALID_IRQ
ENIRQ_VDD5V_
VDDIO_BO_IRQ
ENIRQ_VDDIO_
ENIRQ_DC_OK
VDDD_BO_IRQ
ENIRQ_VDDD_
VDDA_BO_IRQ
ENIRQ_VDDA_
ENIRQ_VBUS_
BATT_BO_IRQ
ENIRQBATT_BO
VDD5V_GT_
VDD5V_GT_
VBUSVALID
POLARITY_
POLARITY_
VDDIO_IRQ
R
GT_VDDIO
DC_
VDDIO
VALID
BO
BO
BO
OK_
IRQ
W
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0
HW_POWER_CTRL field descriptions

Field Description
31–28 Reserved.
RSRVD2
27 When this bit is set, it selects the from-mid-transition interrupt functionality for PSWITCH. When set, in
PSWITCH_MID_ conjuction with ENIRQ_PSWITCH, it will set PSWITCH_IRQ when either a 01 to 11 or 01 to 00 transition
TRAN is detected on the PSWITCH comparators. When this bit is set, PSWITCH_IRQ_SRC and
POLARITY_PSWITCH have no effect.
26–25 Reserved.
RSRVD1
24 Interrupt Status for 4P2_BO. Reset this bit by writing a one to the SCT clear address space and not by a
DCDC4P2_BO_ general write.
IRQ
23 Enable interrupt for 4P2_BO.
ENIRQ_
DCDC4P2_BO
22 Interrupt Status for VDD5V_DROOP. Reset this bit by writing a one to the SCT clear address space and
VDD5V_ not by a general write.
DROOP_IRQ
21 Enable interrupt for VDD5V_DROOP.
ENIRQ_VDD5V_
DROOP
20 Interrupt status for PSWITCH signals. Interrupt polarity is set using POLARITY_PSWITCH. Comparator bit
PSWITCH_IRQ is selected through PSWITCH_IRQ_SRC. Reset this bit by writing a one to the SCT clear address space
and not by a general write.
19 Set to 1 to use HW_POWER_STS_PSWITCH bit 1 as source, 0 for HW_POWER_STS_PSWITCH bit 0

PSWITCH_IRQ_
SRC

HW_POWER_CTRL field descriptions (continued)

Field Description
18 Set to 1 to interupt when the interrupt source is high, 0 for low
POLARITY_
PSWITCH
17 Interrupt status for PSWITCH signal. Interrupt polarity is set using POLARITY_PWITCH and source selected
ENIRQ_ by PSWITCH_SRC.
PSWITCH
16 Debug use only. Set to 1 to check for linear regulators ok. Set to 0 to check for 5V disconnected.
POLARITY_DC_
OK
15 Interrupt Status for DC_OK. Reset this bit by writing a one to the SCT clear address space and not by a
DC_OK_IRQ general write.
14 Enable interrupt for DC_OK.

ENIRQ_DC_OK
13 Interrupt Status for BATT_BO. Reset this bit by writing a one to the SCT clear address space and not by a
BATT_BO_IRQ general write.
12 Enable interrupt for battery brownout.

ENIRQBATT_BO
11 Interrupt Status for VDDIO_BO. Reset this bit by writing a one to the SCT clear address space and not by
VDDIO_BO_IRQ a general write.
10 Enable interrupt for VDDIO brownout.

ENIRQ_VDDIO_
BO
9 Interrupt Status for VDDA_BO. Reset this bit by writing a one to the SCT clear address space and not by a
VDDA_BO_IRQ general write.
8 Enable interrupt for VDDIO brownout.

ENIRQ_VDDA_
BO
7 Interrupt Status for VDDD_BO. Reset this bit by writing a one to the SCT clear address space and not by a
VDDD_BO_IRQ general write.
6 Enable interrupt for VDDD brownout.

ENIRQ_VDDD_
BO
5 Set to 1 to check for 5V connected using VBUSVALID status bit. Set to 0 to check for 5V disconnected.
POLARITY_
VBUSVALID
4 Interrupt status for VBUSVALID signal. Interrupt polarity is set using POLARITY_VBUSVALID. Reset this
VBUSVALID_IRQ bit by writing a one to the SCT clear address space and not by a general write.
3 Enable interrupt for 5V detect using VBUSVALID.

ENIRQ_VBUS_
VALID

HW_POWER_CTRL field descriptions (continued)

Field Description
2 Set to 1 to check for 5V connected. Set to 0 to check for 5V disconnected.
POLARITY_
VDD5V_GT_
VDDIO
1 Interrupt status for VDD5V_GT_VDDIO signal. Interrupt polarity is set using POLARITY_VDD5V_GT_VDDIO.
VDD5V_GT_ Reset this bit by writing a one to the SCT clear address space and not by a general write.
VDDIO_IRQ
0 Enable interrupt for 5V detect.
ENIRQ_VDD5V_
GT_VDDIO
11.12.2 DC-DC 5V Control Register (HW_POWER_5VCTRL)

This register contains the configuration options of the power management subsystem that
are available when external 5V is applied.
HW_POWER_5VCTRL: 0x010
HW_POWER_5VCTRL_SET: 0x014
HW_POWER_5VCTRL_CLR: 0x018
HW_POWER_5VCTRL_TOG: 0x01C
Address: HW_POWER_5VCTRL – 8004_4000h base + 10h offset = 8004_4010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VBUSDROOP_TRSH
RSRVD5
R RSRVD6 RSRVD4 RSRVD3

PWD_ CHARGE_
HEADROOM_ADJ CHARGE_ 4P2_ILIMIT
4P2 [17:16]
W
Reset 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWRUP_VBUS_CMPS
PWDN_5VBRNOUT
ENABLE_LINREG_
VBUSVALID_TO_B
RSRVD2
ILIMIT_EQ_ZERO
ENABLE_DCDC
DCDC_XFER
VBUSVALID_
R
5VDETECT
ILIMIT
CHARGE_4P2_ILIMIT[15:12] VBUSVALID_TRSH
Reset 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0

HW_POWER_5VCTRL field descriptions

Field Description
31–30 Reserved.
RSRVD6
29–28 Set the threshold for the VBUSDROOP comparator. This comparator should typically be programmed at
VBUSDROOP_ least 200mV above VBUSVALID, and can be used to terminate battery charge when the voltage on VDD5V
TRSH falls below the programmed threshold. This comparator has ~50mV of hystersis to prevent chattering at the
comparator trip point.
0b00: 4.3V
0b01: 4.4V
0b10: 4.5V(default)
0b11: 4.7V
27 Reserved.
RSRVD5
26–24 Adjustment to optimize the performance of the battery charge and 4.2V regulation circuit at low 5v voltages.
HEADROOM_
ADJ
23–22 Reserved.
RSRVD4
21–20 Controls the power down of both the battery charger and 4.2V regulation circuit. Default is powered down.
PWD_CHARGE_
4P2
19–18 Reserved.
RSRVD3
17–12 Limits the combined current from 5V that the battery charger and DCDC_4P2 circuit consume. Current
CHARGE_4P2_ represented by each bits is as follows: (400 mA, 200 mA, 100 mA, 50 mA, 20 mA, 10 mA) = (bit 5,bit 4, bit
ILIMIT 3, bit 2, bit 1, bit 0). The DCDC_4P2 circuit is given priority as the sum of the currents exceeds the limit.
11 Reserved.
RSRVD2
10–8 Set the threshold for the VBUSVALID comparator.This comparator is the most accurate method to determine
VBUSVALID_ the presence of 5v, and includes hystersis to minimize the need for software debounce of the detection.
TRSH This comparator has ~50mV of hystersis to prevent chattering at the comparator trip point.
0b000: 2.9V
0b001: 4.0V
0b010: 4.1V
0b011: 4.2V
0b100: 4.3V(default)
0b101: 4.4V
0b110: 4.5V
0b111: 4.6V
7 The purpose of this bit is to power down the device if 5V is removed before the system is completely initialized.
PWDN_ Clear this bit to disable automatic hardware powerdown AFTER the system is configured for 5v removal.
5VBRNOUT This bit should not be set if DCDC_XFER is set.

HW_POWER_5VCTRL field descriptions (continued)

Field Description
6 Enable the current limit in the linear regulators. The current limit is active during powerup from 5v and
ENABLE_ automatically disables before the ROM executes. This limit is needed to meet the USB in rush current
LINREG_ILIMIT specification of 100mA + 50uC. Note this linear regulator current limit is not related to the
CHARGE_4P2_ILIMIT.
5 Enable automatic transition to switching DC-DC converter when VDD5V is removed. The LRADC must be
DCDC_XFER operational and the BATT_VAL field must be written with the battery voltage using 8-mV step-size. It is also
important to set the EN_BATADJ field.
4 Power up and use VBUSVALID comparator as detection circuit for 5V in the switching converter. The
VBUSVALID_ VBUSVALID comparator provides a more accurate and adjustable threshold to determine the presence of
5VDETECT 5V in the system, and is the recommended method of detecting 5V.
3 This bit muxes the Bvalid comparator to the VBUSVALID comparator and is used for test purposes only.
VBUSVALID_
TO_B
2 The amount of current the device will consume from the 5V rail is minimized. The VDDIO linear regulator
ILIMIT_EQ_ current limit is set to zero mA. Also, the source of current for the crystal oscillator and RTC is switched to
ZERO the battery. Note that this functionality does not affect battery charge.
1 Powers up comparators for 5v

PWRUP_VBUS_
CMPS
0 Enables the switching DC-DC converter when 5V is present. It is recommended to set ILIMIT_EQ_ZERO,
ENABLE_DCDC ENABLE_ILIMIT, and all LINREG_OFFSET bits when enabling this functionality.
11.12.3 DC-DC Minimum Power and Miscellaneous Control Register

(HW_POWER_MINPWR)
This register controls options to drop the power used by the switching DC-DC converter.
These bits should only be modified with guidance from Freescale.
HW_POWER_MINPWR: 0x020
HW_POWER_MINPWR_SET: 0x024
HW_POWER_MINPWR_CLR: 0x028
HW_POWER_MINPWR_TOG: 0x02C

Address: HW_POWER_MINPWR – 8004_4000h base + 20h offset = 8004_4020h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOWPWR_4P2
USE_VDDXTAL_
HALF_FETS
RSRVD1
PWD_ANA_
LESSANA_I
DOUBLE_
STOPCLK
ENABLE_
HALFCLK
SELECT_
PWD_BO
R
XTAL24
EN_
RSVD1
[15:15]
CMPS
PWD_
FETS
OSC
OSC
VBG_
DC_
DC_
VBG
DC_
OFF
W PFM
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_POWER_MINPWR field descriptions

Field Description
31–15 Reserved.
RSRVD1
14 Enable low power regulation of DCDC_4P2 limited to 2.5mA.
LOWPWR_4P2
13 Program this field to 0x0.
RSVD1
12 Powers down supply brownout comparators. This should only be used when monitoring supply brownouts
PWD_BO is not needed.
11 Change the reference used in the dcdc converter to a low power, less accurate reference. This should only
USE_VDDXTAL_ be used when achieving minimum system power is more important than supply voltage accuracy.
VBG
10 Powers down analog comparators used in the power module, including the VDD and VDDA brownout
PWD_ANA_ comparators, low power reference. This bit should only be set to reach absolute minimum system power
CMPS when running from the linear regulators and supply accuracy and VDDD/VDDA brownout detection is not
important.
9 Enables the internal oscillator. This oscillator is less accurate , but lower power than the 24 MHz xtal.
ENABLE_OSC
8 Switch internal 24 MHz clock reference to the less accurate internal oscillator. This bit should be set only
SELECT_OSC when accuracy of the 24 MHz clock is not important. The value of this bit should only be changed when
ENABLE_OSC=1 and PWD_XTAL24=0.
7 Powers down the bandgap reference. This should only be used in 5v-powered applications when absolute
VBG_OFF minimum power is more important than supply voltage accuracy. USB_I_SUSPEND must be set before this
bit is set.
6 Approximately doubles the size of power transistors in DC-DC converter. This maybe be useful in high power
DOUBLE_FETS conditions.
5 Disable half the power transistors in DC-DC converter. This maybe be useful in low-power conditions when
HALF_FETS the increased resistance of the power FETs is acceptable.

HW_POWER_MINPWR field descriptions (continued)

Field Description
4 Reduce DC-DC analog bias current 20%. This bit is intended to reduce power in low-performance operating
LESSANA_I modes, such as USB suspend.
3 Powers down the 24 MHz oscillator, even when the system is still operating. This can be used with
PWD_XTAL24 ENABLE_OSC and SELECT_OSC to reduce current in usb suspend and other low power modes where
the accuracy of the clock is not important.
2 Stop the clock to internal logic of switching DC-DC converter. This bit will take effect only after the switching
DC_STOPCLK FETs are off, due to battery configuration, PFM mode, or internal linear regulator operation.
1 Forces DC-DC to operate in a Pulse Frequency Modulation mode. Intended to allow minimum system power
EN_DC_PFM in very low-power configurations when increased ripple on the supplies is acceptable. Also, HYST_SIGN in
HW_POWER_LOOPCTRL should be set high when using PFM mode.
0 Slow down DC-DC clock from 1.5 MHz to 750 kHz. This maybe be useful to improve efficiency at light loads
DC_HALFCLK or improve EMI radiation, although peak-to-peak voltage on the supplies will increase.
11.12.4 Battery Charge Control Register (HW_POWER_CHARGE)

This register cotrols the battery charge features for both NiMH slow charge and Li-Ion
charge.
HW_POWER_CHARGE: 0x030
HW_POWER_CHARGE_SET: 0x034
HW_POWER_CHARGE_CLR: 0x038
HW_POWER_CHARGE_TOG: 0x03C
Address: HW_POWER_CHARGE – 8004_4000h base + 30h offset = 8004_4030h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD5
RSRVD4
RSRVD3
PWD_BATTCHRG
CHRG_STS_OFF
ENABLE_FAULT_
ENABLE_LOAD
R RSRVD6
LIION_4P1
DETECT
ADJ_VOLT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENABLE_CHARGER_
ENABLE_CHARGER_
R RSRVD2 RSRVD1
USB1
USB0
STOP_ILIMIT BATTCHRG_I
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_POWER_CHARGE field descriptions

Field Description
31–27 Reserved.
RSRVD6
26–24 Adjustments to the final LiIon final voltage. These bits should not be set unless recommended by Freescale.
ADJ_VOLT
0b000: no change
0b001: -0.25%
0b010: +0.50%
0b011: -0.75%
0b100: +0.25%
0b101: -0.50%
0b110: +0.75%
0b111: -1.00%
23 Reserved.
RSRVD5
22 Enable 100ohm load on the regulated 4.2V output. This bit should not be set unless recommended by
ENABLE_LOAD Freescale.
21 Reserved.
RSRVD4
20 Enable fault detection in the battery charger. When enabled, this bit will power down the battery charger
ENABLE_ when the VDD5V voltage falls below the battery voltage. The fault can be cleared by cycling
FAULT_DETECT PWD_CHARGE_4P2. The fault detection is visible through HW_POWER_STS_VDD5V_FAULT.
19 Setting this bit disables the CHRGSTS status bit. Disabling CHRGSTS should only be done when the
CHRG_STS_OFF switching converter is enabled during battery charge if noise from the switching converter causes CHRGSTS
to toggle excessively.
18 This bit has no effect.

LIION_4P1
17 Reserved.
RSRVD3
16 Power-down the battery charge circuitry. This should only be set low when 5V is present. This bit can be
PWD_ set (charger turned off) automatically by the threshold units of the LRADC if programmed to do so.
BATTCHRG
15–14 Reserved.
RSRVD2

HW_POWER_CHARGE field descriptions (continued)

Field Description
13 Enable 125k pullup on USB_DP and 375k on USB_DN to provide USB_CHARGER functionality for USB1.
ENABLE_ This functionality is a new USB spec and should not be enabled unless recommended by Freescale.
CHARGER_
USB1
12 Enable 125k pullup on USB_DP and 375k on USB_DN to provide USB_CHARGER functionality for USB0.
ENABLE_ This functionality is a new USB spec and should not be enabled unless recommended by Freescale.
CHARGER_
USB0
11–8 Current threshold at which the Li-Ion battery charger signals to stop charging. The current represented by
STOP_ILIMIT each bit is as follows: (100 mA, 50 mA, 20 mA, 10 mA) = (bit 3, bit 2, bit 1, bit 0) It is recommended to set
this value to 10% of the charge current.
7–6 Reserved.
RSRVD1
5–0 Magnitude of the battery charge current, the current represented by each bit is as follows: (400 mA, 200
BATTCHRG_I mA, 100 mA, 50 mA, 20 mA, 10 mA) = (bit 5,bit 4, bit 3, bit 2, bit 1, bit 0)
11.12.5 VDDD Supply Targets and Brownouts Control Register

(HW_POWER_VDDDCTRL)
This register controls the voltage targets and brownout targets for the VDDD supply
generated from the switching DC-DC converter and integrated linear regulators. The
brownout comparators default enabled.
Address: HW_POWER_VDDDCTRL – 8004_4000h base + 40h offset = 8004_4040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DISABLE_FET
ENABLE_
STEPPING
RSRVD4 RSRVD3
DISABLE_
BRNOUT
R
LINREG
PWDN_
LINREG_
ADJTN
OFFSET
W
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD2 RSRVD1
BO_OFFSET TRG
W
Reset 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0
HW_POWER_VDDDCTRL field descriptions

Field Description
31–28 Two's complement number that can be used to adjust the duty cycle of VDDD. This is intended for test
ADJTN purposes only

HW_POWER_VDDDCTRL field descriptions (continued)

Field Description
27–24 Reserved.
RSRVD4
23 Powers down the device after the DC-DC converter completes startup if a VDDD brownout occurs. This
PWDN_BRNOUT function is only active when 5V is not present. Additionally, software should clear this bit and disable this
function after the system is configured for a VDDD brownout and the VDDD brownout interrupt is enabled.
22 Disables the default behavior of the voltage stepping algorithm when the TRG field is updated. By default,
DISABLE_ the control loop steps sequentially through 25mV steps on both target and brownout voltage to minimize
STEPPING transients during TRG adjustments.
When this bit is set, the entire target voltage and brownout adjustment takes place at one time, which will
speed transitions, but will result in increased supply transients as well as possible brownouts when the new
(TRG - BO_OFFSET) >= old TRG.Thus, it is recommended to change TRG by less than the (BO_OFFSET-2)
value when using DISABLE_STEPPING.This bit should be set high when powering VDDD from the integrated
linear regulators.
21 Enables the VDDD linear regulator converter when the switching converter is active. By default, the linear
ENABLE_ regulator is not active when the switching converter is active.
LINREG
20 Disable the VDDD switching converter output.
DISABLE_FET
19–18 Reserved.
RSRVD3
17–16 Number of 25mV steps between linear regulator output voltage and switching converter target.
LINREG_
00b = 0 steps, recommended when powering VDDD only from linear regulator and
OFFSET
ENABLE_DCDC=DCDC_XFER=0. It is also recommended to set DISABLE_STEPPING when powering
VDDD from the linear regulators.
01b = 1 step above.
10b = 1 step below (default), important when powering VDDD from DC-DC converter and linear regulator
simultaneously.
11b = 2 steps below.
15–11 Reserved.
RSRVD2
10–8 Brownout voltage offset in 25mV steps below the TRG value. Note that the hardware only supports brownout
BO_OFFSET voltages between 0.8V and 1.475V, and values outside this range should not be programmed. The brownout
trip voltage will adjust as the target voltage changes.
7–5 Reserved.
RSRVD1
4–0 Voltage level of the VDDD supply. The step size of this field is 25 mV. 0x00 = 0.8 V, 0x1F = 1.575 V, and
TRG the reset value = 1.2 V. This field should not be set above the VDDD operating maximum voltage as specified
in the Datasheet. It is also recommended to set DISABLE_STEPPING when powering VDDD from the
integrated linear regulators. Setting DISABLE_STEPPING does set additional restrictions on TRG adjusments.

11.12.6 VDDA Supply Targets and Brownouts Control Register

(HW_POWER_VDDACTRL)
This register controls the voltage targets and brownout targets for the VDDA supply
Address: HW_POWER_VDDACTRL – 8004_4000h base + 50h offset = 8004_4050h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DISABLE_STEPPING
ENABLE_LINREG
PWDN_BRNOUT
R RSRVD4
DISABLE_FET
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD2
R RSRVD3 RSRVD1
LINREG_
BO_OFFSET TRG
OFFSET
Reset 0 0 1 0 0 1 1 1 0 0 0 0 1 1 0 0
HW_POWER_VDDACTRL field descriptions

Field Description
31–20 Reserved.
RSRVD4
19 Powers down the device after the DC-DC converter completes startup if a VDDA brownout occurs. This
function after the system is configured for a VDDA brownout and the VDDA brownout interrupt is enabled.
value when using DISABLE_STEPPING.This bit should be set high when powering VDDA from the integrated
linear regulators.
17 Enables the VDDA linear regulator converter when the switching converter is active. By default, the linear
ENABLE_ regulator is not active when the switching converter is active.
LINREG

HW_POWER_VDDACTRL field descriptions (continued)

Field Description
16 Disable the VDDA switching converter output. The switching converter is enabled by default when the battery
DISABLE_FET is present or the ENABLE_DCDC is set.
15–14 Reserved.
RSRVD3
LINREG_
00b = 0 steps, recommended when powering VDDA from linear regulator and
OFFSET
VDDA from the linear regulators.
01b = 1 step above.
10b = 1 step below (default), important when powering VDDA from DC-DC converter and linear regulator
simultaneously.
11 Reserved.
RSRVD2
7–5 Reserved.
RSRVD1
4–0 Voltage level of the VDDA supply. The step size of this field is 25 mV. 0x00 = 1.5 V, 0x1F = 2.275 V, and
TRG the reset value = 1.8 V. This field should not be set above the VDDA operating maximum voltage as specified
in the Datasheet. It is also recommended to set DISABLE_STEPPING when powering VDDA from the
integrated linear regulators. Setting DISABLE_STEPPING does set additional restrictions on TRG adjusments.
11.12.7 VDDIO Supply Targets and Brownouts Control Register

(HW_POWER_VDDIOCTRL)
This register controls the voltage targets and brownout targets for the VDDIO supply

Address: HW_POWER_VDDIOCTRL – 8004_4000h base + 60h offset = 8004_4060h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DISABLE_STEPPING
RSRVD4
PWDN_BRNOUT
DISABLE_FET
R RSRVD5
ADJTN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11
RSRVD2 10 9 8 7 6 5 4 3 2 1 0
R RSRVD3 RSRVD1
LINREG_
BO_OFFSET TRG
OFFSET
Reset 0 0 1 0 0 1 0 0 0 0 0 0 0 1 1 0
HW_POWER_VDDIOCTRL field descriptions

Field Description
31–24 Reserved.
RSRVD5
23–20 Two's complement number that can be used to adjust the duty cycle of VDDIO. This is intended for test
ADJTN purposes only
19 Reserved.
RSRVD4
18 Powers down the device after the DC-DC converter completes startup if a VDDIO brownout occurs. This
function after the system is configured for a VDDIO brownout and the VDDIO brownout interrupt is enabled.
value when using DISABLE_STEPPING. This bit should be set high when powering VDDIO from the
integrated linear regulators.
16 Disable the VDDIO switching converter output. The switching converter is enabled by default when the
DISABLE_FET battery is present or the ENABLE_DCDC is set.
15–14 Reserved.
RSRVD3
LINREG_
OFFSET

HW_POWER_VDDIOCTRL field descriptions (continued)

Field Description
00b = 0 steps, recommended when powering VDDIO from linear regulator and
VDDIO from the linear regulators.
01b = 1 step above.
10b = 1 step below (default), important when powering VDDIO from DC-DC converter and linear regulator
simultaneously.
11 Reserved.
RSRVD2
10–8 Brownout voltage offset in 50 mV steps below the TRG value. Note that the hardware only supports brownout
7–5 Reserved.
RSRVD1
4–0 Voltage level of the VDDIO supply. The step size of this field is 50 mV. 0x00 = 2.8 V and the reset value =
TRG 3.1 V. Note that the maximum programmable voltage is 3.6V, therefore code values of 0x10 to 0x1F all map
to 3.6 V. It is also recommended to set DISABLE_STEPPING when powering VDDIO from the integrated
linear regulators. Setting DISABLE_STEPPING does set additional restrictions on TRG adjusments.
11.12.8 VDDMEM Supply Targets Control Register

(HW_POWER_VDDMEMCTRL)
This register controls the voltage target for a memory supply generated from VDDA. This
supply is intended for use with external memories such as LV-DDR that have unique voltage
requirements not compatible with VDDIO, VDDA , or VDDD.
Address: HW_POWER_VDDMEMCTRL – 8004_4000h base + 70h offset = 8004_
4070h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD2[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENABLE_LINREG
ENABLE_ILIMIT
PULLDOWN_
R RSRVD2[15:11]
ACTIVE
BO_OFFSET TRG
W
Reset 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0
HW_POWER_VDDMEMCTRL field descriptions

Field Description
31–11 Reserved.
RSRVD2
10 Activates pulldown on external memory supply. This bit should be set before the regulator is enabled to be
PULLDOWN_ sure the supply voltage powers up from ground. Default is pulldown inactive.
ACTIVE
9 Controls the inrush limit (~10mA) for the memory supply voltage. Default is active. This should remain active
ENABLE_ILIMIT until the supply settles after enabling the linreg. This should be disabled before accessing the memory.
8 Enables the regulator that creates the external memory supply voltage. After enabling the linreg need to
ENABLE_ wait until the VDDMEM rail is up before disabling the linreg current limit and accessing the memories. 500uS
LINREG is usually an adequate delay, but it can be longer if VDDMEM cap is >1uF.
4–0 Voltage level of the external memory supply. The step size of this field is 25 mV. 0x00 = 1.1 V, 0x1A...0x1F
TRG = 1.75 V, and the reset value = 1.5 V.
11.12.9 DC-DC Converter 4.2V Control Register

(HW_POWER_DCDC4P2)
This register contains controls that need to be adjusted to select the 4.2V source as the input
for the dcdc converter
Address: HW_POWER_DCDC4P2 – 8004_4000h base + 80h offset = 8004_4080h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD3
ENABLE_DCDC
HYST_THRESH
ENABLE_4P2
R RSRVD5
HYST_DIR
ISTEAL_
DROPOUT_CTRL TRG
THRESH
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD2 RSRVD1
BO CMPTRIP
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
HW_POWER_DCDC4P2 field descriptions

Field Description
31–28 Adjusts the behavior of the dcdc converter and 4.2V regulation circuit. The two msbs control the VDD4P2
DROPOUT_ brownout below the target set by DCDC4p2_trg before the regulation circuit steals battery charge current
CTRL to support the voltage on VDD4P2. The two lsbs control which power source is selected by the dcdc converter
after ENABLE_DCDC is set.
0b11XX: 200mV
0b10XX: 100mV
0b01XX: 50mV
0b00XX: 25mV
0bXX00: DcDc Converter power source is DCDC_4P2 regardless of BATTERY voltage
0bXX01: DcDc converter uses DCDC_4P2 always, and only enables DCDC_BATT when VDD4P2 is less
than BATTERY.
0bXX1X: DcDc converter selects either VDD4P2 or BATTERY, which ever is higher.
27–26 Reserved.
RSRVD5
25–24 Has no effect.
ISTEAL_
THRESH
23 Enables the DCDC_4P2 regulation circuitry. The 4p2V load current has priority over the battery charge
ENABLE_4P2 current when the sum of the two tries to exceed the limit set with CHARGE_4P2_ILIMIT.
22 Enable the dcdc converter to use the DCDC_4P2 pin as a power source based on a voltage comparison
ENABLE_DCDC between the BATTERY pin voltage and the VDD4P2 pin voltage. The trip point of this comparator is controlled
by the CMPTRIP bitfield.
21 Enable hysteresis in analog comparator.

HYST_DIR
20 Increase the threshold detection for DCDC_4P2/BATTERY analog comparator.
HYST_THRESH
19 Reserved.
RSRVD3
18–16 Regulation voltage of the DCDC_4P2 pin.
TRG
0b000 : 4.2V
0b001 : 4.1V
0b010 : 4.0V

HW_POWER_DCDC4P2 field descriptions (continued)

Field Description
0b011 : 3.9V
0b1XX : BATTERY
15–13 Reserved.
RSRVD2
12–8 Brownout voltage in 25mV steps for the DCDC_4P2 pin.
BO
0b00000 : 3.6V
..
0b11111 : 4.375V
7–5 Reserved.
RSRVD1
4–0 Sets the trip point for the comparison between the DCDC_4P2 and BATTERY pin. When the comparator
CMPTRIP output is high then, the switching converter may use the DCDC_4P2 pin as the source for the switching
converter, otherwise it will use the DCDC_BATT pin.
0b00000 DCDC_4P2 pin >= 0.85 * BATTERY pin
0b11000 DCDC_4P2 pin >= BATTERY pin (default)
11.12.10 DC-DC Miscellaneous Register (HW_POWER_MISC)

This register contains controls that may need to be adjusted to optimize DC-DC converter
performance using the battery voltage information
Address: HW_POWER_MISC – 8004_4000h base + 90h offset = 8004_4090h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD2[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISABLEFET_BO_
DELAY_TIMING
SEL_PLLCLK
R RSRVD2[15:7]
LOGIC
FREQSEL TEST
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_POWER_MISC field descriptions

Field Description
31–7 Reserved.
RSRVD2
6–4 This register will select the PLL-based frequency that the dcdc uses when SEL_PLLCLK is set high. The
FREQSEL decode is as follows:
0x0=Reserved
0x1=20MHz
0x2=24MHz
0x3=19.2MHz
0x4=14.4MHz
0x5=18MHz
0x6=21.6MHz
0x7=17.28Mhz
.
3 This bit can be used to enable/disable the logic which stops the power-FETs in the DC-DC converter from
DISABLEFET_ switching when a brown-out condition is detected.
BO_LOGIC
2 This bit delays the timing of the output fets in the switching dcdc converter. This may provide improved
DELAY_TIMING ground noise performance in high power applications.
1 Reserved. Do not set.

TEST
0 This bit selects the source of the clock used for the DC-DC converter. The default is to use the 24-MHz
SEL_PLLCLK clock. Setting this bit selects the PLL clock as a clock source for the DC-DC converter. It is required to
program FREQSEL before setting this bit.
11.12.11 DC-DC Duty Cycle Limits Control Register

(HW_POWER_DCLIMITS)
This register defines the upper and lower duty cycle limits of DC-DC. These values depend
on details of switching converter implementation and should not be changed without guidance
from Freescale.

Address: HW_POWER_DCLIMITS – 8004_4000h base + A0h offset = 8004_40A0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD3
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD2
RSRVD1
R
POSLIMIT_BUCK NEGLIMIT
Reset 0 0 0 0 1 1 0 0 0 1 0 1 1 1 1 1
HW_POWER_DCLIMITS field descriptions

Field Description
31–16 Reserved.
RSRVD3
15 Reserved.
RSRVD2
14–8 Upper limit duty cycle limit in DC-DC converter. This field will limit the maximum VDDIO acheivable for a
POSLIMIT_BUCK given battery voltage, and it's value may be increased if very low battery operation is desired.
7 Reserved.
RSRVD1
6–0 Negative duty cycle limit of DC-DC converter.
NEGLIMIT
11.12.12 Converter Loop Behavior Control Register

(HW_POWER_LOOPCTRL)
This register defines the control loop parameters available for the DC-DC converter.
HW_POWER_LOOPCTRL: 0x0B0
HW_POWER_LOOPCTRL_SET: 0x0B4
HW_POWER_LOOPCTRL_CLR: 0x0B8
HW_POWER_LOOPCTRL_TOG: 0x0BC

Address: HW_POWER_LOOPCTRL – 8004_4000h base + B0h offset = 8004_40B0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CM_HYST_THRESH
EN_CM_HYST
EN_DF_HYST
R RSRVD3
HYST_SIGN
TOGGLE_DIF
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCSCALE_THRESH
DF_HYST_THRESH
RSRVD2
EN_RCSCALE
R RSRVD1
DC_FF DC_R DC_C
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1
HW_POWER_LOOPCTRL field descriptions

Field Description
31–21 Reserved.
RSRVD3
20 Set high to enable supply stepping to change only after the differential control loop has toggled as well. This
TOGGLE_DIF should eliminate any chance of large transients when supply voltage changes are made.
19 Invert the sign of the hysteresis in DC-DC analog comparators. This bit should set when using PFM mode.
HYST_SIGN
18 Enable hysteresis in switching converter common mode analog comparator.This feature will improve transient
EN_CM_HYST supply ripple and efficiency.
17 Enable hysteresis in switching converter differential mode analog comparators. This feature will improve
EN_DF_HYST transient supply ripple and efficiency.
16 Increase the threshold detection for common mode analog comparator.

CM_HYST_
THRESH
15 Increase the threshold detection for common mode analog comparator.
DF_HYST_
THRESH
14 Increase the threshold detection for RC scale circuit.
RCSCALE_
THRESH
13–12 Enable analog circuit of DC-DC converter to respond faster under transient load conditions.
EN_RCSCALE
00: disabled
01: 2X increase
10: 4X increase

HW_POWER_LOOPCTRL field descriptions (continued)

Field Description
11: 8X increase
11 Reserved.
RSRVD2
10–8 Two's complement feed forward step in duty cycle in the switching DC-DC converter. Each time this field
DC_FF makes a transition from 0x0, the loop filter of the DC-DC converter is stepped once by a value proportional
to the change. This can be used to force a certain control loop behavior, such as improving response under
known heavy load transients.
7–4 Magnitude of proportional control parameter in the switching DC-DC converter control loop.
DC_R
3–2 Reserved.
RSRVD1
1–0 Ratio of integral control parameter to proportional control parameter in the switching DC-DC converter, and
DC_C can be used to optimize efficiency and loop response.
00: Maximum
01: Decrease ratio 2X
10: Decrease ratio 4X
11: Lowest ratio.
11.12.13 Power Subsystem Status Register (HW_POWER_STS)

This register contains status information for the battery charger, DCDC converter and
USB/OTG connections.
Address: HW_POWER_STS – 8004_4000h base + C0h offset = 8004_40C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VDDMEM_BO
THERMAL_
BVALID0_
AVALID0_
WARNING
STATUS
STATUS
R RSRVD3 PWRUP_SOURCE RSRVD2 PSWITCH
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCDC_4P2_BO
VDD5V_FAULT
VDD5V_GT_
SESSEND0_
VDDIO_BO
VBUSVALID0_
CHRGSTS
VDDD_BO
VDDA_BO
BATT_BO
VDD5V_
DROOP
STATUS
VDDIO
STATUS
DC_
R
OK
VBUSVALID0
SESSEND0
BVALID0
AVALID0
W
Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
HW_POWER_STS field descriptions

Field Description
31–30 Reserved.
RSRVD3
29–24 These read-only bits determine which source was active when the dcdc converter powerup sequence was
PWRUP_ complete. This can be used to determine what event caused the device to powerup.
SOURCE
bit5 : five volts
bit4 : rtc wakeup
bit3 : reserved
bit2 : reserved
bit1 : high level pswitch voltage
bit0 : midlevel pswitch voltage
23–22 Reserved.
RSRVD2
21–20 These read-only bits reflect the current state of the pswitch comparators. The lsb is high when voltage on
PSWITCH the PSWITCH pin is above 0.8V, and the msb is high when the voltage on the PSWITCH pin is above 1.75V
19 Asserting this signal is a last warning to the cpu before the temp sensor shuts down the power system
THERMAL_
. It will be asserted at a small temperature offset below the chip thermal limit.
WARNING
18 Output of VDDMEM brownout comparator. High when a brownout is detected. This comparator's
VDDMEM_BO power-up/power-down follows the VDDMEM regulator power-up.
17 Indicates VBus is valid for a A-peripheral. This bit is a read only version of the state of the analog signal. It
AVALID0_ can not be overritten by software like the AVALID bit below.
STATUS
16 Indicates VBus is valid for a B-peripheral. This bit is a read only version of the state of the analog signal. It
BVALID0_ can not be overwritten by software like the BVALID bit below.
STATUS
15 VBus valid for USB OTG. This bit is a read only version of the state of the analog signal. It can not be
VBUSVALID0_ overwritten by software like the VBUSVALID bit below.
STATUS

HW_POWER_STS field descriptions (continued)

Field Description
14 Session End for USB OTG. This bit is a read only version of the state of the analog signal. It can not be
SESSEND0_ overwritten by software like the SESSEND bit below. NOTE: This bit's default value depends on whether
STATUS VDD5V is present, 0 if VDD5V presents, 1 if VDD5V not presents.
13 Output of battery brownout comparator.

BATT_BO
12 Battery charging fault status. If the battery charger is not powered down, the bit is high when the 5V supply
VDD5V_FAULT falls below the battery voltage. If the charger is powered down, the bit asserts high when 5V falls to below
roughly VDDIO/2. If the charger is not powered down, the bit is sticky and remains set until the
PWD_CHARGE_4P2 bit is cycled. Otherwise, the bit is cleared when 5V is restored. NOTE: The default
value depends on whether VDD5V is present, 0 if 5V presents, 1 if 5V not presents.
11 Battery charging status. High during Li-Ion battery charge until the charging current falls below the
CHRGSTS STOP_ILIMIT threshold.
10 Output of the brownout comparator on the DCDC_4P2 pin.

DCDC_4P2_BO
9 High when switching DC-DC converter control loop has stabilized after a voltage target change. When linear
DC_OK regulators are active, this bit goes high when the actual voltage is above the target voltage. Therefore,
DC_OK will go high when changing a linear regulator output to a lower value before the actual voltage
decreases to the new target value.
8 Output of VDDIO brownout comparator. High when a brownout is detected. This comparator defaults powered
VDDIO_BO up, but can be powered down through the POWER_MINPWR register.
7 Output of VDDA brownout comparator. High when a brownout is detected. It is not possible to power-down
VDDA_BO this comparator.
6 Output of VDDD brownout comparator. High when a brownout is detected. It is not possible to power-down
VDDD_BO this comparator.
5 Indicates the voltage on the VDD5V pin is higher than VDDIO by a Vt voltage, nominally 500 mV.
VDD5V_GT_
VDDIO
4 Indicates the voltage on the VDD5V pin is below the VBUSDROOP_TRSH defined in the 5VCTRL register.
VDD5V_DROOP
3 Indicates VBus is above the VA_SESS_VLD threshold, that is, high if VBus greater than 2.0, low if VBus
AVALID0 less than 0.8, otherwise unknown.
2 Indicates VBus is above the VB_SESS_VLD threshold, high if VBus greater than 4.0, low if VBus less than
BVALID0 0.8, otherwise unknown.
1 Accurate detection of the presence of 5v power. This can be used for detection of 5v in all modes of operation
VBUSVALID0 including USB OTG. See POWER_5VCTRL to enable and set threshold for comparison.
0 Indicates VBus is below the VB_SESS_END threshold, that is, 0 if VBus is greater than 0.8 V, 1 if VBus is
SESSEND0 less than 0.2 V, otherwise unknown. See POWER_5VCTRL to enable comparators. NOTE: This bit's default
value depends on whether VDD5V is present, 0 if VDD5V presents, 1 if VDD5V not presents.

11.12.14 Transistor Speed Control and Status Register

(HW_POWER_SPEED)
This register contains the setup and controls needed to measure silicon speed.
HW_POWER_SPEED: 0x0D0
HW_POWER_SPEED_SET: 0x0D4
HW_POWER_SPEED_CLR: 0x0D8
HW_POWER_SPEED_TOG: 0x0DC
Address: HW_POWER_SPEED – 8004_4000h base + D0h offset = 8004_40D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1 STATUS[23:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R STATUS[15:8] RSRVD0
STATUS_SEL CTRL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_POWER_SPEED field descriptions

Field Description
31–24 Reserved.
RSRVD1
23–8 Result from the speed sensor.This result is only valid when SPEEDCTRL=0b11; otherwise this field contains
STATUS debug information from the switching DC-DC converter.
7–6 Speed Sensor Status Select. This defines the meaning on the STATUS field in this register.
STATUS_SEL
0x0 DCDC_STAT — DC-DC speed sensor (lower 8 bits)
0x1 CORE_STAT — core logic speed sensor
0x2 ARM_STAT — arm9 speed sensor
5–2 Reserved.
RSRVD0
1–0 Speed Control bits. 00: Speed sensor off, 0b01: Speed sensor enabled, 11: Enable speed sensor
CTRL measurement. Every time a measurement is taken, the sequence of 0x00 ; 01 ; 11 must be repeated. This
sequence should proceed no faster than 1.5 MHz to ensure proper operation.

11.12.15 Battery Level Monitor Register (HW_POWER_BATTMONITOR)

This register provides brownout controls and monitors the battery voltage.
Address: HW_POWER_BATTMONITOR – 8004_4000h base + E0h offset = 8004_
40E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD3
BATT_VAL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRWNOUT_PWD
5VDETECT_ENABLE
BATTBRNOUT
BATTBRNOUT_
EN_BATADJ
R RSRVD2 RSRVD1
PWDN_
PWDN_
BRWNOUT_LVL
W
Reset 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0
HW_POWER_BATTMONITOR field descriptions

Field Description
31–26 Reserved.
RSRVD3
25–16 Software should be configured to place the battery voltage in this register measured with an 8-mV LSB
BATT_VAL resolution through the LRADC.This value is used by the DC-DC converter and must be correct before setting
EN_BATADJ.
15–12 Reserved.
RSRVD2
11 Enable the use of the programmed 5V detect signal to gate off the powering down of the device when a
PWDN_
battery brownout occurs. Clear this bit to power-down the device when a battery brown-out occurs regardless
BATTBRNOUT_
of the state of the 5
5VDETECT_
ENABLE V detect signal.
10 This bit enables the DC-DC to improve efficiency and minimize ripple using the information from the
EN_BATADJ BATT_VAL field. It is very important that BATT_VAL contain accurate information before setting EN_BATADJ.
Note: HW_LRADC_CONVERSION_SCALE_FACTOR must be programmed to 0x2 before setting this bit
to 0x1.
9 Powers down the device after the DC-DC converter completeS startup if a battery brownout occurs. This
PWDN_ function is only active when 5V is not present. Additionally, software should clear this bit and disable this
BATTBRNOUT function after the system is configured for a battery brownout and the battery brownout interrupt is enabled.
8 Power-down circuitry for battery brownout detection. This bit should only be set when it is not important to
BRWNOUT_PWD montior battery brownouts and minimum system power consumption is required.

HW_POWER_BATTMONITOR field descriptions (continued)

Field Description
7–5 Reserved.
RSRVD1
4–0 The default setting of the brownout settings decode to a voltage as follows:
BRWNOUT_LVL
Li-Ion = 2.4 V
The voltage level can be calculated for other values by the following equation:
Li-Ion brownout voltage = 2.4 V + 0.04 * BRWNOUT_LVL
11.12.16 Power Module Reset Register (HW_POWER_RESET)

This register allows software to put the chip into the off state.
HW_POWER_RESET: 0x100
HW_POWER_RESET_SET: 0x104
HW_POWER_RESET_CLR: 0x108
HW_POWER_RESET_TOG: 0x10C
Address: HW_POWER_RESET – 8004_4000h base + 100h offset = 8004_4100h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UNLOCK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FASTFALLPSWITCH_OFF
R RSRVD1
PWD_OFF
PWD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

HW_POWER_RESET field descriptions

Field Description
31–16 Write 0x3E77 to unlock this register and allow other bits to be changed. NOTE: This register must be
UNLOCK unlocked on a write-by-write basis, so the UNLOCK bitfield must contain the correct key value during
all writes to this register in order to update any other bitfield values in the register.
0x3E77 KEY — Key needed to unlock HW_POWER_RESET register.
15–3 Reserved.
RSRVD1
2 Set this bit to 1'b1 to disable the chip shutting down by a fast falling edge of PSWITCH. Setting this
FASTFALLPSWITCH_ bit will be useful for preventing fast falling edges on the PSWITCH pin from resetting the chip. It may
OFF also be useful increasing system tolerance of noisy EMI environments.
1 Optional bit to disable all paths to power off the chip except the watchdog timer. Setting this bit will be
PWD_OFF useful for preventing fast falling edges on the PSWITCH pin from resetting the chip. It may also be
useful increasing system tolerance of noisy EMI environments.
0 Powers down the chip.

PWD
11.12.17 Power Module Debug Register (HW_POWER_DEBUG)

Debug Register.
HW_POWER_DEBUG: 0x110
HW_POWER_DEBUG_SET: 0x114
HW_POWER_DEBUG_CLR: 0x118
HW_POWER_DEBUG_TOG: 0x11C
Address: HW_POWER_DEBUG – 8004_4000h base + 110h offset = 8004_4110h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD0[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SESSENDPIOLOCK
VBUSVALIDPIOLOCK
BVALIDPIOLOCK
AVALIDPIOLOCK
R RSRVD0[15:4]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_POWER_DEBUG field descriptions

Field Description
31–4 Reserved.
RSRVD0
3 Reserved for Freescale Debugging Purposes Only.
VBUSVALIDPIOLOCK
AVALIDPIOLOCK
BVALIDPIOLOCK
SESSENDPIOLOCK
11.12.18 Power Module Thermal Reset Register

(HW_POWER_THERMAL)
Thermal Reset Register.
HW_POWER_THERMAL: 0x120
HW_POWER_THERMAL_SET: 0x124
HW_POWER_THERMAL_CLR: 0x128
HW_POWER_THERMAL_TOG: 0x12C
This register contains the controls for the thermal temp sensor that can be used to reset the
chip when a temperature threshold is reached.

Address: HW_POWER_THERMAL – 8004_4000h base + 120h offset = 8004_4120h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD0[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET_
R RSRVD0[15:9]
ENABLE
POWER
LOW_
ADJ_
TEST PWD OFFSET_ADJ TEMP_THRESHOLD
W
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
HW_POWER_THERMAL field descriptions

Field Description
31–9 Reserved.
RSRVD0
8 This bit is used for debug purposes only.
TEST
7 Power-down the thermal temp sensor block.
PWD
6 Set to operate thermal temp sensor with less power.
LOW_POWER
5–4 Add offset to the programmed trip point. 00 adds 5degC, 01 adds 10degC, 10 subtracts 5degC, 11 subtracts
OFFSET_ADJ 10degC. These are valid only when HW_POWER_THERMAL_OFFSET_ADJ_ENABLE=1
3 Enable the offset adjustment capability.

OFFSET_ADJ_
ENABLE
2–0 This field programs the thermal reset trip point. A value of 000 sets to 115degC and 111 sets to 150degC.
TEMP_ The intermediate values are in steps of 5degC. When TEST=1, all the trip points are set to 65degC less
THRESHOLD than their programmed values.
11.12.19 Power Module USB1 Manual Controls Register

(HW_POWER_USB1CTRL)
USB1 control Register.
HW_POWER_USB1CTRL: 0x130
HW_POWER_USB1CTRL_SET: 0x134
HW_POWER_USB1CTRL_CLR: 0x138

HW_POWER_USB1CTRL_TOG: 0x13C
This register contains the connection controls for the USB instance 1.
Address: HW_POWER_USB1CTRL – 8004_4000h base + 130h offset = 8004_4130h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD0[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VBUSVALID1
RSRVD0[15:4]
SESSEND1
R
BVALID1
AVALID1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
HW_POWER_USB1CTRL field descriptions

Field Description
31–4 Reserved.
RSRVD0
3 This bit indicates the value for the sessend signal for USB instance 1. It is analogous to the
AVALID1 HW_POWER_STS_AVALID0 bit but this bit is not set by the hardware. It is controlled by software.
BVALID1 HW_POWER_STS_BVALID0 bit but this bit is not set by the hardware. It is controlled by software.
1 This bit indicates the value for the vbusvalid signal for USB instance 1. It is analogous to the
VBUSVALID1 HW_POWER_STS_VBUSVALID0 bit but this bit is not set by the hardware. It is controlled by software.
SESSEND1 HW_POWER_STS_SESSEND0 bit but this bit is not set by the hardware. It is controlled by software.
11.12.20 Power Module Special Register (HW_POWER_SPECIAL)

Special test functionality.
HW_POWER_SPECIAL: 0x140
HW_POWER_SPECIAL_SET: 0x144
HW_POWER_SPECIAL_CLR: 0x148

HW_POWER_SPECIAL_TOG: 0x14C
Address: HW_POWER_SPECIAL – 8004_4000h base + 140h offset = 8004_4140h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TEST
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_POWER_SPECIAL field descriptions

Field Description
31–0 Reserved for Freescale Debugging Purposes Only
TEST
11.12.21 Power Module Version Register (HW_POWER_VERSION)

of the block.
Address: HW_POWER_VERSION – 8004_4000h base + 150h offset = 8004_4150h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MAJOR MINOR STEP

W
Re- 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_POWER_VERSION field descriptions

Field Description
MAJOR
MINOR
STEP
11.12.22 Analog Clock Control Register (HW_POWER_ANACLKCTRL)

HW_POWER_ANACLKCTRL: 0x160
HW_POWER_ANACLKCTRL_SET: 0x164

HW_POWER_ANACLKCTRL_CLR: 0x168
HW_POWER_ANACLKCTRL_TOG: 0x16C
This register provides analog clock control.
Address: HW_POWER_ANACLKCTRL – 8004_4000h base + 160h offset = 8004_
4160h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INVERT_OUTCLK
R RSRVD4[25:16]
CKGATE_O
CKGATE_I
OUTDIV
Reset 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD2
SLOW_DITHER
INVERT_INCLK
DITHER_OFF
INCLK_SHIFT INDIV
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
HW_POWER_ANACLKCTRL field descriptions

Field Description
31 Analog Output Clock Gate, Reserved for Freescale Debugging Purposes Only
CKGATE_O
30–28 Analog Output Clock Divider, Reserved for Freescale Debugging Purposes Only
OUTDIV
27 Analog Output Clock Invert, Reserved for Freescale Debugging Purposes Only
INVERT_
OUTCLK
26 Analog Input Clock Gate, Reserved for Freescale Debugging Purposes Only
CKGATE_I
25–11 Reserved
RSRVD4
10 Clock Dither Disable, Reserved for Freescale Debugging Purposes Only
DITHER_OFF
9 Set 0x1 to make the configuration INDIV<1:0> and INCLK_SHIFT available, but there would be <= 0.67us
SLOW_DITHER timing delay between HSADC start conversion and ‘start run’ command from software trigger or PWM trigger.
If this delay is not desired, it is recommended to set INDIV<1:0> to 0x2 and using PWM trigger for HSADC.
8 Analog Input Clock Invert, Reserved for Freescale Debugging Purposes Only
INVERT_INCLK

HW_POWER_ANACLKCTRL field descriptions (continued)

Field Description
7–6 Reserved
RSRVD3
5–4 Recommended value 0x2 when HSADC works at 1.5 MHz sampling rate with DCDC working. This
INCLK_SHIFT configuration can attenuate the impact of DCDC noise on HSADC performance only when HSADC working
at 1.5 MHz sampling rate, and the configuration is available only when set SLOW_DITHER to 0x1.
3 Reserved
RSRVD2
2–0 INDIV<2>: Set 1 for HSADC working at 1.5 MHz sampling rate. INDIV<1:0>: Recommended value 0x2 when
INDIV HSADC works at 1.5 MHz sampling rate with DCDC working. This configuration can attenuate the impact
of DCDC noise on HSADC performance only when HSADC working at 1.5 MHz sampling rate, and the
configuration is available when set SLOW_DITHER to 0x1 or using PWM trigger for HSADC.
11.12.23 POWER Reference Control Register (HW_POWER_REFCTRL)

This register provides control bits for changing analog voltage and current references.
HW_POWER_REFCTRL: 0x170
HW_POWER_REFCTRL_SET: 0x174
HW_POWER_REFCTRL_CLR: 0x178
HW_POWER_REFCTRL_TOG: 0x17C
The power reference control register provides control over the voltage and power for the
analog circuits.
Address: HW_POWER_REFCTRL – 8004_4000h base + 170h offset = 8004_4170h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD4
RSRVD3
XTAL_BGR_BIAS
FASTSETTLING
R RSRVD5
RAISE_REF
LOW_PWR
VBG_ADJ BIAS_CTRL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VDDXTAL_TO_VDDD
RSRVD2
R RSRVD1
ADJ_ ADJ_
ANA_REFVAL VAG_VAL
ANA VAG
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_POWER_REFCTRL field descriptions

Field Description
31–27 Reserved. Always write zeroes to this bit field.
RSRVD5
26 Set to high to detect the existence of battery. After this bit is set to high, if no battery brownout is detected,
FASTSETTLING then the battery really exists. Reset this bit to low after complete detecting.
25 Reserved for Freescale Debugging Purposes Only

RAISE_REF
24 Switch the XTAL bias from self-bias to bandgap-based bias current. Also switches the source of the XTAL
XTAL_BGR_BIAS supply to the core supply to save power. Note that this bit is not reset by the POWER's SFTRST bit. It is
reset by a power-on reset only, and CLKGATE has no effect on reads/writes.
23 Reserved. Always write zeroes to this bit field.

RSRVD4
22–20 Small adjustment for VBG value. Will affect ALL reference voltages. Expected to be used to tweak final
VBG_ADJ Li-Ion charge voltage. 000=Nominal. 001=+0.3%. 010=+0.6%. 011=0.85%. 100=-0.3%. 101=-0.6%.
110=-0.9%. 111=-1.2%. Note that this bit is not reset by the POWER's SFTRST bit. It is reset by a power-on
reset only, and CLKGATE has no effect on reads/writes.
19 Lowers power (~100 uA) in the bandgap amplifier. This mode is useful in USB suspend or standby when
LOW_PWR bandgap accuracy is not critical. Note that this bit is not reset by the POWER's SFTRST bit. It is reset by a
power-on reset only, and CLKGATE has no effect on reads/writes.

RSRVD3
17–16 Bias current control for all analog blocks: 00=Nominal. 01=-20%. 10=-10%. 11=+10%. Note that this bit not
BIAS_CTRL reset by the POWER's SFTRST bit. It is reset by a power-on reset only, and CLKGATE has no effect on
reads/writes. These bits should only be used for test/debug, and not in an application.

RSRVD2
14 Shorts the supply of the XTAL oscillator to VDDD. This bit may be used to reduce power consumption, but
VDDXTAL_TO_ should only be used on the advice of Freescale.
VDDD
ADJ_ANA
ADJ_VAG

HW_POWER_REFCTRL field descriptions (continued)

Field Description
ANA_REFVAL
VAG_VAL
3–0 Reserved. Always write zeroes to this bit field.
RSRVD1


Chapter 12
Boot Modes
12.1 Overview
The i.MX28 boot process begins at Power On Reset (POR) where the hardware reset logic
forces the ARM core to begin execution starting from the on-chip boot ROM. The boot
ROM logic reads hardware inputs such as the boot pins on the IC or OCOTP bits to determine
the boot flow behavior of the i.MX28.
The main features of the ROM include:
• Support for booting from various boot devices
• USB recovery support
• Encrypted boot image
• Device Configuration Data (DCD) support in boot image
• Digital signature based High Assurance Boot (HAB)
• Secondary boot from NAND and SD/MMC boot devices
The i.MX28 boot ROM supports the following boot devices:
• NAND Flash
• ONFI 2.x BA-NAND
• SD/eSD/MMC/eMMC
• Serial ROM devices, including SPI NOR/EEPROM and I2C EEPROM
Secure Boot
A key feature of the i.MX28 ROM is the ability to perform a secure boot. This is supported
by
• The encrypted boot feature and
• The High Assurance Boot (HAB)
These are independent features and are not dependent on each other.
The encrypted boot feature is an inherent element of the SB boot format used by the i.MX28
ROM. The encrypted boot feature is easily enabled through the use of tools provided by
Freescale to provide image confidentiality..

Boot Modes
A HAB secure boot makes use of a security library which is a subcomponent of the i.MX28
ROM. The HAB uses a combination of hardware and software together with a Public Key
Infrastructure (PKI) protocol to protect the system from executing unauthorized programs.
HAB differs from the encrypted boot feature in that image authentication is performed.
Before the HAB allows a user’s image to execute, the image must be signed. The signing
process is done during the image build process by the private key holder and the signatures
are then included as part of the final Program Image. If configured to do so, the i.MX28
verifies the signatures using the public keys included in the Program Image. A secure boot
with HAB can be performed on all boot devices supported on i.MX28. The HAB library in
the i.MX28 boot ROM also provides API functions, allowing additional boot chain
components (bootloaders) to extend the secure boot chain. The out-of-fab setting for
SEC_CONFIG is the Open configuration in which the ROM/HAB performs image
authentication but all authentication errors are ignored and the image is still allowed to
execute.
The remainder of this chapter provides information on above features and boot modes and
how to configure and use boot features of i.MX28 ROM.
12.2 Boot Modes

Table 12-1 lists all the boot modes supported by i.MX28 ROM. The boot mode can be
selected either through external resistors or through OTP eFuse bit programming.
Table 12-1. Boot Modes
PORT BOOT MODE
USB Encrypted/unencrypted USB slave boot mode.
2 2
I C Encrypted/unencrypted I C0 master—Boots from 1.8- and 3.3-V EEPROM.
SPI2 Encrypted/unencrypted SPI2 master from SSP2—Boots from 1.8- and 3.3-V flash memory.
SPI3 Encrypted/unencrypted SPI3 master from SSP3—Boots from 1.8- and 3.3-V flash and EEPROM.
Encrypted/unencrypted SD/MMC master from SSP1—Boots from 1.8- and 3.3-V 1-bit, 4-bit, and 8-
SSP0
bit SD/MMC/eSD/eMMC cards.
Encrypted/unencrypted SD/MMC master from SSP2—Boots from 1.8- and 3.3-V 1-bit, 4-bit, and 8-
SSP1
bit SD/MMC/eSD/eMMC cards.
GPMI Encrypted/unencrypted NAND, 1.8- and 3.3-V, 8-bit wide, BCH2 to BCH20.
JTAG Wait JTAG connection

Chapter 12 Boot Modes
12.2.1 Boot Mode Selection Map

Table 12-2. Boot Mode Selection Map
VOLTAGE
SELECT-
OR/ BM3/ BM2/ BM1/ BM0/ PORT BOOT MODE
LCD_ LCD_ LCD_ LCD_ LCD_ LCD_
DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0]
USB (unencrypted vs. encrypted is

x x 0 0 0 0 USB0
under OTP control)
x 0 0 0 0 1 I2C0 I2C0 master, 3.3 V
x 1 0 0 0 1 I2C0 I2C0 master, 1.8 V
SPI master SSP2 boot from flash, 3.3

x 0 0 0 1 0 SPI2
V

x 1 0 0 1 0 SPI2
V

x 0 0 0 1 1 SPI3
V

x 1 0 0 1 1 SPI3
V
x 0 0 1 0 0 GPMI NAND, 3.3 V
x 1 0 1 0 0 GPMI NAND, 1.8 V
x 0 0 1 0 1 Reserved
x 0 0 1 1 0 JTAG Wait JTAG connection mode
SPI master SSP3 boot from EEP-

x 0 1 0 0 0 SPI3
ROM, 3.3 V
SPI master SSP3 boot from EEP-

x 1 1 0 0 0 SPI3
ROM, 1.8 V
x 0 1 0 0 1 SSP0 SD/MMC master on SSP0, 3.3 V
x 1 1 0 0 1 SSP0 SD/MMC master on SSP0 1.8 V

OTP eFuse and Persistent Bit Definitions
VOLTAGE
SELECT-
OR/ BM3/ BM2/ BM1/ BM0/ PORT BOOT MODE
LCD_ LCD_ LCD_ LCD_ LCD_ LCD_
DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0]
12.3 OTP eFuse and Persistent Bit Definitions

This section provides tables that show the location and function of the OTP eFuse and
persistent bits.
12.3.1 OTP eFuse

The device contains a 1280-bit array of OTP eFuse bits, some of which are used by ROM.
The bits listed in Table 12-3 – Table 12-5 can be configured by the customers and are
typically programmed on the customer's board assembly line. For more information about
the OTP bits, see OCOTP Overview.
Table 12-3. General ROM Bits
eFuse eFuse Function
Bank:Address:Bit
HW_OCOTP_ROM0:0x8002C1A0:31:24 Boot Modes OCOTP bits, please refer to table12-3 for definitions
HW_OCOTP_ROM0:0x8002C1A0:23:22 SD_MMC_MODE[1:0]
00 = MBR
01 = RESERVED
10 = eMMC fast boot
11 = eSD fast boot
HW_OCOTP_ROM0:0x8002C1A0:21:20 POWER_GATE_GPIO-SD/MMC card power gate GPIO pin select.

00 = PWM3
01 = PWM4
10 = LCD_DOTCLK
11 = NO_GATE


Bank:Address:Bit
HW_OCOTP_ROM0:0x8002C1A0:19:14 POWER_UP_DELAY—SD/MMC card power up delay required after enabling

GPIO power gate.
000000 = 20 ms (default)
000001 = 10 ms
000010 = 20 ms
….
111111 = 630 ms
HW_OCOTP_ROM0:0x8002C1A0:13:12 SD_BUS_WIDTH—SD/MMC card bus width.

00 = 4-bit
01 = 1-bit
10 = 8-bit
11 = Reserved
HW_OCOTP_ROM0:0x8002C1A0:11:8 Index to SSP clock speed. By default (0x0), the clock speed is set to 12 MHz. The
value of the index will modify the SPI clock speed accordingly.
HW_OCOTP_ROM0:0x8002C1A0:7 EMMC_USE_DDR - Blow to enable DDR access mode when fast boot from eM-
MC4.4 card.
HW_OCOTP_ROM0:0x8002C1A0:6 DISABLE_SPI_NOR_FAST_READ—Blow to disable SPI NOR fast reads, which

are used by default. Some SPI NORs do not support this functionality.
HW_OCOTP_ROM0:0x8002C1A0:5 ENABLE_USB_BOOT_SERIAL_NUMBER—If set, the device serial number is

reported to the host during USB boot mode initialization, else no serial number is
reported.
HW_OCOTP_ROM0:0x8002C1A0:4 ENABLE_UNENCRYPTED_BOOT—If clear, allows only booting of encrypted im-

ages. If set, both encrypted/unencrypted images are valid.
HW_OCOTP_ROM0:0x8002C1A0:3 Reserved.
HW_OCOTP_ROM0:0x8002C1A0:2 DISABLE_RECOVERY_MODE—If set, does not allow booting in recovery mode.
HW_OCOTP_ROM0:0x8002C1A0:1:0 USE_ALT_DEBUG_UART_PINS[1:0]
00 - I2C0
01 - AUART0
10 - PWM
11 - reserved
[note] on EVK/Armadillo, PWM0/1 are used as Debug UART Pins, so these two
bits must be blown "10".

Table 12-4. NAND/SD-MMC-Related Bits

eFuse
eFuse Function
Bank:Address:Bit
HW_OCOTP_ROM1:0x8002C1B0:30 DISABLE_SECONDARY_BOOT - Blow this bit to disable the secondary boot.
HW_OCOTP_ROM1:0x8002C1B0:29 SSP3_EXT_PULLUP - This bit is blown to enable external pull up of SSP3 signals.
HW_OCOTP_ROM1:0x8002C1B0:28 SSP2_EXT_PULLUP - This bit is blown to enable external pull up of SSP2 signals.
HW_OCOTP_ROM1:0x8002C1B0:27 ENABLE_NAND7_CE_RDY_PULLUP - If the bit is blown then ROM NAND driver

will enable internal pull-up for GPMI_CE7 and GPMI_RDY7 pins.







HW_OCOTP_ROM1:0x8002C1B0:19 UNTOUCH_INTERNAL_SSP_PULLUP - If this bit is blown then internal pull-ups

for SSP are neither enabled nor disabled. This bit is used only if the external pull-
ups are implemented and ROM1:18 and/or ROM1:17 are blown.
HW_OCOTP_ROM1:0x8002C1B0:18 SSP1_EXT_PULLUP - Blow to indicate external pull-ups implemented for SSP1.
HW_OCOTP_ROM1:0x8002C1B0:17 SSP0_EXT_PULLUP - Blow to indicate external pull-ups implemented for SSP0.
HW_OCOTP_ROM1:0x8002C1B0:16 SD_INCREASE_INIT_SEQ_TIME - Blow to increase the SD card initialization se-

quence time from 1 ms (default) to 4 ms.
HW_OCOTP_ROM1:0x8002C1B0:15 SD_INIT_SEQ_2_ENABLE - Blow to enable the second initialization sequence for

SD boot.
HW_OCOTP_ROM1:0x8002C1B0:14 SD_CMD0_DISABLE - Cmd0 (reset cmd) is called by default to reset the SD card
during startup. Blow this bit to not to reset the card during SD boot.
HW_OCOTP_ROM1:0x8002C1B0:13 SD_INIT_SEQ_1_DISABLE - Blow to disable the first initialization sequence for

SD.

eFuse
eFuse Function
Bank:Address:Bit
HW_OCOTP_ROM1:0x8002C1B0:11:8 BOOT_SEARCH_COUNT - Number of 64-page blocks skipped by the NAND driver

when searching for information saved into the NAND (see NAND Boot Mode for
details). Default value of 0 means 4 blocks to skip.
HW_OCOTP_ROM1:0x8002C1B0:7:4 BOOT_SEARCH_STRIDE - the value of these bits is multiplied by 64 to get boot

search stride. The default is 1 boot search stride, that is, 64 pages.
HW_OCOTP_ROM1:0x8002C1B0:2:0 NUMBER_OF_NANDS - Indicates the number of external NANDs. A 0 value means

that the NAND driver will scan the chip selects to dynamically find the correct
number of NANDs.
Table 12-5. USB-Related Bits

eFuse
eFuse Function
Bank:Address:Bit
HW_OCOTP_ROM2:0x8002C1C0:31:16 USB_VID—Vendor ID used in recovery mode. If the field is 0, Freescale vendor

ID is used.
HW_OCOTP_ROM2:0x8002C1C0:15:0 USB_PID—Product ID used in recovery mode.
Table 12-6. eMMC Fast Boot-Related Bits

eFuse
eFuse Function
Bank:Address:Bit
HW_OCOTP_ROM3:0x8002C1D0:11 FAST_BOOT_ACK—Enable the fast boot acknowledge.
HW_OCOTP_ROM3:0x8002C1D0:10 ALT_FAST_BOOT—Enable the alternative fast boot mode.
Table 12-7. NAND Access-Related Bits

Bank:Address:Bit
HW_OCOTP_ROM4:0x8002C1E0:31 NAND_BADBLOCK_MARKER_RESERVE
If this bit is blown, the factory bad block marker preservation will be disabled.
HW_OCOTP_ROM4:0x8002C1E0:23:16 NAND_READ_CMD_CODE2
NAND Flash read command confirm code.
HW_OCOTP_ROM4:0x8002C1E0:15:8 NAND_READ_CMD_CODE1
NAND Flash read command setup code.
HW_OCOTP_ROM4:0x8002C1E0:7:4 NAND_COLUMN_ADDRESS_BYTES
NAND Flash column address cycles.


Bank:Address:Bit
HW_OCOTP_ROM4:0x8002C1E0:3:0 NAND_ROW_ADDRESS_BYTES
NAND Flash row address cycles.
Table 12-8. General ROM Bit in ROM7 OCOTP Bank

Bank:Address:Bit
HW_OCOTP_ROM7:0x8002C210:23 Reserved
HW_OCOTP_ROM7:0x8002C210:22 ARM_PLL_DISABLE
PLL is enabled by default, the ARM clock will run at 240 MHz. If blown, the PLL
will be disabled and ROM will run at 24 MHz during the boot except for USB mode.
HW_OCOTP_ROM7:0x8002C210:21:20 HAB_CONFIG
00 = Reserved
01 = HAB_OPEN, default mode
Other = HAB_CLOSED
HW_OCOTP_ROM7:0x8002C210:19:12 Reserved
HW_OCOTP_ROM7:0x8002C210:8 ENABLE_SSP_12MA_DRIVE
Blow to force SSP pins to drive 12 mA, default is 4 mA.
HW_OCOTP_ROM7:0x8002C210:7:4 Reserved.
HW_OCOTP_ROM7:0x8002C210:3 I2C_USE_400 KHZ

2
Blow to force the I C to be programmed by the boot loader to run at 400 KHz. 100
KHz is the default.
HW_OCOTP_ROM7:0x8002C210:2 ENABLE_ARM_ICACHE
Blow to enable the ARM 926 ICache during boot.
HW_OCOTP_ROM7:0x8002C210:1 MMU_DISABLE
0 =MMU and D-Cache are enabled in default to speed up HAB functions execution
speed.
1 =MMU and D-Cache are disabled during boot if blown.
HW_OCOTP_ROM7:0x8002C210:0 ENABLE_PIN_BOOT_CHECK
Blow to enable boot loader to first test the LCD_RS pin to determine if the pin boot
mode is enabled. If this bit is blown and LCD_RS is pulled high, then boot mode
is determined by the state of LCD_D[5:0] pins. If this bit is not blown, skip testing
the LCD_RS pin and go directly to determine the boot mode by reading the state
of LCD_D[5:0].

The following bits are used to store super root key hash value, which will be used by the
ROM HAB (high assurance boot) library to check the boot image has the correct super root
key. The SRK hash value will be read by the ARM CPU, so those registers are shadowed
and can also be locked. If HAB is not used, these fuses can be used for other purposes.
Table 12-9. Super Root Key Hash Bits
eFuse
eFuse Function
Bank:Add:Bit
HW_OCOTP_SRK0: 0x8002C220:31:0 Super Root Key hash value bits 255-254
12.3.2 Persistent Bits

Persistent bits are used to control certain features in ROM, as shown in Table 12-10. For
more information on persistent bits, see RTC Overview.
Table 12-10. Persistent Bits
Persistent Bit Function
HW_RTC_PERSISTENT1:0x8005C070:3 SD_SPEED_ENABLE—If this bit is set, ROM puts the SD/MMC card in
high-speed mode.
HW_RTC_PERSISTENT1:0x8005C070:2 NAND_SDK_BLOCK_REWRITE—The NAND driver sets this bit to indicate

to the SDK that the boot image has ECC errors that reached the warning
threshold. The SDK regenerates the firmware by copying it from the backup
image. The SDK clears this bit.
HW_RTC_PERSISTENT1:0x8005C070:1 ROM_SECONDARY_BOOT—When this bit is set, ROM attempts to boot

from the secondary image if the boot driver supports it. This bit is set by the
ROM boot driver and cleared by the SDK after repair.
HW_RTC_PERSISTENT1:0x8005C070:0 FORCE_RECOVERY—When this bit is set, the ROM code forces the system
to boot in recovery mode, regardless of the selected mode. The ROM clears
the bit.

Memory Map
12.4 Memory Map

The illustration below shows the memory map of the boot loader.
ROM boot code resides in the top 128 K address space. The boot code uses the top 16 K
of OCRAM for MMU first level page table. The lowest 60 K of OCRAM is used for loading
application data. The 42 KB of OCRAM region called "ROM Data" is used for data by
ROM code.
If a system uses external memory, then a boot image may be created which first loads a
small SDRAM initialization program into OCRAM. The program will set up the SDRAM,
and then the rest of the boot image may continue to load, overwriting the initialization
program in OCRAM.
0xFFFF_FFFF 0x0001_FFFF
First Level Page
Table (16kB)
0x0001_C000
RESERVED (6kB) 0x0001_BFFF

0x0001_A800
0x0001_A7FF
ROM Data
(42kB)
0x0001_0000
Vector table 0x0000_FFFF
Boot ROM Code @0xFFFF_0000 RESERVED(4kB)
0x0000_F000
0x0000_EFFF
Application Load Region

(60kB)
0xFFFE_0000 0x0000_0000
OCROM OCRAM
Figure 12-1. i.MX28 ROM Code Memory Map
12.5 General Boot Procedure

During ROM startup, the boot mode is sampled by boot pins, and then the ROM loader will
take control. The ROM loader first calls an initialization function for the selected boot
driver, which initializes the hardware port and external device corresponding to the boot
mode. After that, the loader requests for the stream of boot image data from the driver. The
boot image contains a stream of boot commands, such as LOAD, LOAD DCD, SKIP, HAB
JUMP and HAB CALL commands. The loader implemented in ROM code will interpret

these commands and load the boot image into memory and execute HAB JUMP or HAB
CALL command. In the case of HAB JUMP, the ROM will pass control to the boot image
and will leave the ROM context.
Boot images can be encrypted and customers have full control over the encryption keys
through the CRYPTO_KEY OTP fuse bits. Encryption can be turned on/off by
ENABLE_UNENCRYPTED_BOOT fuse (boot unencrypted image if the fuse is blown).
Also, the HAB_CONFIG fuse (01’b for HAB_OPEN and 10'b and 11'b for HAB_CLOSED)
control the type of HAB security type. If HAB_CONFIG is programmed as HAB_CLOSED,
the boot image will not be executed unless the HAB authenticates the boot image. If
HAB_CONFIG is programmed as HAB_Open , the boot image will be executed even if
the HAB authentication fails. The Open configuration is used for non-secure products or
for development purposes on secure products. Customers have the control over the HAB
super root key hash through HW_OTP_SRK fuses, which will be used to compare the DCP
SHA-256 generated super root key (public key) hash from the boot image.
To accelerate the boot process, the MMU/d-cache is enabled during the time consuming
HAB authentication process (RSA). This feature can be turned off by blowing the
MMU_DISABLE fuse. For the same purpose of speeding boot, the ARM clock has been
boosted from 24 MHz to 240 MHz. The feature could be disabled by blowing the
ARM_PLL_DISABLE fuse. The i-Cache can be turned on by blowing the
ENABLE_ARM_ICACHE fuse.
12.6 Program Image

This section describes the data structures that are required to be included in a user’s Program
Image. A Program Image consists of:
• Image Vector Table - a list of pointers that the ROM examines to determine where
other components of the program image are located.
• Boot Data: This field is not used on i.MX28
• Device Configuration Data: IC configuration data
• User Code and Data
Additional data is required if the High Assurance Boot (HAB) feature of the ROM is used.
In this case, additional HAB Command Sequence File (CSF) data is also required. See High
Assurance Boot (HAB) for additional details.

Program Image
12.6.1 Image Vector Table (IVT)

The IVT is the data structure that the ROM reads from the boot device supplying the program
image containing the required data components to perform a successful boot. The IVT
includes the program image entry point, a pointer to Device Configuration Data (DCD) and
other pointers used by the ROM during the boot process. The ROM locates the IVT at a
fixed address that is determined based on the boot device connected to i.MX28. The IVT
offset from the base address and initial load region size for each boot device type is defined
in the following table. The location of the IVT is the only fixed requirement by the ROM.
The remainder or the image memory map is flexible and is determined by the contents of
the IVT.
NOTE
On i.MX28 the IVT must not be placed at offset 0x00000000.
The ROM will interpret this as a NULL pointer and reject the
location of the IVT as invalid.
NOTE
The i.MX28 ROM does not make use of the DCD or boot data
fields of the IVT. These fields must be set to NULL.
Boot Device Memory Destination Device Memory
Boot Device
Base Address
header header
Image Vector Table
Image Vector Table
entry entry
reserved1 reserved1
dcd dcd
boot data boot data
self self
csf csf
NULL
NULL
reserved2 reserved2
CSF CSF
DCD DCD
Program Image Program Image

12.6.1.1 Image Vector Table Structure

The IVT has the following format where each entry is a 32 bit word:
Table 12-11. IVT Format
header
entry
reserved1
dcd
boot data
self
csf
reserved2
• header: The IVT header has the following format:

Table 12-12. IVT Header Format
ga T hL
e
n
g
t Ve-r
o
sin
where:
• Tag: A single byte field set to 0xD1
• Length: a two byte field in big endian format containing the overall length of the
IVT, in bytes, including the header. (the length is fixed and must have a value of
32 bytes)
• Version: A single byte field set to 0x40
• entry: Absolute address of the first instruction to execute from the image.
• reserved1: Reserved and should be zero.
• dcd: Absolute address of the image DCD. The DCD is optional so this field may be set
to NULL if no DCD is required. See Device Configuration Data (DCD) for further
details on DCD.
• boot data: Absolute address of the Boot Data. For i.MX28 this field should be zero.
• self: Absolute address of the IVT. Used internally by the ROM.
• csf: Absolute address of Command Sequence File (CSF) used by the HAB library. See
High Assurance Boot (HAB) for details on secure boot using HAB. This field must be
set to NULL when not performing a secure boot when HAB is enabled.
• reserved2: Reserved and should be zero.

Program Image
12.6.2 Device Configuration Data (DCD)

Upon reset the i.MX28 uses the default register values for all peripherals in the system. The
i.MX50 ROM changes some of these defaults such as clock frequencies for boot purposes.
However, these settings typically are not ideal for achieving optimal system performance
and there are even some peripherals that must configured before they can be used. The DCD
is configuration information contained in a Program Image, external to the ROM, that the
ROM interprets to configure various peripherals on i.MX28. Some components such as
SDRAM require some sequence of register programming as part of configuration before it
is ready to be used. The DCD feature can be used to program the EIM registers and
DATABAHN SDRAM control registers to the optimal settings.
NOTE
The i.MX28 ROM does not use the Image Vector Table (IVT) to
locate the DCD. Instead, the i.MX28 ROM uses the Load DCD
command. See ROM Commands for details on the Load DCD
ROM command.
The DCD table shown in below is a big endian byte array of the allowable DCD commands.
The maximum size of the DCD limited by the ROM to 1768 bytes.
Table 12-13. DCD Data Format
Header
[CMD]
[CMD]
...
The DCD header is 4 bytes with the following format:

Table 12-14. DCD Header
Tag Length Version
where:
• Tag: A single byte field set to 0xD2
• Length: a two byte field in big endian format containing the overall length of the DCD,
in bytes, including the header.
• Version: A single byte field set to 0x40
Below is an example DCD for i.MX28. Note that this example is not a complete DCD and
is shown here to illustrate how a DCD is structured.

// Multi Write Data Command

//
// Creates Write Data Command header which performs writes to multiple taget
// addresses
//
// inputs: flags - DCD command flags
// bytes - size of write by command (1, 2, or 4)
// number - number of writes performed by the DCD write data command
#define MULTI_WRT_DAT(flags, bytes, number) \
HDR(HAB_CMD_WRT_DAT, (number * 2 + 1) * 4, WRT_DAT_PAR((flags), (bytes)))
// DCD Table definition

uint8_t input_dcd[] = {
/* DCD header */
DCD_HDR(HDR_BYTES + 26 * WRT_DAT_BYTES + (63 * 2 + 1) * 4, HAB_VER(4,0)),
//void POWER_Init(void) just pick one register since no impact on RTL

// HW_POWER_LOOPCTRL.B.EN_RCSCALE = 3;
WRT_DAT(0, HAB_DATA_WIDTH_WORD, 0x800440b4, 0x00003000),
// PLL already turn on by ROM

// HW_CLKCTRL_FRAC0_CLR(BM_CLKCTRL_FRAC0_CLKGATEEMI);
// Turn on fractional clock control 0 EMI clkgate,
// setmem /32 0x800401b8=0x00008000
WRT_DAT(0, HAB_DATA_WIDTH_WORD, 0x800401b8, 0x00008000),
// Set up the EMI clock

// case EMI_CLK_150MHz:
// use_xtal_src = 0;
// new_pll_frac_div = 29;
// new_pll_int_div = 2;
// Write the PLL fractional divider W_CLKCTRL_FRAC0_WR(frac_val);
// Clear the EMI frac first
WRT_DAT(0, HAB_DATA_WIDTH_WORD, 0x800401b8, 0x00003F00),
// write new_pll_frac_div
WRT_DAT(0, HAB_DATA_WIDTH_WORD, 0x800401b4, 29 << 8),
.
.
.
// init_dram_regs(); // Write the Databahn SDRAM setup register values

// use mobile_ddr_mt46h32m16lf_5_150MHz_for_dcd.c -- for 150MHz mDDR, 63 entries
MULTI_WRT_DAT(0, HAB_DATA_WIDTH_WORD, 63),
// DRAM_REG[0] = 0x00000000;
EXPAND_UINT32(0x800e0000 + 0 * 4), EXPAND_UINT32(0x00000000),
.
.
.
// DRAM_REG[177] = 0x01030101;
//000_00001 tccd(RW) 0000_0011 trp_ab(RW)
//0000_0001 cksrx(RW) 0000_0001 cksre(RW)
// DRAM_REG[178] = 0x01001901;
//0_0100001 axi5_bdw(RW) 0_0000000 axi4_current_bdw(RD)
//0_0100001 axi4_bdw(RW) 000_00001 tckesr(RW)
// DRAM_REG[181] = 0x00320032;
//0_000000000110010 mr0_data_1(RW) 0_000000000110010 mr0_data_0(RW)

Program Image

// DRAM_REG[183] = 0x00000000;
//0_000000000000000 mr1_data_1(RW) 0_000000000000000 mr1_data_0(RW)
// DRAM_REG[189] = 0xffffffff;
EXPAND_UINT32(0x800e0000 + 189 * 4), EXPAND_UINT32(0xffffffff),
// HW_DRAM_CTL17.B.SREFRESH = 0;
WRT_DAT(0, HAB_DATA_WIDTH_WORD, 0x800e0044, 0x00000000),
// HW_DRAM_CTL16_SET(0x00000001); //set "start"
WRT_DAT(0, HAB_DATA_WIDTH_WORD, 0x800e0040, 0x00000001),
// temp = HW_DRAM_CTL58_RD(); //Wait for EMI initialization completed

// while ( (temp & 0x00100000) != 0x00100000 ){
// temp = HW_DRAM_CTL58_RD();
CHK_DAT_FOREVER(HAB_CMD_CHK_DAT_SET, HAB_DATA_WIDTH_WORD, 0x800e00e8, 0x00100000),
// Now try to write something to ddr addresses 0x40200000 and 0x40200400

WRT_DAT(0, HAB_DATA_WIDTH_WORD, 0x40200000, 0xAAAAAAAA),
WRT_DAT(0, HAB_DATA_WIDTH_WORD, 0x40200400, 0x12345678),
// Verify above two writes to ddr addresses

CHK_DAT_FOREVER(HAB_CMD_CHK_DAT_SET, HAB_DATA_WIDTH_WORD, 0x40200000, 0xAAAAAAAA),
CHK_DAT_FOREVER(HAB_CMD_CHK_DAT_SET, HAB_DATA_WIDTH_WORD, 0x40200400, 0x12345678),
};
12.6.2.1 Write Data Command

The Write Data Command is used to write a list of given 1, 2 or 4-byte values or bitmasks
to a corresponding list of target addresses. The format of Write Data Command, again a big
endian byte array, is shown in the Write Data Command table below.
Table 12-15. Write Data Command Format
Tag Length Parameter
Address
Value/Mask
[Address]
[Value/Mask]
...
[Address]
[Value/Mask]
where:
• Tag: A single byte field set to 0xCC
• Length:
A two byte field in big endian format containing the length of the Write Data Command,
• Address: Target address to which the data should be written
• Value/Mask: Data value or bit mask to be written to the preceding address

The Parameter field is a single byte divided into bit fields as follows:
Table 12-16. Write Data Command Parameter Field
7 6 5 4 3 2 1 0
flags bytes
where:
• bytes: width of target location(s) in bytes. Either 1, 2 or 4.
• flags: control flags for command behavior.
One or more target address and value/bitmask pairs can be specified. The same bytes and
flags parameters apply to all locations in the command.
When successful, this command writes to each target address in accordance with the flags
as follows:
Table 12-17. Interpretation of Write Data Command Flags
"Mask: "Set" Action Interpretation
0 0 *address = val msk Write value
0 1 *address = val_msk Write value
1 0 *address &= ~val_msk Clear bitmask
1 1 *address |= val_msk Set bitmask
Notes:
• If any of the target addresses does not have the same alignment as the data width
indicated in the parameter field, none of the values are written.
• If any of the values is larger or any of the bitmasks is wider than permitted by the data
width indicated in the parameter field, none of the values are written.
• If any of the target addresses do not lie within an allowed region, none of the values
are written. The list of allowable modules and target addresses for i.MX28 are given
below.
Table 12-18. Valid DCD Address Ranges for i.MX28
Address Range Start Address Last Address
DRAM Controller registers 0x800E0000 0x800EFFFF
BCH ECC Accelerator 0x8000A000 0x8000BFFF
GMPI registers 0x8000C000 0x8000DFFF
Synchronous Serial Port 0 registers 0x80010000 0x80011FFF

Program Image
Address Range Start Address Last Address

Pin Control Block registers 0x80018000 0x80019FFF
Digital Control registers 0x8001C000 0x8001DFFF
GPIO Control registers 0x8003C500 0x8003C5FF
Clock Control registers 0x80040000 0x80041FFF
Power Control registers 0x80044000 0x80045FFF
Real Time Clock registers 0x80056000 0x80057FFF
I2C0 registers 0x80058000 0x80059FFF
I2C1 registers 0x8005A000 0x8005BFFF
UART0 registers 0x8006A000 0x80000000
UART1 registers 0x8006C000 0x8006DFFF
UART2 registers 0x8006E000 0x8006FFFF
UART3 registers 0x80070000 0x80071FFF
UART4 registers 0x80072000 0x80073FFF
UARTDBG registers 0x80074000 0x80075FFF
External memory 0x40000000 0x5FFFFFFF
OCRAM free space 0x00000000 0x0000E3FF
12.6.2.2 Check Data Command

The Check Data Command is used to test for a given 1, 2 or 4-byte bit masks from a source
address. The Check Data Command is a big endian byte array with format shown below.
Table 12-19. Check Data Command Format
Tag Length Parameter
Address
[Count]
where:
• Tag: A single byte field set to 0xCF
• Length:
A two byte field in big endian format containing the length of the Check Data Command,
• Address: Source Address to test

• Mask: Bit mask to test

• Count: optional poll count. If count is not specified this command will poll indefinitely
until the exit condition is met. If count = 0, this command behaves as for NOP.
The Parameter field is a single byte divided into bit fields as follows:
Table 12-20. Write Data Command Parameter Field
7 6 5 4 3 2 1 0
flags bytes
where:
• bytes: width of target location in bytes. Either 1, 2 or 4.
• flags: control flags for command behavior.
• Data Mask = bit 3: if set, only specific bits may be overwritten at target address
(otherwise all bits may be overwritten)
• Data Set = bit 4: if set, bits at the target address overwritten with this flag (otherwise
it is ignored)
This command polls the source address until either the exit condition is satisfied, or the poll
count is reached. The exit condition is determined by the flags as follows:
Table 12-21. Interpretation of Check Data Command Flags
"Mask: "Set" Action Interpretation
0 0 (*address & mask) == 0 All bits clear
0 1 (*address & mask) == mask All bits set
1 0 (*address & mask) != mask Any bit clear
1 1 (*address & mask) != 0 Any bit set
Notes:
• If the source address does not have the same alignment as the data width indicated in
the parameter field, the value is not read.
• If the bit mask is wider than permitted by the data width indicated in the parameter
field, the value is not read.
12.6.2.3 NOP Command

This command has no effect. The format of NOP Command is a little endian four byte array
as shown below:

High Assurance Boot (HAB)
Table 12-22. NOP Command Format

Tag Length Undefined
where:
• Tag: A single byte field set to 0xC0
• Length: A two byte field containing the length of the NOP Command in bytes. Fixed
to a value of 4.
• Undefined: This byte is ignored and can be set to any value.
12.7 High Assurance Boot (HAB)

The High Assurance Boot (HAB) component of the ROM protects against the potential
threat of attackers modifying areas of code or data in programmable memory to make it
behave in an incorrect manner. The HAB also prevents attempts to gain access to features
which should not be available. The integration of the HAB feature with the ROM code
ensures that i.MX28 does not enter an operational state if the existing hardware security
modules have detected a condition that may be a security compromise or areas of memory
deemed to be important have been modified. The HAB uses RSA digital signatures to
enforce these policies. Note that the HAB feature is independent of the encrypted boot
feature. The HAB checks the authenticity of a Progam Image using a public key infrastructure
whereas the encrypted boot feature provides confidentiality.
Boot
Device
Security Hardware
HAB Library
Boot ROM
(DCP)
ARM 926
Processor Core
RAM
The figure above illustrates the components used during a secure boot using HAB. The
HAB makes use of the DCP2 hardware module to accelerate SHA-256 message digest
operations performed during signature verifications. The HAB also includes a software
implementation of SHA-256 for cases where a hardware accelerator cannot be used. The
core RSA signature verification operations are performed by a software implementation
contained in the HAB library. The main features supported by HAB are:

• X.509 pulic key certificate support

• CMS signature format support
For further details on making use of the High Assurance Boot feature of i.MX28, please
contact your local Freescale representative.
12.7.1 ROM Vector Table Addresses

For devices that are performing a secure boot using HAB, the HAB library may be called
from additional boot stages that execute after ROM code. The RVT table contains the
pointers to the HAB API functions such that these boot stage can authenticate the stage that
follows. The RVT is fixed in ROM and is located at 0xFFFF8508.
For additional information on using HAB on i.MX28, including the HAB API, please contact
your local Freescale representative.
12.8 Constructing Boot Image (SB Files) to Be Loaded by ROM

Boot images are created by the Freescale supplied elftosb application, which handles both
encryption and HAB signature if required. Freescale provides a sample code signing tool.
It can be used for reference purposes in integrating with third-party tools or a proprietary
signing infrastructure.
Preparing a bootable image for all boot modes includes the following high-level steps:
1. Prepare the unsigned Image ELF file for the firmware that is to be booted by the ROM.
2. Sign the image with the code signing tool, which generates one HAB.ELF file (Freescale
provides example tools, and third party code signing tools may also be available. Contact
your local Freescale representative for further details). This file contains the CSF (HAB
command sequence file) and certificates.
3. Use the elftosb tool to combine the unsigned Image ELF and HAB.ELF together and
convert them to a boot stream (SB file), which the ROM loader will understand. The
elftosb tool also handles encryption if an encryption key is provided.
The following figures shows the process of creating a boot loader image from ELF files by
elftosb. A key set must be input to the elftosb program to properly encrypt and authenticate
the image.

Constructing Boot Image (SB Files) to Be Loaded by ROM
Figure 12-2. i.MX28 Boot Image Generation
C and
ASM
LIBs
LIBs
Tools (GHS or GNU)
ELF
elftosb
Image
Load
(SB)
Figure 12-3. i.MX28 Boot Image Build Process
12.8.1 ROM Commands

The i.MX28 ROM boots from an image residing on an external boot device using a number
of built in commands. These commands are used by the ROM to establish the boot image
including the Image Vector Table (IVT). The ElftoSB tool provided by Freescale converts
a typical image file in ELF format to the Freescale SB format consisting of the following
commands:
LOAD DCD Command

LOAD DCD is an extension from LOAD command by adding an additional flag. When the
DCD flag is set, ROM runs DCD to configure the external memory. The ROM command
is 16 bytes in length. The following table shows the field description. Bold indicates the
changes.
Table 12-23. LOAD DCD Command Field Descriptions
Field Description
m_checksum Simple checksum of other fields of boot_command_t.
m_tag 0x02 or ROM_LOAD_CMD.
m_flags Normal load 0x0000, DCD load 0x0001.
m_address Memory address to which data is stored.
m_count Number of bytes to load. This is also the number of valid bytes in the data cipher blocks following this command.
m_data CRC-32 over the data to be loaded.
0 1 2
ROM_LOAD_CMD data data
padding
m_count = 18
Figure 12-4. LOAD DCD Command
HAB Jump Command

The HAB Jump command is overload from Jump command by adding an additional flag.
When the HAB flag is set, ROM calls the HAB4 Authenticate image function with IVT as
argument. The authenticate image function returns the image entry, and then ROM performs
a real jump to that address. The following table shows the HAB Jump command fields.
Bold indicates the changes. For i.MX28, JUMP without HAB is no longer valid hence HAB
flag should always be set.
Table 12-24. HAB Jump Command Field Descriptions
Field Description
m_tag 0x04 or ROM_JUMP_CMD.
m_flags HAB jump 0x0001. HAB flag should always be set for i.MX28.
m_address Address of the IVT pointer for HAB jump.
m_count 0
m_data Argument to pass to the entry point in R0.
HAB Call Command

I2C Boot Mode
The HAB Call command is overload from Call command by adding an additional flag.
When the HAB flag is set, ROM calls the HAB4 authenticate image function with IVT as
an argument. The authenticate image function returns the image entry, and then ROM
performs a real call to that address. Bold indicates the changes. For i.MX28,CALL without
HAB is no longer valid hence HAB flag should always be set.
Table 12-25. HAB Call Command Field Descriptions
Field Description
m_tag 0x05 or ROM_CALL_CMD.
m_flags HAB call 0x0001. HAB flag should always be set for i.MX28.
m_address Address of the IVT pointer for HAB call.
m_count 0
m_data Argument to pass to the function in R0.
2
12.9 I C Boot Mode
EEPROMs must have the slave address 0xA0 (that is, 1010000R, where R indicates a read
if 1 and a write if 0). Also, the EEPROM must have exactly a two-byte subaddress.
Boot images must start at address 0x0 of the EEPROM and cannot exceed 64 Kbytes in
size. The I2C port is set to run at 100 KHz by default. The clock is increased to 400 KHz
if I2C_USE_400 KHz is blown.
12.10 SPI Boot Mode

SPI memories are either EEPROMs or NORs.
By default, the SPI serial clock is set to 1 MHz for EEPROMs and 12 MHz for NORs. The
SSP_SCK_INDEX OTP 4 bits are used to change the SPI serial clock from defaults. These
bits serve as the index for the SSP HAL clock rate array (see SSP for details on the clock
rate array).
The defaults may also be changed by using the ConfigBlock.Clocks field. If
ConfigBlock.Clocks.SspClockConfig is non-zero, then that struct will be used to change
the SPI SCK rate and will override the SSP_SCK_INDEX OTP setting.
This driver supports only 2-byte addresses for EEPROMs and 3-byte addresses for NORs.

SSP2 and SSP3 are used for SPI boot mode.
12.10.1 SSP Pin Configuration

SSP boot mode supports the standard package and the small package of i.MX28.
Table 12-26. SSP Ports Pin-Mux Configuration
SSP SSP0 SSP1 SSP2 SSP3 SSP3
Pins
(standard package) (small package)
SCK SSP0_CLK GPMI_WRN SSP2_SCK SSP3_SCK GPMI_RDN
DETECT SSP0_DETECT GPMI_RDY0 — — —
CMD SSP0_CMD GPMI_RDY1 SSP2_MOSI SSP3_MOSI GPMI_RESETN
DATA7 SSP0_DATA7 GPMI_D07 — — —
DATA3 SSP0_DATA3 GPMI_D03 SSP2_S30 SSP3_S30 GPMI_CE1N
DATA0 SSP0_DATA0 GPMI_D00 SSP2_MISO SSP3_MISO GPMI_CE0N
12.10.2 Media Format

The media is arbitrarily partitioned into 128-byte sectors. An optional configuration block
may reside on the media at byte address 0. This block has the following format:
//! \brief Spi media configuration block structs

typedef struct _spi_ConfigBlockFlags
{
uint32_t DisableFastRead:1; // Ignored for Spis
// 0 - Do not disable fast reads
// 1 - Disable fast reads
} spi_ConfigBlockFlags_t;
typedef struct _spi_ConfigBlockClocks
{
uint32_t SizeOfSspClockConfig; // sizeof(ssp_ClockConfig_t)
ssp_ClockConfig_t SspClockConfig; // SSP clock configuration structure. A null
// structure indicates no clock change.
} spi_ConfigBlockClocks_t;
typedef struct _spi_ConfigBlock // Little Endian
{

SPI Boot Mode
uint32_t Signature; // 0x4D454D53, or "SMEM"

uint32_t BootStartAddr; // Start address of boot image. Must be >=
// sizeof(spi_ConfigBlock_t)
uint32_t SectorSize; // Sector size in bytes. Overrides ROM default
// of 128-bytes. Max is 1024-bytes. 0 is
// default 128-bytes.
spi_ConfigBlockFlags_t Flags; // Various flags. See spi_ConfigBlockFlags
spi_ConfigBlockClocks_t Clocks; // SCK clock update structure.
} spi_ConfigBlock_t;
If the block is present, then the boot image is found at the address specified by BootStartAddr.
If the block is not present, then it assumes that the boot image resides on the media starting
at byte address 0.
12.10.3 SSP
The SSP2 and SSP3 ports are used for the SPI boot mode.
The following table is used to look up a requested speed. If the speed is not an exact match,
the boot ROM picks the next lowest value. Speed values can range from 1 to 51.4 MHz. A
speed value of 0 is not allowed.
// Lookup Table entry

typedef struct _ssp_clockConfig
{
int clkSel :1; //!< Clock Select (0=io_ref 1=xtal_ref)
int io_frac :6; //!< IO FRAC 18-35 (io_frac+16)
int ssp_frac :9; //!< SSP FRAC (1=default)
int ssp_div :8; //!< Divider: Must be an even value 2-254
int ssp_rate :8; //!< Serial Clock Rate
}
ssp_clockConfig_t;
The table is loaded with the clock rates listed in Table 12-27.
Table 12-27. SCK Clock Standard Values Lookup Table
SCK N/A .24 1 2 4 6 8 10 12 16 20 30 40 48 51.4 X
INDEX 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK_SEL X 1 1 1 1 1 0 0 1 0 0 0 0 0 0
IOFRAC X X X X X X 18 18 X 18 18 18 18 18 21 X
SSP_FRAC X X X X X X 6 6 X 5 6 8 6 5 4 X
SSP_CLK 24 24 24 24 24 80 80 24 96 80 60 80 96 102.8 X
SSP_DIV X 100 24 12 6 4 10 8 2 6 4 2 2 2 2 X
SSP_RATE X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X

12.11 SD/MMC Boot Mode

SD/MMC boot mode supports booting from SD/MMC cards adhering to the following
specifications:
• iNand Product Manual, Version 2.1
• SD Specifications, Part 1, Physical Layer Specification, Version 1.10
• SD Specifications, Part 1, Physical Layer Specifications, Version 2.0 Draft
• SD Specifications, Part 1, eSD (Embedded SD Specifications), Version 2.10 Draft Rev
• MultiMediaCard System Specification, Version 4.1
Note, however, that this mode does not support dynamic insertion removal, so the systems
will typically not include removable cards.
The following modes are supported:
• SD/MMC on SSP0
• SD/MMC on SSP1
The SD_POWER_GATE_GPIO eFuse bits indicate which GPIO pin to use for controlling
an external power gate for the connected device.
SD_POWER_GATE_GPIO Gate GPIO
00b PWM3
01b PWM4
10b LCD DOTCK
11b NONE

SD/MMC Boot Mode
If a gate GPIO is used, then the driver will use the SD_POWER_UP_DELAY eFuse to
determine the amount of time, in 10-ms increments, to wait until starting the 1-ms
initialization sequence. This eFuse field is 6-bits wide, providing from 10–600 ms of delay.
If the field is 000000b, then the delay is a default 20 ms. If no gate GPIO is specified in
SD_POWER_GATE_GPIO, then the delay is skipped.
The SSP ports on the i.MX28 top out at 51.4 MHz with 20–40 pF loading. By default, the
serial clock is set to 12 MHz. If the SD_SPEED_ENABLE persistent bit is set, then the
driver will use a maximum speed based on the results of device identification and limited
by choices available in the SSP clock index.
For eMMC fast boot mode, serial clock is just decided by SSP_SCK_INDEX OTP bits. If
SSP_SCK_INDEX is not burned, that is invalid clock index, then ROM chooses the default
clock (12 MHz).
This mode supports the 1-bit, 4-bit, and 8-bit data MMC/SD buses. The SD_BUS_WIDTH
efuse bits selects how many bus pins are physically available for the SSP port. Bus width
will be limited based on these bits, as well as the bus width capabilities indicated by the
connected device.
SD_BUS_WIDTH Width
00b 4-bit
01b 1-bit
10b 8-bit
11b Reserved
The eFuse ROM0:23:22 defines one of four possible media formats, as shown in the
following table.
Table 12-28. Media Formats
SD_MMC_MODE Media Format
00b MBR_MEDIA_FORMAT
01b RESERVED
10b eMMC_FASTBOOT_MEDIA_FORMAT
11b eSD_FASTBOOT_MEDIA_FORMAT

12.11.1 Boot Control Block (BCB) Data Structure

The design of BCB is to allow multiple copies of firmware to be stored on media each
identified by its unique tag. The tags can be defined either by the user or the firmware
download application. The ROM is only interested in user-defined primary and secondary
boot tags. The ROM loads primary firmware, if ROM_REDUNDANT_BOOT persistent
bit is not set; otherwise it loads a secondary image, providing support for a redundant boot.
The config block has the following format:
typedef struct _DriveInfo_t

{
uint32_t u32ChipNum; //!< Chip Select, ROM does not use it
uint32_t u32DriveType; //!< Always system drive, ROM does not use it
uint32_t u32Tag; //!< Drive Tag
uint32_t u32FirstSectorNumber; //!< Start sector/block address of firmware.
uint32_t u32SectorCount; //!< Not used by ROM
} DriveInfo_t;
typedef struct _ConfigBlock_t

{
uint32_t u32Signature; //!< Signature 0x00112233
uint32_t u32PrimaryBootTag; //!< Primary boot drive identified by this tag
uint32_t u32SecondaryBootTag; //!< Secondary boot drive identified by this tag
uint32_t u32NumCopies; //!< Num elements in aFWSizeLoc array
DriveInfo_t aDriveInfo[]; //!< Let array aDriveInfo be last in this data
//!< structure to be able to add more drives in future
//!< without changing ROM code

} ConfigBlock_t;
The driver first verifies the signature and version, then searches all NumRegions for the
appropriate tag. The following table shows the expected values for these parameters.
Table 12-29. Media Config Block Parameters
Field Value
Signature 0x00112233
u32PrimaryBootTag User-defined primary boot firmware tag
u32SecondaryBootTag User- defined secondary boot tag
u32NumCopies Number of firmware copies present in array aDriveInfo

Each element in array describes the tag and start address
aDriveInfo
for the image

SD/MMC Boot Mode
12.11.2 Master Boot Record (MBR) Media Format

If the eFuse media format mode is MBR_MEDIA_FORMAT, then ROM expects a valid
master boot record (MBR) to be present on the first block of media. The MBR is identified
by its signature located at offset 0x1FE of the first sector. The partition table is stored at
address 0x1BE. The Freescale firmware partition is identified by MBR_SIGMATEL_ID
at an offset 0x04 from partition table. The firmware partition’s start block address is located
at offset 0x08 of firmware partition entry of partition table.
Field Value
MBR Signature 0x55AA
MBR_SIGMATEL_ID 'S'
The first block of firmware partition contains BCB, allowing multiple copies of firmware
to reside inside firmware partition and to support redundant boot feature of ROM. Refer to
Boot Control Block (BCB) Data Structure for a detailed view of BCB data structure and its
use. All firmware copies specified in BCB should be located inside the firmware partition.
12.11.3 eMMC Fast Boot Media Format

This section describes the behavior of ROM when the eFuse state of SD_MMC_MODE is
0x10 (eMMC_FASTBOOT_MEDIA_FORMAT). The eMMC4.3 and eMMC4.4 fast boot
modes are supported. By default, primary fast boot mode, pull down CMD line after eMMC
card power up, is enabled. The ALT_FAST_BOOT OTP bit enables the alternative fast
boot mode, which sends CMD0 with an argument 0xFFFF_FFFA after power up.
The boot image for eMMC fast boot does not contain a MBR block or a configuration block.
It is the user’s responsibility to program the EXT_CSD register when loading the boot image
into an eMMC card.
The bytes in EXT_CSD register have to be read or programmed to include the following:
• [228] BOOT_INFO
• [226] BOOT_SIZE_MULT
• [179] BOOT_CONFIG(eMMC4.3) PARTITION_CONFIG(eMMC4.4)
• [177] BOOT_BUS_WIDTH
The ALT_FAST_BOOT, FAST_BOOT_ACK, EMMC_USE_DDR and SD_BUS_WIDTH
OTP bits must be consistent with the setting in EXT_CSD register.

12.11.4 eSD Fast Boot Media Format

The ROM supports eSD by following the same flow as SD 2.0, except that ROM selects
the physical partition 1(boot code area) by sending CMD43. The CMD43 is reserved
command in SD2.0. Therefore, for eSD boot mode, boot image has to be located in partition
1.
If eSD fast boot mode is enabled, the FAST_BOOT bit in the argument of ACMD41 is set.
The eSD device partition 1 should be defined as a fast boot physical partition. Otherwise,
the device still initializes the entire media and not a partial initialization.
The ROM expects the BCB data structure to be present on the first block of boot partition.
Like the BCB and MBR media formats, the ROM uses the persistent bit
ROM_REDUNDANT_BOOT to decide whether to load primary or secondary boot firmware.
12.11.5 Device Identification

SD/MMC boot mode uses the identification processes specified as follows:
• SD Specifications, Part 1, Physical Layer Specifications, Version 2.0 Draft.
• SD Specifications, Part 1, eSD (Embedded SD) Specification Version 2.10 Draft Rev.
0.91.
• MultiMediaCard System Specification Version 4.2, Version 4.3, Version 4.4.
12.12 NAND Boot Mode

NAND boot mode is used to boot from both raw NAND devices and block abstracted ONFi
BA NAND devices, with error correction capability in the controller.
12.12.1 Raw NAND Device Boot

The ROM relies on the BCH hardware engine for handling error corrections when reading
data from a raw NAND device.
The boot ROM expects the NAND Flash to be partitioned into the following areas:
• Search Area for Firmware Configuration Block (FCB)
• Search Area for Discovered Bad Block Table (DBBT)
• Firmware blocks with primary and secondary boot firmware
The rest of NAND Flash is available for non-boot purposes. FCB and DBBT together are
referred to as boot control blocks, or BCB.
NAND Boot Mode
12.12.1.1 Search Area

The search area is defined by search count times search stride.
12.12.1.2 Search Count

Search count is defined as the number of copies of BCB data structures present in a given
search area. It is 2^efNANDBootSearchCount (a value from OTP/eFuses). The default
search count when OTP is not programmed is 4. This is the most common case. The
minimum search count is 2 and the maximum search count is 32768.
12.12.1.3 Search Stride

Search stride is defined as the distance in pages between two BCB data structures in a given
search area. It is 64 pages times efNANDBootSearchStride (a value from OTP/eFuses).
When efNANDBootSearchStride is not blown, the boot ROM defaults it to 1. Therefore,
the minimum search stride is always 64 pages apart (the most common case), and the
maximum search stride is (64 * 15 = 960) pages apart.
12.12.1.4 Boot Control Blocks (BCB)

There are two BCB data structures: FCB and DBBT. As part of the NAND media
initialization, the ROM driver uses safe NAND timings to search for a Firmware
Configuration Block (FCB) that contains the optimum NAND timings, the page address of
Discovered Bad Block Table (DBBT) Search Area and the start page address of the primary
and secondary firmware.
In i.MX28, there are no separate boot modes for each type of ECC level. The hardware
ECC level to use is embedded inside FCB block. The FCB data structure is itself protected
using software ECC (SEC-DED Hamming Codes). Driver reads raw 2112 bytes of first
sector and runs through software ECC engine that determines whether FCB data is valid or
not.
If the FCB is found, the optimum NAND timings are loaded for further reads. If the ECC
fails, or the fingerprints do not match, the Block Search state machine increments the page
number to Search Stride number of pages to read for the next BCB until 2^n
efNANDBootSearchCount pages have been read.
If search fails to find a valid FCB, the NAND driver responds with an error and the boot
ROM enters into the recovery mode.

The FCB contains the page address of DBBT Search Area, and the page address of primary
and secondary boot images. DBBT is searched in DBBT Search Area just like how FCB is
searched. A flowchart for this process is shown in Figure 12-5. After the FCB is read, the
DBBT is loaded, and the primary or secondary boot image is loaded using the starting page
address from FCB.
START
CurrentPage = 0;
BootSearchStride = (value read from OTP * 64)
BootSearchCount = 2 ^ (value read from OTP)
ReadCount = 0;
Read NAND Page at

address CurrentPage;
ReadCount ++;
CurrentPage = CurrentPage
+ BootSearchStride
YES
ReadCount <
Is Page FCB NO
BootSearchCount
YES NO
FCB Found FCB Not Found
Figure 12-5. Firmware Control Blocks Flowchart

NAND Boot Mode
START
CurrentPage = DBBT Search Area Start Address From FCB;

BootSearchStride = (value read from OTP * 64)
BootSearchCount = 2 ^ (value read from OTP)
ReadCount = 0;
Read NAND Page at

address CurrentPage;
ReadCount ++;
CurrentPage = CurrentPage
+ BootSearchStride
YES
ReadCount <
Is Page DBBT NO
BootSearchCount
YES NO
DBBT Found DBBT Not Found
Figure 12-6. DBBT Search Process Flowchart
The BCB search and the load function also monitors the ECC correction threshold and sets
the NAND_SDK_BLOCK_REWRITE persistent bit if the threshold exceeds the max ecc
correction ability. One bit is used for all boot block images. If the
NAND_SDK_BLOCK_REWRITE bit is set, the ROM continues loading the image, but
the SDK needs to refresh the boot blocks at a later time.
12.12.1.5 Redundant Boot Support in ROM NAND driver

ROM checks the state of ROM_SECONDARY_BOOT persistent bit to decide which
firmware to load, either primary or secondary. If the bit is not set, it will load the primary
image. Otherwise, it will load the secondary image.
If ROM fails to load from primary boot image due to ECC failures, it will set the persistent
bit ROM_SECONDARY_BOOT and soft resets the chip to let ROM come up again and
load from secondary image. The persistent bit will retain its status until power down.
If ROM NAND driver fails to load from primary boot image due to non-ECC failures like
invalid header, and so on, it will return an error code to the ROM loader. The secondary
boot will be initiated by the loader if the driver supports redundant boot. ROM NAND
driver and ROM SD driver are the only two drivers that currently support ROM redundant
boot.
12.12.1.6 NAND Patch Boot using FCB

A secondary mechanism to boot NAND patch image is implemented in i.MX28 ROM. A
flag is used in the FCB data structure which indicates to the ROM to boot the patch binary
image present on the second page of first good block of NAND. If this flag is set, the ROM
does not try to locate other boot blocks, but rather starts loading the patch image.
12.12.1.7 Expected NAND Layout

This section shows several potential expected NAND layouts.
The following figure shows the default layout if no efuses are blown.
FCB Search Area Page 0 Firmware Configuration Block
(FCB)
Page 64
Firmware Configuration Block
(FCB)
Page 128
Firmware Configuration Block
(FCB)
Page 192 Firmware Configuration Block

(FCB)
DBBT Search Area Page 256 Discovered Bad Block Table

(DBBT)
Page 320
Discovered Bad Block Table
(DBBT)
Page 384
(DBBT)
Page 448
(DBBT)
Page 512
Boot Firmware 1
Page 1024
Boot Firmware 2
Figure 12-7. Expected NAND Layout with search count = 4 and search stride = 1*64

NAND Boot Mode
To work with the following layout, efuses need to be blown, efNANDBootSearchCount to

0x1 and efNANDBootSearchStride to 0x2.
(FCB)

(FCB)
DBBT Search Area Page 256 Discovered Bad Block Table

(DBBT)
Page 384 Discovered Bad Block Table

(DBBT)
Page 512
Boot Firmware 1
Page 1024
Boot Firmware 2
Figure 12-8. Expected NAND Layout with search count = 2 and search stride = 2*64
To work with the following layout efuses need to be blown, efNANDBootSearchCount to

0x1 and efNANDBootSearchStride to 0xF.
(FCB)
Page 1
Boot Firmware 1
Page 500
Boot Firmware 2

(FCB)
Figure 12-9. Expected NAND Layout for patch boot with search count = 2 and search stride
= 15*64 and no DBBT
To work with the following layout, efuses need to be blown, efNANDBootSearchCount to

0x1 and efNANDBootSearchStride to 0xF.


(FCB)
Page 1
Boot Firmware 1
Page 500
Boot Firmware 2

(FCB)
Figure 12-10. Expected NAND Layout for patch boot with search count = 2 and search
stride = 15*64 and valid DBBT
12.12.1.8 Firmware Configuration Block

The FCB is the first sector in the first good block. The FCB should be present at each search
stride of the search area. The search area contains copies of the FCB at each stride distance,
so in case the first NAND block becomes corrupted, the ROM will find its copy in the next
NAND block. The search area should span over at least two NAND blocks. The location
information of DBBT search area, FW1 and FW2 are all specified in the FCB. This case is
shown in more detail in Firmware Layout on the NAND.
The layout of the first good page containing FCB is shown in the following figure.
2111
Spare
1036
Parity Bits For FCB Data
524
FCB Data
12
Bytes Left
Figure 12-11. Layout of Boot Page Containing FCB
The FCB is located on the first good page of the NAND; the minimum size of a page is
2112 bytes. The first 12 bytes of an FCB page are reserved and left blank (all zeros); the
next 512 bytes are reserved for FCB data. The remaining 512 bytes are available for software
ECC, and the rest are all zeros. FCB is protected using SEC-DED Hamming codes.

NAND Boot Mode
12.12.1.9 Single Error Correct and Double Error Detect (SEC-DED)

Hamming
For each 8-bit of data in the 512 byte FCB, 5-bit parity is used. Each byte of parity area
contains 5 parity bits (LSB) and 3 unused bits (MSB).
For each 8-bit of FCB data, parity is calculated and compared with the corresponding parity
bits read from the parity area of the FCB page to detect errors and correct any single error.
If there is more than one error, a flag is raised against the block.
To determine a good FCB, all three fingerprints must match and the ECC must not fail.
The data held in the FCB includes the following:
• NAND Timing parameters
• Geometry information (sectors per block, sectors per page, and so on)
• The page address of the discovered bad block table (DBBT)
• BCH ECC type
• A flag to boot the NAND patch image located at sector 2 of first block
• Starting page addresses of primary and secondary firmware
• Bad block marker bit offset in page data
Additionally, the FCB is marked with three fingerprints in the sector.
12.12.1.10 Firmware Layout on the NAND

The boot image is typically located on the first good block after the FCB, DBBT blocks
and any additional blocks reserved for BCBs in case they go bad.
ROM shall support boot from only first NAND. In case of multi-NAND system, both
firmware copies should be located on first NAND, same as in the single-NAND system.
The DBBT will be located in its own search area and a copy of DBBT will be present at
each stride of the search area.
12.12.1.11 Recovery From a Failed Boot Firmware Image Read

The mechanism for recovering from a failed FCB read is covered in Boot Control Blocks
(BCB). The SDK is warned about impending errors with the
NAND_SDK_BLOCK_REWRITE persistent bit and is notified of firmware boot errors
with the ROM_SECONDARY_BOOT persistent bit.

In the case of a warning, the read routine will monitor the ECC threshold and set the
NAND_SDK_BLOCK_REWRITE bit if the threshold is within one symbol of the maximum
correctable number of symbols. The ROM continues to load from the primary boot image.
At a later time, the SDK will refresh the primary boot images by copying and rewriting the
primary boot image blocks.
If an error is discovered while reading the boot firmware image, the NAND driver sets the
ROM_SECONDARY_BOOT persistent bit and resets the device. Booting will proceed the
second time from the secondary boot images. If booting continues uninterrupted, no
unwinding needs to take place at the loader level.
Boot Image Load
Do ReadSector() until image is loaded
Boot Image
N Loaded
Did error occur
during read ?
Boot Complete
Exit
Y
Set ROM_SECONDARY_BOOT
persistent bit
Reset Device
Figure 12-12. Boot Image Recovery
12.12.1.12 Bad Block Handling in the ROM

Bad blocks are not an issue for the FCB, because FCB found from a search. The search for
the DBBT works with a similar mechanism. The search starts where the FCB indicates the
DBBT Search Area should be and progresses until efNANDBootSearchLimit times in the
same fashion as the search described in Boot Control Blocks (BCB).
ROM uses DBBT to skip any bad block that falls within firmware data on NAND Flash
device.
If the address of DBBT Search Area in FCB is 0, ROM will rely on factory marked bad
block markers to find out if a block is good or bad. The location of bad block information
is at the first 3 or last 3 pages in every block of the NAND Flash. NAND manufacturers
normally use one byte in the spare area of certain pages within a block to mark a block to
be good or bad. 0xFF means good block, non FF means bad block.

NAND Boot Mode
In order to preserve the BI (bad block information), flash updater or gang programmer
applications need to swap Bad Block Information (BI) data to byte 0 of metadata area for
every page before programming NAND Flash. ROM when loading firmware, copies back
the value at metadata[0] to BI offset in page data. The following figure shows how the
factory bad block marker is preserved.
Bad block information at
column address 2048
64B
2KB Main area
spare
512 main parity 512 main parity 512 main parity 512 main parity
metadata
Bad block information at 4th
block’s data area
Swap byte
Figure 12-13. Factory Bad Block Marker Preservation
In the FCB structure, there are two elements m_u32BadBlockMarkerByte and

m_u32BadBlockMarkerStartBit to indicate the byte offset and start bit of BI. ROM will
use 8 bits from start bit as BI.
The DBBT structure is contained within a block and is discussed in more detail below. The
figure below depicts the layout of the Discovered Bad Block Table block. The first 8K are
reserved for the DBBT Header. The following pages are used by the DBBT for each NAND.
The Bad Block table for each NAND begins on a 2 KB boundary that coincides with current
NAND page sizes and is a subset of future NAND page sizes. The BBT can extend beyond
2K, which is the purpose of the #2K_num, and translates to the number of 2K pages that
NAND0 through NAND3 require. In this way, the ROM can quickly index to the appropriate
NAND table.
Only the Bad Blocks for NAND0 are required and loaded.

FGR1 #BB_0 #BB_1 #BB_2 #BB_3 #2K_0

#2K_1 #2K_2 #2K_3
8K FGR2 Discovered Bad Block Table Header FGR3
NAND0 #BB BB1 BB2 BB3 BB4

# of 2K
pages BB5 NAND0 Bad Block Table
NAND0
BB511 BB512 BB513
# of 2K
NAND1 BB511 BB512 BB513
# of 2K
NAND2
BB511 BB512 BB513
# of 2K
NAND3
BB511 BB512 BB513
Figure 12-14. DBBT Structure
12.12.1.13 Firmware Configuration Block Structure and Definitions

The FCB structure is as follows:
Table 12-30. Firmware Configuration Block Structure
Name Start Byte Size in bytes Description
m_u32Checksum 0 4 32 bit checksum of 508 bytes of FCB data from

offset 4 to 512 XOR with 0xFFFFFFFF.
m_u32FingerPrint 4 4 32 bit word with a value of 0x20424346, in ascii

“FCB ”.
m_u32Version 8 4 32 bit version number; this version of FCB is

0x01000000.
m_NANDTiming 12 4 8 bytes of data for 8 NAND Timing Parameters

from NAND datasheet. The 8 parameters are:
data_setup, data_hold, address_setup,
dsample_time, nand_timing_state, REA, RLOH,
RHOH.
m_u32PageDataSize 20 4 Number of bytes of data in a page. Typically,

this is 2048 bytes for 2112 bytes page size or
4096 bytes for 4314 bytes page size.
m_u32TotalPageSize 24 4 Total number of bytes in page. Typically, 2112

for 2K page or 4224 or 4314 for 4K page.
m_u32SectorsPerBlock 28 4 Number of pages per block. Typically 64 or 128

or depending on NAND device type.
m_u32NumberOfNANDs 32 4 Number of NAND devices present on the chip,

this is ignored in i.MX28 ROM. May be useful
for by other applications.

NAND Boot Mode
m_u32TotalInternalDie 36 4 Number of internal dice present on the NAND

chip. Not used by ROM.
m_u32CellType 40 4 MLC or SLC, not used by ROM.
m_u32EccBlockNEccType 44 4 Type of BCH Error Correction Level used for

encoding BCH Blocks B1 through BN. Should
be one of the following:
0 - BCH0
1 - BCH2
2 - BCH4
3 - BCH6
4 - BCH8
5 - BCH10
6 - BCH12
7 - BCH14
8 - BCH16
9 - BCH18
10 - BCH20
m_u32EccBlock0Size 48 4 Size of BCH Block B0. Typically 512 but can be

any value limited to 900 bytes.
m_u32EccBlockNSize 52 4 Size of BCH Blocks B1 through BN. Typically

512 but can be any value limited to 900 bytes.
m_u32EccBlock0EccType 56 4 Type of BCH Error Correction Level used for

encoding BCH Block B0. Should be one of the
following:
0 - BCH0
1 - BCH2
2 - BCH4
3 - BCH6
4 - BCH8
5 - BCH10
6 - BCH12
7 - BCH14
8 - BCH16
9 - BCH18
10 - BCH20
m_u32MetadataBytes 60 4 Number of bytes in metadata of a page. Minim-

um value allowed is 1. If set to 0, ROM may not
boot the image successfully.

m_u32NumEccBlocksPerPage 64 4 Number of BCH Blocks excluding B0.
m_u32EccBlockNEccLevelSDK 68 4 This is for SDK/Application use only. Not used

by ROM.
m_u32EccBlock0SizeSDK 72 4 This is for SDK/Application use only. Not used

by ROM.
m_u32EccBlockNSizeSDK 76 4 This is for SDK/Application use only. Not used

by ROM.
m_u32EccBlock0EccLevelSDK 80 4 This is for SDK/Application use only. Not used

by ROM.
m_u32NumEccBlocksPerPageSDK 84 4 This is for SDK/Application use only. Not used

by ROM.
m_u32MetadataBytesSDK 88 4 This is for SDK/Application use only. Not used

by ROM.
m_u32EraseThreshold 92 4 This value will be set into BCH_MODE register.
m_u32BootPatch 96 4 0 for normal boot and 1 for NAND patch boot.
m_u32PatchSectors 100 4 Size of patch in pages.
m_u32Firmware1_StartingSector 104 4 Starting page address of primary boot firmware.
m_u32Firmware2_StartingSector 108 4 Starting page address of secondary boot firm-

ware.
m_u32SectorsInFirmware1 112 4 Number of pages occupied by primary boot

firmware.
m_u32SectorsInFirmware2 116 4 Number of pages occupied by secondary boot

firmware.
m_u32DBBTSearchAreaStartAddress 120 4 Starting page address of DBBT Search Area.
m_u32BadBlockMarkerByte 124 4 Byte offset in page data containing manufacturer

marked bad block marker information.
m_u32BadBlockMarkerStartBit 128 4 For BCH ECC Levels other than BCH8 or BCH16
BI byte does not start at a byte boundary. This
field will give the start bit number of BI in
m_u32BadBlockMarkerByte.
m_u32BBMarkerPhysicalOffset 132 4 This is the physical byte offset where manufac-

turer marked bad block marker.
- 136 376 Spare bytes, should be set to 0.

NAND Boot Mode
12.12.1.14 Discovered Bad Block Table Header Layout Block Structure

and Definitions
The first 512 bytes of the DBBT header structure are as follows:
Table 12-31. DPPT Header Structure
Name Start Byte Size in Bytes Description
m_u32Checksum 0 4 32 bit checksum of 508 bytes of DBBT

data from offset 4 to 512 XOR with
0xFFFF_FFFF
m_u32FingerPrint 4 4 32 bit word with a value of 0x54424244,

in ascii “DBBT”
m_u32Version 8 4 32 bit version number; this version of

DBBT is 0x0100_0000
m_u32NumberBB 12 4 Number of bad blocks present in the table.
m_u32Number2KPagesBB 16 4 Bad blocks consume these many 2048

byte size pages.
— 20 492 Spare bytes, should be set to 0.
12.12.1.15 Discovered Bad Block Table Layout Block Structure and

Definitions
The actual bad block table structure is as follows:
Table 12-32. Bad Block Table Structure
Name Start Byte Size in Bytes Description
uNAND 0 4 NAND number
uNumberBB 4 4 Number of entries in DBBT
u32BadBlock 8 2040 Array or Table for bad block entries, each

4 byte word in this array contain the block
number that is bad.
12.12.2 Typical NAND Page Organization

This section discusses the typical NAND page organization. In particular, it discusses the
BCH ECC page organization, metadata requirements, and efuses/OTP bits used by the ROM
NAND driver

12.12.2.1 BCH ECC Page Organization.

For NAND boot, ROM restricts the size of a BCH data block to 512 bytes. The first data
block is called block 0 and the rest of the blocks are called block N. Separate ECC levels
can be used for block 0 and block N. The metadata bytes should be located at the beginning
of a page, starting at byte 0, followed by data block 0, followed by ECC bytes for data block
0, followed by block 1 and its ECC bytes, and so on until N data blocks. The ECC level for
block 0 can be different from the ECC level of rest of the blocks. Metadata bytes can be 0.
For NAND boot, with page size restrictions and data block size restricted to 512 bytes, only
few combinations of ECC for block 0 and block N are possible.
Block 0 Block 1 Block 2 Block 3

M 512 bytes EccB 0 512 bytes EccBN 512 bytes EccBN 512 bytes EccBN
Figure 12-15. Valid layout for 2112 bytes sized page
The number of ECC bits required for a data block is calculated using (ECC_Correction_Level
* 13) bits.
In the above layout, the ECC size for EccB0 and EccBN should be selected to not exceed
a total page size of 2112 bytes. EccB0 and EccBN can be one of 2, 4, 6, 8, 10, 12, 14, 16,
18, 20 bits ECC correction level. The total bytes would then be:
[M + (data_block_size * 4) + ([EccB0 + (EccBN * 3)] * 13) / 8] <= 2112;
M=metadata bytes and data_block_size is 512.
There are four data blocks of 512 bytes, each in a page of 2K page sized NAND. The values
of EccB0 and EccBN should be such that the above calculation would not result in a value
greater than 2112 bytes.

M 512 bytes EccB 0 512 bytes EccBN 512 bytes EccBN 512 bytes EccBN

512 bytes EccBN 512 bytes EccBN 512 bytes EccBN 512 bytes EccBN
Figure 12-16. Valid layout for 4K bytes sized page
Different NAND manufacturers have different sizes for a 4K page, 4314 bytes is typical.
[M + (data_block_size * 8) + ([EccB0 + (EccBN * 7)] * 13) / 8] <= 4314;
M=metadata bytes and data_block_size is 512.

NAND Boot Mode
There are eight data blocks of 512 bytes, each in a page of a 4K page sized NAND. The
values of EccB0 and EccBN should be such that above calculation should not result in a
value greater than the size of a page in a 4K page NAND.
12.12.2.2 Metadata
The number of bytes used for metadata are specified in FCB. Metadata for BCH encoded
pages will be placed at the beginning of a page. ROM only cares about the first byte of
metadata to swap it with bad block marker byte in page data after each page read. It is
therefore important to have at least one byte for metadata bytes field in FCB data structure.
12.12.2.3 efuses/OTP bits used by ROM NAND Driver

Table 12-33. eFuses
Register Name Description
ROM1:2..0 NUMBER_OF_NANDS Three bits used for number of NANDs on the device. If left unblown,
boot ROM will default to 1 device. It is important to program these
bits to exact number of NANDs in the system, using this information
ROM will enable internal pullups. The boot may fail if this field is in-
correctly programmed. Max number of NAND devices allowed in
MX28 is 8, but ROM only supports boot from NAND0.
ROM1:7..4 BOOT_SEARCH_STRIDE Four bits for boot search stride. Boot ROM defaults it to 1. ROM
multiplies this number with 64 to get search stride in pages. Typically,
this should be left 0 or 1 for NAND devices with number of pages per
block as 64. For 128 pages per block, it is recommended to program
these bits to a value of 2 in order for each BCB to be placed in a new
block.
ROM1:11..8 BOOT_SEARCH_COUNT Four bits for boot search count. If not programmed, boot ROM will
default to 2. This value is raised to the power of 2 to get actual boot
search count. Boot search count will tell ROM how many times a BCB
is duplicated in a search area.
ROM1:27..20 ENABLE_NAND_CE_RDY_PULLUPS Eight bits to enable internal pullups on CE and RDY pins. Bit 20 is
used to enable pullups on NAND0,
Bit 21 is used to enable pullups on NAND1,...
...
Bit 27 is used to enable pullups on NAND7.
ROM1:30 DISABLE_SECONDARY_BOOT One bit to disable redundant boot. If this bit is programmed to 1, ROM
will not try to boot from the secondary image if the primary image
failed to boot.
ROM4:3..0 NAND_ROW_ADDRESS_BYTES Four bits for number of row address bytes. If not programmed, ROM
will default to 3 bytes for row (page) address.
ROM4:7..4 NAND_COLUMN_ADDRESS_BYTES Four bits for number of column address bytes. If not programmed,
ROM will default to 2 column address bytes.

Register Name Description
ROM4:15..8 NAND_READ_CMD_CODE1 Eight bits for NAND read cmd code 1. If not programmed, ROM will
default to 0 as NAND read cmd code 1. For BA NAND, these bits
should be programmed to a value of 0xC0.
ROM4:23..16 NAND_READ_CMD_CODE2 Eight bits for NAND read cmd code 2. If not programmed, ROM will
default to 0x30 as NAND read cmd code 2.
ROM4:31 NAND_BADBLOCK_MARKER_PRE- One bit to indicate that bad block marker byte is not preserved for
SERVE_DISABLE page data, this will result in ROM not swapping metadata[0] with bad
block byte offset in page data. This bit should never be programmed.
It is available to cover up any defective ROM code in handling bad
block marker byte swapping.
12.12.3 ONFi BA NAND Device Boot

i.MX28 ROM supports boot from ONFI-BA (Open NAND Flash Interface - Block
Abstracted) NAND. BA-NAND manages ECC, bad-blocks and wear-leveling inside its
controller. ROM reads ONFI NAND device’s parameter page to determine if the NAND
device is ONFI-BA. The command set of BA NAND is different from the traditional raw
NAND devices. For ONFI-BA NAND, ROM expects the first sector to contain a MBR with
partition table. One of the partitions is firmware partition. ROM then expects a configuration
block to be present on the first sector of firmware partition. The configuration block will
have start address for FW1 and FW2.
Here is the data structure of configuration block, it is same as config block described in SD
Boot.
#define FIRMWARE_CONFIG_BLOCK_SIGNATURE (0x00112233) //STMP
typedef struct _DriveInfo_t

{
uint32_t u32ChipNum; //!< Chip Select, ROM does not use it
uint32_t u32DriveType; //!< Always system drive, ROM does not use it
uint32_t u32Tag; //!< Drive Tag
// Below field u32FirstSectorNumber should be divisible by 4. Protocol is set to 4 sectors
// of 512 bytes. Firmware can start at sectors 4, 8, 12, 16, ...
uint32_t u32FirstSectorNumber; //!< Start sector/block address of firmware.
uint32_t u32SectorCount; //!< Not used by ROM
} DriveInfo_t;
typedef struct _ConfigBlock_t

{
uint32_t u32Signature; //!< Signature 0x00112233
uint32_t u32PrimaryBootTag; //!< Primary boot drive identified by this tag
uint32_t u32SecondaryBootTag; //!< Secondary boot drive identified by this tag
uint32_t u32NumCopies; //!< Num elements in aFWSizeLoc array
DriveInfo_t aDriveInfo[]; //!< Let array aDriveInfo be last in this data
//!< structure to be able to add more drives in future
//!< without changing ROM code
} ConfigBlock_t;

USB Boot Driver
12.13 USB Boot Driver

The USB Boot Driver is implemented as a USB HID class and is referred to as the Recovery
HID, or RHID. The RHID serves as a fail-safe mechanism for downloading and
communicating with application-specific code.
The system is based on two HID Application collections: the Boot Loader Transfer Controller
(BLTC) and the Plug-in Transfer Controller (PITC). Each collection has its own set of HID
reports.
12.13.1 Boot Loader Transaction Controller (BLTC)

The BLTC provides a tunnel to download application-specific PITCs to the local system
memory. The BLTC runs completely from ROM and interfaces directly to the ROM Loader.
Typically, a PITC will be packaged on the host and downloaded through the BLTC and
ROM Loader straight to OCRAM (or SDRAM).
Four HID reports are provided for communication with the BLTC:
• BLTC Command Out (BLCO)
• BLTC Data Out (BLDO)
• BLTC Data In (BLDI)
• BLTC Status In (BLSI)
The BLTC provides a command/data protocol for downloading code to the ROM Loader.
The BLTC has no knowledge of the contents of the data passing through so, it is really
possible to download anything (not just PITCs).
12.13.2 Plug-in Transaction Controller (PITC)

The PITC is a generic command/data/status tunnel that may be used for any type of
application. The implementation only specifies the HID report structure and the ROM
HID-stack installation for a PITC—the protocol implementation is specific to a given PITC.
Typically, a PITC will be downloaded to memory through the BLTC.
Four HID reports are provided for communication with a PITC:
• PITC Command Out (PICO)
• PITC Data Out (PIDO)

• PITC Data In (PIDI)

• PITC Status In (PISI)
The command/data protocol is specific to any given PITC.

Only one PITC may be installed at any given time.
12.13.3 USB IDs and Serial Number

By default, the USB Device Descriptor Vendor ID, Product ID, and serial number are
reported as follows:
• Vendor ID—0x15A2
• Product ID—0x004F
• Serial Number String—none
If any of the HW_OCOTP_ROM2 bits are blown, then the full contents of that OTP register
are used to report the Vendor ID and Product ID. If the
ENABLE_USB_BOOT_SERIAL_NUMBER OTP is blown, then a unique serial number
will be generated from the factory-programmed SGTL_OPS3 OTP registers.
12.13.4 USB Recovery Mode

USB boot mode is provided as a fail-safe mechanism for writing system firmware to the
boot media. The boot mode is not usually entered by the normal methods of setting the boot
pins or OTP, the other methods of entering USB boot mode are referred to generally as
recovery mode.
An end user can manually start the recovery mode by holding the recovery switch for several
seconds while plugging in USB. Holding the recovery switch is defined as reading the
i.MX28 PSWITCH input as a 0x3. There are several switch circuits that will produce this
input. The loader also automatically starts recovery mode if a non-recoverable error is
detected from any boot mode other than USB.
If the DISABLE_RECOVERY_MODE OTP bit is blown, then USB boot mode is disabled
completely. Attempts to enter USB boot mode through boot pins, OTP, or recovery methods
will result in a chip power-down.

USB Boot Driver

Chapter 13
Data Co-Processor (DCP)
13.1 Data Co-Processor (DCP) Overview

The DCP module provides support for general encryption and hashing functions typically
used for security functions. Because the basic job of the DCP module is moving data from
memory to memory, the DCP module also incorporates memory-copy (memcopy) function
for both debugging and as a more efficient method of copying data between memory blocks
than the DMA-based approach. The memcopy function also has a blit mode of operation
where it can transfer a rectangular block of data to a video frame buffer.
AXI Bus Master
Hash
Dual-Port FIFO
Control
Cipher
APBH Slave
Figure 13-1. Data Co-Processor (DCP) Block Diagram
The i.MX28 DCP module implementation supports AES-128 encryption and CRC32,
SHA-1, and SHA-256 hashing (see the Capability Register).
The DCP module processes data based on chained command structures written to the system
memory by software (in a manner similar to the DMA engine). The control block maintains
registers to support four independent and concurrent chains, allowing software to virtualize
access to the DCP block. Each command in a chain represents a work unit that the module
will process to completion. At the end of each work unit, the control logic arbitrates among
chains with outstanding commands and processes a command from that chain. Arbitration
among the channels is round-robin, allowing all active channels equal access to the data

Data Co-Processor (DCP) Overview
engine. Each channel also supports a high-priority mode that allows it to have priority over
the remaining channels. If multiple channels are selected as high-priority, the channel arbiter
selects among the high-priority channels in a round-robin fashion.
The data flow through the DCP module can be configured in one of five fashions, depending
on the functionality activated by the control packet:
• Memcopy/Blit Mode—Data is moved unchanged from one memory buffer to another.
AXI FIFO AXI
Figure 13-2. Memcopy/Blit Mode
• Encryption Only—Data from source buffer is encrypted/decrypted into the destination

buffer.
Encryption
AXI FIFO FIFO AXI
Decryption
Figure 13-3. Encryption Only
• Hashing Only—Data from source buffer is read, and a hash is generated.
AXI Hash
Figure 13-4. Hashing Only
• Encryption and Input Hashing—Data from source buffer is encrypted/decrypted into

destination, and source buffer is hashed.
Encryption
AXI FIFO FIFO AXI
Decryption
Hash
Figure 13-5. Encryption and Input Hashing
• Encryption and Output Hashing—Data from source buffer is encrypted/decrypted

into destination, and output data is hashed.
Encryption
AXI FIFO FIFO AXI
Decryption
Hash
Figure 13-6. Encryption and Output Hashing

Chapter 13 Data Co-Processor (DCP)
13.1.1 DCP Limitations for Software

While the DCP module has been designed to be as flexible as possible, there are a few
limitations to which software must adhere:
• Buffer sizes for all operations MUST be aligned to the natural size of the transfer
algorithm used. Memcopy operations can transfer any number of bytes (one-byte
granularity) and AES operations must be multiples of 16 bytes (four-word granularity).
For all operations, if the byte count is not a word granularity, the hardware rounds up
to the next word. Hashing is supported at a byte granularity.
• The DCP module supports buffer operations to any byte alignment, but performance
will be improved if buffers are aligned to a four-byte boundary, since fetch/store
operations can be performed without having to do byte operations to accommodate the
misaligned addresses.
• Hash operations are limited to a 512 Mbyte buffer size. The hardware only implements
a 32-bit hash length counter instead of the 64-bit counter supported by the
SHA-1/SHA-256 algorithm (counter counts bits, not bytes, therefore a total of 512
Mbytes).
• For chained hashing operations (operations involving multiple descriptors), every
descriptor except the last must have a byte count that is a 16-word multiple (granularity
of the hash algorithm).
• Key values cannot be written while the AES block is active. This limitation exists
because the key RAM is in use while AES is operational. Any writes from the APB
cannot be held in wait states; therefore, the RAM must be accessible during key writes.
• The byte-swap controls can only be used with modulo-4 length buffers. For
non-modulo-4 lengths, the final partial word will contain incorrect data. Any address
alignment can be used with byte swapping, however.
• The word-swap controls are only useful with cipher operations, because the logic forms
the 128-bit cipher data from four words from system memory. The word-swap controls
are ignored for memcopy or hashing operations.
• DCP only supports writes to word boundaries to OCRAM. This is not required for EMI
DRAM address.

Operation
13.2 Operation
The top-level DCP module contains the AXI master, APB slave bus interface units, the
main control block and FIFO, and any encryption or hashing blocks included with the
design.
The controller manages the fetching of work blocks, the fetching/storing of context
information when switching between chain pointers, and the data flow through FIFO, SHA,
and AES blocks. Data entering the block from the AXI master is placed in the FIFO for
consumption by the cipher block. After the cipher module has finished its operation, data
is placed back into the FIFO and stored back to memory through the AXI master. When
hashing is enabled, the SHA block takes its inputs from the bus side of the FIFO to allow
it to operate without waiting for the cipher block to complete. The APB slave provides all
register controls and interfaces mainly with the control block.
13.2.1 Memory Copy, Blit, and Fill Functionality

In its most basic operation, the DCP supports moving unmodified data from one place in
system memory to another. This functionality is referred to as memcopy, because it operates
only on memory and it copies data from one place to another. Typical uses of memcopy
might be for fast virtual memory page moves or repositioning data blocks in memory.
Memcopy buffers can be aligned to any memory address and can be of any length (byte
granularity). For best performance, buffers should be word-aligned, although the DCP
includes enhancements to improve performance for unaligned cases.
The DCP also has the ability to perform basic blit operations that are typical in graphics
operations. To specify a blit, the control packet must have the ENABLE_BLIT bit set in
the packet control register. Blit source buffers must be contiguous. The output destination
buffer for a blit operation is defined as a "M runs of N bytes" that define a rectangular region
in a frame buffer. For blit operations, each line of the blit may consist of any number of
bytes. After performing a run, the DCP updates the destination pointer such that the next
destination address falls on the pixel below the start of the previous run operation. This is
performed by incrementing the starting pointer by the frame buffer width, which is specified
in Control1 field.
In addition to being able to copy data within memory, the DCP also provides a fill operation,
where source data comes not from another memory location, but from an internal register
(the source buffer address in the control packet). This is performed whenever the
CONSTANT_FILL flag is set in the packet control register. This feature may be used with
memcopy to prefill memory with a specified value or during a blit operation to fill a
rectangular region with a constant color.

13.2.2 Advanced Encryption Standard (AES)

The AES block implements a 128-bit key/data encryption/decryption block as defined by
the National Institute of Standards and Technology (NIST) as US FIPS PUB 197, dated
November 2001 (see references for specifications and toolkits)1.
There are three variations of AES, each corresponding to the key size used: AES-128,
AES-192 or AES-256. AES always operates on 128 bits of data at a time. Only the AES-128
algorithm is implemented at this time.
13.2.2.1 Key Storage

The DCP implements four SRAM-based keys that may be used by software to securely
store keys on a semi-permanent basis. The keys may be written through the PIO interface
by specifying a key index to specify which key to load and a subword pointer that indicates
which word to write within the key. After a subword is written, the logic automatically
increments the subword pointer so that software can program the higher-order words of the
key without rewriting the key index. Keys written into the key storage are not readable.
To use a key in the key storage, the cipher descriptor packet should select the key by setting
the KEY_SELECT field in the Control1 descriptor field without setting the OTP_KEY or
PAYLOAD_KEY fields in the Control0 register.
13.2.2.2 OTP Key

After a system reset, the OTP controller reads the e-fuse devices and provides the OTP key
information over a parallel 128-bit interface. The key transfer interface runs on HCLK and
provides the key over the serialized otp_data signal. The otp_crypto_key_smpl signal
indicates when the key value is valid and causes the control logic to capture the key into
the key RAM.
To use the OTP key, the descriptor packet should set the OTP_KEY field in the Control1
register.
1. The AES core used in the design was derived from the AES design available from OpenCores.org under a modified BSD
license as described here: http://www.opencores.org/projects.cgi/web/aes_core/overview The license for this code is documented
in Disclaimer for compliance.

Operation
13.2.2.3 Encryption Modes

The most basic form of encryption is the Electronic Code Book (ECB) mode. In this mode,
the encryption output is a function only of the key and the plaintext, therefore, it can be
visualized as a giant lookup table. While this provides a great deal of security, there are a
few limitations. For instance, if the same plaintext appears more than once in a block of
data, the same ciphertext will also appear. This can be very evident if the plaintext contains
large blocks of constant data (0s for example) and can be used to formulate attacks against
a key.
In order to make ciphers stronger, several modes of operation can be implemented around
the basic ECB cipher to provide additional security. One such mode is CBC mode (Cipher
Block Chaining), which takes the previous encrypted data and logically XORs it with the
next incoming plaintext before performing the encryption. During decryption, the process
is reversed and the previous encrypted data is XORed with the decrypted ECB data to
provide the plaintext again.
The AES engine supports handling the various modes of operation. The core AES block
supports ECB mode and other algorithms are handled in the wrapper around the encryption
blocks. The DCP module supports Cipher Block Chaining (CBC), which chains the data
blocks by XORing the previously encrypted data with the plaintext before encryption. Cipher
block chaining encryption is illustrated in Figure 13-7.
Plaintext Plaintext Plaintext
Initialization Vector (IV)
Block Cipher Block Cipher Block Cipher

Encryption Encryption Encryption
Key Key Key
Ciphertext Ciphertext Ciphertext
Figure 13-7. Cipher Block Chaining (CBC) Mode Encryption
Decryption (shown in the following figure) works in a similar manner, where the cipher
text is first decrypted and then XORed with the previous ciphertext. For the first
encryption/decryption operation, an initialization vector (IV) is used to seed the operation.
The IV must be the same for both the encryption and decryption steps; otherwise, decrypted
data will not match the original plaintext.

Ciphertext Ciphertext Ciphertext
Initialization Vector (IV)
Block Cipher Block Cipher Block Cipher

Decryption Decryption Decryption
Key Key Key
Plaintext Plaintext Plaintext
Figure 13-8. Cipher Block Chaining (CBC) Mode Decryption
13.2.3 Hashing
The hashing module implements SHA-1 and SHA-256 hashing algorithms and a modified
CRC-32 checksum algorithm. These algorithms produce a signature for a block of data that
can be used to determine whether the data is intact.
The CRC-32 algorithm implements a 32-bit CRC algorithm similar to the one used by
Ethernet and many other protocols. The CRC differs from Unix cksum() function in three
ways:
• The CRC is initialized as 0xFFFFFFFF instead of 0x00000000.
• Logic pads zeros to a 32-bit boundary for trailing bytes.
• Logic does not post-pend the file length.
The SHA-1 block implements a 160-bit hashing algorithm that operates on 512-bit (64-byte)
blocks as defined by US FIPS PUB 180-1 in 1995. The SHA-256 mode implements a 256-bit
hashing algorithm that operates on 512-bit (64-byte) blocks as defined by US FIPS PUB
180-2 in 2002. The purpose of the hashing module is to generate a unique signature for a
block of data that can be used to validate the integrity of the data by comparing the resulting
digest with the original digest.
Results from hash operations are written to the beginning of the payload for the descriptor.
The DCP also has the ability to check the resulting hash against a value in the payload and
issue an interrupt if a mismatch occurs.

Operation
13.2.4 OTP Key

After a system reset, the OTP controller will read the e-fuse devices and provide the OTP
key information over a private parallel 32-bit interface. While the OTP key is normally not
available to read operations, the module will allow the key to be read if the
otp_crypto_key_ren (read-enable) input is active (high). This allows verification of the key
after it has been programmed in to the e-fuse device. After programming has been validated,
another fuse will be set to disable the read capability.
The OTP key may be selected using the OTP_KEY bit in the control field of the packet
descriptor or by using the key select 0xFF in the CTRL1 field of the descriptor. The DCP
also supports a second hardware key called the UNIQUE_KEY which is generated from
the OTP KEY (OCOTP_CRYPTO0,1,2,3) and key modifier bits from another OTP fields
(OCOTP_OPS2 and OCOTP_UN2) with unique number for every chip. This key is unique
to the device and may be used for encrypting private data stored on the NAND. This key
may be selected by writing 0xFE to the KEY_SELECT field in the CTRL1 packet data.
13.2.5 Managing DCP Channel Arbitration and Performance

The DCP can have four channels all competing for DCP resources to complete their
operations. Depending on the situation, critical operations may need to be prioritized above
less important operations to ensure smooth system operation. To help software achieve this
goal, the DCP implements a programmable arbiter for internal DCP operations and provides
recovery timers on each channel to throttle channel activity.
13.2.5.1 DCP Arbitration

The DCP implements a multi-tiered arbitration policy that allows software a lot of flexibility
in scheduling DCP operations. The following figure illustrates the arbitration levels and
where each channel fits into the arbitration scheme.

Channels
0 1 2 3
High 1 1 1 1
Priority Level
Low 0 0 0 0
Figure 13-9. DCP Arbitration
Each channel can be programmed as being in either the high-priority or low-priority

arbitration pool, depending on the setting in the HIGH_PRIORITY_CHANNEL field of
the HW_DCP_CHANNELCTRL register. When the corresponding bit is programmed as
a 1, the channel arbitrates in the high-priority pool; otherwise, it arbitrates in the low-priority
pool. Once a channel has been selected, it completes one packet and then the arbiter
re-arbitrates. The channel that just completed participates in the new arbitration round.
13.2.5.2 Channel Recovery Timers

Each channel also contains a channel recovery timer in its HW_DCP_CHnOPTS register.
The purpose of the recovery timer is to keep the channel inactive for a period of time after
it completes an operation. This capability could be used for a high-priority channel to ensure
that at least some lower-priority requests get serviced between packets or to simply allow
more timeslices for other channels to perform operations. The value programmed into the
recovery timers register delays the channel from operations until 16 times the programmed
value. Any non-zero value should prevent the channel from participating in the next
arbitration cycle.
13.2.6 Programming Channel Operations

The control logic block maintains the channel pointers and manages arbitration and context
switching between the different channels. It also manages the fetching of work packets and
data fetch/store operations from the AXI master interface and coordinates the actions of the
hashing and encryption blocks.
The control logic maintains four channels that allow software to effectively create four
independent work sets for the DCP module. Software can construct chained control packets
in memory that describe encryption/hashing/memcopy operations to the hardware unit. The
address for this first control packet can be written to one of the four virtual channels and

Operation
enabled. When one or more of the channels is enabled, the controller fetches the control
packet pointed to by that channel and initiates data fetches from the source buffer. Data is
then processed as described in the control packet and stored back to the system memory.
Once the processing for a control packet is complete, the controller writes completion status
information back to the control packet, and optionally stores relevant state information to
the context buffer. If the control packet specifies a subsequent control packet, the channel's
pointer is updated to the address for the next packet and an optional interrupt can be issued
to the processor.
At this point, the DCP module arbitrates among the virtual channels for the next operation
and processes its control packet. If a subsequent operation is continued from a previous
operation, the controller automatically loads the context from the previous session into the
working registers before resuming operation for that channel.
13.2.6.1 Virtual Channels

The DCP module processes data through work packets stored in memory. Each of the
channels contains a pointer to the current work packet and enough control logic to determine
whether the channel is active and to provide status to the processor. Each channel also
provides a recovery timer to help throttle processing by a particular channel. After processing
a packet, the channel enables its 16-bit recovery timer (if the recovery time is set to a
non-zero value). The channel will not become active again until its recovery timer has
expired. The recovery timer timebase is 16 HCLK cycles, so the timer acts as a 20-bit timer
with the bottom four bits implicitly tied to 0. This provides an effective range of zero to
220-1 clocks or 0 ns to 7.8 ms at 133 MHz.
A channel is activated any time its semaphore is non-zero and its recovery timer is cleared.
The semaphore can be incremented by software to indicate that the chain pointer has been
loaded with a valid pointer. As the hardware completes the work packets, it decrements the
semaphore if the Decrement Semaphore flag in the Control 0 field is set. Work packets may
be chained together using the CHAIN or CHAIN_CONTIGUOUS bits in the Control0 field,
which causes the channel to automatically update the work packet pointer to the value in
the NEXT_COMMAND_ADDRESS field at the end of the current work packet.
13.2.6.2 Context Switching

The control logic maintains four virtual channels that allow the DCP block to time-multiplex
encryption, hashing and memcopy operations, it must also retain state information when
changing channels so that when a channel is resumed, it can resume the operation from
where it left off. This process is called context-switching.

To minimize the number of registers used in the design, the controller saves context
information from each channel into a private context area in the system memory. When
initializing the DCP module, software must allocate memory for the context buffer and
write the address into the Context Buffer Pointer register. As the DCP module processes
packets, it saves the context information for each channel to the buffer after completing
each control packet. When the channel is subsequently activated, the DCP module's internal
registers are then reloaded with the proper context before resuming the operation.
Each channel reserves one-fourth of the context buffer area for its context storage. The
context buffer consumes 208 bytes of system memory and is formatted as shown in the
following table.
Table 13-1. DCP Context Buffer Layout
RANGE Channel Data Size
0x00–0x0C 3 Cipher Context 16 bytes
0x10–0x30 Hash Context 36 bytes
0x34–0x40 2 Cipher Context 16 bytes
0x68–0x74 1 Cipher Context 16 bytes
0x9C–0xA8 0 Cipher Context 16 bytes
0xAC–0xCC Hash Context 36 bytes
The control logic writes to the context buffer only if the function is being used. This
effectively means that the cipher context is stored for CBC encryption/decryption operations
only and the hash context is written only if SHA-1/SHA-256 is utilized. If neither of these
modes are used for a given channel, the memory for the context buffer need not be allocated
by the software.
Since channel 0 is likely to be used for VMI in an SDRAM-based system-to-page data from
the SDRAM to on-chip SRAM, the buffer allocation table has been organized so that the
highest numbered channel uses the lowest area in the context buffer. For this reason, software
should allocate the higher numbered channels for encryption/hashing operations and the
lower numbered channels for memcopy operations to reduce the size of the context buffer.
If only a single channel is used for CBC mode operations or hashing operations, the controller
provides a bit in the control register to disable context switching. In this scenario, context
switching is not required, because other channels will not corrupt the state of the hashing
or cipher modes. Therefore, when the channel resumes, a context load is not required.
Operation
Additionally, the control logic monitors the use of CBC/hashing, so that a context reload
is not performed if the previous channel resumes an operation without an intermediate
operation from another channel.
13.2.6.3 Working with Semaphores

Each channel has a semaphore register to indicate that control packets are ready to be
processed. Several techniques can be used when programming the semaphores to control
the execution of packets within a channel. The channel will continue to execute packets as
long as the semaphore is non-zero, a chain bit is set in the descriptor and no error has
occurred.
• Software can write the number of pending packets into the semaphore register with the
Decrement Semaphore bit in each control packet set. In this scenario, the channel simply
decrements the semaphore for each packet set and terminates at the end of the packet
chain. The benefit of this method is that software can easily determine how many
packets have executed by reading the semaphore status register.
• Software can create a packet chain with the Decrement Semaphore bit set only in the
last packet. In this case, software would write a 1 to the semaphore register to start the
chains and the DCP will terminate after executing the last packet.
• Software can create a packet chain with the Decrement Semaphore bit set for each
packet and write either a 1 or a number less than the number of packets to the semaphore
register. This can be useful when debugging, because it allows the channel to execute
only a portion of the packets and software can inspect intermediate values before
restarting the channel again.
If an error occurs, the channel issues an interrupt and clears the semaphore register. The
channel does not perform any further operations until the error bits in the status register
have been cleared. Software can manually clear a non-zero semaphore by writing 0xFF to
the CLR (clear) address of the semaphore register.
13.2.6.4 Work Packet Structure

Work packets for the DCP module are created in memory by the processor. Each work
packet includes all information required for the hardware to process the data. The general
structure of the packet is shown below.
Table 13-2. DCP Work Packet Structure
Word0 Next Cmd Addr
Word1 Control0

Word2 Control1
Word3 Source Buffer Addr
Word4 Destination Buffer Addr
Word5 Buffer Size
Word6 Payload Pointer
Word7 Status
For some operations, additional information is required to process the data in the packet.
This additional information is provided in the variable-sized payload buffer, which can be
found at the address specified in the payload pointer field. When encryption is specified,
the payload may include the encryption key (if the key selected resides in the packet), an
initialization vector (for modes of operation such as CBC), and expected hash values when
data hashing is indicated. The hardware can automatically compare the expected hash with
the actual hash and interrupt the processor only on a mismatch. The payload area is used
by software to store the calculated hash value at the end of hashing operations (when the
HASH_TERM control bit is set).
13.2.6.4.1 Next Command Address Field
The NEXT_COMMAND_ADDRESS field (as shown in the following table) is used to
point to the next work packet in the chain. This field is loaded into the channel's command
pointer after the current packet has completed processing if the CHAIN bit in the
CONTROL0 field (see Table 13-4) is set. The Next Command Address field should be
programmed to a non-zero value when the CHAIN bit is set; otherwise, the channel will
flag an invalid setup error.
Table 13-3. DCP Next Command Address Field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
13.2.6.4.2 Control0 Field

The main functions of the DCP module are enabled with the ENABLE_MEMCOPY,
ENABLE_BLIT, ENABLE_CIPHER and ENABLE_HASH bits from the Control0 field
in the work packet. The combinations of these bits determine the function performed by
the DCP. Table 13-5 summarizes the function performed for each combination.
Table 13-4. DCP Control0 Field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Operation
OUTPUT_WORDSWAP
OUTPUT_BYTESWAP
INPUT_WORDSWAP
INPUT_BYTESWAP
KEY_WORDSWAP
KEY_BYTESWAP
TEST_SEMA_IRQ
HASH_OUTPUT
HASH_CHECK
HASH_TERM
OTP_KEY
CIPHER_INIT
CIPHER_ENCRYPT
ENABLE_BLIT
ENABLE_HASH
ENABLE_CIPHER
ENABLE_MEMCOPY
DECR_SEMAPHORE
INTERRUPT_ENABLE
CHAIN_CONTINUOUS
PAYLOAD_KEY
CHAIN
TAG
CONSTANT_FILL
HASH_INIT
Table 13-5. DCP Function Enable Bits
HASH Cipher Blit Memcopy Description
0 0 0 X Simple memcopy operation.
0 0 1 0 Blit operation.
0 1 0 0 Simple encrypt/decrypt operation.
1 0 0 0 Simple hash. Only reads performed.
1 0 0 1 Memcopy and hash operation.
1 1 0 0 Hash with encryption/decryption.
All Others Invalid setup.
The CHAIN bit should be set if the NEXT_COMMAND_ADDRESS field has a valid
pointer to the next work packet. When set, this bit causes the channel to update its pointer
to the next packet. The CHAIN_CONTINUOUS bit is similar, but it indicates that the next
packet follows immediately after the current packet. This allows software to generate
templates of operations without regard to the actual physical addresses used, which makes
programming easier, especially in a virtual memory environment.
If the INTERRUPT_ENABLE bit is set, the channel generates an interrupt to the processor
after completing the work for this packet. When the interrupt is issued, the packet will have
been completely processed, including the update of the status/payload fields in the work
packet.
Each channel contains an eight-bit counting semaphore that controls whether it is in the run
or idle state. When the semaphore in non-zero, the channel is ready to run and process
commands. Whenever a command finishes its operation, it checks the DECR_SEMAPHORE
bit. If set, it decrements the counting semaphore. If the semaphore goes to 0 as a result, then
the channel enters the idle state and remains there until the semaphore is incremented by
software. When the semaphore goes to non-zero and the channel is in its idle state, it then
uses the value in the NEXT_COMMAND_ADDRESS field to begin processing.

If the ENABLE_CIPHER bit is set, the data is encrypted or decrypted based on the
CIPHER_ENCRYPT bit using the key/encryption settings from the Control1 field. The
OTP_KEY and PAYLOAD_KEY indicates the source of the keys for the operation. If the
OTP_KEY value is set, the KEY_SELECT field from the Control1 register indicates which
OTP key is to be used. If the PAYLOAD_KEY bit is set, the first entry in the payload is
the key to be used for the operation. If neither bit is set, the KEY_SELECT field indicates
an index in the key RAM that contains the key to be used. (For cases when both the
OTP_KEY and PAYLOAD_KEY bits are set, the PAYLOAD_KEY takes precedence.)
The HASH_ENABLE enables hashing of the data with the HASH_OUTPUT bit controlling
whether the input data (HASH_OUTPUT=0) or output data (HASH_OUTPUT=1) is hashed.
In addition, the hardware can be programmed to automatically check the hashed data if the
HASH_CHECK bit is set. If the hash does not match, an interrupt is generated and the
channel terminates operation on the current chain. The hashing algorithms also require two
additional fields in order to operate properly. The HASH_INIT bit should be set for the first
block in a hashing pass to properly initialize the hashing function. The HASH_TERM bit
must be set on the final block of a hash to notify the hardware that the hashing operation is
complete so that it can properly pad the tail of the buffer according to the hashing algorithm.
This flag also triggers the write-back of the hash output to the work packet's payload area.
The CONSTANT_FILL flag may be used for both memcopy and blit operations. When this
is set, the source address field is used instead as a constant that is written to all locations in
the output buffer.
The WORDSWAP and BYTESWAP bits enable muxes around the FIFO to swap data to
handle little-endian and big-endian storage of data in system memory. When these bits are
cleared, data is assumed to be in little-endian format. When all bits are set, data is assumed
to be in big-endian format.
The TAG field is used to identify the work packet and the associated completion status. As
each packet is completed, the channel provides the status and tag information of the last
packet processed.
13.2.6.4.3 Control1 Field
The Control1 field (shown in the following table) provides additional values used when
hashing or encrypting/decrypting data. For blit operations, this field indicates the number
of bytes in a frame buffer line, which is used to calculate the address for successive lines
in each blit operation.
Table 13-6. DCP Control1 Field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Operation
CIPHER_CONFIG HASH_SE- KEY_SELECT CIPHER_MODE CIPHER_SE-

LECT LECT
FRAMEBUFFER_LENGTH (in bytes, blit mode)
The CIPHER_SELECT field selects from one of sixteen possible encryption algorithms
(0=AES128). The CIPHER_MODE selects the mode of operation for that cipher (0=ECB,
1=CBC).
The KEY_SELECT field allows key selection for one of several sources. Keys can be
included in the packet payload or may come from OTP or write-only registers.
The HASH_SELECT field selects a hashing algorithm for the operation (0=SHA-1,
1=CRC32, 2=SHA-256).
The CIPHER_CONFIG field provides the optional configuration information for the selected
cipher. An example would be a key length for the RC4 algorithm.
13.2.6.4.4 Source Buffer
The SOURCE_BUFFER pointer (shown in the following table) specifies the location of
the source buffer in memory. The buffer may reside at any byte alignment and should refer
to an on-chip SRAM of off-chip SDRAM location. For optimal performance, buffers should
be word aligned. When the CONSTANT_FILL flag is set in the Control0 field, the value
in this field is used as the data written to all destination buffer locations.
Table 13-7. DCP Source Buffer Field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
SOURCE_BUFFER
CONSTANT (CONSTANT_FILL mode)
13.2.6.4.5 Destination Buffer

The DESTINATION_BUFFER (shown in the following table) specifies the location of the
destination buffer in on-chip SRAM or off-chip SDRAM memory and may be set to any
byte alignment. For in-place encryption, the destination buffer and source buffer should be
the same value. For optimal performance, the buffer location should be word-aligned.
Table 13-8. DCP Destination Buffer Field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
DESTINATION_BUFFER

13.2.6.4.6 Buffer Size Field

The BUFFER_SIZE field (shown in the following table) indicates the size of the buffers
for memcopy, encryption, and hashing modes. For memcopy and hashing operations, the
value may be any number of bytes (byte granularity) and for encryption modes, the length
must be a multiple of the selected encryption algorithm's natural data size (16 bytes for
AES).
Table 13-9. DCP Buffer Size Field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
NUMBER_LINES (blit mode) BLIT_WIDTH (in bytes, blit mode)
BUFFER_SIZE (in bytes, memcopy, encryption, hashing modes)
For blit operations, the buffer size field is split into two portions, a BLIT_WIDTH value,
which specifies the number of bytes in each line of the blit operation and a NUMBER_LINES
value, which specifies how many vertical rows of pixels are in the image buffer.
13.2.6.4.7 Payload Pointer
Some operations require additional control values that are stored in a Payload Buffer (shown
in the table below), which is pointed to by this field. After the DCP reads the control packet,
it examines the Control0 register and determines whether any payload information is required.
If so, the DCP loads the payload from the address specified in this field. (See Payload for
more details.)
Table 13-10. DCP Payload Buffer Pointer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PAYLOAD_POINTER
The payload area is also written to by the DCP at the completion of a hash operation (when
the HASH_TERM) bit is set. Software must allocate the appropriate amount of storage (20
bytes for SHA-1 and 4 bytes for CRC32) in the payload or risk having the DCP write to an
unallocated address.
13.2.6.4.8 Status
After the DCP engine has completed processing a descriptor, it writes the packet status
(shown in the following table) back to the descriptor In the Status field. The packet status
is the value of the channel status register at the time the packet completed processing.

Operation
Table 13-11. DCP Status Field

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ERROR_DST
ERROR_SRC
ERROR_PACKET
ERROR_SETUP
COMPLETE
HASH_MISMATCH
TAG ERROR_CODE
For various error conditions, the DCP encodes additional error information in the
ERROR_CODE field. See Programmable Registers for more details on assignments of error
codes. For any completion codes besides the COMPLETE flag, the channel suspends
processing the command chain until the error status values are cleared in the channel status
register.
The format for this field is same as the channel status register, with the exception that the
COMPLETE bit is written to the payload status but is not present in the channel status
register.
13.2.6.4.9 Payload
The payload is a variable-length field that is used to provide key, initialization values, and
expected results from hashing operations. The payload may consist of the data fields listed
in the following table.
Table 13-12. DCP Payload Field
FIELD NAME SIZE DESCRIPTION CONDITION
Cipher Key 16 bytes AES key Cipher enable with PAYLOAD_KEY
Cipher IV 16 bytes CBC initialization vector Cipher enable with CBC mode.
Hash Check 20 bytes Hash completion value Hash enabled with HASH_TERM fields set.
If fields are not used, they do not appear in the payload and the other payload values move
upwards in the payload area. For instance, if only hashing is used, then the HASH_CHECK
value would appear at offset 0 in the payload area. The following table should be used by
software to determine the amount of payload to allocate and initialize.
Table 13-13. DCP Payload Allocation by Software
CONTROL BITS PRESENT
HASH_CHECK CIPHER_INIT PAYLOAD_KEY PAYLOAD SIZE
0 0 0 0 words / 0 bytes

CONTROL BITS PRESENT
HASH_CHECK CIPHER_INIT PAYLOAD_KEY PAYLOAD SIZE
SHA-1: 5 words / 20 bytes

1 0 0

1 0 1

1 1 0

1 1 1
SHA-2 16 words / 64 bytes
For hashing operations, the DCP module writes the final hash value back to the start of the
payload area for descriptors with the HASH_TERM bit set in the control packet. It is
important that software allocates the required payload space, even though it is not required
to set up the payload for control purposes.
13.2.7 Programming DCP Functions
13.2.7.1 Basic Memory Copy Programming Example

To perform a basic memcopy operation, only a single descriptor is required. The DCP
simply copies data from the source to the destination buffer. This process is illustrated in
the following figure.
Next
Source
Ctrl0 Tag 0x13
Buffer
Ctrl1
Src Source Buffer Address
Dst Destination Buffer Address
Bytes Byte Count

Destination
Payld Buffer
Stat
0x13 = Memcopy | DecrSema | Interrupt
Figure 13-10. Basic Memory Copy Operation

Programming DCP Functions
<code>
typedef struct _dcp_descriptor

{
u32 *next;
hw_dcp_packet1_t ctrl0;
u32 *src,
*dst,
buf_size,
*payload,
stat;
} DCP_DESCRIPTOR;
DCP_DESCRIPTOR dcp1;
u32 *srcbuffer, *dstbuffer;
// set up control packet

dcp1.next = 0; // single packet in chain
dcp1.ctrl0.U = 0; // clear ctrl0 field
dcp1.ctrl0.B.ENABLE_MEMCOPY = 1; // enable memcopy
dcp1.ctrl0.B.DECR_SEMAPHORE = 1; // decrement semaphore
dcp1.ctrl0.B.INTERRUPT = 1; // interrupt
dcp1.ctrl1.U = 0; // clear ctrl1
dcp1.src = srcbuffer; // source buffer
dcp1.dst = dstbuffer; // destination buffer
dcp1.buf_size = 512; // 512 bytes
dcp1.payload = NULL; // not required
dcp1.status = 0; // clear status
// Enable channel 0
HW_DCP_CHnCMDPTR_WR(0, dcp1); // write packet address to pointer register
HW_DCP_CHnSEMA_WR(0, 1); // increment semaphore by 1
// now wait for interrupt or poll

// polling code
while ( (HW_DCP_STAT_RD() & 0x01) == 0x00 );
// now check/clear channel status

if ( (HW_DCP_CHnSTAT_RD(0) & 0xFF) != 0 ) {
// an error occurred
HW_DCP_CHnSTAT_CLR(0, 0xff);
}
// clear interrupt register
HW_DCP_STAT_CLR(1);
</code>
13.2.7.2 Basic Hash Operation Programming Example

To perform a basic hash operation, only a single descriptor is required. The DCP simply
reads data from the source buffer and computes the hash value on the contents. This process
is illustrated below.

Next
Source
Ctrl0 Tag 0x70 0x43
Buffer
Ctrl1 SHA1
Dst Payload
Bytes Byte Count Expected
Hash
Payld Payload Addrses
Stat
0x70 = Hash Check | Hash Term | Hash Init

0x43 = Hash Enable | DecrSema | Interrupt
Figure 13-11. Basic Hash Operation

<code>

{
u32 *next;
u32 *src,
*dst,
buf_size,
*payload,
stat;
} DCP_DESCRIPTOR;
u32 *srcbuffer;
u32 payload[5];
// set up expected hash check value

payload[0]=0x01234567;
payload[1]=0x89ABCDEF;
payload[2]=0x00112233;
payload[3]=0x44556677;
payload[4]=0x8899aabb;

dcp1.ctrl0.B.HASH_CHECK = 1; // check hash when complete
dcp1.ctrl0.B.HASH_INIT = 1; // initialize hash with this block
dcp1.ctrl0.B.HASH_TERM = 1; // terminate hash with this block
dcp1.ctrl0.B.ENABLE_HASH = 1; // enable hash
dcp1.dst = 0; // no destination buffer
dcp1.payload = payload; // holds expected hash value
// Enable channel 0

// polling code


}
HW_DCP_STAT_CLR(1);
</code>
13.2.7.3 Basic Cipher Operation Programming Example

To perform a basic cipher operation, only a single descriptor is required. The DCP reads
data from the source buffer, encrypts it, and writes it to the destination buffer. For this
example, the key is provided in the payload and the algorithm uses the AES CBC mode of
operation. This requires a payload with both the key and CBC initialization value. This
process is illustrated below.
Next
Source
Ctrl0 Tag 0x0B 0x23
Buffer
Ctrl1 CBC AES
Dst Destination Buffer Address
Bytes Byte Count

Destination
Payld Payload Address Buffer
Stat
0x0B = Payload Key | Cipher Init | Encrypt

Payload
0x23 = Cipher Enable | DecrSema | Interrupt
Key
CBC
Init
Figure 13-12. Basic Cipher Operation

<code>

{
u32 *next;
u32 *src,
*dst,
buf_size,
*payload,
stat;
} DCP_DESCRIPTOR;
u32 *srcbuffer;
u32 *dstbuffer;
u32 payload[8];
// set up key/CBC init in the payload

payload[0]=0x01234567; // key
payload[1]=0x89ABCDEF;
payload[2]=0xfedcba98;
payload[3]=0x76543210;

payload[4]=0x00112233; // CBC initialization

payload[5]=0x44556677;
payload[6]=0x8899aabb;
payload[7]=0xccddeeff;

dcp1.ctrl0.B.PAYLOAD_KEY = 1; // key is located in payload
dcp1.ctrl0.B.CIPHER_ENCRYPT = 1; // encryption operation
dcp1.ctrl0.B.CIPHER_INIT = 1; // init CBC for this block (from payload)
dcp1.ctrl0.B.ENABLE_CIPHER = 1; // enable cipher
dcp1.ctrl1.B.CIPHER_MODE = 1; // select CBC mode of operation
dcp1.payload = payload; // holds key/CBC init
// Enable channel 0


// polling code

}
HW_DCP_STAT_CLR(1);
</code>
13.2.7.4 Multi-Buffer Scatter/Gather Cipher and Hash Operation

Programming Example
For this example, three separate buffers are encrypted and hashed with the results being
directed to a unified buffer (gather operation). Three descriptors are used for the operation
because there are three separate source buffer pointers. The DCP reads data from the source
buffer and computes a hash on the unencrypted data. It then encrypts the data and writes it
to the destination buffer. For this example, the key is located in the key RAM, and the
algorithm uses the AES CBC mode of operation with a SHA-1 hash. The payload for the
first operation contains the CBC initialization value, and the payload for the last packet
contains the expected hash value. The middle packet requires no payload. This process is
illustrated below.

Next Packet 1 Address

Source
Ctrl0 Tag 0x00 0x13 0x66
Buffer 0
Ctrl1 SHA1 Key# CBC AES
Src Source Buffer 0 Address
Dst Destination Buffer 0 Address
Bytes Byte Count

Payload
Payld Payload 0 Address
CBC Init
Stat
0x13 = Hash Init | Cipher Init | Encrypt
0x66 = Hash Enable | Cipher Enable | Chain | DecrSema
Next Packet 2 Address

Dest
Ctrl0 Tag 0x00 0x01 0x66 Source Buffer 0
Buffer 1
Dst Destination Buffer 1 Address Dest

Buffer 1
Bytes Byte Count
Payld
Stat
Dest
0x01 = Encrypt Buffer 2
0x66 = Hash Enable | Cipher Enable | Chain | DecrSema
Next
Source
Ctrl0 Tag 0x00 0x61 0x63
Buffer 2
Dst Destination Buffer 2 Address Payload

Bytes Byte Count Hash
Check
Payld Payload 2 Address
Stat
0x61 = Hash Check | Hash Term | Encrypt
0x63 = Hash Enable | Cipher Enable | DecrSema | Interrupt
Figure 13-13. Multi-Buffer Scatter/Gather Cipher and Hash Operation

<code>

{
u32 *next;
u32 *src,
*dst,
buf_size,
*payload,
stat;
} DCP_DESCRIPTOR;
DCP_DESCRIPTOR dcp1, dcp2, dcp3;

u32 *srcbuffer0, *srcbuffer2, *srcbuffer3;
u32 *dstbuffer;
u32 payload0[4], payload2[5];
// set up CBC init in the payload

payload0[0]=0x01234567; // key
payload0[1]=0x89ABCDEF;
payload0[2]=0xfedcba98;
payload0[3]=0x76543210;
payload2[0]=0x00112233; // CBC initialization

payload2[1]=0x44556677;
payload2[2]=0x8899aabb;
payload2[3]=0xccddeeff;
payload2[3]=0xaabbccdd;

dcp1.next = dcp2; // point to packet 2
dcp1.ctrl0.B.CIPHER_INIT = 1; // init CBC for this block (from payload)
dcp1.ctrl0.B.HASH_INIT = 1; // init hash this block
dcp1.ctrl0.B.ENABLE_HASH = 1; // enable cipher
dcp1.ctrl0.B.CHAIN = 1; // chain to next packet
dcp1.ctrl1.B.CIPHER_MODE = BV_DCP_PACKET2_CIPHER_MODE_CBC; //select CBC mode of operation
dcp1.ctrl1.B.HASH_SELECT = BV_DCP_PACKET2_HASH_SELECT_SHA1; // select SHA1 hash
dcp1.ctrl1.B.KEY_SELECT = 2; // select key #2
dcp1.src = srcbuffer0; // source buffer
dcp1.payload = payload0; // holds key/CBC init

dcp2.ctrl0.B.CHAIN = 1; // chain to next packet
dcp2.dst = dstbuffer+512; // destination buffer
dcp2.payload = NULL; // no payload required

dcp3.ctrl0.B.HASH_TERM = 1; // terminate hash block
dcp3.ctrl0.B.HASH_CHECK = 1; // check hash against payload value
dcp3.ctrl0.B.INTERRUPT = 1; // interrupt on completion
dcp3.dst = dstbuffer+1024; // destination buffer
dcp3.payload = payload2; // payload is hash check value
// Enable channel 0
HW_DCP_CHnSEMA_WR(0, 3); // increment semaphore by 3 (for 3 packets)

// polling code

}
HW_DCP_STAT_CLR(1);
</code>

DCP Hardware Register Format Summary
HW_DCP memory map
Absolute
Width Section/
(in bits) page
(hex)
8002_8000 DCP Control Register 0 (HW_DCP_CTRL) 32 R/W F080_0000h 13.3.1/1025
8002_8010 DCP Status Register (HW_DCP_STAT) 32 R/W 1000_0000h 13.3.2/1027
8002_8020 DCP Channel Control Register (HW_DCP_CHANNELCTRL) 32 R/W 0000_0000h 13.3.3/1028
8002_8030 DCP Capability 0 Register (HW_DCP_CAPABILITY0) 32 R/W 0000_0404h 13.3.4/1030
8002_8040 DCP Capability 1 Register (HW_DCP_CAPABILITY1) 32 R/W 0007_0001h 13.3.5/1031
8002_8050 DCP Context Buffer Pointer (HW_DCP_CONTEXT) 32 R/W 0000_0000h 13.3.6/1031
8002_8060 DCP Key Index (HW_DCP_KEY) 32 R/W 0000_0000h 13.3.7/1032
8002_8070 DCP Key Data (HW_DCP_KEYDATA) 32 R/W 0000_0000h 13.3.8/1033
8002_8080 DCP Work Packet 0 Status Register (HW_DCP_PACKET0) 32 R/W 0000_0000h 13.3.9/1034
8002_8090 DCP Work Packet 1 Status Register (HW_DCP_PACKET1) 32 R/W 0000_0000h 13.3.10/1034
8002_80A0 DCP Work Packet 2 Status Register (HW_DCP_PACKET2) 32 R/W 0000_0000h 13.3.11/1036
8002_80B0 DCP Work Packet 3 Status Register (HW_DCP_PACKET3) 32 R/W 0000_0000h 13.3.12/1038
8002_80C0 DCP Work Packet 4 Status Register (HW_DCP_PACKET4) 32 R/W 0000_0000h 13.3.13/1038
8002_80D0 DCP Work Packet 5 Status Register (HW_DCP_PACKET5) 32 R/W 0000_0000h 13.3.14/1039
8002_80E0 DCP Work Packet 6 Status Register (HW_DCP_PACKET6) 32 R/W 0000_0000h 13.3.15/1039
8002_8100 DCP Channel 0 Command Pointer Address Register 32 R/W 0000_0000h 13.3.16/1040
(HW_DCP_CH0CMDPTR)
8002_8110 DCP Channel 0 Semaphore Register (HW_DCP_CH0SEMA) 32 R/W 0000_0000h 13.3.17/1040
8002_8120 DCP Channel 0 Status Register (HW_DCP_CH0STAT) 32 R/W 0000_0000h 13.3.18/1041
8002_8130 DCP Channel 0 Options Register (HW_DCP_CH0OPTS) 32 R/W 0000_0000h 13.3.19/1043
(HW_DCP_CH1CMDPTR)

HW_DCP memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
8002_8160 DCP Channel 1 Status Register (HW_DCP_CH1STAT) 32 R/W 0000_0000h 13.3.22/1046
8002_8170 DCP Channel 1 Options Register (HW_DCP_CH1OPTS) 32 R/W 0000_0000h 13.3.23/1048
(HW_DCP_CH2CMDPTR)
8002_81A0 DCP Channel 2 Status Register (HW_DCP_CH2STAT) 32 R/W 0000_0000h 13.3.26/1050
8002_81B0 DCP Channel 2 Options Register (HW_DCP_CH2OPTS) 32 R/W 0000_0000h 13.3.27/1052
8002_81C0 DCP Channel 3 Command Pointer Address Register 32 R/W 0000_0000h 13.3.28/1053
(HW_DCP_CH3CMDPTR)
8002_81D0 DCP Channel 3 Semaphore Register (HW_DCP_CH3SEMA) 32 R/W 0000_0000h 13.3.29/1054
8002_81E0 DCP Channel 3 Status Register (HW_DCP_CH3STAT) 32 R/W 0000_0000h 13.3.30/1055
8002_81F0 DCP Channel 3 Options Register (HW_DCP_CH3OPTS) 32 R/W 0000_0000h 13.3.31/1056
8002_8400 DCP Debug Select Register (HW_DCP_DBGSELECT) 32 R/W 0000_0000h 13.3.32/1057
8002_8410 DCP Debug Data Register (HW_DCP_DBGDATA) 32 R/W 0000_0000h 13.3.33/1058
8002_8420 DCP Page Table Register (HW_DCP_PAGETABLE) 32 R/W 0000_0000h 13.3.34/1058
8002_8430 DCP Version Register (HW_DCP_VERSION) 32 R/W 0201_0000h 13.3.35/1059
13.3.1 DCP Control Register 0 (HW_DCP_CTRL)

The CTRL register contains controls for the DCP module.
HW_DCP_CTRL: 0x000
HW_DCP_CTRL_SET: 0x004
HW_DCP_CTRL_CLR: 0x008
HW_DCP_CTRL_TOG: 0x00C
The Control register contains the primary controls for the DCP block. The present bits
indicate which of the sub-features of the block are present in the hardware. The context
control bits control how the DCP utilizes it's context buffer and the gather residual writes
bit controls how the master handles writing misaligned data to the bus. Each channel and
the color-space converter contains an independent interrupt enable.
EXAMPLE
HW_DCP_CTRL_SET(BM_DCP_CTRL_SFTRST);
HW_DCP_CTRL_CLR(BM_DCP_CTRL_SFTRST | BM_DCP_CTRL_CLKGATE);

Address: HW_DCP_CTRL – 8002_8000h base + 0h offset = 8002_8000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESENT_SHA
GATHER_RESIDUAL_
PRESENT_
ENABLE_CONTEXT_
ENABLE_CONTEXT_
CRYPTO
R RSVD1 RSVD0[20:16]
SWITCHING
CACHING
CLKGATE
SFTRST
WRITES
W
Reset 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTERRUPT_
RSVD_CSC_
ENABLE
R RSVD0[15:9]
CHANNEL_INTERRUPT_ENABLE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_DCP_CTRL field descriptions

Field Description
31 Set this bit to zero to enable normal DCP operation. Set this bit to one (default) to disable clocking with the
SFTRST DCP and hold it in its reset (lowest power) state. This bit can be turned on and then off to reset the DCP
block to its default state.
CLKGATE
29 Indicates whether the crypto (Cipher/Hash) functions are present.
PRESENT_
0x1 Present —
CRYPTO
0x0 Absent —
28 Indicates whether the SHA1/SHA2 functions are present.
PRESENT_SHA
0x1 Present —
0x0 Absent —
RSVD1
23 Software should set this bit to enable ragged writes to unaligned buffers to be gathered between multiple
GATHER_ write operations. This improves performance by removing several byte operations between write bursts.
RESIDUAL_ Trailing byte writes are held in a residual write data buffer and combined with a subsequent write to the
WRITES buffer to form a word write.
22 Software should set this bit to enable caching of contexts between operations. If only a single channel is
ENABLE_ used for encryption/hashing, enabling caching causes the context to not be reloaded if the channel was the
CONTEXT_ last to be used.
CACHING

HW_DCP_CTRL field descriptions (continued)

Field Description
21 Enable automatic context switching for the channels. Software should set this bit if more than one channel
ENABLE_ is doing hashing or cipher operations that require context to be saved (for instance, when CBC mode is
CONTEXT_ enabled). By disabling context switching, software can save the 208 bytes used for the context buffer.
SWITCHING
RSVD0
8 Reserved, always set to zero.
RSVD_CSC_
INTERRUPT_
ENABLE
7–0 Per-channel interrupt enable bit. When set, the channel's interrupt will get routed to the interrupt controller.
CHANNEL_ Channel 0 is routed to the dcp_vmi_irq signal and the other channels are combined (along with the CRC
INTERRUPT_ interrupt) into the dcp_irq signal.
ENABLE
0x01 CH0 —
0x02 CH1 —
0x04 CH2 —
0x08 CH3 —
13.3.2 DCP Status Register (HW_DCP_STAT)

The DCP Interrupt Status register provides channel interrupt status information.
HW_DCP_STAT: 0x010
HW_DCP_STAT_SET: 0x014
HW_DCP_STAT_CLR: 0x018
HW_DCP_STAT_TOG: 0x01C
This register provides status feedback indicating the channel currently performing an
operation and which channels have pending operations.
EXAMPLE
Address: HW_DCP_STAT – 8002_8000h base + 10h offset = 8002_8010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTP_
R RSVD2 KEY_ CUR_CHANNEL READY_CHANNELS
READY
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD_
R RSVD1 RSVD0
IRQ
IRQ
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_DCP_STAT field descriptions

Field Description
RSVD2
28 When set, indicates that the OTP key has been shifted from the fuse block and is ready for use.
OTP_KEY_
READY
27–24 Current (active) channel (encoded).
CUR_CHANNEL
0x0 None —
0x1 CH0 —
0x2 CH1 —
0x3 CH2 —
0x4 CH3 —
23–16 Indicates which channels are ready to proceed with a transfer (active channel also included). Each bit is a
READY_ one-hot indicating the request status for the associated channel.
CHANNELS
0x01 CH0 —
0x02 CH1 —
0x04 CH2 —
0x08 CH3 —
RSVD1
RSVD_IRQ
RSVD0
3–0 Indicates which channels have pending interrupt requests. Channel 0's interrupt is routed through the
IRQ dcp_vmi_irq and the other interrupt bits are routed through the dcp_irq.
13.3.3 DCP Channel Control Register (HW_DCP_CHANNELCTRL)

The DCP Channel Control register provides controls for channel arbitration and channel
enables.
HW_DCP_CHANNELCTRL: 0x020
HW_DCP_CHANNELCTRL_SET: 0x024
HW_DCP_CHANNELCTRL_CLR: 0x028
HW_DCP_CHANNELCTRL_TOG: 0x02C
This register provides status feedback indicating the channel currently performing an
operation and which channels have pending operations.
EXAMPLE
BW_DCP_CHANNELCTRL_ENABLE_CHANNEL(BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH0); // enable
channel 0
Address: HW_DCP_CHANNELCTRL – 8002_8000h base + 20h offset = 8002_8020h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH0_IRQ_
RSVD
MERGED
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HIGH_PRIORITY_CHANNEL ENABLE_CHANNEL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_DCP_CHANNELCTRL field descriptions

Field Description
RSVD
16 Indicates that the interrupt for channel 0 should be merged with the other interrupts on the shared dcp_irq
CH0_IRQ_ interrupt. When set to 0, channel 0's interrupt will be routed to the separate dcp_vmi_irq. When set to 1, the
MERGED interrupt will be routed to the shared DCP interrupt.
15–8 Setting a bit in this field causes the corresponding channel to have high-priority arbitration. High priority
HIGH_ channels will be arbitrated round-robin and will take precedence over other channels that are not marked
PRIORITY_ as high priority.
CHANNEL
0x01 CH0 —
0x02 CH1 —
0x04 CH2 —
0x08 CH3 —
7–0 Setting a bit in this field will enabled the DMA channel associated with it. This field is a direct input to the
ENABLE_ DMA channel arbiter. When not enabled, the channel is denied access to the central DMA resources.
CHANNEL
0x01 CH0 —
0x02 CH1 —
0x04 CH2 —
0x08 CH3 —

13.3.4 DCP Capability 0 Register (HW_DCP_CAPABILITY0)

This register contains additional information about the DCP module implementation
parameters.
This register provides capability information for the DCP block. It indicates the number of
channels implemented as well as the number of key storage locations available for software
use.
Address: HW_DCP_CAPABILITY0 – 8002_8000h base + 30h offset = 8002_8030h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UNIQUE_KEY
ENABLE_
RSVD[28:16]
DISABLE_
DISABLE_
R
DECRYPT
TZONE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD[15:12] NUM_CHANNELS NUM_KEYS
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0
HW_DCP_CAPABILITY0 field descriptions

Field Description
31 Write to a 1 to disable decryption. This bit can only be written by secure software and the value can only be
DISABLE_ cleared by a reset.
DECRYPT
30 Write to a 1 to enable trustzone support. Channel operations initiated by secure operations will be protected
ENABLE_TZONE from non-secure operations and the secure channel interrupts will be routed to the secure DCP interrupt.
This bit can only be written by secure software and the value can only be cleared by a reset.
29 Write to a 1 to disable the per-device unique key. The device-specific hardware key may be selected by
DISABLE_ using a value of 0xFE in the key select field.
UNIQUE_KEY
RSVD
11–8 Encoded value indicating the number of channels implemented in the design.
NUM_
CHANNELS
7–0 Encoded value indicating the number of key storage locations implemented in the design.
NUM_KEYS

13.3.5 DCP Capability 1 Register (HW_DCP_CAPABILITY1)

This register contains information about the algorithms available on the implementation.
This register provides capability information for the DCP block. It contains two fields
indicating which encryption and hashing algorithms are present in the design. Each bit set
indicates that support for the associated function is present.
Address: HW_DCP_CAPABILITY1 – 8002_8000h base + 40h offset = 8002_8040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R HASH_ALGORITHMS CIPHER_ALGORITHMS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
set
HW_DCP_CAPABILITY1 field descriptions

Field Description
31–16 One-hot field indicating which hashing features are implemented in HW.
HASH_
0x0001 SHA1 —
ALGORITHMS
0x0002 CRC32 —
0x0004 SHA256 —
15–0 One-hot field indicating which cipher algorithms are available.
CIPHER_
0x0001 AES128 —
ALGORITHMS
13.3.6 DCP Context Buffer Pointer (HW_DCP_CONTEXT)

This register contains a pointer to the memory region to be used for DCP context swap
operations.
This register contains a pointer to the start of the context pointer memory in on-chip SRAM
or off-chip SDRAM. This buffer will be used to store state information when the DCP
module changes from one channel to another.
Address: HW_DCP_CONTEXT – 8002_8000h base + 50h offset = 8002_8050h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

HW_DCP_CONTEXT field descriptions

Field Description
31–0 Context pointer address. Address should be located in system RAM and should be word-aligned for optimal
ADDR performance.
13.3.7 DCP Key Index (HW_DCP_KEY)

This register contains a pointer to the key location to be written.
The DCP module maintains a set of write-only keys that may be used by software. To write
a key, software must first write the desired key index/subword to this register and then write
the key values to the key registers (below). After each write to the key data register, the
SUBWORD field will increment to allow software to write the subsequent key to be written
without having to rewrite the key index.
EXAMPLE
// write key 0 to 0x00112233_44556677_8899aabb_ccddeeff

HW_DCP_KEY_WR(BF_DCP_KEY_INDEX(0) | BF_DCP_KEY_SUBWORD(0)); // set key index to key 0, subword
0
HW_DCP_KEYDATA_WR(0xccddeeff); // write key values (subword 0)
HW_DCP_KEYDATA_WR(0x8899aabb); // write key values (subword 1)
HW_DCP_KEYDATA_WR(0x44556677); // write key values (subword 2)
Address: HW_DCP_KEY – 8002_8000h base + 60h offset = 8002_8060h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD_
R RSVD[15:8] RSVD_INDEX
SUBWORD
INDEX SUBWORD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_DCP_KEY field descriptions

Field Description
RSVD

HW_DCP_KEY field descriptions (continued)

Field Description
RSVD_INDEX
5–4 Key index pointer. Valid indices are 0-[number_keys].
INDEX
RSVD_
SUBWORD
1–0 Key subword pointer. Valid indices are 0-3. After each write to the key data register, this field will increment.
SUBWORD
13.3.8 DCP Key Data (HW_DCP_KEYDATA)

This register provides write access to the key/key subword specified by the Key Index
Register.
Writing this location updates the selected subword for the key located at the index specified
by the Key Index Register. A write also triggers the SUBWORD field of the KEY register
to increment to the next higher word in the key.
EXAMPLE
// write key 0 to 0x00112233_44556677_8899aabb_ccddeeff

HW_DCP_KEY_WR(BF_DCP_KEY_INDEX(0) | BF_DCP_KEY_SUBWORD(0)); // set key index to key 0, subword
0
HW_DCP_KEYDATA_WR(0xccddeeff); // write key values (subword 0)
HW_DCP_KEYDATA_WR(0x8899aabb); // write key values (subword 1)
Address: HW_DCP_KEYDATA – 8002_8000h base + 70h offset = 8002_8070h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DATA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_DCP_KEYDATA field descriptions

Field Description
31–0 Word 0 data for key. This is the least-significant word.
DATA

13.3.9 DCP Work Packet 0 Status Register (HW_DCP_PACKET0)

This register displays the values for the current work packet offset 0x00 (Next Command)
field.
The Work Packet Status Registers show the contents of the currently executing packet.
When the channels are inactive, the packet status register return 0. The register bits are fully
documented here to document the packet structure in memory.
Address: HW_DCP_PACKET0 – 8002_8000h base + 80h offset = 8002_8080h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_DCP_PACKET0 field descriptions

Field Description
31–0 Next Pointer Register,
ADDR

This register displays the values for the current work packet offset 0x04 (control) field.
This register shows the contents of the Control0 register from the packet being processed.
Address: HW_DCP_PACKET1 – 8002_8000h base + 90h offset = 8002_8090h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CONSTANT_FILL
TEST_SEMA_
BYTESWAP
BYTESWAP
BYTESWAP
WORDSWAP
WORDSWAP
WORDSWAP
OUTPUT_
OUTPUT_
INPUT_
INPUT_
KEY_
KEY_
IRQ
R TAG
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENABLE_HASH
PAYLOAD_KEY
CHECK_HASH
ENABLE_BLIT
CIPHER_INIT
HASH_TERM
SEMAPHORE
CONTIGUOUS
HASH_INIT
MEMCOPY
INTERRUPT
ENCRYPT
ENABLE_
ENABLE_
CIPHER_
OUTPUT
CIPHER
HASH_
CHAIN
DECR_
CHAIN_
OTP_
R
KEY
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
31–24 Packet Tag
TAG
23 Reflects whether the DCP engine will wordswap output data (big-endian data).
OUTPUT_
WORDSWAP
22 Reflects whether the DCP engine will byteswap output data (big-endian data).
OUTPUT_
BYTESWAP
21 Reflects whether the DCP engine will wordswap input data (big-endian data).
INPUT_
WORDSWAP
20 Reflects whether the DCP engine will byteswap input data (big-endian data).
INPUT_
BYTESWAP
19 Reflects whether the DCP engine will swap key words (big-endian key).
KEY_
WORDSWAP
18 Reflects whether the DCP engine will swap key bytes (big-endian key).
KEY_
BYTESWAP
17 This bit is used to test the channel semaphore transition to 0. FOR TEST USE ONLY!
TEST_SEMA_
IRQ
16 When this bit is set (MEMCOPY and BLIT modes only), the DCP will simply fill the destination buffer with
CONSTANT_FILL the value found in the
Source Address field.
15 When hashing is enabled, this bit controls whether the input or output data is hashed.
HASH_OUTPUT
0x00 INPUT —
0x01 OUTPUT —
14 Reflects whether the calculated hash value should be compared against the hash provided in the payload.
CHECK_HASH

HW_DCP_PACKET1 field descriptions (continued)

Field Description
13 Reflects whether the current hashing block is the final block in the hashing operation, so the hash padding
HASH_TERM should be applied by hardware.
12 Reflects whether the current hashing block is the initial block in the hashing operation, so the hash registers
HASH_INIT should be initialized before the operation.
11 When set, indicates the payload contains the key. This bit takes precedence over the OTP_KEY control
PAYLOAD_KEY
10 Reflects whether a hardware-based key should be used. The KEY_SELECT field from the Control1 field is
OTP_KEY used to select from multiple hardware keys. The PAYLOAD_KEY bit takes precedence over the OTP_KEY
bit.
9 Reflects whether the cipher block should load the initialization vector from the payload for this operation.
CIPHER_INIT
8 When the cipher block is enabled, this bit indicates whether the operation is encryption or decryption.
CIPHER_
0x01 ENCRYPT —
ENCRYPT
0x00 DECRYPT —
7 Reflects whether the DCP should perform a blit operation. Source data is always continuous and the
ENABLE_BLIT destination buffer is written in run/stride format. When set, the
BUFFER_SIZE field is treated as two 16-bit values for the X-Y extents of the blit operation.
6 Reflects whether the selected hashing function should be enabled for this operation.
ENABLE_HASH
5 Reflects whether the selected cipher function should be enabled for this operation.
ENABLE_
CIPHER
4 Reflects whether the selected hashing function should be enabled for this operation.
ENABLE_
MEMCOPY
3 Reflects whether the next packet's address is located following this packet's payload.
CHAIN_
CONTIGUOUS
2 Reflects whether the next command pointer register should be loaded into the channel's current descriptor
CHAIN pointer.
1 Reflects whether the channel's semaphore should be decremented at the end of the current operation. When
DECR_ the semaphore reaches a value
SEMAPHORE
of zero, no more operations will be issued from the channel.
0 Reflects whether the channel should issue an interrupt upon completion of the packet.
INTERRUPT

This register displays the values for the current work packet offset 0x08 (Control1) field.

This register shows the contents of the Control0 register from the packet being processed.
Address: HW_DCP_PACKET2 – 8002_8000h base + A0h offset = 8002_80A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CIPHER_CFG RSVD HASH_SELECT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R KEY_SELECT CIPHER_MODE CIPHER_SELECT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
31–24 Cipher configuration bits. Optional configuration bits required for ciphers
CIPHER_CFG
RSVD
19–16 Hash Selection Field
HASH_SELECT
0x00 SHA1 —
0x01 CRC32 —
0x02 SHA256 —
15–8 Key Selection Field. The value here reflects the key index for the cipher operation. Values 0-3 refer to the
KEY_SELECT software keys that can be written to the key RAM. The OTP key or the unique device-specific key may also
be selected with a value of 0xFF (OTP key) or 0xFE (unique key).
0x00 KEY0 —
0x01 KEY1 —
0x02 KEY2 —
0x03 KEY3 —
0xFE UNIQUE_KEY —
0xFF OTP_KEY —
7–4 Cipher Mode Selection Field. Reflects the mode of operation for cipher operations.
CIPHER_MODE
0x00 ECB —
0x01 CBC —
3–0 Cipher Selection Field
CIPHER_
0x00 AES128 —
SELECT


This register displays the values for the current work packet offset 0x0C (Source Address)
field.
This register shows the contents of the Source Address register from the packet being
processed. When the CONSTANT_FILL bit in the Control 0 field is set, this field contains
the data written to the destination buffer.
Address: HW_DCP_PACKET3 – 8002_8000h base + B0h offset = 8002_80B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Source Buffer Address Pointer. This value is the working value and will update as the operation proceeds.
ADDR

This register displays the values for the current work packet offset 0x10 (Destination Address)
field.
This register shows the contents of the Destination Address register from the packet being
processed.
Address: HW_DCP_PACKET4 – 8002_8000h base + C0h offset = 8002_80C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Destination Buffer Address Pointer. This value is the working value and will update as the operation proceeds.
ADDR


This register displays the values for the current work packet offset 0x14 (Buffer Size) field.
This register shows the contents of the bytecount register from the packet being processed.
The field can be considered either a byte count or a buffer size. The logic treats this as a
decrmenting count of bytes from the buffer size programmed into the field. As the transaction
proceeds, the logic will decrement the bytecount as data is written to the destination buffer.
For blit operations, the top 16-bits of this field represents the number of lines (y size) in the
blit and the lower 16-bits represent the number of bytes in a line (x size).
Address: HW_DCP_PACKET5 – 8002_8000h base + D0h offset = 8002_80D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Byte Count register. This value is the working value and will update as the operation proceeds.
COUNT

This register displays the values for the current work packet offset 0x1C (Payload Pointer)
field.
This register shows the contents of the payload pointer fieldr from the packet being processed.
Address: HW_DCP_PACKET6 – 8002_8000h base + E0h offset = 8002_80E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 This regiser reflects the payload pointer for the current control packet.
ADDR

13.3.16 DCP Channel 0 Command Pointer Address Register

(HW_DCP_CH0CMDPTR)
The DCP channel 0 current command address register points to the multiword descriptor
that is to be executed (or currently being executed). The channel may be activated by writing
the command pointer address to a valid descriptor in memory and then updating the
semaphore to a non-zero value. After the engine completes processing of a descriptor, the
next_ptr field from the descriptor is moved into this register to enable processing of the
next descriptor. All channels with a non-zero semaphore value will arbitrate for access to
the engine for the subsequent operation.
DCP Channel 0 is controlled by a variable sized command structure. This register points
to the command structure to be executed.
EXAMPLE
HW_DCP_CHnCMDPTR_WR(0, v); // Write channel 0 command pointer

pCurptr = (hw_DCP_chncmdptr_t *) HW_DCP_CHnCMDPTR_RD(0); // Read current command
pointer
Address: HW_DCP_CH0CMDPTR – 8002_8000h base + 100h offset = 8002_8100h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_DCP_CH0CMDPTR field descriptions

Field Description
31–0 Pointer to descriptor structure to be processed for channel 0.
ADDR
13.3.17 DCP Channel 0 Semaphore Register (HW_DCP_CH0SEMA)

The DCP Channel 0 semaphore register is used to synchronize the CPU instruction stream
and the DMA chain processing state. After a command chain has been generated in memory,
software should write the address of the first command descriptor to the CMDPTR register
and then write a non-zero value to the semaphore register to indicate that the channel is
active. Each command packet has a chaining bit which indicates that another descriptor
should be loaded into the channel upon completion of the current descriptor. If the chaining
bit is not set, the next address will not be loaded into the CMDPTR register. Each packet

also contains a decrement semaphore bit, which indicates that the counting semaphore
should be decremented after the operation. A channel is considered active when the
semaphore is a non-zero value. When programming a series operations, software must
properly program the semaphore values in conjunction with the decrement_semaphore bits
in the control packets to ensure that the proper number of descriptors are activated. A
semaphore may be cleared by software by writing 0xFF to the HW_DCP_CHnSEMA_CLR
register. The logic will also clear the semaphore if an error has occurred.
Each DCP channel has an 8 bit counting semaphore that is used to synchronize between
the program stream and and the DCP chain processing. After processing each control packet,
the DCP decrements the semaphore if it is non-zero. The channel will continue processing
packets as long as the semaphore contains a non-zero value and the CHAIN or
CHAIN_CONTIGOUS control bits in the Control0 field are set.
Address: HW_DCP_CH0SEMA – 8002_8000h base + 110h offset = 8002_8110h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 VALUE RSVD1

INCREMENT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_DCP_CH0SEMA field descriptions

Field Description
RSVD2
VALUE
RSVD1
INCREMENT software adds and DCP hardware substracts happening on the same clock are protected. This bit field reads
back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DCP
channel decrements the count on the same clock, then the count is incremented by a net one.The semaphore
may be cleared by writing 0xFF to the HW_DCP_CHnSEMA_CLR register.
13.3.18 DCP Channel 0 Status Register (HW_DCP_CH0STAT)

The DCP Channel 0 Interrupt Status register contains the interrupt status bit and the tag of
the last completed operation from the command chain. If an error occurs during processing,
the ERROR bit is set and an interrupt is generated.
HW_DCP_CH0STAT: 0x120

HW_DCP_CH0STAT_SET: 0x124
HW_DCP_CH0STAT_CLR: 0x128
HW_DCP_CH0STAT_TOG: 0x12C
The interrupt status register is updated at the end of each work packet. If the interrupt bit
is set in the command packet's command field, an interrupt will be generated once the packet
has completed. In addition, the tag value from the command is stored in the TAG field so
that software can identify which command structure was the last to complete. If an error
occurs, the ERROR bit is set and processing of the command chain is halted.
Address: HW_DCP_CH0STAT – 8002_8000h base + 120h offset = 8002_8120h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R TAG
ERROR_CODE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMPLETE
ERROR_PAGEFAULT
RSVD_
HASH_MISMATCH
ERROR_PACKET
ERROR_SETUP
R RSVD0
ERROR_SRC
ERROR_DST
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_DCP_CH0STAT field descriptions

Field Description
31–24 Indicates the tag from the last completed packet in the command structure
TAG
23–16 Indicates additional error codes for some error conditions.
ERROR_CODE
0x01 NEXT_CHAIN_IS_0 — Error signalled because the next pointer is 0x00000000
0x02 NO_CHAIN — Error signalled because the semaphore is nonzero and neither chain bit is set
0x03 CONTEXT_ERROR — Error signalled because an error was reported reading/writing the context
buffer
0x04 PAYLOAD_ERROR — Error signalled because an error was reported reading/writing the payload
0x05 INVALID_MODE — Error signalled because the control packet specifies an invalid mode select (for
instance, blit + hash)

HW_DCP_CH0STAT field descriptions (continued)

Field Description
RSVD0
6 This bit indicates a page fault occurred while converting a virtual address to a physical address.. When an
ERROR_ error is detected, the channel's processing will stop until the error handled by software.
PAGEFAULT
5 This bit indicates a bus error occurred when storing to the destination buffer. When an error is detected, the
ERROR_DST channel's processing will stop until the error handled by software.
4 This bit indicates a bus error occurred when reading from the source buffer. When an error is detected, the
ERROR_SRC channel's processing will stop until the error handled by software.
3 This bit indicates that a a bus error occurred when reading the packet or payload or when writing status
ERROR_ back to the packet payload. When an error is detected, the channel's processing will stop until the error is
PACKET handled by software.
2 This bit indicates that the hardware has detected an invalid programming configuration such as a buffer
ERROR_SETUP length that is not a multiple of the natural data size for the operation. When an error is detected, the channel's
processing will stop until the error is handled by software.
1 The bit indicates that a hashing check operation mismatched for control packets that enable the
HASH_ HASH_CHECK bit. When an error is detected, the channel's processing will stop until the error is handled
MISMATCH by software.
0 This bit will always read 0 in the status register, but will be set to 1 in the packet status field after processing
RSVD_ of the packet has completed. This was done so that software can verify that each packet completed properly
COMPLETE in a chain of commands for cases when an interrupt is issued only for the last item in a packet. The completion
bit for the channel is effectively the channel interrupt status bit.
13.3.19 DCP Channel 0 Options Register (HW_DCP_CH0OPTS)

The DCP Channel 0 Options Status register contains optional control information that may
be used to further tune the behavior of the channel.
HW_DCP_CH0OPTS: 0x130
HW_DCP_CH0OPTS_SET: 0x134
HW_DCP_CH0OPTS_CLR: 0x138
HW_DCP_CH0OPTS_TOG: 0x13C
The options register can be used to control optional features of the channels.

Address: HW_DCP_CH0OPTS – 8002_8000h base + 130h offset = 8002_8130h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD
RECOVERY_TIMER
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_DCP_CH0OPTS field descriptions

Field Description
RSVD
15–0 This field indicates the recovery time for the channel. After each operation, the recover timer for the channel
RECOVERY_ is initiallized with this value and then decremented until the timer reaches zero. The channel will not initiate
TIMER another operation for the next packet in the chain until the recovery time has been satisfied. The timebase
for the recovery timer is 16 HCLK clock cycles, providing a range of 0ns to 8.3ms at 133 MHz operation.

(HW_DCP_CH1CMDPTR)
EXAMPLE
HW_DCP_CHn_CMDPTR_WR(1, v); // Write channel 1 command pointer

pCurptr = (hw_DCP_chn_cmdptr_t *) HW_DCP_CHn_CMDPTR_RD(1); // Read current command
pointer

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
ADDR

the program stream and and the DCP chain processing. DCP processing continues until the
engine attempts to decrement a semaphore that has already reached a value of zero. When
the attempt is made, the DCP channel is stalled until software increments the semaphore
count.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 VALUE RSVD1

INCREMENT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
VALUE

HW_DCP_CH1SEMA field descriptions (continued)

Field Description
RSVD1

HW_DCP_CH1STAT: 0x160
HW_DCP_CH1STAT_SET: 0x164
HW_DCP_CH1STAT_CLR: 0x168
HW_DCP_CH1STAT_TOG: 0x16C
Address: HW_DCP_CH1STAT – 8002_8000h base + 160h offset = 8002_8160h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R TAG
ERROR_CODE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMPLETE
ERROR_PAGEFAULT
RSVD_
HASH_MISMATCH
ERROR_PACKET
ERROR_SETUP
R RSVD0
ERROR_SRC
ERROR_DST
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
TAG
ERROR_CODE
buffer
RSVD0
PAGEFAULT
3 This bit indicates that a bus error occurs when reading the packet or payload or when writing status back
ERROR_ to the packet paylaod. When an error is detected, the channel's processing will stop until the error is handled
PACKET by software.
2 This bit indicates that the hardware detected an invalid programming configuration such as a buffer length
ERROR_SETUP that is not a multiple of the natural data size for the operation. When an error is detected, the channel's


HW_DCP_CH1OPTS: 0x170
HW_DCP_CH1OPTS_SET: 0x174
HW_DCP_CH1OPTS_CLR: 0x178
HW_DCP_CH1OPTS_TOG: 0x17C
Address: HW_DCP_CH1OPTS – 8002_8000h base + 170h offset = 8002_8170h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD
RECOVERY_TIMER
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD
TIMER operation on the next packet in the chain until the recovery time has been satisfied. The timebase for the
recovery timer is 16 HCLK clock cycles, providing a range of 0ns to 8.3ms at 133 MHz operation.

(HW_DCP_CH2CMDPTR)

EXAMPLE

pointer

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDR


count.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 VALUE RSVD1

INCREMENT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
VALUE
RSVD1

HW_DCP_CH2STAT: 0x1A0
HW_DCP_CH2STAT_SET: 0x1A4
HW_DCP_CH2STAT_CLR: 0x1A8
HW_DCP_CH2STAT_TOG: 0x1AC

Address: HW_DCP_CH2STAT – 8002_8000h base + 1A0h offset = 8002_81A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R TAG
ERROR_CODE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMPLETE
ERROR_PAGEFAULT
RSVD_
HASH_MISMATCH
ERROR_PACKET
ERROR_SETUP
R RSVD0
ERROR_SRC
ERROR_DST
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
TAG
ERROR_CODE
buffer
RSVD0
PAGEFAULT

HW_DCP_CH2STAT field descriptions (continued)

Field Description
3 This bit indicates that a bus error occurred when reading the packet or payload or when writing status back
PACKET by software.

HW_DCP_CH2OPTS: 0x1B0
HW_DCP_CH2OPTS_SET: 0x1B4
HW_DCP_CH2OPTS_CLR: 0x1B8
HW_DCP_CH2OPTS_TOG: 0x1BC
Address: HW_DCP_CH2OPTS – 8002_8000h base + 1B0h offset = 8002_81B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD
RECOVERY_TIMER
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
RSVD

(HW_DCP_CH3CMDPTR)
EXAMPLE

pointer
Address: HW_DCP_CH3CMDPTR – 8002_8000h base + 1C0h offset = 8002_81C0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
ADDR


count.
Address: HW_DCP_CH3SEMA – 8002_8000h base + 1D0h offset = 8002_81D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 VALUE RSVD1

INCREMENT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
VALUE
RSVD1


HW_DCP_CH3STAT: 0x1E0
HW_DCP_CH3STAT_SET: 0x1E4
HW_DCP_CH3STAT_CLR: 0x1E8
HW_DCP_CH3STAT_TOG: 0x1EC
Address: HW_DCP_CH3STAT – 8002_8000h base + 1E0h offset = 8002_81E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R TAG
ERROR_CODE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMPLETE
ERROR_PAGEFAULT
RSVD_
HASH_MISMATCH
ERROR_PACKET
ERROR_SETUP
R RSVD0
ERROR_SRC
ERROR_DST
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Field Description
TAG
ERROR_CODE
buffer
RSVD0
PAGEFAULT
3 This bit indicates that a bus error occurred when reading the packet or payload or when writing status back
PACKET by software.

HW_DCP_CH3OPTS: 0x1F0
HW_DCP_CH3OPTS_SET: 0x1F4

HW_DCP_CH3OPTS_CLR: 0x1F8
HW_DCP_CH3OPTS_TOG: 0x1FC
Address: HW_DCP_CH3OPTS – 8002_8000h base + 1F0h offset = 8002_81F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD
RECOVERY_TIMER
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD
13.3.32 DCP Debug Select Register (HW_DCP_DBGSELECT)

This register selects a debug register to view.
This register selects debug information to return in the debug data register.
Address: HW_DCP_DBGSELECT – 8002_8000h base + 400h offset = 8002_8400h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD
INDEX
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_DCP_DBGSELECT field descriptions

Field Description
RSVD
7–0 Selects a value to read through the debug data register.
INDEX
0x01 CONTROL —
0x10 OTPKEY0 —
0x11 OTPKEY1 —
0x12 OTPKEY2 —

HW_DCP_DBGSELECT field descriptions (continued)

Field Description
0x13 OTPKEY3 —
13.3.33 DCP Debug Data Register (HW_DCP_DBGDATA)

Reading this register returns the debug data value from the selected index.
This register returns the debug data from the selected debug index source.
Address: HW_DCP_DBGDATA – 8002_8000h base + 410h offset = 8002_8410h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DATA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_DCP_DBGDATA field descriptions

Field Description
31–0 Debug Data
DATA
13.3.34 DCP Page Table Register (HW_DCP_PAGETABLE)

The DCP Page Table register controls the virtual memory functionality of the DCP. It
provides a base address for the page table as well as an enable/disable bit and the ability to
flush the cached page table entries.
Address: HW_DCP_PAGETABLE – 8002_8000h base + 420h offset = 8002_8420h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BASE[31:16]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENABLE
FLUSH
BASE[15:2]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_DCP_PAGETABLE field descriptions

Field Description
31–2 Page Table Base Address. The page table must be word aligned and the pointer should reference a page
BASE table in the standard ARM format.
1 Page Table Flush control. To flush the TLB, write this bit to a 1 then back to a 0.
FLUSH
0 Page Table Enable control. Virtual addressing will only be used when this bit is set to a 1. Disabling the
ENABLE page table will not flush any cached entries, so software should write the FLUSH high and enable LOW
when updating page tables.
13.3.35 DCP Version Register (HW_DCP_VERSION)

Read-only register indicating implemented version of the DCP.
Address: HW_DCP_VERSION – 8002_8000h base + 430h offset = 8002_8430h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MAJOR MINOR STEP

W
Re- 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_DCP_VERSION field descriptions

Field Description
31–24 Fixed read-onlyl value reflecting the MAJOR version of the design implementation.
MAJOR
23–16 Fixed read-onlyl value reflecting the MINOR version of the design implementation.
MINOR
15–0 Fixed read-onlyl value reflecting the stepping of version of the design implementation.
STEP

Disclaimer
13.4 Disclaimer
The license for the AEC code is documented here for compliance:
Copyright (C) 2000-2003, ASICS World Services, LTD., AUTHORS
All rights reserved. Redistribution and use in source, netlist, binary and silicon forms, with
or without modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list of conditions
and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of
conditions and the following disclaimer in the documentation and/or other materials provided
with the distribution.
Neither the name of ASICS World Services, the Authors and/or the names of its contributors
may be used to endorse or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE

Chapter 14
External Memory Interface (EMI)
14.1 Overview
The i.MX28 supports off-chip DRAM storage through the EMI controller, which is connected
to the four internal AHB/AXI busses. The EMI supports multiple external memory types,
including the following:
• 1.8-V mobile DDR1 (LP-DDR1)
• Standard 1.8 V DDR2
• Low-voltage 1.5 V DDR2 (LV-DDR2)
The EMI uses two primary clocks: the AHB bus, HCLK, and the DRAM source clock,
EMI_CLK. The maximum specified frequencies for these two clocks are 200 MHz. The
HCLK and EMI_CLK can be either synchronous or asynchronous, configurable.
The EMI consists of the following 3 major components:
• AXI/AHB bus interface and multi-port arbiter
• DRAM Control Logic
• DRAM PHY
14.1.1 Block Diagram

A high-level block diagram of the EMI is shown in the following figure.

EMI Address Mapping
EMI
AXI
AXI - 64 Bus
Interface
Arbiter
&
AHB-2-AXI AXI
AHB - 32 Read/Write
Bridge Interface DDR
Command DDR External
Control DFI
Queue PHY DDR Memory
AHB-2-AXI AXI Logic
AHB - 32 &
Bridge Interface
Read/Write
Data
AHB-2-AXI AXI
AHB - 32 Queues
Bridge Interface
AHB
AHB - 32 Programmable Register Settings
Register Port
Figure 14-1. EMI Top-Level Block Diagram
EMI implements the following five bus interfaces:

• One 64-bit AXI bus interface
• Three 32-bit AHB bus interfaces to read or write data from or to external DDR memory
• One AHB interface dedicated to read/write PIO registers
14.2 EMI Address Mapping

The EMI automatically maps AXI and AHB bus addresses to the DRAM memory in a
contiguous block. Addressing starts at user address 0 and ends at the highest available
address according to the size and number of DRAM devices present. This mapping is
dependent on how the memory controller was configured and how the parameters in the
internal EMI registers are programmed. The exact number and values of these parameters
depends on the configuration and the type of memory for which the memory controller was
designed.
The mapping of the address space to the internal data storage structure of the DRAM devices
is based on the actual size of the DRAM devices available. The size is stored in
user-programmable parameters that must be initialized at power up. Certain DRAM devices
allow for different mapping options to be chosen, while other DRAM devices depend on
the burst length chosen.

Chapter 14 External Memory Interface (EMI)
14.2.1 DDR SDRAM Address Mapping Options

The address structure of DDR SDRAM devices contains five fields. Each of these fields
can be individually addressed when accessing the DRAM. The address map for this EMI
is ordered as follows:
Chip Select → Row → Bank → Column → Data Path
The maximum widths of the fields are based on the configuration settings. The actual widths
of the fields may be smaller if the device address width parameters (addr_pins,
eight_bank_mode, and column_size) are programmed differently.
• Chip Select—EMI supports 2 chip-select. The “Chip Select” field occupies 1-bit.
• Datapath—EMI supports 16-bit data width for external DDR memory. The “Datapath”
field occupies 1-bit.
• Bank—The DDR memory device defines the bank number. The EMI supports 4 or 8
banks of DDR memory, which occupies 2 or 3-bits
• Row, Column—The DDR memory device defines the width of these fields
14.2.2 Maximum Address Space

The maximum user address range is determined by the width of the memory datapath, the
number of chip select pins, and the address space of the DRAM device. The maximum
amount of memory can be calculated by the following formula:
chip-selects x bank x 2^(row + column) x datapath (unit: byte)
For this DRAM controller, the maximum values for these fields are as follows:
• Chip Selects = 2
• Bank : 4 or 8, max 8
• Row : max 15-bits
• Column : max 12-bits
• Datapath width = 2 bytes (16-bits)
As a result, the maximum memory area supported by EMI module is 4 Gbytes. But in
i.MX28, the system memory-map limits the maximum accessible area to 1 Gbytes.

EMI Clocking
14.2.3 Memory Mapping to Address Space

The following figures provide examples of address space mapping from a 32-bit bus address
to DRAM address fields. The first example corresponds to a memory device with 8 banks,
13 row bits, and 10 column bits. The second example corresponds to a memory device with
8 banks, 14 row bits, and 10 column bits.
dont care chip-select row bank column datapath
[31:29] [28] [27:14] [13:11] [10:1] [0]
Figure 14-2. Memory Address Mapping Example 1
dont care chip-select row bank column datapath

[31:28] [27] [26:14] [13:11] [10:1] [0]
Figure 14-3. Memory Address Mapping Example 2
14.3 EMI Clocking

The EMI uses an external clock input from the ASIC device. Considering the design speed
and complexity, this design may not be able to adhere to the skew and delay requirements
of a PLL-based clocking scheme. As an alternative, this EMI uses a clocking system that
propagates a clock from the memory controller to the memory devices. The largest challenge
with this clock forwarding scheme is the management of the clock skew for the round-trip
data transfer.
14.3.1 General System Behavior

In this system, the command and address for the transaction are sent from the memory
controller coincident with the falling edge of the memory controller clock. Because the
clock, command, and address signals all have roughly the same pad and flight delays to
travel to the memory, the rising edge of the clock at the memory is centered with the
command and address signals, allowing reliable capture. In addition, because all signals
are sourced from the same location, this clocking system can tolerate a significant skew
and provides more flexibility in timing.
14.3.2 Changing Input Clock Frequency

The operating frequency of the EMI is dependent on an ASIC-level input clock. There are
situations in which the user may wish to modify the frequency of the clock without resetting
the memory controller. To change the clock frequency at which the EMI operates, the

memory controller must stop processing requests, the clock must be adjusted, the memory
controller’s timing parameters must be reprogrammed, and then the memory controller can
be restarted. The procedure to follow for changing the clock frequency is as follows:
1. Ensure that the EMI is idle, which is when the controller_busy signal is low.
2. Put the memory devices into self-refresh mode by asserting the srefresh parameter to
‘b1. It is imperative that the memory devices be placed into self-refresh through this
parameter and not through any other means. If the devices were placed into self-refresh
mode through one of the low-power modes (programming of the lowpower_control
parameter), then the user should first bring the devices out of that low power mode
manually and then program the srefresh parameter with a ‘b1.
3. Wait until the memory devices have been placed into self-refresh mode, as indicated
by the cke_status signal. This signal is the value of the control_cke signal inside the
memory controller, delayed by the number of clocks specified in the cke_delay
parameter.
4. Mask the DLL lock state change bit (bit 8) in the int_status parameter by setting bit 8
in the int_mask parameter to ‘b1.
5. Stop the memory controller by writing a ‘b0 to the start parameter.
6. Clear the DLL lock state change bit (bit 8) in the int_status parameter by writing bit 8
in the int_ack parameter to ‘b1. Also, clear any other interrupts in the int_status
parameter by writing to the int_ack parameter.
7. If the user wishes to use a controller interrupt to signal when the DLL has relocked,
then unmask the DLL lock state change bit (bit 8) in the int_status parameter by clearing
bit 8 in the int_mask parameter to a ‘b0. If the user wishes to poll the dlllockreg
parameter for this indication, then this step may be skipped.
8. The clock frequency may now be changed. Once the clock frequency has stabilized,
the user should modify any parameters that may be affected by the frequency change
such as caslat_lin, caslat_lin_gate, any of the timing parameters, and so on. The user
should review the parameters carefully to ensure that all parameters that require
modification are changed.
9. After all parameters have been updated, restart the EMI by writing a ‘b1 to the start
parameter. This forces the DLL to lock to the new frequency.
10. Once the DLL has locked and the PHY has initialized, the memory controller input
signal dfi_init_complete will be asserted. If the user is using a controller interrupt to
monitor DLL re-lock, then wait for a controller interrupt or poll the int_status parameter
for the DLL lock state change bit (bit 8) to be set. If the controller interrupt is not being
used, poll the dlllockreg parameter for the bit to be set.
11. At this point, the user may bring the memory devices out of self-refresh by clearing the
srefresh parameter to ‘b0. The user does not need to wait to send commands to the
memory controller after clearing the srefresh parameter; the memory controller will
adjust for self-refresh exit time before processing memory commands.

EMI AHB and AXI Interface
14.4 EMI AHB and AXI Interface

This section discusses how to cofingure and use the EMI AHB and AXI interface.
14.4.1 AHB-AXI Bridges

An incoming AHB transaction is translated to an AXI command in the AHB-AXI bridge.
The AHB-AXI bridges support the AHB-lite protocol and are designed for multilayer AHB
architectures. This implies that an AHB slave port never responds with a SPLIT or a RETRY
response type. Early termination of AHB bursts is fully supported.
Note that an the AHB slave port can be used in a system with masters that support the full
AHB protocol as long as the system is multilayer AHB. For simplicity, the AHB-AXI
bridges do not support exclusive access or lock accesses.
14.4.2 AXI Interfaces

The AXI interfaces function as AXI slaves to the AHB-AXI bridges. Transfers are
burst-based of variable byte counts. The transfer types INCR and WRAP are fully supported.
FIXED burst types are not supported.
Each interface contains five separate channels of traffic to/from the memory: write response,
read command, write command, read data, and write data.
14.4.2.1 Internal Command Handling

The EMI uses placement logic to fill the command queue with a command order that
maximizes the throughput and efficiency of the core logic. Command reordering in the
placement queue supports AXI and AHB restrictions.
Note: The AHB bus does not allow multiple threads on a single port; therefore, ports with
an AHB-AXI bridge only use thread ID “0” for all commands.
Note: For simplicity, ports that connect to an AHB bus through an AHB-AXI bridge will
be referenced as “AHB-bridged” ports. Ports that connect directly to an AXI bus will be
referenced as “native AXI” ports.
If the placement logic is being used, the EMI will optimize the core by re-ordering read and
write commands as necessary based on these rules:

• For the AHB-bridged ports, read commands will always execute in the same order as
they were accepted into the port. Similarly, write commands will always execute in the
same order as they were accepted into the port.
• For the native AXI ports, read commands from the same thread ID will always execute
in the same order as they were accepted into the port. However, read commands from
different thread IDs on the native AXI ports may be automatically re-arranged in the
core logic to execute out-of-order. When commands from different thread IDs are
re-ordered, read data returned to the AXI port interfaces will also be out-of-order and
may be interleaved. To avoid re-ordering within a port, the AXI bus master should use
one thread ID for all commands from any port.
• For the native AXI ports, write commands from the same or different thread IDs will
always execute in the same order as they were accepted into the port.
• Read or Write commands from different AHB-bridged or native AXI ports may be
automatically re-arranged in the EMI to execute out-of-order.
• Within an AHB-bridged port, a write command that is accepted into the port after a
read will not be executed ahead of the read command. However, a read command that
is accepted into the port after a write may be indeterminably re-arranged in the EMI
ahead of the write command.
• Within a native AXI port, read and write commands from the same or different thread
IDs may be re-arranged in the core logic. Read and write commands with different
thread IDs will be automatically re-arranged to execute in an optimal order, as long as
there are no collisions between the commands.
Command handling is summarized in the following table.
Table 14-1. Reordering/Interleaving Behavior
Commands Thread ID Can Commands be Rearranged and Data be
Interleaved?
Two Read Commands from 1 port Same No
1
Two Read Commands from 1 port Different Yes
Two Read Commands from Different ports Same or Different Yes
Two Write Commands from 1 port Same No
Two Write Commands from 1 port Different No 1
Two Write Commands from Different ports Same or Different Yes
2
Read/Write or Write/Read Command from 1 port Same Maybe
Read/Write or Write/Read Command from 1 port Different Yes 1
Read/Write or Write/Read Command from Different ports Same or Different Yes

1. Since all commands from an AHB-bridged port use a single thread ID, this option is not applicable for AHB-bridged ports.
2. For a native AXI port, read and write commands may be interleaved. For an AHB-bridged port, a write command will not be
placed ahead of a read command from the same port. However, a read command may be placed ahead of a write command.
An incoming AXI transaction is mapped into a core logic-level transaction, then synchronized
from the AXI clock domain to the core logic clock domain and stored in the AXI port FIFOs.
Each instruction consists of an address, size, length and thread ID. Since a port may utilize
multiple thread IDs, the source ID that is used in the core logic is a combination of both the
port and thread information. This concatenation occurs in the Arbiter and this source ID is
used in the placement logic. From the AXI FIFOs, the transaction is presented to the Arbiter
which arbitrates requests from all ports and forwards a single transaction to the core logic.
14.4.2.2 AHB Signal to AXI Signal Translation

Table 14-2. Burst Type Translation
AHB AXI Burst type AXI Burst length
(ahb_hburst) (axi_awburst / axi_arburst) (axi_awlen / axi_arlen)
SINGLE ‘b000 FIXED ‘b00 1 word ‘b0000

INCR ‘b001 INCR ‘b01 4 words ‘b0011
WRAP4 ‘b010 WRAP ‘b10 4 words ‘b0011
INCR4 ‘b011 INCR ‘b01 4 words ‘b0011
14.4.2.3 Configured Options

Each AXI port has been defined for the requirements of the intended system. The configured
options are:
• Type of interface to the EMI core clock (emi_clk)
All ports are clock domain programmable relative to the emi_clk. These ports initialize
in asynchronous operation, but can be changed by programming the associated
axiY_fifo_type_reg parameter. For more information on the programming of this
parameter, refer to section Port Clocking. Asynchronous FIFOs handle the clock domain
crossing when operating in any of the non-synchronous modes.
• Width of the ID
Each port is configured with a thread ID of 10 bits.

• Priority Definition
Command priority is defined based on the port and the command type. For each port
Y, there is an axiY_r_priority parameter which defines priorities for all read commands
and an axiY_w_priority parameter which defines priorities for all write commands.
Supported priority values range from 0 to 7, with 0 as the highest priority.
• Register Port
The 32-bit AHB register port is fixed in Asynchronous mode between the AHB bus
clock domain and the emi_clk domain.
• Port Bridging
The following table shows the front-end bridge settings.
Table 14-3. Front-End Bridge Settings
Port Number Bus Connection Internal Port Type
Port 0 AXI Native AXI
Port 1 AHB AHB-AXI

Bridged
Port 2 AHB AHB-AXI

Bridged
Port 3 AHB AHB-AXI

Bridged
• Buffering
Each AXI interface contains a command, a read and a write FIFO, and a response
storage array. In addition, each programmable port contains an asynchronous response
FIFO to synchronize the memory response to the port clock domain when operating
asynchronously.
Table 14-4. AXI Port FIFOs
Port Num- Port Data Clock Domain Type Command Write FIFO Read FIFO Response Response
ber Width FIFO Depth Depth Depth FIFO Depth Storage Ar-
ray Depth
Port 64 Programmable 4 8 8 4 8
0
1
2

Port Num- Port Data Clock Domain Type Command Write FIFO Read FIFO Response Response
ber Width FIFO Depth Depth Depth FIFO Depth Storage Ar-
ray Depth
3
• Exclusive Access Buffer Depth

Exclusive access is an optional AXI feature that is only supported for the native AXI
ports. This type of access will only be used if exclusive access commands are issued
to the memory controller by driving the axiY_ARLOCK signal to ‘b10 with a read
command.
Each native AXI port contains 1 exclusive buffer and therefore each port may monitor
the exclusivity of up to 1 transaction at any time. Refer to section Exclusive Access for
more information.
• Error Detection
When an illegal operational condition is detected on a new AXI transaction entering
the port, the port responds through an AXI error signal and the controller interrupt
signal, and the error signature is recorded in the register space.
The AXI error signal flagged is dependent on the type of transaction that caused the
error (read or write). The controller interrupt and the signature information is dependent
on type of error (command or data). Refer to section Error Responses for more
information on error detection.
14.4.3 Port Clocking

There are four user-selectable modes of operation for each of the AXI port interfaces. The
mode is set by programming the corresponding axiY_fifo_type_reg parameter. The four
settings are:
• Synchronous (‘b11)
The AXI port clock and the emi_clk must be aligned in frequency in phase. The AXI
port interface block will not be required to perform any clock synchronization in any
of the FIFOs.
• 1:2 Port:Core Pseudo-Synchronous (‘b10)
Reserved. Do not select this mode. Select “Asynchronous” instead.

The port operates at half of the frequency of the emi_clk frequency, with clocks that
are aligned in phase. One stage of the two-stage synchronization logic of the FIFOs
will be utilized to synchronize commands, write data and read data to the appropriate
clock domain.
• 2:1 Port:Core Pseudo-Synchronous (‘b01)
Reserved. Do not select this mode. Select “Asynchronous” instead.
The port frequency is twice the emi_clk frequency, although the clocks are aligned in
phase. One stage of the two-stage synchronization logic of the FIFOs will be utilized
to synchronize commands, write data, and read data to the appropriate clock domain.
• Asynchronous (‘b00)
The AXI bus and the core logic operate on clocks that are mismatched in frequency
and phase. The AXI port FIFOs use two stages of synchronization logic to synchronize
commands, write data, and read data to the appropriate clock domain.
14.4.4 AXI Interface FIFOs

Each programmable port contains four FIFOs for commands, read data, write data and
response synchronization. The response synchronization FIFOs are only used when operating
in asynchronous mode. In addition to the FIFOs, each port contains a storage array to hold
the read and write responses. The depths and clock domain relativity of the FIFOs and the
array are shown in Table 14-4.
The five channels of traffic and their relationship to the port FIFOs are shown below.

AXI Interface
Synch
AXI Write Response Channel Resp FIFO
Array
Bus
Arbiter
AXI Write Data Channel &
Write Data FIFO
Read/Write
Command
AXI Write Command Channel Queue
AXI &
Port Command Read/Write
FIFO Data
AXI Read Command Channel Arbiter
Queues
AXI Read Data Channel

Read Data FIFO
Figure 14-4. AXI Interface FIFOs
14.4.5 AXI Write Response Channel

When a write request is accepted into the AXI interface, an entry will be created in the
Write-Response FIFO for that command. When a write response is ready, the response will
be returned to the AXI master.
Different masters may require this response at different stages of the write command. A
master that needs to quickly release the bus would optimally receive the completion response
as soon as the port has accepted the write command and all of the corresponding data.
Another master may wish to wait until the data has been accepted into the core logic, or
successfully written to memory.
Each AXI interface is configured with two signals that work together to determine when
an instruction is considered complete and the write completion response will be returned
to the master. These signals are axi_AWCACHE [0] and axi_AWCOBUF. The following
table details the relationship between these signals.
Table 14-5. Write Response Types
1
axi_AWCACHE[0] axi_AWCOBUF Response Information
0 Irrelevant Non-bufferable write command. Response is ready after the write data is
committed to memory.
1 0 Standard bufferable write command. Response is ready when the command

and all associated data have been received by the AXI data port. There is
no guarantee of data coherency across all AXI ports.

1
axi_AWCACHE[0] axi_AWCOBUF Response Information
1 1 Coherent bufferable write command. Response is ready when the command

has been accepted by the command queue in the core logic.This guarantees
data coherency across all ports but reduces the overall write response latency
relative to the non-bufferable option.
1. The response will only be sent if all of the older write responses have been issued for any thread ID on that port.
axi_AWCACHE [0] comes from the standard AXI bus signal and the axi_AWCOBUF is
configured by user-defined register “BRESP_TIMING” (Bit [0] of register
HW_DRAM_CTL00).
Note that in the “AHB-AXI Bridge”, axi_AWCACHE [0] is tied-off to 1, and the
axi_AWCOBUF is tied-off to 0. Therefore, the write reponse type of AXI Interface 1~3 is
forced to “Standard Bufferable Write.”
14.4.6 AHB Register Port

The register port is an independent AHB port to the EMI. This port operates asynchronously.
The register port only supports the AHB SINGLE burst type.
The register port only supports transfer types of NONSEQ or IDLE. There is no support
for INCR or WRAP burst types. There is no support for SEQ or BUSY transfer types.
14.4.7 AXI Transactions

The AXI Interface supports burst tpye of INCR and WRAP.
The AXI Interface supports burst length of 1-16 beats.
14.4.8 Exclusive Access

Note: The exclusive access option is an AXI-specific feature that requires use of the
axi_ARLOCK and axi_AWLOCK signals. Therefore, this feature is only relevant for the
native AXI ports.
The exclusive access feature allows a master to monitor if a memory area has been altered
since its last read. Exclusive access does not imply that the memory area is locked; other
thread IDs of that port, or other ports, may access the area for reads or writes even though
an exclusive access exists. If any writes occur to a memory area with a valid exclusive
access request, the master will lose exclusivity and be informed of this status when it attempts
to write to the area again. A loss of exclusivity does not trigger an interrupt or any error
conditions; however, the AXI protocol requires that the write data is not written to memory

if an exclusive write fails its exclusivity check. The master that has lost exclusivity must
determine whether to restart the sequence by requesting another exclusive read or to write
the data to the memory regardless through a non-exclusive write.
14.4.8.1 Initiating an Exclusive Access Request

Exclusivity is enabled by issuing a read command to memory with the axi_ARLOCK signal
driven to ‘b01.
14.4.8.2 Verifying the Request

The AXI specification dictates restrictions for exclusive access requests. After being accepted
in the port, an exclusive read request will be checked against these requirements. If any of
these conditions are violated, the command will be passed to the core logic as a non-exclusive
read. These restrictions are:
• The address must be aligned to the total byte count. (Byte Count = (axi_ARLEN + 1)
x 2^axi_ARSIZE)
• The byte count must be a power-of-two, and less than 128 bytes.
In addition, the AXI specification states that exclusive accesses can not be cacheable.
However, since the EMI does not support cacheable commands, this bit is ignored and any
cacheable exclusive access requests will be processed as non-cacheable exclusive accesses.
14.4.8.3 Validity of an Exclusive Request

The exclusive access will be considered valid from the point that the entry is created in the
buffer until an activity occurs to invalidate it. These activities cause the “valid” bit of the
exclusive access buffer entry to be cleared:
• The same source ID issues a write command for the same starting addressing of the
same length and beat size.
• Any other source ID, from that port or another port, writes to any memory address in
that memory span.
Note: The EMI assumes that a single master will only communicate with a single port.
Therefore, a command to another port, with the same AXI ID (axi_AWID or axi_AWID)
will not violate the exclusivity of another port’s exclusive region simply based on ID match.

• The user is tracking enough exclusive access commands that the exclusive access buffer
for this port is full. Newer commands will be stored, overriding a previous exclusive
access entry.
• The same source ID issues another exclusive read request for another memory region.
This will not clear the valid bit, but will actually overwrite the entire exclusive access
buffer entry (and then set the valid bit). The EMI will only track one exclusive region
for each source ID.
14.4.8.4 Read Commands to Exclusive Access Regions

A memory area is not locked while an exclusive access is valid and therefore other source
IDs may issue read commands to a memory area identified as exclusive. Reads, even other
exclusive reads, do not affect the exclusivity of a region. Normal read commands will be
processed as usual and, if successful, respond to the master with an OKAY (‘b00) on the
axi_RRESP signal. Exclusive read commands will result in additional entries being created
in the exclusive access buffers and, if successful, an EXOKAY (‘b01) response will be sent
on the axi_RRESP signal.
Note: An exclusive read request from any source ID, from the same port or another port,
even to an overlapping address within an exclusive access region, will not affect the initial
exclusive access. Another entry will be created in that port’s buffer for this request.
14.4.8.5 Non-Exclusive Write Commands to Exclusive Access Regions

Any master in the system may issue a write command to a memory area identified as
exclusive. However, a standard write to any address within an active exclusive access region
will invalidate the exclusivity of that region. In this case, the “valid” bit of any exclusive
access buffer entry that spans the modified locations in memory will be cleared and future
exclusive write requests to this region will fail their exclusivity check.
14.4.8.6 Exclusive Writes

An exclusive write command is only distinguished from a standard write command by the
axi_AWLOCK signal being driven to ‘b01. When an exclusive write is received, the EMI
first compares the source ID (axi_AWID and port number), transaction beat length
(axi_AWLEN), transaction start address (axi_AWADDR), and transaction beat size
(axi_AWSIZE) to the entries in the exclusive access buffer of that port.

14.4.8.7 Passing Exclusive Access Check

If any of the valid buffer entries exactly match the incoming command, the following
activities occur:
• That buffer entry's “valid” bit is cleared.
• All other buffer entries, from this port or other ports, are checked to see if this write
invalidates any other exclusive access regions. If so, the “valid” bits of these entries
will be cleared.
• The transaction is processed.
• If successful, the write response channel (axi_BRESP) returns an EXOKAY response
(‘b01) to the master.
14.4.8.8 Failing Exclusive Access Check

If an invalid buffer entry exactly matches the incoming command, or no buffer entries
exactly match the incoming command, then the write will fail. The command will be
processed internally as a flushed write command.
For a flushed write, the write data will be cleared out of the memory controller FIFOs but
the data stored in external DRAM memory will NOT change.
The user will be informed of this condition through the write response channel (axi_BRESP).
However, instead of an EXOKAY response, the memory controller will issue an OKAY
response. This indicates to the master that the exclusive write did not occur. The master
may re-issue the request as a non-exclusive write, or may restart the process by re-issuing
the exclusive read.
14.4.9 Error Responses

This section discusses AXI error responses and AXI error reporting.
14.4.9.1 AXI Error Response

When an illegal operational condition is detected on a new AXI transaction entering the
port, the port responds with an error condition. Instructions that generate AXI errors result
in unpredictable behavior and may cause memory corruption and/or hang conditions.

14.4.9.2 AXI Error Reporting

If an AXI command error occurs, a bit will be set in the int_status parameter and the address
and source ID of the command are saved in the port_cmd_error_addr and port_cmd_error_id
parameters, respectively. In addition, the access type that relate to the error are stored in
the port_cmd_error_type parameter.
Similarly, when a data error occurs, the source ID of the command is saved in the
port_data_error_id parameter. The access type that relate to the error are stored in the
port_data_error_type parameter.
The bits in the error type parameters are not exclusive. Multiple bits may be set to indicate
the type of errors that occurred. Reading the int_ack parameter will allow future errors to
be captured in these error parameters.
If multiple errors occur prior to an acknowledgment of the first error, the parameters will
still represent the first error attributes. Other error signatures will be lost. If multiple errors
occur simultaneously on different ports, the error information will represent the lowest
numbered erring port.
14.4.10 Arbiter
From the port interface blocks, commands are presented to the Arbiter, which is responsible
for arbitrating between the port requests and sending a single command to the core logic.
Refer to the “EMI Multi-Port Arbiter” Chapter for details.
14.4.11 Write Data Queue

The write data queue is a write data storage array for transactions. The queue consists of
multiple buffers holding write data for the write requests of a particular port. Write data is
stored in these buffers for commands in the command queue until the command is processed
in the placement logic and needed by the DRAM command arbitration logic. The buffers
can accept data whenever any space is available.
14.4.12 DRAM Command Processing

The DRAM command processing logic is used to process the commands in the Command
Queue. The logic organizes the commands to the memory devices in such a way that data
throughput is maximized. DRAM-Bank opening and closing cycles are used for data
transfers.

The logic uses a variety of factors to determine when to issue bank open and close commands.
The logic reviews the entire Command Queue for look-ahead of which banks are to be
accessed in the future. The timing is then set to meet the trc and tras_min timing parameters
of the memory devices, values which were programmed into the memory controller on
initialization. This flexibility allows the memory controller to be tuned to extract the
maximum performance out of memory devices. The parameters that relate to DRAM device
protocol are listed in the “EMI Parameter Descriptions” Chapter.
14.4.13 Latency
By using the placement logic of the command queue in the core logic, a new request through
any port can be immediately placed at the top of the command queue or can interrupt an
ongoing request. This scheme allows a high priority request to be serviced in the shortest
possible time.
However, since there are many factors that determine the placement into the command
queue, there are also many factors that affect the actual latency of the command. These
factors include:
• The coherency status of the transactions already in the command queue: If there is a
data coherency conflict with a transaction already in the command queue, the new
transaction will be placed after the transaction that produced the conflict. The position
of the conflicting transaction determines the latency of the high priority read or write
command.
• The priority status of the transactions already in the command queue: If the new
command has a higher priority than those already in the command queue, the new
request will be serviced ahead of the lower priority command. As a result, the latency
of the new command will be lower than the latency of the older command.
• The read, write, and bank information of the transactions already in the command queue:
In general, reads will be placed ahead of writes when both are of the same priority level.
Read commands are grouped with other read commands of similar priorities and write
commands are grouped with other write commands of similar priorities. Among these
groupings, transactions with similar bank and different row destinations are separated
as much as possible.
If all of the placement conditions are met, then a new command would be placed at the top
of the command queue. However, if the new command is of a higher priority than the
transaction that is executing, the current command will be interrupted and the new command
will execute first. The interruption will occur at a natural burst boundary of the DRAMs.
The interrupted transaction will be placed at the top of the placement queue and it will
resume after the new request is completed. The page status of the new transaction determines
when the current transaction is interrupted. If the page for the new transaction is already
open, then the current transaction will be interrupted at the next natural burst boundary of
the DRAM device. If the page is not currently open, then the new request will be placed at
the top of the command queue while its page is prepared.
There are a fixed number of latency cycles in the memory controller, based on the pipeline
through the memory controller logic. These steps are:
1. Command passing through the port interface. (fixed)
2. Arbitration through the Arbiter. (fixed)
3. Placement into the Command Queue. (fixed)
4. Memory Command Generation. (variable)
5. Sending of control signals from the core logic to flip-flops near the I/O drivers. (fixed)
6. Flight time to the DRAM device. (variable)
7. Flight time from the DRAM device. (variable)
8. For reads, synchronization of read data from the data strobe domain. (fixed)
9. For reads, data pass through the port interface. (fixed)
For asynchronous AXI interfaces, an additional 4–5 cycles are included for the round-trip
transaction to synchronize to the EMI_CLK.

EMI Multi-Port Arbiter
14.5 EMI Multi-Port Arbiter

Synch
Resp FIFO
Array
Write Response
Control Logic
Write Data FIFO
AXI
Command
Port
FIFO
Arbiter
Read Data FIFO
Write Data
Queue
Synch
Resp FIFO
Array ( N channels )
Write Data FIFO
AXI
Command
Port
FIFO
Arbiter
Command
Read Data FIFO Queue
DDR
Core
with DFI
Arbiter Control
Synch
Resp FIFO Placement
Array Logic
Logic
Write Data FIFO
AXI
Command
Port
FIFO
Arbiter
Read Data FIFO

Read Data
Queue
Synch ( 1 channel )
Resp FIFO
Array
Write Data FIFO

Core Logic
AXI
Command
Port
FIFO
Arbiter
Read Data FIFO
Figure 14-5. EMI Core Logic
The Arbiter is responsible for arbitrating requests from the ports and sending requests to
the core logic. Each transaction received at the Arbiter logic has an associated priority,
which works with each port’s arbitration logic to determine how ports issue requests to the
core logic. This memory controller supports the Bandwidth Allocation/Priority Round-Robin
arbitration scheme.

The Arbiter logic routes read data from the core logic to the appropriate port. The requesting
port is assumed able to receive the data. Write data from each port is connected directly to
its own write data interface in the core logic, allowing the ports to independently pass write
data to the core buffers.
14.5.1 Arbitration Overview

The bandwidth allocation scheme is an extension of simple round-robin arbitration. It is
based on the priority of the requests and is influenced by the actual bandwidth consumed
by the port inside the core logic.
Priority round-robin arbitration is a complex arbitration scheme. In order to understand its
operation, each concept must be first understood individually. Section Understanding
Round-Robin Arbitration through section Understanding Port Bandwidth Hold-Off describe
the various components of priority round-robin arbitration.
14.5.2 Understanding Round-Robin Arbitration

Round-robin operation is a simple form of arbitration which offers each port an opportunity
to issue a command. This scheme uses a counter that rotates through the port numbers,
incrementing every time a port request is granted.
If the port that the counter is referencing has an active request, and the core command queue
is not full, then this request will be sent to the core. If there is not an active request for that
port, then the port will be skipped and the next port will be checked. The counter will
increment by one whenever any request has been processed, regardless of which port’s
request was arbitrated.
Round-robin operation ensures that each port’s requests can be successfully arbitrated into
the core logic every N cycles, where N is the number of ports in the EMI. No port will ever
be locked out, and any port can have its requests serviced on every cycle as long as all other
ports are quiet and the command queue is not full.
An example of the round-robin scheme is shown in Table “Round-Robin Operation
Example”.
Cycles 0, 2 and 6 show the system behavior when the command queue is full. Cycle 8 shows
the system behavior when the port addressed by the arbitration counter does not have an
active request. All other cycles show normal behavior.

Table 14-6. Round-Robin Operation Example

CYCLE PORT AD- PORTS REQUESTING COMMAND WINNER OF ARBIT- VALUE OF
DRESSED BY QUEUE FULL ? RATION COUNTER AT
THE ARBITRA- PORT PORT PORT PORT NEXT CYCLE
TION COUNTER 0 1 2 3
0 0 Y Y Y Y Yes None 0
1 0 Y Y Y Y No P0 1
2 1 - Y Y Y Yes None 1
3 1 Y Y Y Y No P1 2
4 2 Y - Y Y No P2 3
5 3 Y - - Y No P3 0
6 0 Y - Y - Yes None 0
7 0 Y - Y - No P0 1
8 1 - - Y - No P2 2
9 2 - - Y Y No P2 3
10 3 Y - - Y No P3 0
14.5.3 Understanding Port Priority

For AXI ports, the priority is associated with a port and each port has separate priority
parameter for reads and writes. These values are stored into the programmable parameters
axiY_r_priority and axiY_w_priority (where Y represents the port number) at controller
initialization.
Internally, the ports are organized into priority groups based on their priority settings. All
ports within a priority group are treated equally for arbitration unless a port has exceeded
its allocated bandwidth. The priority value is also used by the placement logic inside the
core logic when filling the command queue.
A priority value of 0 is highest priority, and a priority value of (decimal) 7 is the lowest
priority. The user may program at priority level 0; however, it is best to reserve this priority
value so that the placement queue can elevate to this level through aging.

14.5.4 Understanding Port Bandwidth

Each port has an associated bandwidth limit that sets the maximum percentage of the core
logic bandwidth that the port is allowed to use. Once this level is reached, the Arbiter will
no longer accept requests from this port until the bandwidth usage drops below the threshold.
This scheme allows for the bandwidth to be shared between the ports. If required, an overflow
option allows the port to continue to receive requests after the bandwidth limit has been
reached. See section Understanding Port Bandwidth Hold-Off for more information on this
option.
The bandwidth limits are stored in the programmable parameters axiY_bdw for each port
Y at EMI initialization. The axiY_current_bdw parameters are used to track the actual
bandwidth utilized as computed by the bandwidth calculation module inside the Arbiter.
Port bandwidth is computed by counting the number of cycles that the core logic is busy
actively processing that port’s request in each 100 cycle period, referred to as the statistics
window.
In the EMI, 10 counters are used for this computation. The counters track the number of
active cycles in each statistics window, generating a moving average bandwidth value for
each port. This is the actual bandwidth utilized value saved in the current bandwidth
parameters (axiY_current_bdw). The values in the current bandwidth parameters are updated
every 10 cycles with the actual bandwidth used in the last 100 cycles.
The core logic is defined as actively processing for a port if any of the following situations
occur:
• The core logic is ready to transfer write data from the port to memory, but the data has
not arrived from the port.
• The core logic is holding the port’s command and is ready to transfer to memory, but
is waiting to open a bank, precharge a bank, or some other memory-related action.
• The core logic is actively transferring data from the port to memory.
• The core logic is ready to transfer read data from memory to the port but the port is
busy and unable to accept the data.
If all ports are assigned 100% bandwidth, then bandwidth usage will not factor and arbitration
will be purely based on priority.
The following figure shows bandwidth usage for a 4-port system with a 100-cycle calculation
window and 10 counters.

Number of Active Cycles

Bandwidth
out of 10 Cycles
Cycle
Window Port 0 Port 1 Port 2 Port 3
0-9 10 10 0 0
10-19 5 3 3 5
20-29 7 3 3 5
Counter 0
30-39 2 10 3 3
Counter 1
40-49 9 1 3 4
Counter 2
50-59 7 3 5 3
Counter 3
60-69 1 3 5 7
Counter 4
70-79 9 7 5 3
Counter 5
80-89 9 4 8 2
Counter 6
90-99 2 1 2 9
Counter 7
100-109 3 4 3 3
Counter 8
110-119 0 0 10 10
Counter 9
120-129 0 0 10 10
Counter 0
130-139 3 3 1 1
140-149 3 3 0 0
150-159 6 0 7 1
160-169 8 1 8 1
170-179 1 2 3 5
180-189 3 3 5 3
190-199 3 1 0 0
Figure 14-6. System Bandwidth Example
For this system, the bandwidth will be monitored over each 100 cycles. The bandwidth
calculation parameters will be updated every 10 cycles with the bandwidth usage of the last
100 cycles as shown graphically in the figure.
The bandwidth totals are shown in #system_bandwidth_usage_example. In the system,
these values would be stored in the axiY_current_bdw parameters after each calculation.
Table 14-7. System Bandwidth Usage Example
COUNTER CYCLES COUNTING CALCULATED USAGE
NUMBER
PORT 0 PORT 1 PORT 2 PORT 3
0 0 - 99 61 / 100 = 61% 45 / 100 = 45% 37 / 100 = 37% 41 / 100 = 41%
1 10 - 109 54 / 100 = 54% 39 / 100 = 39% 40 / 100 = 40% 44 / 100 = 44%
2 20 - 119 49 / 100 = 49% 36 / 100 = 36% 47 / 100 = 47% 49 / 100 = 49%
3 30 - 129 42 / 100 = 42% 33 / 100 = 33% 54 / 100 = 54% 54 / 100 = 54%
4 40 - 139 43 / 100 = 43% 26 / 100 = 26% 52 / 100 = 52% 52 / 100 = 52%
5 50 - 149 37 / 100 = 37% 28 / 100 = 28% 49 / 100 = 49% 48 / 100 = 48%
6 60 - 159 36 / 100 = 36% 25 / 100 = 25% 51 / 100 = 51% 46 / 100 = 46%

COUNTER CYCLES COUNTING CALCULATED USAGE

NUMBER
PORT 0 PORT 1 PORT 2 PORT 3
7 70 - 169 43 / 100 = 43% 23 / 100 = 23% 54 / 100 = 54% 40 / 100 = 40%
8 80 - 179 35 / 100 = 35% 18 / 100 = 18% 52 / 100 = 52% 42 / 100 = 42%
9 90 - 189 29 / 100 = 29% 17 / 100 = 17% 49 / 100 = 49% 43 / 100 = 43%
0 100 - 199 30 / 100 = 30% 17 / 100 = 17% 47 / 100 = 47% 34 / 100 = 34%
14.5.5 Understanding Port Bandwidth Hold-Off

When the bandwidth used by a port exceeds its specified limit, that port is held off from
subsequent arbitration decisions for a period of time known as the statistics reporting time.
This causes a period of inactivity from that port, allowing the actual bandwidth used for
that port to fall below the threshold. Since the bandwidth used is updated every ten cycles,
the minimum hold off period for this system is ten cycles.
This scheme is designed to constrain individual ports (especially ports programmed at higher
priority) from overtaking all available bandwidth and locking out other ports. However,
this can have its drawbacks.
Consider a situation where only one port has been actively requesting and has therefore
used all of its available bandwidth. The bandwidth hold-off will prevent additional requests
from being accepted, even though no other ports are requesting. The core logic command
queue will sit empty for several cycles while the hold-off is cleared. This is obviously wasted
bandwidth and is detrimental to overall system performance. EMI has incorporated a
bandwidth hold-off override function for such a situation in the axiY_bdw_ovflow
parameters.
A port will be allowed to exceed its allocated bandwidth when all of these conditions are
true:
• The bandwidth overflow parameter (axiY_bdw_ovflow) is set to ‘b1 for port Y.
• No other port, whose bandwidth has not been exceeded, is requesting at the same priority
level.
• The command queue has less than the number of entries specified in the
arb_cmd_q_threshold parameter.
This last condition is a preventative measure to maintain latency requirements for ports
programmed at higher priority. When a port is allowed to exceed bandwidth, it may fill the
command queue with transactions. If this occurs, and a higher priority port starts requesting,
then there will be no room in the command queue for the new requests. This means that the

higher priority port will actually be held off for potentially several cycles. In this situation,
even though the core logic bandwidth is being utilized well, the latency requirements of the
higher priority port are not being met. The arb_cmd_q_threshold parameter is used to limit
the bandwidth overflow and prevent this condition. It ensures that a certain number of slots
remain available in the command queue for other ports. As a result, bandwidth overflow
will be allowed as long as there are less than arb_cmd_q_threshold number of entries in the
command queue.
14.5.6 Priority Round-Robin Arbitration Summary

The MC priority round-robin arbitration system combines the concepts of round-robin
operation, priority, bandwidth, and port bandwidth hold-off. The incoming commands are
separated into priority groups based on the priority of the associated port for that type of
command. Within each priority group, the Arbiter evaluates the requesting ports, the
command queue, the priority of the requests, the bandwidth being used and the overflow
option to determine the winner of the arbitration.
The order of steps is as follows:
1. Is the core logic command queue full?
• Yes: No further action is taken.
• No: Review the ports.
2. For all requests at each priority level, use round-robin arbitration to select a request for
that priority level.
3. For the highest priority port that is selected, has the bandwidth allocation for this port
been exceeded?
• No: This request wins arbitration. Move to step 6.
• Yes: Check the bandwidth overflow status.
4. Is bandwidth overflow enabled?
• No: Repeat step 3 for the next highest priority request.
• Yes: Check the conditions for overflow.
5. Are the overflow conditions met?
• No: Repeat step 3 for the next highest priority request.
• Yes: This request wins arbitration.
6. Once a request wins arbitration, it is processed into the command queue and the
round-robin counter is updated to the next port in the circular queue.

14.5.7 Arbitration Examples

To demonstrate arbitration behavior, consider the following system:
• Four ports.
• Ports 0 and 1 request only at priority 1. Ports 2 and 3 request only at priority 2.
• All ports have bandwidth allocations of 100% and the bandwidth overflow bit is set to
‘b1. (Bandwidth will not affect arbitration.)
An example with these settings is shown in Table 14-8. Note that priority 2 requests will
only win arbitration when there are no priority 1 requests. Also note that each arbitration
counter only increments, and always increments, when a request of that priority is processed.
Cycle 5 demonstrates the always condition of counter incrementing: even though the
arbitration was won by the other port of highest priority instead of the one in the counter,
the counter still increments.
Table 14-8. Priority Round-Robin without Bandwidth Consideration
Cycle Current Arbitra- Ports Requesting Command Winner of Arbitra- Next Arbitration
tion Counter Queue Full tion Counter
PG 1 PG 2 Port 0 Port 1 Port 2 Port 3 PG 1 PG 2
0 0 2 Y Y Y Y Yes None 0 2
1 0 2 Y Y Y Y No P0 1 2
2 1 2 — Y Y Y No P1 0 2
3 9 2 Y — Y Y No P0 1 2
4 1 2 — — Y Y No P2 1 3
5 1 3 Y — — Y No P0 1 3
6 0 3 — — — Y No P3 0 2
7 0 2 — — — — No None 0 2
8 0 2 — — Y Y Yes None 0 2
9 0 2 Y — Y Y No P0 1 2
10 1 2 — — Y Y No P2 1 3
11 1 3 — — — Y No P3 1 2
PG1 = Priority Group 1 and PG2 = Priority Group 2

The example was a very simplified case without considering bandwidth. However, in most
cases, bandwidth will factor into the arbitration. Therefore, consider the same system as
used in the previous example. However, now the allocated bandwidth is less than 100%.
This system is shown in Table 14-9. The “Bandwidth Held Off” column indicates if the
bandwidth was held off for any port in that cycle. (Note cycles 3 and 11.) Even though the
priority group 1 arbitration counter is pointing to port 0 in both cases, because the port is
held off, port 0 does not win arbitration. A lower priority port, from priority group 2, wins
arbitration instead.
Table 14-9. Priority Round-Robin with Bandwidth Consideration
Cycle Current Arbit- Ports Requesting Command Bandwidth Winner of Ar- Next
ration Counter Queue Full Held Off bitration Arbit-
ration
Counter
PG 1 PG 2 Port 0 Port 1 Port 2 Port 3 PG 1 PG 2
0 0 2 Y Y Y Y Yes No None 0 2
1 0 2 Y Y Y Y No No P0 1 2
2 1 2 — Y Y Y No No P1 0 2
3 0 2 Y — Y Y No Yes, port 0 P2 0 3
4 0 3 Y — — Y No No P0 1 3
5 1 3 Y — — Y No No P0 0 3
6 0 3 — — — Y No No P3 0 2
7 0 2 — — — — No No None 0 2
8 0 2 — — Y Y Yes No None 0 2
9 0 2 Y — Y Y No No P0 1 2
10 1 2 Y — Y Y No No P0 0 2
11 0 2 Y — Y Y No Yes, port 0 P2 0 3
12 0 3 Y — — Y No No P0 1 3
13 1 3 — — — Y No No P3 1 2
PG1 = Priority Group 1 and PG2 = Priority Group 2

14.5.8 Configuring and Programming for Priority Round-Robin

Arbitration
The priority round-robin arbitration scheme requires the use of the following programmable
parameters:
• axiY_r_priority, axiY_w_priority, axiY_bdw, axiY_current_bdw, axiY_bdw_ovflow
• arb_cmd_q_threshold
Since these parameters work together, there are trade-offs for the settings.
Note: All of the arbitration parameters must be programmed prior to setting the start
parameter to ‘b1. Any subsequent changes to the arbitration parameters may result in
unpredictable system operation.
14.5.8.1 Definition of the Statistics Window and the Number of Counters

The statistics window sets the length of time used to measure port bandwidth and the number
of counters determines the granularity of the measurement. The values set for both factors
affect bandwidth measurement accuracy, gate area and arbitration latency. Accuracy can
be added to the bandwidth measurements by increasing the number of counters and the
length of time for a calculation. However, this results in a large increase in the gate area.
Arbitration latency for a port is affected by how often bandwidth is updated. This is based
on the amount of time over which each counter tabulates activity: the statistics window
divided by the number of counters. As a general guideline, the statistics window should be
just large enough that the bandwidth used for one complete transaction does not exceed the
allocated bandwidth.
In the EMI, the statistics window is defined as 100 cycles, and there are ten counters per
port.
14.5.8.2 Command Priority, Port Bandwidth, and Bandwidth Overflow

Command priority, bandwidth and bandwidth overflow play an important role in arbitration.
Priority is the most important factor since commands are first sorted into priority groups
based on their priority settings. In a multi-port system, all ports with tight latency
requirements should be assigned higher priority values (lower numbers). Note that the
priority of the command affects both arbitration and placement into the core logic command
queue. As a result, it is more complicated to meet the latency requirements of all ports. For

Core Command Queue with Placement Logic
high priority commands or ports with low allocated bandwidths, bandwidth overflow may
be useful. To mimic simple round-robin arbitration, program all ports to have the same
priority and full bandwidth allocations.
Note: The bandwidth parameter (axiY_bdw) is a seven-bit parameter. However, any
programmed value greater than 0x64 is interpreted as 100%.
14.5.9 Command Queue with Placement Logic

From the Arbiter, commands are routed to the command queue of the core logic. The
command queue is fed using a placement algorithm. For more information on this algorithm,
refer to section Core Command Queue with Placement Logic.
14.6 Core Command Queue with Placement Logic

The core logic contains a command queue that accepts commands from the Arbiter. This
command queue uses a placement algorithm to determine the order that commands will
execute in the core logic. The placement logic follows many rules to determine where new
commands should be inserted into the queue, relative to the contents of the command queue
at the time. Placement is determined by considering address collisions, source collisions,
data collisions, command types and priorities. In addition, the placement logic attempts to
maximize efficiency of the core logic through command grouping and bank splitting. Once
placed into the command queue, the relative order of commands is constant.
Many of the rules used in placement may be individually enabled/disabled. In addition, the
queue may be disabled by clearing the placement_en parameter, resulting in an in-line queue
that services requests in the order they are received. If the placement_en parameter is cleared
to ‘b0, the placement algorithm will be ignored.
14.6.1 Rules of the Placement Algorithm

The factors affecting command placement all work together to identify where a new
command fits into the execution order. They are listed in order of importance, as follows:
• Address collision/data coherency violation
• Source ID collision
• Write buffer collision
• Priority
• Bank splitting
• Read/write grouping

14.6.1.1 Address Collision/Data Coherency Violation

The order in which read and write commands are processed in the memory controller is
critical for proper system behavior. While reads and writes to different addresses are
independent and may be re-ordered without affecting system performance, reads and writes
that access the same address are significantly related. If the port requests a read after a write
to the same address, then repositioning the read before the write would return the original
data, not the changed data. Similarly, if the read was requested ahead of the write but
accidentally positioned after the write, then the read would return the new data, not the
original data prior to being overwritten. These are significant data coherency mistakes.
To avoid address collisions, reads or writes that access the same chip select, bank and row
as a command already in the command queue will be inserted into the command queue after
the original command, even if the new command is of a higher priority.
This factor may be enabled/disabled through the addr_cmp_en parameter and should only
be disabled if the system can guarantee coherency of reads and writes.
14.6.1.2 Source ID Collision

Each port is assigned a specific source ID that is a combination of the port and thread ID
information, and identifies the source uniquely. This allows the memory controller to map
data from/to the correct source/destination.
Note that a source ID does contain port identification information, which means that the
rules for placement are dependent on the requesting port. There will not be source ID
collisions between ports.
In general, read commands from the same source ID will be placed in the command queue
in order. Therefore, a read command with the same source ID as a read command already
in the command queue will be processed after the original read command. All write
commands from a port, even with different source IDs, will be executed in order.
The behavior of commands of different types from the same source ID is dependent on the
user configuration. For this Memory Controller, the placement of new read/write commands
that collide in terms of source ID with existing entries in the command queue will only
depend on other commands of the same type, not on different types. This means that, if
there are no address conflicts, a read command could be executed ahead of a write command
with the same source ID, and likewise a write command could be executed ahead of a read
command with the same source ID.
This feature will always be enabled.

14.6.1.3 Write Buffer Collision

Incoming write requests in the command queue are allocated to one of the four write buffers
of the core logic automatically based on availability. New write commands will be designated
to any of the available buffers. However, back-to-back write requests from a particular
source ID will be allocated to the same write buffer as the previous command.
Since the core logic must pull data out of the buffers in the order it was stored, if a write
command is linked to a buffer that is associated with another command in the queue, then
the new command will be placed in the command queue after that command, regardless of
priority. This feature will always be enabled.
14.6.1.4 Priority
Priorities are used to distinguish important commands from less important commands. Each
command is given a priority based on the command type through the programmable
parameters axiY_r_priority and axiY_w_priority (where Y represents the port number). A
priority value of 0 is the highest priority, and a priority value of 7 is the lowest priority.
The placement algorithm will attempt to place higher priority commands ahead of lower
priority commands, as long as they have no source ID, write buffer or address collisions.
Higher priority commands will be placed lower in the command queue if they access the
same address, are from the same requestor or use the same buffer as lower priority commands
already in the command queue.
14.6.1.5 Bank Splitting

Before accesses can be made to two different rows within the same bank, the first active
row must be closed (pre-charged) and the new row must be opened (activated). Both activities
require some timing overhead; therefore, for optimization, the placement queue will attempt
to insert the new command into the command queue such that commands to other banks
may execute during this timing overhead. The placement of the new commands will still
follow priority, source ID, write buffer and address collision rules.
The placement logic will also attempt to optimize the core logic by inserting a command
to the same bank as an existing command in the command queue immediately after the
original command. This reduces the overall timing overhead by potentially eliminating one
pre-charging/activating cycle. This placement will only be possible if there are no priority,
source ID, write buffer or address collisions or conflicts with other commands in the
command queue.
All bank splitting features are enabled through the bank_split_en parameter.

14.6.1.6 Read/Write Grouping

The memory suffers a small timing overhead when switching from read to write mode. For
efficiency, the placement queue will attempt to place a new read command sequentially
with other read commands in the command queue, or a new write command sequentially
with other write commands in the command queue. Grouping will only be possible if no
priority, source ID, write buffer or address collision rules are violated.
This feature is enabled through the rw_same_en parameter.
14.6.2 Command Execution Order After Placement

Once a command has been placed in the command queue, its order relative to the other
commands in the queue at that time is fixed. While this provides simplicity in the algorithm,
there are drawbacks. For this reason, the Memory Controller offers two options that affect
commands once they have been placed in the command queue.
14.6.2.1 Command Aging

Since commands can be inserted ahead of existing commands in the command queue, the
situation could occur where a low priority command remains at the bottom of the queue
indefinitely. To avoid such a lockout condition, aging counters have been included in the
placement logic that measure the number of cycles that each command has been waiting.
If command aging is enabled through the active_aging parameter, then if an aging counter
hits its maximum, the priority of the associated command will be decremented by one (lower
priority commands are executed first). This increases the likelihood that this command will
move to the top of the command queue and be executed. Note that this command does not
move relative positions in the command queue when it ages; the new priority will be
considered when placing new commands into the command queue.
Aging is controlled through a master aging counter and command aging counters associated
with each command in the command queue. The age_count and command_age_count
parameters hold the initial values for each of these counters, respectively. When the master
counter counts down the age_count value, a signal is sent to the command aging counters
to decrement. When the command aging counters have completely decremented, then the
priority of the associated command is decremented by one number and the counter is reset.
Therefore, a command does not age by a priority level until the total elapsed cycles has
reached the product of the age_count and command_age_count values. The maximum
number of cycles that any command can wait in the command queue until reaching the top
priority level is the product of the age_count value, the command_age_count value, and the
number of priority levels in the system.

14.6.2.2 High-Priority Command Swapping

Commands are assigned priority values to ensure that critical commands are executed more
quickly in the memory controller than less important commands. Therefore, it is desirable
that high-priority commands pass into the core logic as soon as possible. The placement
algorithm takes priority into account when determining the order of commands, but still
allows a scenario in which a high-priority command sits waiting at the top of the command
queue while another command, perhaps of a lower priority, is in process.
The high-priority command swapping feature allows this new high-priority command to be
executed more quickly. If the user has enabled the swapping function through the swap_en
parameter, then the entry at the top of the command queue will be compared with the current
command in progress. If the command queue’s top entry is of a higher priority (not the same
priority), and it does not have an address, source ID or write buffer conflict with the current
command being executed, then the original command will be interrupted.
For this memory controller, an additional check is performed before a read command is
interrupted. If the read command in progress and the read command at the top of the
command queue is from the same port, then the executing command will only be interrupted
if the swap_port_rw_same_en parameter is set to ‘b1. If this parameter is cleared to ‘b0, a
read command from the same port as a read command in progress, even with a higher
priority and without any conflicts, would remain at the top of the command queue while
the current command completes.
Note: All write commands from a single port, even with different source IDs, will be executed
in order. Therefore, two write commands from the same port will never be swapped
regardless of the settings of the swap_en and swap_port_rw_same_en parameters.
Note: Priorities are assigned to read commands based on the settings in the axiY_r_priority
parameters. While all read commands from a port are assigned the same priority when
placed in the command queue, their priorities may change over time through command
aging. While uncommon, it is possible that a higher-priority read command may be at the
top of the command queue while a lower-priority read command is executing. The behavior
of the system in this scenario is based on the value of the swap_en and
swap_port_rw_same_en parameters.
Refer to the following table for details:
Table 14-10. Swapping Behavior
Active Command New Command Originating Port Conflicts? Action
Priority Priority for Commands
Higher Lower Same or Different Yes or No Current command continues

Active Command New Command Originating Port Conflicts? Action

Priority Priority for Commands
Lower Higher Same Yes Current command continues
Lower Higher Same No Will swap IF swap_en = 1 and

swap_port_rw_same_en = 1
Lower Higher Different No Will swap IF swap_en = 1
If the command is to be interrupted, it will be halted after completing the current burst,
stored and placed at the top of the queue, and the new command will be executed. As long
as the command queue is not full, new commands may continue to be inserted into the
command queue based on the placement rules, even at the head of the queue ahead of the
interrupted command. The top entry in the command queue will be executed next. Whenever
the interrupted command is resumed, it will start from the point at which it was interrupted.
Note that priority 0 commands will never be interrupted, so the user should set any commands
that should not be interrupted to priority 0. If supported by the port interfaces, setting the
swap_port_rw_same_en parameter will enable interleaving.
14.7 DDR PHY

The DDR PHY encapsulates all functionality required to interface to external DDR DRAM
devices into a single module. This module is used to control the off-chip data capture and
synchronization logic for the read data. This module performs the following functions:
• Contains all data registers used to launch data, address and control signals to the DDR
memory and the memory controller.
• Controls the off-chip data capture and synchronization logic for the read data.
• Includes a DLL for timing.
14.7.1 High Level Block Diagram

EMI uses a slice-based approach for the DDR PHY. Each slice manages a byte (8-bit) of
data and it’s corresponding dqs and dm signals. A high level block diagram of the PHY is
provided below.

DDR PHY
EMI Core Logic
DFI
DDR PHY
Addr, Command &

Data Slice 0 Data Slice 1
Misc I/O control
Other I /Os
DQ [15:8]
DQ [7:0]
DQS [0]
DQS [1]
DM [0]
DM [1]
I /O PADs
External DRAM Device
Figure 14-7. DDR PHY High-Level Block Diagram
14.7.2 DFI
The interface between the EMI core logic and the DDR_PHY is named as “DFI”.
“D” stands for “DRAM Controller” while “FI” is alias to “PHY”.
14.7.3 I/O Timing of Address and Command

The figure below illustrates the I/O timing of Address and Command.

emi_clk
io_addr_out addr
At the port of DDR_PHY
fly time = PAD _Delay + Board_Delay
At the DRAM device Pins

emi_addr_o addr
emi_clk_o
DRAM device capture ADDR by the rise-edge of emi_clk_o
Figure 14-8. I/O Address Timing
The address and command signals including all DRAM interface signals except the DQ
and DQS: clock-enable (CKE), chip-select, bank-address, row/cloumn_address, CASn,
RASn, WEn, and so on.
• The Address and command signals are latched out by the falling-edge of emi_clk; In
another words, the rise-edge of emi_clk is center-aligned with the output Address and
Command signals.
• The fly-time is the signal's propagation time start from the DDR_PHY logic, go across
the output I/O (PAD) of i.MX28, go through the signal trace on the board, then arrive
the PIN of the DRAM device.
• The DRAM device captures the Address and Command signals with the rising edge of
emi_clk_o.

DDR PHY
14.7.4 Data Slice Overview
Data Slice
read Read Data
data Path io_dq_in [7:0]
write Write Data io_dq_out [7:0]

data Path
delayed_dqs io_dq_oe [7:0]
Read Delay-Line io_dqs_in
EMI_CLK Write Delay-Line io_dqs_out

clk_wr
Digital DLL & (delayed) io_dqs_oe
Core Logic
Delay Control
EMI
io_dm
io_dm_oe
Registers
io_tsel
Control
I/O Control
io_tsel_dm
Figure 14-9. DDR PHY Data Slice
Each data-slice manages a byte (8-bit) of data and it’s corresponding signals.
The Read Data Path captures read data by latching it into read data buffers by both the
posedge and negedge of delayed_dqs. Then, the read data is synchronized from delayed_dqs
clock domain to emi_clk domain.
The Write Data Path synchronizes write data and write data mask (the dm) from emi_clk
domain to the dqs_out domain.
The Digital DLL controls the delay values of read delay-line and write delay-line. It can be
bypassed and switched to manual delay control mode. In manual delay control mode, the
delay values of read/write delay-line can be programmed separately into the control registers.

14.7.5 Read Data Capture

When reading, DDR (dual data rate) devices send a data strobe (DQS) signal coincident
with the read data. The edges of this DQS strobe are aligned (edge-aligned) with the data
output by the DDR devices.
To latch read data into the EMI read data buffer, it is required that the latch clock edge is
center-aligned with the data. Thus, a delayed version of the DQS strobe signal must be used
to capture the data. Because the frequency of the DQS strobe signal is matched to the
emi_clk, the delay is a relative number based on the period of the emi_clk. In the example
shown below, the delay is set to approximately 25% of the emi_clk cycle.
emi_clk
io_dqs_in
io_dq_in d0 d1 d2 d3
dqs delay = 1/4 cycle
delayed_dqs
capture data by the rise & fall edge of delayed _dqs
Figure 14-10. Read Data Capture
14.7.6 Synchronize Read Data From delayed_dqs to emi_clk

Domain
Read data is captured into data buffers by the delayed_dqs. It need to be synchronized to
the emi_clk domain, then returned to EMI core logic.
The following figure illustrates how the read data from an external DRAM device was
captured and synchronized to EMI core logic.

DDR PHY
1 2 3 4
emi_clk
io_dq_in d0 d1 d2 d3 d4 d5
delayed_dqs
d0
d1
data buffers
d2
@delayed_dqs
d3
clock domain
d4
d5
1 2 3 4
Synchronize data
d0,d1 d2,d3 d4,d5
to emi_clk doamin
phy_ctrl_reg_0 [26:24]
dfi_rddata: data returned to core-logic

@emi_clk domain d0,d1 d2,d3 d4,d5
dfi_rddata_valid: phy_ctrl_reg_2 [3:0]
Figure 14-11. Synchronized Read Data
io_dq_in and io_dqs_in are not aligned with emi_clk in phase. Many factors affect the phase
of io_dq/dqs_in, such as voltage, temperature, board layout, manufacturing process, and so
on.
1. Must capture the io_dq_in by delayed_dqs to meet the critical timing requirement in
high frequency.
2. The data path width @emi_clk domain is twice the data path width @delayed_dqs
domain.
3. The EMI core logic fetch read data by the rise-edge of emi_clk.
4. The EMI core logic fetch read data by two important signals: dfi_rddata and
dfi_rddata_valid.
5. The user can program the timing position of dfi_rddata and dfi_rddata_valid by
programmable registers phy_ctrl_reg_0[26:24] and phy_ctrl_reg_2[3:0]. The unit is
one cycle of emi_clk.

6. In this example, read data d0,d1 getting valid before edge number 1 of emi_clk and is
synchronized at edge 2 of emi_clk. Both the setup and hold time requirement are met
which means that the read data could be fetched by core logic safely.
Alternatively, read data can also be returned to core logic at edge number 1 of emi_clk, a
cycle prior to the example. In this scenario, you need to set the value of register
phy_ctrl_reg_0[26:24] and phy_ctrl_reg_2[3:0] to one number less. Then, the dfi_rddata
and dfi_rddata_valid would become valid one cycle earlier.
NOTE
The benefit is that the read latency is shortened by one cycle,
which helps increase the system performance. But, there’s a timing
risk on the setup time. If the io_dq/dqs_in comes a little late, a
setup time violation can occur and the unexpected data is returned
to core logic, which can cause a system crash.
14.7.7 Write Data Path

The following figure illustrates the write data path.
emi_clk
clk_wr delay = 1/4 cycle

1
write data latch d0 d2
@emi_clk domain d1 d3
clk_wr
write data latch d0 d2

@clk_wr domain d1 d3
clk_wr
io_dq_out :
write data muxed out d0 d1 d2 d3
mux_sel = clk_wr
io_dqs_out
DRAM device capture write data by the edge of io_dqs_out
Figure 14-12. Write Data Path

DDR PHY
NOTE
The marker 1 emphasizes that the setup time here for data d0 is
only 1/4 cycle, that would be critical in timing. Write Data Path
Low-Latency Option provides more details.
The io_dqs_out and the emi_clk are edge-aligned in this EMI design. This help to meet the
tDQSS timing requirement defined by DRAM device.
The io_dqs_out and the io_dq_out are center-aligned which is required by the DRAM
device.
14.7.8 Write Data Path Low-Latency Option

In the example of Figure 14-12, note the marker 1. It emphasizes that the setup time is only
1/4 cycle for data d0, which is critical in timing.
This DDR_PHY provides two write data path options for the user :
• The Standard Latency option.
An extra latch at emi_clk domain is asserted into the write data path, right ahead of the
latch at clk_wr domain (at the place of marker 1 in Figure 14-12). By this means, the
asserted-latch and the latch at clk_wr are put back-to-back. The total delay in write data
path is 1 + 1/4 cycle.
It is safe in timing, but decreases performance by adding one cycle of latency.
• The Low-Latency option.
The asserted latch for standard-latency is bypassed. The total delay in write data path
is 1/4 cycle.
There is risk in the timing of the write data path, but it has higher performance than the
standard-latency case.
14.7.9 Digital DLL and the Delay-Line

Due to the asynchronous nature of the DRAM devices, the timing requirements for capturing
and receiving data between the i.MX28 and the DRAM devices must be addressed. This
EMI contains a circuit that, in conjunction with I/O cell circuitry, can be used to meet the
timing requirements for DRAM devices. The delay compensation circuit was designed with
the following features:
• Programmable read strobe delay specified as a percentage of a clock cycle.

• Programmable write data delays specified as percentages of a clock cycle.

• Delay compensation circuit re-sync circuitry activated during refresh cycles to
compensate for temperature and voltage drift.
• Separate delay chains for each read DQS signal from the DRAM devices.
The delay compensation circuitry relies on a master/slave approach. There is a master delay
line which is used to determine how many delay elements constitute a complete cycle. This
count is used, along with the programmable fractional delay settings, to determine the actual
number of delay elements to program into the slave delay lines. The master and slave delay
lines are identical. This approach allows the memory controller to observe a clock and then
delay other signals a fixed percentage of that clock. The DLL logic does not actively generate
clock signals.
The actual delay element for the delay lines is user-selectable.
The following figure shows the block diagram for a digital DLL.

DDR PHY
dll phase detector

emi_clk
detector control logic
Detector Delay -Line
dll_lock
Digital DLL Main Control Logic
dll_lock_value
programmable delay-line control logic

Write delay value (select number of delay elements)
clk_wr
Write Delay -Line
programmable delay-line control logic

Read delay value (select number of delay elements)
io_dqs_in delayed_dqs
Read Delay -Line
Figure 14-13. Digital DLL
The delay-line is comprised of 137 tiny delay-elements. The delay value of each delay
element is almost the same. And the number of delay elements which is used to form a
delay result is configurable.
There are two modes for the delay-line control :
• Auto configure mode
This process begins by the “phase-detector”. Once the phase-detector successfully
complete the detection, it will raise the “dll_lock” signal and output “dll_lock_value”
which indicates the delay of cone cycle.
The number of elements that are needed to capture an entire clock cycle is then converted
into an unsigned integer named encoder [7:0]. This integer is used as the dividend for
the read and write delay parameters. The actual delay setting for the delay lines is

calculated by multiplying the encoder [7:0] integer by the parameter settings for each
delay line and then dividing by 128 and rounding. These values are then encoded into
a one-hot counter and updated at initialization and at every refresh interval.
• Bypass mode, or manual configure mode
The phase-detector can be bypassed. The number of delay elements for read and write
delay-line is programmed manually.
NOTE
In case the number of delay elements is fixed, the actual delay
value (in nano-second) of a delay-line would change according
to the environmental conditions, such as voltage, temperature,
and so on.
Using the “auto configure mode” help to eliminate the change of delay value because the
reference delay itself also changes along with environmental conditions.
14.7.10 Configure output enable of I/O Control

Some EMI I/Os require a control signal named "output enable". The I/O can drive signals
out only when the "output enable" signal is active. Refer to the figure below.
io_dq_out d0 d1 d2 d3
io_dq_out_oen
io_dqs_out
io_dqs_out_oen
Figure 14-14. EMI I/O Output Enable
There are three kinds of output enable signals in this EMI design:
• io_dq_out_oen
output enable for write data.
• io_dqm_oen
output enable for write data mask. Please configure it exactly the same as io_dq_out_oen.
• io_dqs_oen
output enable for write data strobe.
The suffix "_oen" means the output enable signal is active low.
The start time and the end time of a output enable signal can be configured separately.
The start time and the end time can be adjusted by 1/4 clock cycle in unit.
To meet the timing requirement of the I/O circuits, the start time of each output enable must
be prior to it’s corresponding output signal, and, the end time must be later than it’s
corresponding signal. In another word, the output enable signal must be "wider" than the
output signal. The margin at start time is named "pre-amble" and the margin at end time is
named "post-amble". In the example of Figure 14-14, pre-amble = 1/2 cycle while post-amble
= 1/4 cycle.

EMI Register Format Summary
HW_DRAM memory map
Absolute
Width Section/
(in bits) page
(hex)
800E_0000 DRAM Control Register 00 (HW_DRAM_CTL00) 32 R/W 0000_0000h 14.8.1/1111
800E_0004 AXI Monitor Control (HW_DRAM_CTL01) 32 R/W 0000_0000h 14.8.2/1112
800E_000C DRAM Control Register 03 (HW_DRAM_CTL03) 32 R/W 0000_0000h 14.8.4/1114
800E_0020 DRAM Control Register 08 (HW_DRAM_CTL08) 32 R 0000_0010h 14.8.9/1116
800E_0028 AXI0 Debug 0 (HW_DRAM_CTL10) 32 R 0000_0000h 14.8.11/1118
800E_002C AXI0 Debug 1 (HW_DRAM_CTL11) 32 R 0000_0000h 14.8.12/1118
800E_003C AXI2 Debug 1 (HW_DRAM_CTL15) 32 R 0000_0000h 14.8.16/1120

HW_DRAM memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
800E_0078 DRAM Control Register 30 (HW_DRAM_CTL30) 32 R 0004_0F0Ch 14.8.28/1133
800E_00A0 DRAM Control Register 40 (HW_DRAM_CTL40) 32 R/W 0000_0000h 14.8.38/1144
800E_00AC DRAM Control Register 43 (HW_DRAM_CTL43) 32 R/W 0000_0000h 14.8.41/1146
800E_00B0 DRAM Control Register 44 (HW_DRAM_CTL44) 32 R/W 0000_0000h 14.8.42/1147
800E_00C0 DRAM Control Register 48 (HW_DRAM_CTL48) 32 R/W 0000_0000h 14.8.44/1148
800E_00CC DRAM Control Register 51 (HW_DRAM_CTL51) 32 R/W 0000_0000h 14.8.47/1151
800E_00D0 DRAM Control Register 52 (HW_DRAM_CTL52) 32 R/W 0000_0000h 14.8.48/1151
800E_00DC DRAM Control Register 55 (HW_DRAM_CTL55) 32 R/W 0000_0000h 14.8.51/1154
800E_00E0 DRAM Control Register 56 (HW_DRAM_CTL56) 32 R/W 0000_0000h 14.8.52/1155


Absolute
Width Section/
(in bits) page
(hex)
800E_00EC DRAM Control Register 59 (HW_DRAM_CTL59) 32 R 0000_0000h 14.8.54/1156
800E_00F0 DRAM Control Register 60 (HW_DRAM_CTL60) 32 R 0000_0000h 14.8.55/1157
800E_00FC DRAM Control Register 63 (HW_DRAM_CTL63) 32 R 0000_0000h 14.8.58/1159


Absolute
Width Section/
(in bits) page
(hex)
800E_017C DRAM Control Register 95 (HW_DRAM_CTL95) 32 R 0000_0000h 14.8.90/1185
800E_01A0 DRAM Control Register 104 (HW_DRAM_CTL104) 32 R 0000_0000h 14.8.99/1191
800E_01AC DRAM Control Register 107 (HW_DRAM_CTL107) 32 R 0000_0000h 14.8.102/1192
800E_01B0 DRAM Control Register 108 (HW_DRAM_CTL108) 32 R 0000_0000h 14.8.103/1193
800E_01BC DRAM Control Register 111 (HW_DRAM_CTL111) 32 R 0000_0000h 14.8.106/1194
800E_01C0 DRAM Control Register 112 (HW_DRAM_CTL112) 32 R 0000_0000h 14.8.107/1195
800E_01CC DRAM Control Register 115 (HW_DRAM_CTL115) 32 R 0000_0000h 14.8.110/1196
800E_01D0 DRAM Control Register 116 (HW_DRAM_CTL116) 32 R 0000_0000h 14.8.111/1197
800E_01DC DRAM Control Register 119 (HW_DRAM_CTL119) 32 R 0000_0000h 14.8.114/1198
800E_01E0 DRAM Control Register 120 (HW_DRAM_CTL120) 32 R 0000_0000h 14.8.115/1198
800E_01EC DRAM Control Register 123 (HW_DRAM_CTL123) 32 R 0000_0000h 14.8.118/1200


Absolute
Width Section/
(in bits) page
(hex)
800E_01FC DRAM Control Register 127 (HW_DRAM_CTL127) 32 R 0000_0000h 14.8.122/1201


Absolute
Width Section/
(in bits) page
(hex)
800E_02AC DRAM Control Register 171 (HW_DRAM_CTL171) 32 R/W 0000_0000h 14.8.160/1219
800E_02BC DRAM Control Register 175 (HW_DRAM_CTL175) 32 R/W 0000_0000h 14.8.164/1223
800E_02CC DRAM Control Register 179 (HW_DRAM_CTL179) 32 R/W 0000_0000h 14.8.168/1227
800E_02DC DRAM Control Register 183 (HW_DRAM_CTL183) 32 R/W 0000_0000h 14.8.172/1231
800E_02EC DRAM Control Register 187 (HW_DRAM_CTL187) 32 R/W 0000_0000h 14.8.176/1236
800E_02F0 DRAM Control Register 188 (HW_DRAM_CTL188) 32 R/W 0000_0000h 14.8.177/1237
800E_02F4 DRAM Control Register 189 (HW_DRAM_CTL189) 32 R/W 0000_0000h 14.8.178/1238
14.8.1 DRAM Control Register 00 (HW_DRAM_CTL00)

This is a DRAM configuration register.

Address: HW_DRAM_CTL00 – 800E_0000h base + 0h offset = 800E_0000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USER_DEF_REG_0_1[31:16]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SREFRESH_
R
BRESP_
SELECT
TIMING
ENTER
CKE_
USER_DEF_REG_0_1[15:3]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_DRAM_CTL00 field descriptions

Field Description
31–3 User-defined output register 0.
USER_DEF_
Holds user-defined values that will be available as output signals param_user_def_reg_X (where X ranges
REG_0_1
from 0 to 7)
2 This bit selects which output logic drives the CKE pin.
CKE_SELECT
This is required since the initial state of CKE is low for DDR2 and high for LPDDR.
This bit MUST be set appropriately before (NOT concurrently) the EMI clock is enabled by setting field
EMI_CLK_DLL_ENABLE.
0x0 DDR2 — CKE will be low before the EMI clock is enabled and the initialization sequence commences.
0x1 LPDDR — CKE will be high before the EMI clock is enabled and the initialization sequence commences.
1 Initiates a self-refresh to the DRAMs. This pin updates the srefresh parameter.
SREFRESH_
ENTER
0 This bit changes when the BRESP is issued over the AXI bus interface for bufferable AXI write transactions.
BRESP_TIMING
0x0 BUFFERABLE — BRESP is returned when command and data are received by the AXI port.
0x1 SEMI_BUFFERABLE — BRESP is returned when command is accepted into the internal EMI
command queue.
14.8.2 AXI Monitor Control (HW_DRAM_CTL01)



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USER_DEF_REG_1[31:16]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MON_DBG_
R
STB
USER_DEF_REG_1[15:9] SLVERR MON_DISABLE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
USER_DEF_
REG_1
from 0 to 7)
8 Setting this bit to a logic 1 will initiate sampling the state of each AXI interface monitor. The diagnostic
MON_DBG_STB information available in the debug registers is valid only after this bit is set to a logic one. To take a subsequent
snapshot of the state of each AXI monitor, set this bit low, and then high again.
7–4 Setting this bit will cause all AXI transactions to be processed with a slave error when the respective monitor
SLVERR is enabled.
3–0 Setting this bit will disable the AXI monitors. None of the EMI AXI error conditions will be checked and all
MON_DISABLE AXI traffic will proceed.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
USER_DEF_REG_2
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
USER_DEF_
REG_2
from 0 to 7)

Address: HW_DRAM_CTL03 – 800E_0000h base + Ch offset = 800E_000Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
USER_DEF_REG_3
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
USER_DEF_
REG_3
from 0 to 7)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
USER_DEF_REG_4
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
USER_DEF_
REG_4
from 0 to 7)


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
USER_DEF_REG_5
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
USER_DEF_
REG_5
from 0 to 7)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
USER_DEF_REG_6
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
USER_DEF_
REG_6
from 0 to 7)


Address: HW_DRAM_CTL07 – 800E_0000h base + 1Ch offset = 800E_001Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
USER_DEF_REG_7
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
USER_DEF_
REG_7
from 0 to 7)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R USER_DEF_REG_RO_0[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SREFRESH_ACK
REFRESH_IN_
CKE_STATUS
Q_ALMOST_
CONTROLLER_
PROCESS
FULL
BUSY
R USER_DEF_REG_RO_0[15:9] COMMAND_ACCEPTED
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0


Field Description
31–9 User-defined input register 0.
USER_DEF_
Holds the value driven to the MC by the PHY on the signals param_user_def_reg_ro_X (where X ranges
REG_RO_0
from 0 to 7) at the EMI core level. There are a total of 8 user-defined input registers.
8 Status signal from the EMI. This will only be low when the EMI is not reading data, writing data or processing
CONTROLLER_ a command.
BUSY
7 Active-high signal that indicates that the EMI is executing a refresh command. This signals is asserted when
REFRESH_IN_ a refresh command is sent t othe DRAM devices and the remains asserted until the refresh command has
PROCESS completed.
6 Indicates that the queue has reached the value set in the q_fullness parameter in the controller.
Q_ALMOST_
FULL
5 Acknowledge signal that indicates that the memory devices are in self-refresh mode. This signal will only
SREFRESH_ be asserted if the DRAMs have been placed into self-refresh mode through the assertion of the srefresh_enter
ACK signal and if the signal is still held high until the memory enters self-refresh mode.
4 Indicates the memory devices are in either their self-refresh or power-down mode. This signals is the status
CKE_STATUS of the control_cke signal inside the EMI, but may be delayed through the cke_delay paramter in the contoller
to reflect the inverted CKE status on the memory bus. NOTE: this parameter is inverted with respect to the
logic state on the external CKE pin.
3–0 Indicates when bus interface commands are accepted.

COMMAND_
ACCEPTED

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R USER_DEF_REG_RO_1
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 User-defined input register 1.
USER_DEF_
Holds the value driven to the MC by the PHY on the signals param_user_def_reg_ro_X (where X ranges
REG_RO_1
from 0 to 7) at the EMI core level. There are a total of 8 user-defined input registers.

14.8.11 AXI0 Debug 0 (HW_DRAM_CTL10)

AXI0 Monitor Debug register 0.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD READ_CNT WRESP_CNT WDATA_CNT

W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–24 Reserved.
RSVD
23–16 This field will indicate how many read commands have been accepted in which their respective data beats
READ_CNT have not been returned over the data bus.
15–8 This field will indicate how many write commands have been accepted in which their respective RESP
WRESP_CNT signaling has not completed.
7–0 This field will indicate how many write commands have been accepted in which their respective data beats
WDATA_CNT have not been transferred over the data bus.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R WSTATE RSTATE RLEN WLEN

W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–24 This reflects the monitor write machine's state.
WSTATE
23–16 This reflects the monitor read machine's state.
RSTATE
15–8 This reflects the read length beat counter.
RLEN

HW_DRAM_CTL11 field descriptions (continued)

Field Description
7–0 This reflects the write length beat counter.
WLEN

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–24 Reserved.
RSVD

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
WSTATE
RSTATE
RLEN
WLEN

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–24 Reserved.
RSVD



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
WSTATE
RSTATE
RLEN
WLEN

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
POWER_DOWN
R RSVD3 RSVD2
WRITE_
W
MODEREG
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R OBSOLETE RSVD1
START
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Field Description
RSVD3
24 Write mode register data to the DRAMs. WRITE-ONLY
WRITE_
Writes mode register information into the memory devices. The user should program the appropriate
MODEREG
mrY_data_X parameters with valid information based on the memory type being used. All of the mode
registers that are relevant for the memory type specified in the dram_class parameter will be written on each
write_modereg setting. This parameter will always read back as 'b0.
The mode registers are automatically written at initialization of the EMI. There is no need to initiate a mode
register write after setting the start parameter in the EMI unless some value in these registers needs to be
changed after initialization.
This parameter may not be changed when the memory is in power-down mode (when the CKE input is
de-asserted).

RSVD2
16 Disable clock enable and set DRAMs in power-down state.
POWER_DOWN
When this parameter is set to 'b1, the EMI will complete processing of the current burst for the current
transaction (if any), issue a pre-charge all command and then disable the clock enable signal to the DRAM
devices. Any subsequent commands in the command queue will be suspended until this parameter is cleared
to 'b0.
'b0 = Enable full power state.
'b1 = Disable the clock enable and power down the EMI.

OBSOLETE
RSVD1
0 Initiate cmd processing in the controller.
START
Prior to setting this parameter to 1'b1, the EMI will not issue any commands to the DRAM devices or respond
to any signal activity except for reading and writing parameters and accepting traffic that the customer may
send to the EMI internal queues. Once this parameter is set to 1'b1, the EMI will respond to inputs from the
ASIC and begin to process memory access commands. Note that resetting this parameter to 1'b0 will not
shut off traffic. However, cycling this parameter to 1'b0 and then resetting it to 1'b1 will reset the digital DLL
to a new input clock frequency if desired. This protocol is described in detail in section Changing Input Clock
Frequency. Note: Until the initialization complete bit is set in the int_status parameter and the dfi_init_complete
signal is asserted from the PHY, commands will not be accepted into the core command queue.
'b0 = Controller is not in active mode.
'b1 = Initiate active mode for the EMI.



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AUTO_REFRESH_MODE
R RSVD4 RSVD3
W AREFRESH
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENABLE_QUICK_
R RSVD2 RSVD1
SREFRESH
SREFRESH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSVD4
24 Define auto-refresh to occur at next burst or next cmd boundary.
AUTO_
Sets the mode for when the automatic refresh will occur. If the auto_refresh_mode parameter is set and a
REFRESH_
refresh is required to memory, the EMI will delay this refresh until the end of the current transaction (if the
MODE
transaction is fully contained inside a single page), or until the current transaction hits the end of the current
page.
'b0 = Issue refresh on the next DRAM burst boundary, even if the current command is not complete.
'b1 = Issue refresh on the next command boundary.

RSVD3
16 Trigger auto-refresh at boundary specified by AUTO_REFRESH_MODE. WRITE-ONLY
AREFRESH
Initiates an automatic refresh to the DRAM devices based on the setting of the auto_refresh_mode parameter.
If there are any open banks when this parameter is set, the EMI will automatically close these banks before
issuing the auto-refresh command. This parameter will always read back as 0x0.
'b0 = No action
'b1 = Issue refresh to the DRAM devices

RSVD2


Field Description
8 Allow user to interrupt memory initialization to enter self-refresh mode.
ENABLE_
When this bit is set to 'b1, the memory initialization sequence may be interrupted and the memory may enter
QUICK_
self-refresh mode. This is used to place the memory devices into self-refresh mode when a power loss is
SREFRESH
detected during the initialization process.
'b0 = Continue memory initialization.
'b1 = Interrupt memory initialization and enter self-refresh mode.

RSVD1
0 Place DRAMs in self-refresh mode.
SREFRESH
When this parameter is set to 'b1, the DRAM device(s) will be placed in self-refresh mode. For this, the
current burst for the current transaction (if any) will complete, all banks will be closed, the self-refresh
command will be issued to the DRAM, and the clock enable signal will be de-asserted. The system will
remain in self-refresh mode until this parameter is cleared to 'b0. The DRAM devices will return to normal
operating mode after the self-refresh exit time (the txsr parameter) of the device and any DLL initialization
time for the DRAM is reached. The EMI will resume processing of the commands from the interruption point.
This parameter will be updated with an assertion of the srefresh_enter pin, regardless of the behavior on
the register interface. To disable self-refresh again after a srefresh_enter pin assertion, the user will need
to clear the parameter to 'b0.
'b0 = Disable self-refresh mode.
'b1 = Initiate self-refresh of the DRAM devices.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD3 DLL_LOCK
CKE_DELAY
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLLLOCKREG
DLL_BYPASS_MODE
R RSVD2 RSVD1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSVD3
26–24 Additional cycles to delay CKE for status reporting.
CKE_DELAY
Sets the number of additional cycles of delay to include in the CKE signal cke_status for status reporting.
The default delay is 0 cycles.
23–16 Number of delay elements in master DLL lock. READ-ONLY

DLL_LOCK
Defines the actual number of delay elements used to capture one full clock cycle. This parameter is
automatically updated every time a refresh operation is performed. This parameter is read-only.

RSVD2
8 Status of DLL lock coming out of master delay. READ-ONLY
DLLLOCKREG
Shows status of the DLL as locked or unlocked. This parameter is read-only
'b0 = DLL is unlocked.
'b1 = DLL is locked.

RSVD1
0 Enable the DLL bypass feature of the controller.
DLL_BYPASS_
This parameter has no meaning for this EMI.
MODE



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R OBSOLETE RSVD3 LOWPOWER_ RSVD2 RSVD1

LOWPOWER_ LOWPOWER_
REFRESH_
W CONTROL AUTO_ENABLE
ENABLE
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
OBSOLETE
RSVD3
19–16 Enable refreshes while in low power mode.
LOWPOWER_
Sets whether refreshes will occur while the EMI is in any of the low power modes.
REFRESH_
ENABLE This parameter is active low.
'b0 = Refreshes still occur
'b1 = Refreshes do not occur

RSVD2
12–8 Controls entry into the low power modes.
LOWPOWER_
Enables the individual low power modes of the device.
CONTROL
Bit [4] = Controls memory power-down mode (Mode 1).
Bit [3] = Controls memory power-down with memory clock gating mode (Mode 2).
Bit [2] = Controls memory self-refresh mode (Mode 3).
Bit [1] = Controls memory self-refresh with memory clock gating mode (Mode 4).
Bit [0] = Controls memory self-refresh with memory and controller clock gating mode (Mode 5).
For all bits:
'b0 = Disabled.
'b1 = Enabled.

RSVD1
4–0 Enables automatic entry into the low power mode on idle.
LOWPOWER_
Enables automatic entry into the low power modes of the EMI.
AUTO_ENABLE
Bit [4] = Controls memory power-down mode (Mode 1).
Bit [3] = Controls memory power-down with memory clock gating mode (Mode 2).
Bit [2] = Controls memory self-refresh mode (Mode 3).
Bit [1] = Controls memory self-refresh with memory clock gating mode (Mode 4).
Bit [0] = Controls memory self-refresh with memory and controller clock gating mode (Mode 5).
It is not possible to enter Mode 5 manually. Setting bit [0] of lowpower_control with bit [0] of this parameter
cleared will not result in any change.


Field Description
The user should not use both automatic and manual modes for the various low power modes. All modes
should be entered automatically or all entered manually.
For all bits:
'b0 = Automatic entry into this mode is disabled. The user may enter this mode manually by setting the
associated lowpower_control bit.
'b1 = Automatic entry into this mode is enabled. The mode will be entered automatically when the proper
counters expire, and only if the associated lowpower_control bit is set.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LOWPOWER_INTERNAL_CNT LOWPOWER_EXTERNAL_CNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–16 Counts idle cycles to self-refresh with memory and controller clk gating.
LOWPOWER_
Counts the number of idle cycles before memory self-refresh with memory and controller clock gating low
INTERNAL_CNT
power mode.
15–0 Counts idle cycles to self-refresh with memory clock gating.

LOWPOWER_
Counts the number of idle cycles before memory self-refresh with memory clock gating low power mode.
EXTERNAL_CNT

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LOWPOWER_SELF_REFRESH_CNT LOWPOWER_REFRESH_HOLD
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
31–16 Counts idle cycles to memory self-refresh.
LOWPOWER_
Counts the number of cycles to the next memory self-refresh low power mode.
SELF_
REFRESH_CNT
15–0 Re-Sync counter for DLL in Clock Gate Mode.
LOWPOWER_
Sets the number of cycles that the EMI will wait before attempting to re-lock the DLL when using the controller
REFRESH_
clock gating mode low power mode. This counter will ONLY be used in this mode, the deepest low power
HOLD
mode.
When this counter expires, the DLL will be un-gated for at least 16 cycles during which the DLL will attempt
to re-lock. After 16 cycles have elapsed and the DLL has locked, then the DLL controller clock will be gated
again and the counter will reset to this value. If the DLL requires more than 16 cycles to re-lock, then the
un-gated time will be longer.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R OBSOLETE
LOWPOWER_POWER_DOWN_CNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
OBSOLETE
15–0 Counts idle cycles to memory power-down.
LOWPOWER_
Counts the number of idle cycles before memory power-down or power-down with memory clock gating low
POWER_DOWN_
power mode.
CNT



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY_EN
R OBSOLETE RSVD3
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR_CMP_EN
PLACEMENT_EN
R RSVD2 RSVD1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
OBSOLETE
RSVD3
16 Enable priority for cmd queue placement logic.
PRIORITY_EN
Enables priority as a condition when using the placement logic to fill the command queue.
'b0 = Disabled
'b1 = Enabled

RSVD2
8 Enable address collision detection for cmd queue placement logic.
ADDR_CMP_EN
Enables address collision/data coherency detection as a condition when using the placement logic to fill the
command queue.
'b0 = Disabled
'b1 = Enabled

RSVD1
0 Enable placement logic for cmd queue.
PLACEMENT_
Enables using the placement logic to fill the command queue.
EN
'b0 = Placement logic is disabled. The command queue is a straight FIFO.
'b1 = Placement logic is enabled. The command queue will be filled according to the placement logic factors.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWAP_
R RSVD4 RSVD3
SWAP_EN
PORT_
RW_
W SAME_
EN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RW_SAME_
SPLIT_EN
R RSVD2 RSVD1
BANK_
EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSVD4
24 No meaning for this MC.
SWAP_PORT_
When swapping in enabled (swap_en is set to 'b1), this parameter enables swapping between read commands
RW_SAME_EN
on the same port from different requestors. Commands from the same requestor can not be swapped.
While read data may be interleaved, write data must be accepted in order on a port. The MC logic will not
swap write commands from the same port, even if this bit is enabled.
This situation will be uncommon since all read commands on the same port enter the command queue at
the priority defined in axiY_r_priority. However, this situation may occur through command aging.
'b0 = Disabled
'b1 = Enabled

RSVD3
16 Enable command swapping logic in execution unit.
SWAP_EN
Enables swapping of the active command for a new higher-priority command when using the placement
logic.
'b0 = Disabled
'b1 = Enabled

RSVD2
8 Enable bank splitting for cmd queue placement logic.
BANK_SPLIT_EN
Enables bank splitting as a condition when using the placement logic to fill the command queue.


Field Description
'b0 = Disabled
'b1 = Enabled

RSVD1
0 Enable read/write grouping for cmd queue placement logic.
RW_SAME_EN
Enables read/write grouping as a condition when using the placement logic to fill the command queue.
'b0 = Disabled
'b1 = Enabled

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD4 RSVD3
Q_FULLNESS AGE_COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 RSVD1
ACTIVE_
AGING
COMMAND_AGE_COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSVD4
26–24 Quantity that determines cmd queue full.
Q_FULLNESS
Defines quantity of data that will be considered full for the command queue.

RSVD3
19–16 Initial value of master aging-rate counter for cmd aging.
AGE_COUNT
Holds the initial value of the master aging-rate counter. When using the placement logic to fill the command
queue, the command aging counters will be decremented one each time the master aging-rate counter
counts down age_count cycles.


Field Description
RSVD2
11–8 Initial value of individual cmd aging counters for cmd aging.
COMMAND_
Holds the initial value of the command aging counters associated with each command in the command
AGE_COUNT
queue. When using the placement logic to fill the command queue, the command aging counters decrement
one each time the master aging-rate counter counts down the number of cycles in the age_count parameter.

RSVD1
0 Enable command aging in the command queue.
ACTIVE_AGING
Enables aging of commands in the command queue when using the placement logic to fill the command
queue.
The total number of cycles required to decrement the priority value on a command by one is the product of
the values in the age_count and command_age_count parameters.
'b0 = Disabled
'b1 = Enabled

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD4 RSVD3 COLUMN_ RSVD2 ADDR_ RSVD1

CS_MAP APREBIT
W SIZE PINS
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD4
27–24 Defines which chip selects are active.
CS_MAP
Sets the mask that determines which chip select pins are active, with each bit representing a different chip
select. The user address chip select field will be mapped into the active chip selects indicated by this
parameter in ascending order from lowest to highest. This allows the EMI to map the entire contiguous user
address into any group of chip selects. Bit [0] of this parameter corresponds to chip select [0], bit [1]
corresponds to chip select [1], etc. The number of chip selects, the number of bits set to 1 in this parameter,
must be a power of 2.

RSVD3


Field Description
18–16 Difference between number of column pins available and number being used.
COLUMN_SIZE
Shows the difference between the maximum column width available (12) and the actual number of column
pins being used. The user address is automatically shifted so that the user address space is mapped
contiguously into the memory map based on the value of this parameter.

RSVD2
10–8 Difference between number of addr pins available and number being used.
ADDR_PINS
Defines the difference between the maximum number of address pins configured (15) and the actual number
of pins being used.
The user address is automatically shifted so that the user address space is mapped contiguously into the
memory map based on the value of this parameter.

RSVD1
3–0 Location of the auto pre-charge bit in the DRAM address.
APREBIT
Defines the location of the auto pre-charge bit in the DRAM address in decimal encoding.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R OBSOLETE RSVD3 MAX_CS_REG
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 MAX_ROW_REG RSVD1 MAX_COL_REG
Reset 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0

Field Description
OBSOLETE
RSVD3


Field Description
18–16 Maximum number of chip selects available. READ-ONLY
MAX_CS_REG
Displays the maximum number of chip selects configured for this EMI. This parameter is read-only.

RSVD2
11–8 Maximum width of memory address bus. READ-ONLY
MAX_ROW_REG
Defines the maximum width of the memory address bus for the EMI.
This value can be used to set the addr_pins parameter. This parameter is read-only.
addr_pins = max_row_reg - <number of row bits in memory device>.

RSVD1
3–0 Maximum width of column address in DRAMs. READ-ONLY
MAX_COL_REG
Defines the maximum width of column address in the DRAM devices. This value can be used to set the
column_size parameter. This parameter is read-only.
column_size = max_col_reg - <number of column bits in memory device>.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EIGHT_BANK_
R OBSOLETE RSVD3
MODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRIVE_DQ_
DQS_N_EN
R RSVD2 RSVD1
DQS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
OBSOLETE


Field Description
RSVD3
16 Number of banks on the DRAM(s).
EIGHT_BANK_
Indicates that the memory devices have eight banks.
MODE
'b0 = Memory devices have 4 banks.
'b1 = Memory devices have 8 banks.

RSVD2
8 Sets DQ/DQS output enable behavior when controller is idle.
DRIVE_DQ_DQS
Selects if the DQ output enables and DQS output enables will be driven active when the EMI is in an idle
state.
'b0 = Leave the output enables in their current state when idle.
'b1 = Drive the idle_drive_enable signal high when idle.

RSVD1
0 Set DQS pin as single-ended or differential.
DQS_N_EN
Enables differential data strobe signals from the DRAM. This parameter is only relevant for the DDR PHY.
'b0 = Single-ended DQS signal from the DRAM.
'b1 = Differential DQS signal from the DRAM.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R OBSOLETE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REG_DIMM_
R RSVD2 RSVD1
ENABLE
REDUC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Field Description
OBSOLETE
RSVD2
8 Enable the half datapath feature of the controller.
REDUC
Controls the width of the memory datapath. When enabled, the upper half of the memory buses (DQ, DQS
and DM) are unused and relevant data only exists in the lower half of the buses. This parameter expands
the EMI for use with memory devices of the configured width or half of the configured width.
The entire user datapath is used regardless of this setting.
'b0 = Standard operation using full memory bus.
'b1 = Memory datapath width is half of the maximum size. The upper half of the data_byte_disable bus will
be driven to 'b1.

RSVD1
0 Enable registered DIMM operation of the controller.
REG_DIMM_
Enables registered DIMM operations to control the address and command pipeline of the EMI.
ENABLE
'b0 = Normal operation
'b1 = Enable registered DIMM operation

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R OBSOLETE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CONCURRENTAP
R RSVD2 RSVD1
AP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Field Description
OBSOLETE
RSVD2
8 Allow controller to issue cmds to other banks while a bank is in auto pre-charge.
CONCURRENTAP
Enables concurrent auto pre-charge. Some DRAM devices do not allow one bank to be auto pre-charged
while another bank is reading or writing. The JEDEC standard allows concurrent auto pre-charge. The
user should set this parameter if the DRAM device supports this feature.
'b0 = Concurrent auto pre-charge disabled.
'b1 = Concurrent auto pre-charge enabled.

RSVD1
0 Enable auto pre-charge mode of controller.
AP
Enables auto pre-charge mode for DRAM devices.
This parameter may not be modified after the start parameter has been asserted.
'b0 = Auto pre-charge mode disabled. Memory banks will stay open until another request requires this
bank, the maximum open time (tras_max) has elapsed, or a refresh command closes all the banks.
'b1 = Auto pre-charge mode enabled. All read and write transactions must be terminated by an auto
pre-charge command. If a transaction consists of multiple read or write bursts, only the last command is
issued with an auto pre-charge.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRITEINTERP
R RSVD4 RSVD3 INTRPTWRITEA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTRPTAPBURST
INTRPTREADA
R RSVD2 RSVD1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSVD4
24 Allow controller to interrupt a write burst to the DRAMs with a read cmd.
WRITEINTERP
Defines whether the EMI can interrupt a write burst with a read command. Some memory devices do not
allow this functionality.
For DDR1 or LPDDR1 memory devices, consult the memory specification for the setting for this parameter.
For DDR2memory devices, this parameter must be cleared to 'b0.
'b0 = The device does not support read commands interrupting write commands.
'b1 = The device does support read commands interrupting write commands.

RSVD3
16 Allow the controller to interrupt a combined write with auto pre-charge cmd with another write cmd.
INTRPTWRITEA
Enables interrupting of a combined write with auto pre-charge command with another read or write command
to the same bank before the first write command is completed.
'b0 = Disable interrupting a combined write with auto pre-charge command with another read or write
command to the same bank.
'b1 = Enable interrupting a combined write with auto pre-charge command with another read or write
command to the same bank.

RSVD2
8 Allow the controller to interrupt a combined read with auto pre-charge cmd with another read cmd.
INTRPTREADA
Enables interrupting of a combined read with auto pre-charge command with another read command to
the same bank before the first read command is completed.
'b0 = Disable interrupting the combined read with auto pre-charge command with another read command
to the same bank.
'b1 = Enable interrupting the combined read with auto pre-charge command with another read command
to the same bank.

RSVD1
0 Allow the controller to interrupt an auto pre-charge cmd with another cmd.
INTRPTAPBURST
Enables interrupting an auto pre-charge command with another command for a different bank. If enabled,
the current operation will be interrupted. However, the bank will be pre-charged as if the current operation
were allowed to continue.
'b0 = Disable interrupting an auto pre-charge operation on a different bank.


Field Description
'b1 = Enable interrupting an auto pre-charge operation on a different bank.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SREFRESH_
R OBSOLETE RSVD3
PWRUP_
EXIT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NO_CMD_
R RSVD2 RSVD1
INIT
INITAREF
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
OBSOLETE
RSVD3
16 Allow powerup through self-refresh instead of full memory initialization.
PWRUP_
Allows controller to exit power-down mode by executing a self-refresh exit instead of the full memory
SREFRESH_
initialization. This parameter provides a means to skip full initialization when the DRAM devices are in a
EXIT
known self-refresh state.
'b0 = Disabled
'b1 = Enabled

RSVD2
8 Disable DRAM cmds until TDLL has expired during initialization.
NO_CMD_INIT
Disables DRAM commands until DLL initialization is complete and tdll has expired.
'b0 = Issue only REF and PRE commands during DLL initialization of the DRAM devices. If PRE commands
are issued before DLL initialization is complete, the command will be executed immediately, and then the
DLL initialization will continue.


Field Description
'b1 = Do not issue any type of command during DLL initialization of the DRAM devices. If any other commands
are issued during the initialization time, they will be held off until DLL initialization is complete.

RSVD1
3–0 Number of auto-refresh cmds to execute during DRAM initialization.
INITAREF
Defines the number of auto-refresh commands needed by the DRAM devices to satisfy the initialization
sequence.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD3 RSVD2
LOCKOUT
R
ENABLE
TREF_
TRAS_
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R OBSOLETE RSVD1
WRITE
FAST_
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSVD3
24 Issue auto-refresh cmds to the DRAMs every TREF cycles.
TREF_ENABLE
Enables refresh commands. If command refresh mode is configured, then refresh commands will be
automatically issued based on the tref parameter value and any refresh commands sent through the command
interface or the register interface. Refreshes will still occur even if the DRAM devices have been placed in
power down state by the assertion of the power_down parameter.
'b0 = Refresh commands disabled.
'b1 = Refresh commands enabled.

RSVD2


Field Description
16 Allow the controller to execute auto pre-charge cmds before TRAS_MIN expires.
TRAS_LOCKOUT
Defines the tRAS lockout setting for the DRAM device. tRAS lockout allows the EMI to execute auto pre-charge
commands before the tras_min parameter has expired.
'b0 = tRAS lockout not supported by memory device.
'b1 = tRAS lockout supported by memory device.

OBSOLETE
RSVD1
0 Define when write cmds are issued to DRAM devices.
FAST_WRITE
Controls when the write commands are issued to the DRAM devices.
'b0 = The EMI will issue a write command to the DRAM devices when it has received enough data for one
DRAM burst. In this mode, write data can be sent in any cycle relative to the write command. This mode
also allows for multi-word write command data to arrive in non-sequential cycles.
'b1 = The EMI will issue a write command to the DRAM devices after the first word of the write data is
received by the EMI. The first word can be sent at any time relative to the write command. In this mode,
multi-word write command data must be available to the EMI in sequential cycles.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD4 CASLAT_LIN_ RSVD3 RSVD2 RSVD1

CASLAT_LIN CASLAT WRLAT
W GATE
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD4
27–24 Adjusts data capture gate open by half cycles.
CASLAT_LIN_
Adjusts the data capture gate open time by 1/2 cycle increments. This parameter is programmed differently
GATE
than caslat_lin when there are fixed offsets in the flight path between the memories and the EMI for clock
gating. When caslat_lin_gate is a larger value than caslat_lin, the data capture window will become shorter.
A caslat_lin_gate value smaller than caslat_lin may have no effect on the data capture window, depending
on the fixed offsets in the ASIC and the board.
For optimal synthesis behavior, the ODT path for a CAS latency of three is clocked at a 200 MHz clock
regardless of configured maximum speed.


Field Description
'b0000 - 'b0001 = Reserved
'b0010 = 1 cycle
'b0011 = 1.5 cycles
'b0100 = 2 cycles
'b0101 = 2.5 cycles
'b0110 = 3 cycles
'b0111 = 3.5 cycles
'b1000 = 4 cycles
'b1001 = 4.5 cycles
'b1010 = 5 cycles
'b1011 = 5.5 cycles
'b1100 = 6 cycles
'b1101 = 6.5 cycles
'b1110 = 7 cycles
'b1111 = 7.5 cycles

RSVD3
19–16 Sets latency from read cmd send to data receive from/to controller.
CASLAT_LIN
Sets the CAS latency linear value in 1/2 cycle increments. This sets an internal adjustment for the delay
from when the read command is sent from the EMI to when data will be received back. The window of time
in which the data is captured is a fixed length. The caslat_lin parameter adjusts the start of this data capture
window.
Not all linear values will be supported for the memory devices being used. Refer to the specification for the
memory devices being used.
'b0000 - 'b0001 = Reserved
'b0010 = 1 cycle
'b0011 = 1.5 cycles
'b0100 = 2 cycles
'b0101 = 2.5 cycles
'b0110 = 3 cycles
'b0111 = 3.5 cycles
'b1000 = 4 cycles
'b1001 = 4.5 cycles
'b1010 = 5 cycles
'b1011 = 5.5 cycles
'b1100 = 6 cycles
'b1101 = 6.5 cycles


Field Description
'b1110 = 7 cycles
'b1111 = 7.5 cycles

RSVD2
10–8 Encoded CAS latency sent to DRAMs during initialization.
CASLAT
Sets the CAS (Column Address Strobe) latency encoding that the memory uses.The binary value programmed
into this parameter is dependent on the memory device, since the same caslat value may have different
meanings to different memories. This will be programmed into the DRAM devices at initialization. The CAS
encoding will be specified in the DRAM spec sheet, and should correspond to the caslat_lin parameter.
Refer to the files in the regconfigs/ directory in the release for actual settings for each particular device.

RSVD1
3–0 DRAM WRLAT parameter in cycles.
WRLAT
Defines the write latency from when the write command is issued to the time the write data is presented to
the DRAM devices, in cycles.
This parameter must be set to 'b1 when the EMI is used in DDR1 mode.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 RSVD1
TDAL TCPD TCKE
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
28–24 DRAM TDAL parameter in cycles.
TDAL
Defines the auto pre-charge write recovery time when auto pre-charge is enabled (the ap parameter is set
to 'b1), in cycles. This is defined internally as tRP (pre-charge time) + auto pre-charge write recovery time.


Field Description
Not all memories use this parameter. If tDAL is defined in the memory specification, then program this
parameter to the specified value. If the memory does not specify a tDAL time, then program this parameter
to tWR + tRP. DO NOT program this parameter with a value of 0x0 or the EMI will not function properly
when auto pre-charge is enabled.
23–8 DRAM TCPD parameter in cycles.

TCPD
Defines the clock enable to pre-charge delay time for the DRAM devices, in cycles.

RSVD1
2–0 Minimum CKE pulse width.
TCKE
Defines the minimum CKE pulse width, in cycles.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1 OBSOLETE
TFAW TDLL
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD1
29–24 DRAM TFAW parameter in cycles.
TFAW
Defines the DRAM tFAW parameter, in cycles.

OBSOLETE
15–0 DRAM TDLL parameter in cycles.
TDLL
Defines the DRAM DLL lock time, in cycles.


Address: HW_DRAM_CTL40 – 800E_0000h base + A0h offset = 800E_00A0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1
TMRD TINIT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD1
28–24 DRAM TMRD parameter in cycles.
TMRD
Defines the minimum number of cycles required between two mode register write commands. This is the
time required to complete the write operation to the mode register.
23–0 DRAM TINIT parameter in cycles.

TINIT
Defines the DRAM initialization time, in cycles.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1
TPDEX TRCD_INT TRC
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–16 DRAM TPDEX parameter in cycles.
TPDEX
Defines the DRAM power-down exit command period, in cycles.
15–8 DRAM TRCD parameter in cycles.

TRCD_INT
Defines the DRAM RAS to CAS delay, in cycles.

RSVD1
5–0 DRAM TRC parameter in cycles.
TRC
Defines the DRAM period between active commands for the same bank, in cycles.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R OBSOLETE
TRAS_MAX TRAS_MIN
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
OBSOLETE
23–8 DRAM TRAS_MAX parameter in cycles.
TRAS_MAX
Defines the DRAM maximum row active time, in cycles.
7–0 DRAM TRAS_MIN parameter in cycles.

TRAS_MIN
Defines the DRAM minimum row activate time, in cycles.

Address: HW_DRAM_CTL43 – 800E_0000h base + ACh offset = 800E_00ACh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 RSVD1
TRP TRFC TREF
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
27–24 DRAM TRP parameter in cycles.
TRP
Defines the DRAM pre-charge command time, in cycles.
23–16 DRAM TRFC parameter in cycles.

TRFC
Defines the DRAM refresh command time, in cycles.


Field Description
RSVD1
13–0 DRAM TREF parameter in cycles.
TREF
Defines the DRAM cycles between refresh commands.

Address: HW_DRAM_CTL44 – 800E_0000h base + B0h offset = 800E_00B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD4 RSVD3 RSVD2 RSVD1

TWTR TWR_INT TRTP TRRD
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD4
27–24 DRAM TWTR parameter in cycles.
TWTR
Sets the number of cycles needed to switch from a write to a read operation, as dictated by the DDR SDRAM
specification.

RSVD3
20–16 DRAM TWR parameter in cycles.
TWR_INT
Defines the DRAM write recovery time, in cycles.

RSVD2
10–8 DRAM TRTP parameter in cycles.
TRTP
For DDR1, this parameter has no meaning. For LPDDR1 or DDR2, defines the DRAM tRTP (read to
pre-charge time) parameter, in cycles.

RSVD1
2–0 DRAM TRRD parameter in cycles.
TRRD
Defines the DRAM activate to activate delay for different banks, in cycles.


Address: HW_DRAM_CTL45 – 800E_0000h base + B4h offset = 800E_00B4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TXSR TXSNR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–16 DRAM TXSR parameter in cycles.
TXSR
Defines the DRAM time from a self-refresh exit to a command that requires the memory DLL to be locked.
15–0 DRAM TXSNR parameter in cycles.

TXSNR
Defines the DRAM time from a self-refresh exit to a command that does not require the memory DLL to be
locked. (txs)

Address: HW_DRAM_CTL48 – 800E_0000h base + C0h offset = 800E_00C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AXI0_BDW_
AXI0_CURRENT_BDW RSVD3
OVFLOW
R RSVD4
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 RSVD1
AXI0_FIFO_
AXI0_BDW
TYPE_REG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSVD4


Field Description
30–24 Current bandwidth usage percentage for port 0. READ-ONLY.
AXI0_
CURRENT_BDW
RSVD3
16 Port 0 behavior when bandwidth maximized.
AXI0_BDW_
OVFLOW
RSVD2
14–8 Maximum bandwidth percentage for port 0.
AXI0_BDW
RSVD1
1–0 Clock domain relativity between AXI port 0 and core logic.
AXI0_FIFO_
TYPE_REG

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 AXI0_W_ RSVD1 AXI0_R_

AXI0_EN_SIZE_LT_WIDTH_INSTR
W PRIORITY PRIORITY
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–16 Allow narrow instructions from AXI port 0 requestors with bit enabled.
AXI0_EN_SIZE_
LT_WIDTH_
INSTR
RSVD2
10–8 Priority of write cmds from AXI port 0.
AXI0_W_
PRIORITY
RSVD1


Field Description
2–0 Priority of read cmds from AXI port 0.
AXI0_R_
PRIORITY

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AXI1_BDW_
OVFLOW
R RSVD4
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 RSVD1
AXI1_FIFO_
AXI1_BDW
TYPE_REG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSVD4
AXI1_
CURRENT_BDW
RSVD3
AXI1_BDW_
OVFLOW
RSVD2
AXI1_BDW
RSVD1


Field Description
AXI1_FIFO_
TYPE_REG

Address: HW_DRAM_CTL51 – 800E_0000h base + CCh offset = 800E_00CCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W PRIORITY PRIORITY
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
AXI1_EN_SIZE_
LT_WIDTH_
INSTR
RSVD2
AXI1_W_
PRIORITY
RSVD1
AXI1_R_
PRIORITY


Address: HW_DRAM_CTL52 – 800E_0000h base + D0h offset = 800E_00D0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AXI2_BDW_
OVFLOW
R RSVD4
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 RSVD1
AXI2_FIFO_
AXI2_BDW
TYPE_REG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSVD4
AXI2_
CURRENT_BDW
RSVD3
AXI2_BDW_
OVFLOW
RSVD2
AXI2_BDW
RSVD1
AXI2_FIFO_
TYPE_REG



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W PRIORITY PRIORITY
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
AXI2_EN_SIZE_
LT_WIDTH_
INSTR
RSVD2
AXI2_W_
PRIORITY
RSVD1
AXI2_R_
PRIORITY

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AXI3_BDW_
OVFLOW
R RSVD4
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 RSVD1
AXI3_FIFO_
AXI3_BDW
TYPE_REG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Field Description
RSVD4
AXI3_
CURRENT_BDW
RSVD3
AXI3_BDW_
OVFLOW
RSVD2
AXI3_BDW
RSVD1
AXI3_FIFO_
TYPE_REG

Address: HW_DRAM_CTL55 – 800E_0000h base + DCh offset = 800E_00DCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W PRIORITY PRIORITY
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
AXI3_EN_SIZE_
LT_WIDTH_
INSTR
RSVD2
AXI3_W_
PRIORITY


Field Description
RSVD1
AXI3_R_
PRIORITY

Address: HW_DRAM_CTL56 – 800E_0000h base + E0h offset = 800E_00E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R OBSOLETE[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R OBSOLETE[15:8] RSVD1
ARB_CMD_Q_
THRESHOLD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
OBSOLETE
RSVD1
2–0 Threshold for cmd queue fullness related to overflow.
ARB_CMD_Q_
Sets the command queue fullness that determines if ports will be allowed to overflow. This parameter is
THRESHOLD
used in conjunction with the axiY_bdw_ovflow parameters.


Address: HW_DRAM_CTL58 – 800E_0000h base + E8h offset = 800E_00E8h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 INT_STATUS RSVD1

INT_MASK
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
26–16 Status of interrupt features in the controller. READ-ONLY
INT_STATUS
Shows the status of all possible interrupts generated by the EMI. The MSB is the result of a logical OR of
all the lower bits. This parameter is read-only.
Backwards compatibility is available for register parameters across configurations. However, even with this
compatibility, the individual bits, their meaning and the size of the int_status parameter may change.
The int_status bits correspond to these interrupts:
Bit [10] = Logical OR of all lower bits.
Bit [9] = User-initiated DLL resync is finished.
Bit [8] = DLL lock state change condition detected. (i.e. lock to unlock or unlock to lock)
Bit [7] = Indicates that a read DQS gate error occurred.
Bit [6] = ODT enabled and CAS Latency 3 programmed error detected. This is an unsupported programming
option.
Bit [5] = Both DDR2 and Mobile modes have been enabled.
Bit [4] = DRAM initialization complete.
Bit [3] = Error was found with command data channel in a port.
Bit [2] = Error was found with command channel in a port.
Bit [1] = Multiple accesses outside the defined PHYSICAL memory space detected.
Bit [0] = A single access outside the defined PHYSICAL memory space detected.

RSVD1
10–0 Mask for controller_int signals from the INT_STATUS parameter.
INT_MASK
Active-high mask bits that control the value of the EMI_int signal on the ASIC interface. Unless the user has
suppressed interrupt reporting (by setting bit [10] of this parameter to 'b1), bits [9:0] of the int_mask parameter
will be inverted and logically AND'ed with bits [9:0] of the int_status parameter and the result is reported on
the controller_int signal.


Address: HW_DRAM_CTL59 – 800E_0000h base + ECh offset = 800E_00ECh

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R OUT_OF_RANGE_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Address of cmd that caused an Out-of-Range interrupt. READ-ONLY.
OUT_OF_
RANGE_ADDR

Address: HW_DRAM_CTL60 – 800E_0000h base + F0h offset = 800E_00F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R OBSOLETE[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUT_OF_
R OBSOLETE[15:8] RSVD1 RANGE_
ADDR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
OBSOLETE
RSVD1
1–0 Address of cmd that caused an Out-of-Range interrupt. READ-ONLY.
OUT_OF_
RANGE_ADDR


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD3 OUT_OF_RANGE_TYPE RSVD2 OUT_OF_RANGE_LENGTH
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1 OUT_OF_RANGE_SOURCE_ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSVD3
29–24 Type of cmd that caused an Out-of-Range interrupt. READ-ONLY
OUT_OF_
Holds the type of command that caused an out-of-range interrupt request to the memory devices. This
RANGE_TYPE
parameter is read-only.

RSVD2
22–16 Length of cmd that caused an Out-of-Range interrupt. READ-ONLY
OUT_OF_
Holds the length of the command that caused an out-of-range interrupt request to the memory devices. This
RANGE_
parameter is read-only.
LENGTH
RSVD1
12–0 Source ID of cmd that caused an Out-of-Range interrupt. READ-ONLY
OUT_OF_
Holds the Source ID of the command that caused an out-of-range interrupt request to the memory devices.
RANGE_
This parameter is read-only.
SOURCE_ID



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PORT_CMD_ERROR_ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Address of port that caused the PORT cmd error. READ-ONLY.
PORT_CMD_
ERROR_ADDR

Address: HW_DRAM_CTL63 – 800E_0000h base + FCh offset = 800E_00FCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R OBSOLETE[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PORT_CMD_
R OBSOLETE[15:8] RSVD1
ERROR_ADDR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
OBSOLETE
RSVD1
1–0 Address of port that caused the PORT cmd error. READ-ONLY.
PORT_CMD_
ERROR_ADDR


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R OBSOLETE RSVD2 PORT_CMD_ERROR_ID[20:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PORT_CMD_ERROR_ID[15:8] RSVD1 PORT_CMD_ERROR_TYPE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
OBSOLETE
RSVD2
20–8 Source ID of cmd that caused the PORT cmd error. READ-ONLY
PORT_CMD_
Holds the source ID of the command that caused a port command error condition.
ERROR_ID
For AXI ports, the source ID is comprised of the Port ID and the Requestor ID, where the Requestor ID is
the axiY_AWID for write commands or the axiY_ARID for read commands.

RSVD1
3–0 Type of error and access type that caused the PORT cmd error. READ-ONLY
PORT_CMD_
Defines the type of error and the access type that caused the port command error condition. If multiple bits
ERROR_TYPE
are set to 'b1, then multiple errors were found. This parameter is read-only.
Bit [3] = Narrow transfer requested for a requestor Y whose axiY_en_size_lt_width_instr parameter is clear.
Bit [2] = Reserved.
Bit [1] = Reserved.
Bit [0] = Reserved.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R OBSOLETE RSVD2 PORT_DATA_ERROR_ID[20:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PORT_DATA_
R PORT_DATA_ERROR_ID[15:8] RSVD1
ERROR_TYPE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
OBSOLETE
RSVD2
20–8 Source ID of cmd that caused the PORT data error. READ-ONLY
PORT_DATA_
Holds the source ID of the command that caused a port data error condition.
ERROR_ID
For AXI ports, the source ID is comprised of the Port ID and the Requestor ID, where the Requestor ID is
the axiY_BID for write response errors, the axiY_RID for read data errors, or the axiY_WID for write data
errors.

RSVD1
2–0 Type of error and access type that caused the PORT data error. READ-ONLY
PORT_DATA_
Defines the type of error and the access type that caused the port data error condition. If multiple bits are
ERROR_TYPE
set to 'b1, then multiple errors were found. This parameter is read-only.
Bit [2] = Reserved.
Bit [1] = Reserved.
Bit [0] = Reserved.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R OBSOLETE RSVD2 TDFI_CTRLUPD_MIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1
TDFI_CTRLUPD_MAX
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
OBSOLETE
RSVD2
19–16 Holds the DFI tCTRLUPD_MIN timing parameter. READ-ONLY
TDFI_CTRLUPD_
Holds the DFI tctrlupd_min timing parameter. This parameter is read-only.
MIN
RSVD1
13–0 Holds the DFI tCTRLUPD_MAX timing parameter.
TDFI_CTRLUPD_
Holds the DFI tctrlupd_max timing parameter. This parameter is read-only.
MAX



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD4 RSVD3 TDFI_ RSVD2 RSVD1

TDFI_DRAM_ DRAM_CLK_ TDFI_CTRL_
DRAM_CLK_
W CLK_ENABLE ENABLE DELAY
DISABLE
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD4
27–24 Delay from DFI clock enable to memory clock enable.
TDFI_DRAM_
Holds the DFI tdram_clk_enable timing parameter. This parameter is currently unused in the EMI.
CLK_ENABLE
RSVD3
18–16 Delay from DFI clock disable to memory clock disable.
TDFI_DRAM_
Holds the DFI tdram_clk_disable timing parameter. This parameter should be programmed with the number
CLK_DISABLE
of cycles that the PHY requires to disable the clock after the dfi_dram_clk_disable signal is asserted.

RSVD2
11–8 Set value for the dfi_dram_clk_disable signal.
DRAM_CLK_
Sets value for the DFI output signal dfi_dram_clk_disable. Bit [0] controls CS0, Bit [1] controls CS1. For
ENABLE
each bit:
'b0 = Memory clock/s should be disabled.
'b1 = Memory clock/s should be active.

RSVD1
3–0 Delay from DFI command to memory command.
TDFI_CTRL_
Holds the DFI tctrl_delay timing parameter.This parameter should be programmed with the number of cycles
DELAY
that the PHY requires to send a power-down or self-refresh command to the DRAM devices.



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 RSVD1
TDFI_PHYUPD_TYPE0 TDFI_PHYUPD_RESP
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
29–16 Holds the DFI tPHYUPD_TYPE0 timing parameter.
TDFI_PHYUPD_
Holds the DFI tphyupd_typeX timing parameter. This parameter is read-only.
TYPE0
RSVD1
13–0 Holds the DFI tPHYUPD_RESP timing parameter.
TDFI_PHYUPD_
Holds the DFI tphyupd_resp timing parameter. This parameter is read-only.
RESP

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R OBSOLETE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 RSVD1 TDFI_PHY_WRLAT

TDFI_PHY_WRLAT_BASE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
OBSOLETE
RSVD2


Field Description
11–8 Sets DFI base value for the tPHY_WRLAT timing parameter.
TDFI_PHY_
Used to adjust the tdfi_phy_wrlat parameter for the difference between the PHY's command path delay and
WRLAT_BASE
data path delay.
'b0000 = Command path delay is 2 cycles shorter than the data path delay.
'b0001 = Command path delay is 1 cycle shorter than the data path delay.
'b0010 = Command path delay and data path delay are equivalent.
'b0011 = Command path delay is 1 cycle longer than the data path delay.
'b0100 = Command path delay is 2 cycles longer than the data path delay.
'b0101 = Command path delay is 3 cycles longer than the data path delay.
'b0110, etc.

RSVD1
3–0 Holds the calculated DFI tPHY_WRLAT timing parameter. READ-ONLY
TDFI_PHY_
Holds the calculated value of the tphy_wrlat timing parameter and is used to adjust the dfi_wrdata_en signal
WRLAT
timing. This equation is dependent on the latency setting for the address / control path of the PHY as set in
the phy_ctrl_reg_2 [25] parameter bit.
If phy_ctrl_reg_2 [25] = 0:
If (tdfi_phy_wrlat_base + wrlat_adj) = 2:
tdfi_phy_wrlat = reg_dimm_enable
If (tdfi_phy_wrlat_base + wrlat_adj) > 2:
tdfi_phy_wrlat = tdfi_phy_wrlat_base + wrlat_adj + reg_dimm_enable - WRLAT_WIDTH'h3
Values of (tdfi_phy_wrlat_base + wrlat_adj) < 2 are not supported.
If (tdfi_phy_wrlat_base + wrlat_adj) < 4:
tdfi_phy_wrlat = reg_dimm_enable
If (tdfi_phy_wrlat_base + wrlat_adj) >= 4:
tdfi_phy_wrlat = tdfi_phy_wrlat_base + wrlat_adj + reg_dimm_enable - WRLAT_WIDTH'h4



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R OBSOLETE RSVD3
TDFI_RDDATA_EN_BASE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 TDFI_RDDATA_EN RSVD1

TDFI_PHY_RDLAT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
OBSOLETE
RSVD3
19–16 Sets DFI base value for the tRDDATA_EN timing parameter.
TDFI_RDDATA_
Used to adjust the tdfi_rddata_en parameter to account for the desired delay from the read command to the
EN_BASE
the read data enable signal. The CAS latency is defined in the caslat parameter.
The dfi_rddata_en signal can only be sent at a minimum of 1 cycle after the read command. If the programmed
value results in a delay less than 1 cycle, this value will be ignored and a delay value of 1 will be used.
'b0000 = Delay from read command to read data enable is equivalent to CAS latency-3.
'b0011 = Delay from read command to read data enable is equivalent to CAS latency.
'b0100 = Delay from read command to read data enable is equivalent to CAS latency+1.
'b0101 = Delay from read command to read data enable is equivalent to CAS latency+2.
'b0110, etc.

RSVD2
11–8 Holds the calculated DFI tRDDATA_EN timing parameter. READ-ONLY
TDFI_RDDATA_
Holds the calculated value of the trddata_en timing parameter. This equation is dependent on the latency
EN
setting for the address / control path of the PHY as set in the phy_ctrl_reg_2 [25] parameter bit.
If (tdfi_rddata_en_base + rdlat_adj) = 2:
tdfi_rddata_en = reg_dimm_enable
If (tdfi_rddata_en_base + rdlat_adj) > 2:
tdfi_rddata_en = tdfi_rddata_en_base + rdlat_adj + reg_dimm_enable - RDLAT_WIDTH'h3
Values of (tdfi_rddata_en_base + rdlat_adj) < 2 are not supported.


Field Description
If (tdfi_rddata_en_base + rdlat_adj) < 4:
tdfi_rddata_en = reg_dimm_enable
If (tdfi_rddata_en_base + rdlat_adj) >= 4:
tdfi_rddata_en = tdfi_rddata_en_base + rdlat_adj + reg_dimm_enable - RDLAT_WIDTH'h4

RSVD1
3–0 Holds the tPHY_RDLAT timing parameter.
TDFI_PHY_
Holds the tphy_rdlat timing parameter.
RDLAT

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PHY_CTRL_REG_0_0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Controls pad output enable times and other PHY parameters for data slice 0.
PHY_CTRL_
There is a separate phy_ctrl_reg_0_X parameter for each of the slices of data sent on the DFI data bus.
REG_0_0
Bit [31] = Enables dynamic termination select in the PHY for the DM pads.
'b0 = Disabled
'b1 = Enabled
Bit [29] = Controls termination enable for the DM pads. Set to 'b1 to disable termination.
'b0 = Enabled
'b1 = Disabled
Bits [28] = Echo gate control for data slice X. Default 0x0.
'b0 = Uses the dfi_rddata_en signal to create a gate.
'b1 = Creates an echo_gate signal.
Bit [27] = Gather FIFO Enable
'b0 = Disabled


Field Description
'b1 = Enabled
Bits [26:24] = Defines the read data delay. Holds the number of cycles to delay the dfi_rddata_en signal
prior to enabling the read FIFO. After this delay, the read pointers begin incrementing the read FIFO. Default
0x3.
Bit [20] = Sets the pad output enable polarity. Default 0x0.
'b0 = OEN pad
'b1 = OE pad
Bit [16] = Subtracts 1/2 cycle from the DQS gate value programmed into phy_ctrl_reg_1_X [2:0] by 1/2 cycle.
Default 0x0. This is used when the gate is being aligned to the first DQS, and then is removed to move the
gate back into the center of the preamble. This parameter is controlled by the hardware logic when hardware
gate training is enabled but should be controlled by software when software leveling is used.
'b0 = Do not adjust
'b1 = Adjust the DQS gate by 1/2 clock forward.
Bits [15:12] = Adjusts the starting point of the DQS pad output enable window. Lower numbers pull the rising
edge earlier in time, and larger numbers cause the rising edge to be delayed. Each bit changes the output
enable time by a 1/4 cycle resolution. Default 0x2.
Bits [11:8] = Adjusts the ending point of the DQS pad output enable window. Lower numbers pull the falling
edge earlier in time, and larger numbers cause the falling edge to be delayed. Each bit changes the output
Bits [6:4] = Adjusts the starting point of the DQ pad output enable window. Lower numbers pull the rising
edge earlier in time, and larger numbers cause the rising edge to be delayed. Each bit changes the output
Bits [2:0] = Adjusts the ending point of the DQ pad output enable window. Lower numbers pull the falling
edge earlier in time, and larger numbers cause the falling edge to be delayed. Each bit changes the output
All other bits undefined.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PHY_CTRL_REG_0_1
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
PHY_CTRL_
REG_0_1
The definition of phy_ctrl_reg_0_X parameter is same for data slice 0~3.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PHY_CTRL_REG_0_2
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
PHY_CTRL_
Data slice 2 is disabled.
REG_0_2

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PHY_CTRL_REG_0_3
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
PHY_CTRL_
REG_0_3


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PHY_CTRL_REG_1_0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Controls pad termination and loopback for data slice 0.
PHY_CTRL_
REG_1_0
Bits [31:28] = Defines the pad dynamic termination select enable time. Larger values add greater delay to
when tsel turns on. Each bit changes the output enable time by a 1/2 cycle resolution.
Bits [27:24] = Defines the pad dynamic termination select disable time. Larger values reduce the delay to
when tsel turns off. Each bit changes the output enable time by a 1/2 cycle resolution.
Bit [23] = Enables dynamic termination select in the PHY for the DQS pads.
'b0 = Disabled
'b1 = Enabled
Bit [22] = Controls the polarity of the tsel signal for the DQS and DM pads.
'b0 = Positive Polarity
'b1 = Negative Polarity
Bit [21] = Triggers a data return to the EMI.
'b0 = No action
'b1 = Sends loopback data on the dfi_rddata signal.
Bit [20] = Selects data output type for phy_obs_reg_0_X [23:8].
'b0 = Return the expected data.
'b1 = Return the actual data.
Bits [19:18] = Loopback control.
'b00 = Normal operational mode.
'b01 = Enables loopback write mode.
'b10 = Stop loopback to check the error register.
'b11 = Clear loopback registers.
Bits [17] = Controls the loopback read multiplexer.
Bits [16] = Controls the internal write multiplexer.
Bits [14:12] = Sets the cycle delay between the LFSR and loopback error check logic. Note that 'h7 is not a
valid selection and will result in a false passing result.


Field Description
Bits [10:8] = Gate Error Delay. Allows the user to adjust the length of time from the dfi_rddata_en assertion
to the maximum time in which all of the data should have been returned. If the data is not returned in the
time expected by the MC, an error condition may occur. This field default value is based on the delay
information provided at configuration.
Bits [5:4] = Adjusts the closing of the gate. This field default value is based on the delay information provided
at configuration.
Bits [2:0] = Coarse adjust of gate open time. This value is the number of cycles to delay the dfi_rddata_en
signal prior to opening the gate in full cycle increments. Decreasing this value pulls the gate earlier in time.
This field, along with the phy_ctrl_reg_0_X [16] bit should be programmed such that the gate signal lands
in the valid DQS gate window.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PHY_CTRL_REG_1_1
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
PHY_CTRL_
REG_1_1
The definition of phy_ctrl_reg_1_X parameter is same for data slice 0~3.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PHY_CTRL_REG_1_2
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
PHY_CTRL_
REG_1_2

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PHY_CTRL_REG_1_3
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
PHY_CTRL_
REG_1_3

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PHY_CTRL_REG_2
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Selects the dfi_rddata_valid delay.
PHY_CTRL_
Controls PHY functionality.
REG_2
Bit [25] = Selects the address / command path.
'b0 = DFI control signals are captured 1 cycle after being sent from the MC.
'b1 = DFI control signals are captured 1/4 cycle after being sent from the MC.


Field Description
The Low Latency option is not functional at this time.
Bit [24] = Selects the write latency path.
'b0 = Write Data is captured 1 cycle after being sent from the MC
'b1 = Write data is captured 1/4 cycle after being sent from the MC.
The Low Latency option is not functional at this time.
Bit [23] = DFI control for Mobile MCs.
Bit [5] = Enables the pad inputs specifically for external loopback. This bit is tied to the internal signal
lpbk_rddata_en.
'b0 = Normal Operation
'b1 = Loopback Mode
Bit [4] = Enables the pad outputs specifically for external loopback. This bit is tied to the internal signal
lpbk_wrdata_en.
'b0 = Normal Operation
'b1 = Loopback Mode
Bits [3:0] = Sets the dfi_rddata_valid delay relative to dfi_rddata_en.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DFT_CTRL_REG
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Enables the PHY testing mode.
DFT_CTRL_REG
Enables the PHY testing mode. Bits [2:1] are used.
Bits [2:1] ='b10 = Normal Mode
Bits [2:1] ='b01 = Scan Mode
Currently Not Functional


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R OBSOLETE RSVD2 OCD_ADJUST_ RSVD1 OCD_ADJUST_

W PUP_CS_0 PDN_CS_0
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
OBSOLETE
RSVD2
12–8 OCD pull-up adjust setting for DRAMs for chip select 0.
OCD_ADJUST_
This parameter is reserved for future use and should be programmed to 0x0.
PUP_CS_0
RSVD1
4–0 OCD pull-down adjust setting for DRAMs for chip select 0.
OCD_ADJUST_
This parameter is reserved for future use and should be programmed to 0x0.
PDN_CS_0

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ODT_ALT_
R RSVD1 OBSOLETE[23:16]
EN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R OBSOLETE[15:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSVD1
24 Enable use of non-DFI odt_alt signal.
ODT_ALT_EN
Enables the use of the non-DFI compliant alternative ODT internal signal odt_alt, which is externally viewed
as the signal reserved0. This signal is only required if the user intends to use a CAS latency of 3 with ODT
support. The user will need to modify the dram_asic.v file for this support.
'b0 = ODT support with CAS latency 3 is not supported.
'b1 = ODT support with CAS latency 3 is supported but is not DFI compliant. This disables the interrupt bit
for ODT-with-CAS3 and disables the OVL error.

OBSOLETE

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD4 ODT_RD_ RSVD3 ODT_RD_ RSVD2 ODT_RD_ RSVD1 ODT_RD_

W MAP_CS3 MAP_CS2 MAP_CS1 MAP_CS0
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD4
27–24 Determines which chip(s) will have termination when a read occurs on chip 3.
ODT_RD_MAP_
Sets up which (if any) chip(s) will have their ODT termination active while a read occurs on chip select X.
CS3
EMI will define this parameter at default for internal testing. The user is required is to change this setting to
meet system specifications.
Example: If the system consists of 4 chip selects and odt_rd_map_cs0 is set to 'b0010, then when CS0 is
performing a read, CS1 will have active ODT termination. And if odt_rd_map_cs0 was set to 'b1000, then
instead CS3 would be active.


Field Description
Bit [3] = CS3 will have active ODT termination when chip select X is performing a read.
Etc.

RSVD3
ODT_RD_MAP_
CS2
Etc.

RSVD2
ODT_RD_MAP_
CS1
Etc.

RSVD1
ODT_RD_MAP_
CS0


Field Description
Etc.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD4 ODT_WR_ RSVD3 ODT_WR_ RSVD2 ODT_WR_ RSVD1 ODT_WR_

W MAP_CS3 MAP_CS2 MAP_CS1 MAP_CS0
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD4
27–24 Determines which chip(s) will have termination when a write occurs on chip 3.
ODT_WR_MAP_
Sets up which (if any) chip(s) will have their ODT termination active while a write occurs on chip select X.
CS3
Example: If the system consists of 4 chip selects and odt_wr_map_cs0 is set to 'b0010, then when CS0 is
performing a write, CS1 will have active ODT termination. And if odt_wr_map_cs0 was set to 'b1000, then
Bit [3] = CS3 will have active ODT termination when chip select X is performing a write.
Etc.

RSVD3


Field Description
ODT_WR_MAP_
CS2
Etc.

RSVD2
ODT_WR_MAP_
CS1
Etc.

RSVD1
ODT_WR_MAP_
CS0
Etc.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PAD_CTRL_REG_0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Controls pad termination, type and IDDQ settings.
PAD_CTRL_
These bit settings are specific to the pad models included with this PHY. The user should alter the
REG_0
programming relative to the particular pads being used in their design.
EMI provides a dynamic termination signal tsel that provides one bit per byte of memory data. The user
must attach this signal to the pads dependent on pad requirements.
Bit [12] = Defines the pad impedance if the parallel termination option is enabled. Default 'b1.
'b0 = 75 Ohm
'b1 = 150 Ohm
Bit [8] = Defines the pad type. Default 'b1.
'b0 = DDR1
'b1 = DDR2
Bit [5] = Defines the IDDQ_RX select for the signal pads. Default 'b1.
'b0 = Do not feed input into IDDQ
'b1 = Feed input into IDDQ
Bit [4] = Defines the IDDQ_TX select for the signal pads. Default 'b1.
'b0 = Do not feed output into IDDQ
'b1 = Feed output into IDDQ
Bit [1] = Defines the IDDQ_RX select for the clock pads. Default 'b1.
'b0 = Do not feed input into IDDQ
'b1 = Feed input into IDDQ
Bit [0] = Defines the IDDQ_TX select for the clock pads. Default 'b1.
'b0 = Do not feed output into IDDQ
'b1 = Feed output into IDDQ
All other bits Reserved.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R OBSOLETE VERSION
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0
set

Field Description
OBSOLETE
15–0 Controller version number. READ-ONLY
VERSION
Holds the EMI version number for this controller. This parameter is read-only.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DLL_CTRL_REG_0_0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Controls the DLL bypass logic and holds the DLL start point and read DQS delay settings for data slice 0.
DLL_CTRL_
There is a separate dll_ctrl_reg_0_X parameters for each of the slices of data sent on the DFI data bus.
REG_0_0
Bit [28] = DLL Bypass Control.
'b0 = Normal operational mode. In this mode, the DLL uses dll_ctrl_reg_0_X [14:8] for the read DQS and
dll_ctrl_reg_1_X [14:8] for clk_wr.
'b1 = Bypass Mode is on. In this mode, the DLL uses dll_ctrl_reg_0_X [23:15] for the read DQS and
Bits [23:15] = Holds the read DQS delay setting when the DLL is operating in bypass mode. (dll_ctrl_reg_0_X
[28] = 'b1)


Field Description
Bits [14:8] = Holds the read DQS delay setting when the DLL is operating in normal mode. (dll_ctrl_reg_0_X
[28] = 'b0) Typically, this value is 1/4 of a clock cycle. Each increment of this field represents 1/128th of a
clock cycle.
Bits [7:0] = DLL Start Point Control. This value is loaded into the DLL at initialization and is the value at
which the DLL will begin searching for a lock. Each increment of this field represents 1/128th of a clock
cycle. This value MUST be >= 3.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DLL_CTRL_REG_0_1
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_CTRL_
REG_0_1
[28] = 'b1)
clock cycle.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DLL_CTRL_REG_0_2
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_CTRL_
REG_0_2
[28] = 'b1)
clock cycle.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DLL_CTRL_REG_0_3
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
DLL_CTRL_
REG_0_3
[28] = 'b1)
clock cycle.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DLL_CTRL_REG_1_0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Holds the clk_wr settings and the Dll increment value for data slice 0.
DLL_CTRL_
There is a separate dll_ctrl_reg_1_X parameter for each of the slices of data sent on the DFI data bus.
REG_1_0
Bits [23:15] = Holds the clk_wr delay setting when the DLL is operating in bypass mode. (dll_ctrl_reg_0_X
[28] = 'b1) Each increment of this field represents 1/128th of a clock cycle.
Bits [14:8] = Holds the clk_wr delay setting in normal mode. (dll_ctrl_reg_0_X [28] = 'b0) Typically, this value
is 3/4 of a clock cycle. Each increment of this field represents 1/128th of a clock cycle.
Bits [7:0] = DLL Increment Value. This sets the increment used by the DLL when searching for a lock. It is
recommended to keep this field small (around 0x4) to keep the steps gradual.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DLL_CTRL_REG_1_1
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_CTRL_
REG_1_1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DLL_CTRL_REG_1_2
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_CTRL_
REG_1_2


Field Description

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DLL_CTRL_REG_1_3
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_CTRL_
REG_1_3

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_0_0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
31–0 Reports the lock status and the encoder value for data slice 0. READ-ONLY
DLL_OBS_REG_
There is a separate dll_obs_reg_0_X parameter for each of the slices of data sent on the DFI data bus.
0_0
Bits [31:1] = Reports the DLL encoder value from the master DLL to the slave DLL's. The slaves use this
value to set up their delays for the clk_wr and read DQS signals.
Bit [0] = DLL Lock Indicator.
'b0 = DLL has not locked.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_0_1
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
0_1



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_0_2
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
0_2

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_0_3
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
0_3


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PHY_OBS_REG_0_0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Controls loopback status, data and masking info for slice 0. READ-ONLY
PHY_OBS_REG_
Reports status for the PHY.
0_0
Bit [24] = Status signal to indicate that the logic gate had to be forced closed.
'b1 = Gate close was forced
Bits [23:8] = Loopback data. Reports the actual data or expected data, depending on the setting of the
phy_ctrl_reg_1_X [20] parameter bit.
Bits [5:4] = Loopback mask data. Reports the actual data mask or the expected data mask, depending on
the setting of the phy_ctrl_reg_1_X [20] parameter bit.
Bit [1] = Reports status of loopback errors.
'b0 = Last Loopback test had no errors.
'b1 = Last Loopback test contained data errors.
Bit [0] = Defines the status of the loopback mode.
'b0 = Not in loopback mode.
'b1 = In Loopback mode.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PHY_OBS_REG_0_1
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
PHY_OBS_REG_
0_1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PHY_OBS_REG_0_2
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
PHY_OBS_REG_
0_2


Field Description

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PHY_OBS_REG_0_3
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
PHY_OBS_REG_
0_3


Field Description

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_1_0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Reports master DLL info for delay line 0. READ-ONLY.
DLL_OBS_REG_
1_0

Address: HW_DRAM_CTL104 – 800E_0000h base + 1A0h offset = 800E_01A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_1_0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
1_0


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_1_0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
1_0

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_1_0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
1_0


Address: HW_DRAM_CTL107 – 800E_0000h base + 1ACh offset = 800E_01ACh

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R OBSOLETE RSVD1 DLL_OBS_REG_1_0

W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
OBSOLETE
RSVD1
DLL_OBS_REG_
1_0

Address: HW_DRAM_CTL108 – 800E_0000h base + 1B0h offset = 800E_01B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_1_1
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
1_1



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_1_1
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
1_1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_1_1
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
1_1

Address: HW_DRAM_CTL111 – 800E_0000h base + 1BCh offset = 800E_01BCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_1_1
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
DLL_OBS_REG_
1_1

Address: HW_DRAM_CTL112 – 800E_0000h base + 1C0h offset = 800E_01C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
OBSOLETE
RSVD1
DLL_OBS_REG_
1_1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_1_2
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
DLL_OBS_REG_
1_2

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_1_2
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
1_2

Address: HW_DRAM_CTL115 – 800E_0000h base + 1CCh offset = 800E_01CCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_1_2
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
1_2


Address: HW_DRAM_CTL116 – 800E_0000h base + 1D0h offset = 800E_01D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_1_2
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
1_2

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
OBSOLETE
RSVD1
DLL_OBS_REG_
1_2



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_1_3
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
1_3

Address: HW_DRAM_CTL119 – 800E_0000h base + 1DCh offset = 800E_01DCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_1_3
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
1_3

Address: HW_DRAM_CTL120 – 800E_0000h base + 1E0h offset = 800E_01E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_1_3
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
DLL_OBS_REG_
1_3

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_1_3
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
1_3

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
OBSOLETE
RSVD1


Field Description
DLL_OBS_REG_
1_3

Address: HW_DRAM_CTL123 – 800E_0000h base + 1ECh offset = 800E_01ECh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_2_0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Reports the read DQS delay value for data slice 0. READ-ONLY.
DLL_OBS_REG_
2_0

Address: HW_DRAM_CTL124 – 800E_0000h base + 1F0h offset = 800E_01F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_2_0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
2_0


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_2_0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
2_0

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_2_0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
2_0


Address: HW_DRAM_CTL127 – 800E_0000h base + 1FCh offset = 800E_01FCh

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
OBSOLETE
RSVD1
DLL_OBS_REG_
2_0

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_2_1
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
2_1



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_2_1
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
2_1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_2_1
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
2_1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_2_1
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
DLL_OBS_REG_
2_1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
OBSOLETE
RSVD1
DLL_OBS_REG_
2_1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_2_2
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
DLL_OBS_REG_
2_2

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_2_2
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
2_2

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_2_2
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
2_2


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_2_2
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
2_2

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
OBSOLETE
RSVD1
DLL_OBS_REG_
2_2



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_2_3
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
2_3

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_2_3
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
2_3

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_2_3
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
DLL_OBS_REG_
2_3

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_2_3
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
2_3

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
OBSOLETE
RSVD1


Field Description
DLL_OBS_REG_
2_3

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_3_0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Reports the clk_wr delay value for data slice 0. READ-ONLY.
DLL_OBS_REG_
3_0

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_3_0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
3_0


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_3_0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
3_0

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_3_0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
3_0



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
OBSOLETE
RSVD1
DLL_OBS_REG_
3_0

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_3_1
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
3_1



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_3_1
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
3_1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_3_1
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
3_1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_3_1
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
DLL_OBS_REG_
3_1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
OBSOLETE
RSVD1
DLL_OBS_REG_
3_1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_3_2
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
DLL_OBS_REG_
3_2

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_3_2
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
3_2

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_3_2
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
3_2


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_3_2
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
3_2

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
OBSOLETE
RSVD1
DLL_OBS_REG_
3_2



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_3_3
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
3_3

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_3_3
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
3_3

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_3_3
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
DLL_OBS_REG_
3_3

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DLL_OBS_REG_3_3
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
DLL_OBS_REG_
3_3

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD3 W2R_ RSVD2 W2R_ RSVD1 DLL_OBS_REG_3_3

SAMECS_ DIFFCS_
W DLY DLY
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD3
26–24 Additional delay to insert between writes and reads to the same chip select.
W2R_SAMECS_
Defines the number of additional clocks of delay to insert from a write command to a read command to the
DLY
same chip select.


Field Description
RSVD2
18–16 Additional delay to insert between writes and reads to different chip selects.
W2R_DIFFCS_
Defines the number of additional clocks of delay to insert from a write command to one chip select to a read
DLY
command to a different chip select.

RSVD1
DLL_OBS_REG_
3_3

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD3 RSVD2 RSVD1 DRAM_

DLL_RST_ADJ_DLY WRLAT_ADJ RDLAT_ADJ
W CLASS
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–24 Minimum number of cycles after setting master delay in DLL until reset is released.
DLL_RST_ADJ_
Specifies the minimum number of cycles after the master delay value is programmed before the DLL reset
DLY
may be asserted.

RSVD3
19–16 Adjustment value for PHY write timing.
WRLAT_ADJ
Adjusts the relative timing between DFI write commands and the dfi_wrdata_en signal to conform to PHY
timing requirements. When this parameter is programmed to 0x0, dfi_wrdata_en will assert on the same
cycle as the dfi_address. This parameter only affects the DFI.

RSVD2
11–8 Adjustment value for PHY read timing.
RDLAT_ADJ
Adjusts the relative timing between DFI read commands and the dfi_rddata_en signal to conform to PHY
timing requirements. When this parameter is programmed to 0x0, dfi_rddata_en will assert one cycle after
the dfi_address. This parameter only affects the DFI.


Field Description
RSVD1
3–0 Defines the mode of operation of the controller.
DRAM_CLASS
Selects the mode of operation for the EMI.
'b0000 = DDR1
'b0001 = DDR1 with Mobile (LPDDR1)
'b0100 = DDR2
All other settings reserved.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R OBSOLETE RSVD1
TMOD
W INT_ACK
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
OBSOLETE
RSVD1
17–8 Clear mask of the INT_STATUS parameter. WRITE-ONLY
INT_ACK
Controls the clearing of the int_status parameter. If any of the int_ack bits are set to 'b1, the corresponding
bit in the int_status parameter will be cleared to 'b0. Any int_ack bits cleared to 'b0 will not alter the
corresponding bit in the int_status parameter. This parameter will always read back as 0x0.
7–0 Number of clock cycles after MRS command and before any other command.
TMOD
Defines the number of cycles of wait time after a mode register write to any non-mode register write command.


Address: HW_DRAM_CTL171 – 800E_0000h base + 2ACh offset = 800E_02ACh

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AXI5_BDW_
AXI4_BDW_
RSVD2 RSVD1
OVFLOW
OVFLOW
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLL_RST_DELAY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSVD2
AXI5_BDW_
OVFLOW
RSVD1
AXI4_BDW_
OVFLOW
15–0 Minimum number of cycles required for DLL reset.
DLL_RST_
Sets the number of cycles that the reset must be held asserted for the DLL.
DELAY

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESYNC_DLL_PER_
R RSVD4 RSVD3
AREF_EN
RESYNC_
W
DLL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CONCURRENTAP_WR_
STATUS
CKE_
R RSVD2 RSVD1
ONLY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSVD4
24 Enables automatic DLL resyncs after every refresh.
RESYNC_DLL_
Enables an automatic re-synchronization of the DLL after every refresh.
PER_AREF_EN
RSVD3
16 Initiate a DLL resync. WRITE-ONLY
RESYNC_DLL
Initiates a re-synchronization of the DLL. This parameter is write-only.

RSVD2
8 Limit concurrent auto-precharge by waiting for the write recovery time, tWR, before issuing a read.
CONCURRENTAP_
Limit concurrent auto-precharge by waiting for the write recovery time, tWR, to complete after a write
WR_ONLY
before issuing a read.
'b0 = Do not restrict concurrent auto-precharge.
'b1 = Wait tWR after a write before issuing a read.

RSVD1
0 Register access to cke_status signal. This value also indicates the inverted state of the CKE pin on the
CKE_STATUS external memory bus. READ-ONLY
Provides the value of the cke_status signal in a parameter. This parameter is read-only.



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD4 RSVD3 RSVD2 AXI5_ RSVD1 AXI4_

AXI4_W_ AXI4_R_ FIFO_ FIFO_
W PRIORITY PRIORITY TYPE_ TYPE_

REG REG
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD4
AXI4_W_
PRIORITY
RSVD3
AXI4_R_
PRIORITY
RSVD2
AXI5_FIFO_
TYPE_REG
RSVD1
AXI4_FIFO_
TYPE_REG

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD4 R2R_ RSVD3 R2R_ RSVD2 RSVD1

AXI5_W_ AXI5_R_
SAMECS_ DIFFCS_
W PRIORITY PRIORITY
DLY DLY
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
RSVD4
26–24 Additional delay to insert between reads and reads to the same chip select.
R2R_SAMECS_
Defines the number of additional clocks of delay to insert between two read commands to the same chip
DLY
select.

RSVD3
18–16 Additional delay to insert between reads and reads to different chip selects.
R2R_DIFFCS_
Defines the number of additional clocks of delay to insert from a read command to one chip select to a read
DLY

RSVD2
AXI5_W_
PRIORITY
RSVD1
AXI5_R_
PRIORITY

Address: HW_DRAM_CTL175 – 800E_0000h base + 2BCh offset = 800E_02BCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD4 W2W_ RSVD3 RSVD2 R2W_ RSVD1 R2W_

TBST_INT_
DIFFCS_ SAMECS_ DIFFCS_
INTERVAL
W DLY DLY DLY
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD4
26–24 Additional delay to insert between writes and writes to different chip selects.
W2W_DIFFCS_
Defines the number of additional clocks of delay to insert from a write command to one chip select to a write
DLY


Field Description
RSVD3
18–16 DRAM burst interrupt interval in cycles.
TBST_INT_
Defines the burst interrupt interval. This parameter is only relevant if the burst has not completed.
INTERVAL
This value is loaded into a parameter when a burst is issued and another command may only interrupt the
current burst when this counter value hits 0. If the counter value hits 0 and the burst has not completed, the
counter will be reset with the tbst_int_interval value.
If a command is in progress and the burst has not completed, another command may only be issued on
cycles after the parameter tccd value cycles have elapsed since the last CAS command and this counter
value hits 0.
For example, if the burst length is 8, tccd is 2, tbst_int_interval is 2 and a CAS command was issued on
cycle 0, another CAS command could interrupt the current burst on cycle 2. After cycle 3, the current burst
will complete and this parameter would not be relevant.
If instead the tbst_int_interval was 1 for the same system, then the command could interrupt on cycles 2 or
3.

RSVD2
10–8 Additional delay to insert between reads and writes to the same chip select.
R2W_SAMECS_
Defines the number of additional clocks of delay to insert from a read command to a write command to the
DLY
same chip select.

RSVD1
2–0 Additional delay to insert between reads and writes to different chip selects.
R2W_DIFFCS_
Defines the number of additional clocks of delay to insert from a read command to one chip select to a write
DLY

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD4 RSVD3
ADD_ODT_CLK_ ADD_ODT_CLK_DIFFTYPE_
SAMETYPE_DIFFCS SAMECS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 RSVD1
ADD_ODT_CLK_DIFFTYPE_
W2W_SAMECS_DLY
DIFFCS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSVD4
27–24 Additional delay to insert between same transaction types to different chip selects to meet ODT timing
ADD_ODT_CLK_ requirements.
SAMETYPE_
Defines the number of additional clocks of delay to insert between commands of the same type (read to
DIFFCS
read, write to write) to different chip selects to meet ODT timing requirements.

RSVD3
19–16 Additional delay to insert between different transaction types to the same chip select to meet ODT timing
DIFFTYPE_
Defines the number of additional clocks of delay to insert between commands of different types (read to
SAMECS
write, write to read) to the same chip select to meet ODT timing requirements.

RSVD2
11–8 Additional delay to insert between different transaction types to different chip selects to meet ODT timing
DIFFTYPE_
Defines the number of additional clocks of delay to insert between commands of different types (read to
DIFFCS
write, write to read) to different chip selects to meet ODT timing requirements.

RSVD1
2–0 Additional delay to insert between writes and writes to the same chip select.
W2W_SAMECS_
Defines the number of additional clocks of delay to insert between two write commands to the same chip
DLY
select.



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TCCD TRP_AB CKSRX CKSRE
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD4
28–24 DRAM CAS-to-CAS parameter in cycles.
TCCD
Defines the minimum delay between CAS commands, in cycles. This value is loaded into a counter when
a burst is issued and a new command may be issued when the counter reaches 0.

RSVD3
19–16 DRAM TRP All Bank parameter in cycles.
TRP_AB
Defines the DRAM TRP time for all banks, in cycles.

RSVD2
11–8 Clock stable delay on self-refresh exit.
CKSRX
Sets the number of cycles to hold the clock stable before exiting self-refresh mode. The clock will run for a
minimum of cksrx cycles before CKE rises.

RSVD1
3–0 Clock hold delay on self-refresh entry.
CKSRE
Sets the number of cycles to hold the clock stable after entering self-refresh mode. The clock will run for a
minimum of cksre cycles after CKE falls.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD4 RSVD3 AXI4_CURRENT_BDW

AXI5_BDW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 RSVD1
AXI4_BDW TCKESR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSVD4
AXI5_BDW
RSVD3
AXI4_
CURRENT_BDW
RSVD2
AXI4_BDW
RSVD1
4–0 Minimum CKE low pulse width during a self-refresh.
TCKESR
Defines the minimum number of cycles that CKE must be held low during self-refresh. pulse width, in cycles.
If the memory specification does not define a tckesr, then the tckesr parameter should be programmed with
the tcke value.

Address: HW_DRAM_CTL179 – 800E_0000h base + 2CCh offset = 800E_02CCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD3 RSVD2
TDFI_PHYUPD_TYPE1[21:16]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1 AXI5_CURRENT_BDW
TDFI_PHYUPD_TYPE1[15:8]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSVD3
RSVD2
TDFI_PHYUPD_
TYPE1
RSVD1
AXI5_
CURRENT_BDW

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD2 RSVD1
TDFI_PHYUPD_TYPE3 TDFI_PHYUPD_TYPE2
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RSVD2
TDFI_PHYUPD_
TYPE3
RSVD1
TDFI_PHYUPD_
TYPE2


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD2
MR0_DATA_1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1
MR0_DATA_0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSVD2
30–16 MRS data to program to memory mode register 0 for chip select 1.
MR0_DATA_1
Holds the memory mode register 0 data for chip select X written during memory initialization. Consult the
memory specification for the fields of this mode register.
This parameter correlates to the memory mode register (MR). The use of this parameter varies based on
the memory type connected to this EMI:
For DDR1 memories: The EMI does not support interleaving and therefore the A3 bit should be cleared to
'b0. In addition, the DLL Reset bit (A8) will be ignored in favor of an internal state machine that sets the DLL
Reset bit during initialization. Also, the EMI only supports a burst length of 4 and therefore the bits A2:A0
should be set to 'b010.For DDR2 memories: The EMI does not support interleaving and therefore the A3 bit
should be cleared to 'b0. In addition, the DLL Reset bit (A8) will be ignored in favor of an internal state
machine that sets the DLL Reset bit during initialization. Also, the EMI only supports a burst length of 4 and
therefore the bits A2:A0 should be set to 'b010.
For LPDDR1 memories: The EMI does not support interleaving and therefore the A3 bit should be cleared
to 'b0. Also, the EMI only supports a burst length of 4 and therefore the bits A2:A0 should be set to 'b010.
This data will be programmed into the memory register of the DRAM at initialization or when the write_modereg
parameter is set to 'b1.

RSVD1
MR0_DATA_0


Field Description

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD2
MR0_DATA_3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1
MR0_DATA_2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSVD2
MR0_DATA_3


Field Description

RSVD1
MR0_DATA_2

Address: HW_DRAM_CTL183 – 800E_0000h base + 2DCh offset = 800E_02DCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD2
MR1_DATA_1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1
MR1_DATA_0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSVD2
30–16 Data to program into memory mode register 1 for chip select 1.
MR1_DATA_1
The use of this parameter varies based on the memory type connected to this EMI:
For DDR1 memories: This parameter correlates to the extended memory mode register (EMR).
For DDR2 memories: This parameter correlates to the extended memory mode register 1 (EMR1). The EMI
does not support additive latency and therefore the A5:A3 bits should be cleared to 'b000.
For LPDDR1 memories: This parameter has no meaning for this memory type.
This data will be programmed into the appropriate memory register of the DRAM at initialization or when
the write_modereg parameter is set to 'b1.

RSVD1
MR1_DATA_0



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD2
MR1_DATA_3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1
MR1_DATA_2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSVD2
MR1_DATA_3

RSVD1
MR1_DATA_2


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD2
MR2_DATA_1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1
MR2_DATA_0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSVD2
MR2_DATA_1
For DDR1 memories: This parameter has no meaning for this memory type.
For DDR2 memories: This parameter correlates to the extended memory mode register 2 (EMR2).
For LPDDR1 memories: This parameter correlates to the extended mode register (EMR).

RSVD1
MR2_DATA_0


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD2
MR2_DATA_3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1
MR2_DATA_2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSVD2
MR2_DATA_3

RSVD1
MR2_DATA_2


Address: HW_DRAM_CTL187 – 800E_0000h base + 2ECh offset = 800E_02ECh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD2
MR3_DATA_1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1
MR3_DATA_0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSVD2
MR3_DATA_1

RSVD1
MR3_DATA_0


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD2
MR3_DATA_3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1
MR3_DATA_2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSVD2
MR3_DATA_3

RSVD1
MR3_DATA_2


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
AXI5_EN_SIZE_LT_WIDTH_INSTR AXI4_EN_SIZE_LT_WIDTH_INSTR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
AXI5_EN_SIZE_
LT_WIDTH_
INSTR
AXI4_EN_SIZE_
LT_WIDTH_
INSTR

Chapter 15
General-Purpose Media Interface(GPMI)
15.1 General-Purpose Media Interface Overview

This chapter describes the general-purpose media interface.
The GPMI controller is a flexible interface to up to eight NAND Flash with configurable
address and command behavior, providing support for future devices not yet specified. The
GPMI resides on the APBH and provides an interface to the 20-bit BCH module to allow
direct parity processing.
Registers are clocked on the HCLK domain. The I/O and pin timing are clocked on a
dedicated GPMICLK domain. GPMICLK can be set to maximize I/O performance.
The following figure shows a block diagram of the GPMI controller.

GPMI NAND Mode
ARM Core SRAM System Clock

Generator
AHB
AHB-to-APBH
AHB SLAVE AHB MASTER Bridge
SHARED DMA
HCLK
DMA Request 0
DMA Request 1
DMA Request 2
DMA Request 3
DMA Request 4
DMA Request 5
DMA Request 6
DMA Request 7
APBH MASTER
APBH
GPMI DMA Interface State Machine HCLK
GPMI FIFO
BCH
GPMI
GPMICLK
GPMI Pin State Machine
Memory Controller
GPIO
GPMI / Memory /
GPIO Pin Mux
Pins
Figure 15-1. General-Purpose Media Interface Controller Block Diagram
15.2 GPMI NAND Mode

The general-purpose media interface has several features to efficiently support NAND:
• Individual chip select and ready/busy pins for up to eight NANDs.
• Individual state machine and DMA channel for each chip select.
• Special command modes work with DMA controller to perform all normal NAND
functions without CPU intervention.
• Configurable timing based on a dedicated clock allows optimal balance of high NAND
performance and low system power.

Chapter 15 General-Purpose Media Interface(GPMI)
Since current NAND Flash does not support multiple page read/write commands, the GPMI
and DMA have been designed to handle complex multi-page operations without CPU
intervention. The DMA uses a linked descriptor function with branching capability to
automatically handle all of the operations needed to read/write multiple pages:
• Data/Register Read/Write—The GPMI can be programmed to read or write multiple
cycles to the NAND address, command or data registers.
• Wait for NAND Ready—The GPMI's Wait-for-Ready mode can monitor the ready/busy
signal of a single NAND Flash and signal the DMA when the device has become ready.
It also has a time-out counter and can indicate to the DMA that a time-out error has
occurred. The DMAs can conditionally branch to a different descriptor in the case of
an error.
• Check Status—The Read-and-Compare mode allows the GPMI to check NAND status
against a reference. If an error is found, the GPMI can instruct the DMA to branch to
an alternate descriptor, which attempts to fix the problem or asserts a CPU IRQ.
15.2.1 Multiple NAND Support

The GPMI supports up to eight NAND chip selects, each with independent ready/busy
signals. Since they share a data bus and control lines, the GPMI can only actively
communicate with a single NAND at a time. However, all NANDs can concurrently perform
internal read, write, or erase operations. With fast NAND Flash and software support for
concurrent NAND operations, this architecture allows the total throughput to approach the
data bus speed, which can be as high as 50 MB/s (8-bit bus running at 50 MHz).
There are two options for controlling the eight NAND chip selects through the DMA
interface. The first option is one to one mapping, where each DMA channel is attached to
its own NAND. For example DMA channel 'n' accesses only NAND attached to chip select
'n'. The second option is the decoupled mode where a DMA channel can access any or all
NANDs connected to the GPMI. A DMA channel will signify the NAND it wants to access
by writing its chip select value in the HW_GPMI_CTRL0_CS field and setting the
HW_GPMI_CTRL1_DECOUPLE_CS to '1'. This option is useful if software chooses to
use only one DMA channel to access all the attached NAND devices.
15.2.2 GPMI NAND Timing and Clocking

The dedicated clock, GPMICLK, is used as a timing reference for NAND Flash I/O. Since
various NANDs have different timing requirements, GPMICLK may need to be adjusted
for each application. While the actual pin timings are limited by the NAND chips used, the

GPMI NAND Mode
GPMI can support data bus speeds of up to 50 MHz x 8 bits. The actual read/write strobe
timing parameters are adjusted as indicated in the GPMI register descriptions. See Clock
Structure for more information about setting GPMICLK.
15.2.3 Basic NAND Timing

The following figure illustrates the operation of the timing parameters in NAND mode.
GPMI_CE[7:0] /
ALE / CLE TAS TDH
GPMI_OEn/
GPMI_WRn
TDS TDH
GPMI_DATA Data0 Data1
Figure 15-2. BASIC NAND Timing
15.2.4 High-Speed NAND Timing

In high-speed NANDs, the read data may not be valid until after the read strobe (RDN)
deasserts. This is the case when the minimum tDS is programmed to achieve higher
bandwidth. The GPMI implements a feedback read strobe to sample the read data. The
feedback read strobe can be delayed to support fast NAND EDO (Extended Data Out)
timing where the read strobe may deassert before the read data is valid, and read data is
valid for some time after read strobe. NAND EDO timings is applied typically for read
cycle frequency above 33 MHz.See Figure 15-3.
The GPMI provides control over the amount of delay applied to the feedback read strobe.
This delay depends on the maximum read access time (tREA) of the NAND and the read
pulse width (tRP) used to access the NAND. tRP is specified by
HW_GPMI_TIMING0_DATA_SETUP register. When (tREA + 4 ns) is less than tRP, no
delay is required to sample the NAND read data. (The 4 ns provides adequate data setup
time for the GPMI.) In this case, set HW_GPMI_CTRL1_HALF_PERIOD=0;
HW_GPMI_CTRL1_RDN_DELAY=0; HW_GPMI_CTRL1_DLL_ENABLE=0.
When (tREA + 4 ns) is greater than or equal to tRP, a delay of the feedback read strobe is
required to sample the NAND read data. This delay is equal to the difference between these
two timings:
DELAY= tREA+4 ns - tRP.
Since the GPMI delay chain is limited to 16 ns maximum, if DELAY > 16 ns then increase
tRP by increasing the value of HW_GPMI_TIMING0_DATA_SETUP until DELAY is
less than or equal to 16 ns.

The GPMI programming for this DELAY depends on the GPMICLK period. The GPMI
DLL will not function properly if the GPMICLK period is greater than 32 ns: disable the
DLL if this is the case. If the GPMICLK period is greater than 16 ns (and not greater than
32 ns), set the HW_GPMI_CTRL1_HALF_PERIOD=1; This will cause the DLL reference
period (RP) to be one-half of the GPMICLK period. If the GPMICLK period is 16 ns or
less then set the HW_GPMI_CTRL1_HALF_PERIOD=0; This will cause the DLL reference
period (RP) to be equal to the GPMICLK period. DELAY is a multiple (0 to 1.875) of RP.
The HW_GPMI_CTRL1_RDN_DELAY is encoded as a 1-bit integer and 3-bit fraction
delay factor. See table below. DELAY is a multiple of the delay factor and the reference
period:
HW_GPMI_CTRL1_RDN_DELAY 0 1 2 3 4 5 6 7
Delay Factor 0.000 0.125 0.250 0.375 0.500 0.625 0.750 0.875
HW_GPMI_CTRL1_RDN_DELAY 8 9 10 11 12 13 14 15
Delay Factor 1.000 1.125 1.250 1.375 1.500 1.625 1.750 1.875
DELAY = DelayFactor x RP or DELAY = HW_GPMI_CTRL1_RDN_DELAY x 0.125 x

RP.
Use this equation to calculate the value for HW_GPMI_CTRL1_RDN_DELAY. Then set
HW_GPMI_CTRL1_DLL_ENABLE=1.
GPMI NAND Read Path Timing Diagram (Non-EDO)
tRP
tREA
RDN
Read Data A B C
FeedbackRDN
(tREA + 4ns) is less than tRP, no delay is required on rising edge of FeedbackRDN to sample Read Data
GPMI NAND Read Path Timing Diagram (EDO mode)

tREA
tRP
RDN
Read Data A B C
Delay
FeedbackRDN
When (tREA + 4ns) is greater than or equal to tRP, a delay of the FeedbackRDN is required to sample to nand read data
Figure 15-3. NAND Read Path Timing

GPMI NAND Mode
For example, a NAND with tREAmax=20 ns, tRPmin=12 ns, and tRCmin=25 ns (read
cycle time) may be programmed as follows:
• GPMICLK clock frequency: Consider 480/6=80 MHz which is 12.5 ns clock period.
This is too close to the minimum NAND spec if we program the data setup and hold
to 1 GPMICLK cycle. Consider 480/7=68.57 MHz which is 14.58 ns clock period.
With data setup and hold set to 1, we have a tRP of 14.58 ns and a tRC of 29.16 ns
(good margins).
• Since (tREA +4 ns) is greater than tRP, required DELAY = tREA+4 ns - tRP = 20 + 4
- 14.58 ns = 9.42 ns.
• HALF_PERIOD =0, since GPMICLK period is less than 16 ns. So RP=GPMICLK
period = 14.58 ns.
• DELAY = HW_GPMI_CTRL1_RDN_DELAY x 0.125 x RP.9.42 ns =
HW_GPMI_CTRL1_RDN_DELAY x 0.125 x 14.58
ns.HW_GPMI_CTRL1_RDN_DELAY = 5 (round off 5.169)
Note
It is recommended that the drive strength of GPMI_RDn and
GPMI_WRn output pins be set to 8 mA. This will reduce the
transition time under heavy loads. Low transition times will be
important when NAND interface read and write cycle times are
below 30 ns. The other GPMI pins may remain at 4 mA, since
their frequency is only up to half that of GPMI_RDn and
GPMI_WRn.
15.2.5 NAND Command and Address Timing Example

The following figure illustrates a command and address being sent to a NAND Flash.
Run=1 Run=0 Run=1 Run=0
GPMI_CEn
TAS
GPMI_ALE
TAS
GPMI_CLE
TDH
TDH
GPMI_WEn
TDS
TDS
TDH
read cmd
GPMI_DATA $00 AL[7:0] AL[15:8]
Figure 15-4. NAND Command and Address Timing Example

15.2.6 Hardware BCH Interface

The GPMI provides an interface to the BCH module. This reduces the SOC bus traffic and
the software involvement. When in BCH mode, parity information is inserted on-the-fly
during writes to 8-bit NAND devices. The BCH will supply payload and parity to the GPMI
to write to the NAND. During NAND reads, parity is checked and ECC processing is
performed after each read block. In this case, the GPMI reads the NAND device and redirects
the data and parity to the BCH module for ECC processing.
To program the BCH for NAND writes, remove the soft reset and clock gates from
HW_BCH_CTRL_SFTRST and HW_BCH_CTRL_CLKGATE. The bulk of BCH
programming is actually applied to the GPMI through PIO operations embedded in its DMA
command structures. This has a subtle implication when writing to the GPMI ECC registers:
access to these registers must be written in a progressive register order. Therefore, to write
to the HW_GPMI_ECCCOUNT register, write first (in order) to registers
HW_GPMI_CTRL0, HW_GPMI_COMPARE, and HW_GPMI_ECCCTRL before writing
to HW_GPMI_ECCCOUNT. These additional register writes need to be accounted for in
the CMDWORDS field of the respective DMA channel command register. See the descriptive
text, flowcharts, and code examples in Programming the BCH/GPMI Interfaces for more
information about using GPMI registers to program the ECC function.
The HW_GPMI_PAYLOAD and HW_GPMI_AUXILIARY pointers need to be
word-aligned for proper ECC operation. If those pointers are non-word-aligned, then the
BCH engine will not operate properly and could possibly corrupt system memory in the
adjoining memory regions.

CLKGATE bit fields.

GPMI Hardware Register Format Summary

HW_GPMI memory map

Absolute
Width Section/
(in bits) page
(hex)
8000_C000 GPMI Control Register 0 (HW_GPMI_CTRL0) 32 R/W C000_0000h 15.4.1/1246
8000_C010 GPMI Compare Register (HW_GPMI_COMPARE) 32 R/W 0000_0000h 15.4.2/1248
8000_C020 GPMI Integrated ECC Control Register 32 R/W 0000_0000h 15.4.3/1248
(HW_GPMI_ECCCTRL)
8000_C030 GPMI Integrated ECC Transfer Count Register 32 R/W 0000_0000h 15.4.4/1250
(HW_GPMI_ECCCOUNT)
8000_C040 GPMI Payload Address Register (HW_GPMI_PAYLOAD) 32 R/W 0000_0000h 15.4.5/1250
8000_C050 GPMI Auxiliary Address Register (HW_GPMI_AUXILIARY) 32 R/W 0000_0000h 15.4.6/1251
8000_C060 GPMI Control Register 1 (HW_GPMI_CTRL1) 32 R/W 0004_0004h 15.4.7/1251
8000_C070 GPMI Timing Register 0 (HW_GPMI_TIMING0) 32 R/W 0001_0203h 15.4.8/1253
8000_C080 GPMI Timing Register 1 (HW_GPMI_TIMING1) 32 R/W 0000_0000h 15.4.9/1254
8000_C0A0 GPMI DMA Data Transfer Register (HW_GPMI_DATA) 32 R/W 0000_0000h 15.4.10/1254
8000_C0B0 GPMI Status Register (HW_GPMI_STAT) 32 R 0000_0005h 15.4.11/1255
8000_C0C0 GPMI Debug Information Register (HW_GPMI_DEBUG) 32 R 0000_0000h 15.4.12/1257
8000_C0D0 GPMI Version Register (HW_GPMI_VERSION) 32 R 0301_0000h 15.4.13/1258
15.4.1 GPMI Control Register 0 (HW_GPMI_CTRL0)

HW_GPMI_CTRL0: 0x000
HW_GPMI_CTRL0_SET: 0x004
HW_GPMI_CTRL0_CLR: 0x008
HW_GPMI_CTRL0_TOG: 0x00C
The GPMI control register 0 specifies the GPMI transaction to perform for the current
command chain item.
Address: HW_GPMI_CTRL0 – 8000_C000h base + 0h offset = 8000_C000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK_CS
INCREMENT
R RSVD1 RSVD0
ADDRESS_
LENGTH
CLKGATE
SFTRST
WORD_
COMMAND_
RUN CS ADDRESS
MODE
W
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFER_COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_GPMI_CTRL0 field descriptions

Field Description
31 Set to zero for normal operation. When this bit is set to one (default),
SFTRST
then the entire block is held in its reset state. This will not work if the CLKGATE bit is already set to 1.
CLKGATE must be cleared to 0 before issuing a soft reset. Also the GPMICLK must be running for this to
work properly.
0x0 RUN — Allow GPMI to operate normally.
0x1 RESET — Hold GPMI in reset.
30 Set this bit zero for normal operation. Setting this bit to one (default),
CLKGATE
gates all of the block level clocks off for miniminizing AC energy consumption.
0x0 RUN — Allow GPMI to operate normally.
0x1 NO_CLKS — Do not clock GPMI gates in order to minimize power consumption.
29 The GPMI is busy running a command whenever this bit is set to 1. The GPMI is idle whenever this bit set
RUN to zero. This can be set to one by a CPU write. In addition, the DMA sets this bit each time a DMA command
has finished its PIO transfer phase.
0x0 IDLE — The GPMI is idle.
0x1 BUSY — The GPMI is busy running a command.
28 Always write zeros to this field.
RSVD1
27 For NAND mode: 0= Deassert chip select (CS) after RUN is complete. 1= Continue to assert chip select
LOCK_CS (CS) after RUN is complete.
0x0 DISABLED — Deassert chip select (CS) after RUN is complete.
0x1 ENABLED — Continue to assert chip select (CS) after RUN is complete.
26 Always write zeros to this field.
RSVD0
25–24 00= Write mode.
COMMAND_
01= Read Mode.
MODE
10= Read and Compare Mode (setting sense flop).
11= Wait for Ready.
0x0 WRITE — Write mode.
0x1 READ — Read mode.
0x2 READ_AND_COMPARE — Read and Compare mode (setting sense flop).
0x3 WAIT_FOR_READY — Wait for Ready mode.
23 0= not support.
WORD_LENGTH
1= 8-bit Data Bus mode.
This bit should only 1.

HW_GPMI_CTRL0 field descriptions (continued)

Field Description
22–20 Selects which chip select is active for this command.
CS
19–17 In NAND mode, use A0 for CLE and A1 for ALE.
ADDRESS
0x0 NAND_DATA — In NAND mode, this address is used to read and write data bytes.
0x1 NAND_CLE — In NAND mode, this address is used to write command bytes.
0x2 NAND_ALE — In NAND mode, this address is used to write address bytes.
16 0= Address does not increment.
ADDRESS_
1= Increment address.
INCREMENT
In NAND mode, the address will increment once, after the first cycle (going from CLE to ALE).
0x0 DISABLED — Address does not increment.
0x1 ENABLED — Increment address.
15–0 Number of words (8 bit wide) to transfer for this command. A value of zero will transfer 64K words.
XFER_COUNT
15.4.2 GPMI Compare Register (HW_GPMI_COMPARE)

The GPMI compare register specifies the expect data and the xor mask for comparing to
the status values read from the device. This register is used by the Read and Compare
command.
Address: HW_GPMI_COMPARE – 8000_C000h base + 10h offset = 8000_C010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MASK REFERENCE
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_GPMI_COMPARE field descriptions

Field Description
31–16 16-bit mask which is applied after the read data is XORed with the REFERENCE bit field.
MASK
15–0 16-bit value which is XORed with data read from the NAND device.
REFERENCE
15.4.3 GPMI Integrated ECC Control Register (HW_GPMI_ECCCTRL)

HW_GPMI_ECCCTRL: 0x020
HW_GPMI_ECCCTRL_SET: 0x024

HW_GPMI_ECCCTRL_CLR: 0x028
HW_GPMI_ECCCTRL_TOG: 0x02C
The GPMI ECC control register handles configuration of the integrated ECC accelerator.
Address: HW_GPMI_ECCCTRL – 8000_C000h base + 20h offset = 8000_C020h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HANDLE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENABLE_
R RSVD1 RSVD0
ECC
ECC_CMD BUFFER_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_GPMI_ECCCTRL field descriptions

Field Description
31–16 This is a register available to software to attach an identifier to a transaction in progress. This handle will be
HANDLE available from the ECC register space when the completion interrupt occurs.
15 Always write zeroes to this bit field.

RSVD1
14–13 ECC Command information.
ECC_CMD
0x0 DECODE — Decode.
0x1 ENCODE — Encode.
0x2 RESERVE2 — Reserved.
0x3 RESERVE3 — Reserved.
12 Enable ECC processing of GPMI transfers.
ENABLE_ECC
0x1 ENABLE — Use integrated ECC for read and write transfers.
0x0 DISABLE — Integrated ECC remains in idle.
11–9 Always write zeroes to this bit field.
RSVD0
8–0 ECC buffer information. The BCH error correction only allows two configurations of the buffer mask - software
BUFFER_MASK may either read just the first block on the flash page or the entire flash page. Write operations must be for
the entire flash page. Invalid buffer mask values will cause the DMA descriptor command to be terminated.
0x100 BCH_AUXONLY — Set to request transfer from only the auxiliary buffer (block 0 on flash).
0x1FF BCH_PAGE — Set to request transfer to/from the entire page.

15.4.4 GPMI Integrated ECC Transfer Count Register

(HW_GPMI_ECCCOUNT)
The GPMI ECC Transfer Count Register contains the count of bytes that flow through the
ECC subsystem.
Address: HW_GPMI_ECCCOUNT – 8000_C000h base + 30h offset = 8000_C030h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD0
COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_GPMI_ECCCOUNT field descriptions

Field Description
RSVD0
15–0 Number of bytes to pass through ECC. This is the GPMI transfer count plus the syndrome count that will be
COUNT inserted into the stream by the ECC. In DMA2ECC_MODE this count must match the
HW_GPMI_CTRL0_XFER_COUNT. A value of zero will transfer 64K words.
15.4.5 GPMI Payload Address Register (HW_GPMI_PAYLOAD)

The GPMI payload address register specifies the location of the data buffers in system
memory. This value must be word aligned.
Address: HW_GPMI_PAYLOAD – 8000_C000h base + 40h offset = 8000_C040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD0
ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_GPMI_PAYLOAD field descriptions

Field Description
31–2 Pointer to an array of one or more 512 byte payload buffers.
ADDRESS
RSVD0

15.4.6 GPMI Auxiliary Address Register (HW_GPMI_AUXILIARY)

The GPMI auxiliary address register specifies the location of the auxiliary buffers in system
memory. This value must be word aligned.
Address: HW_GPMI_AUXILIARY – 8000_C000h base + 50h offset = 8000_C050h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD0
ADDRESS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_GPMI_AUXILIARY field descriptions

Field Description
31–2 Pointer to ECC control structure and meta-data storage.
ADDRESS
RSVD0
15.4.7 GPMI Control Register 1 (HW_GPMI_CTRL1)

HW_GPMI_CTRL1: 0x060
HW_GPMI_CTRL1_SET: 0x064
HW_GPMI_CTRL1_CLR: 0x068
HW_GPMI_CTRL1_TOG: 0x06C
The GPMI control register 1 specifies additional control fields that are not used on a
per-transaction basis.
Address: HW_GPMI_CTRL1 – 8000_C000h base + 60h offset = 8000_C060h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DECOUPLE_CS
BCH_MODE
TIMEOUT_
RSVD2
GANGED_
R RSVD1
RDYBUSY
ENABLE
PERIOD
IRQ_EN
HALF_
DLL_
WRN_DLY_
SEL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPMI_MODE
TIMEOUT_IRQ
DEV_RESET
ATA_IRQRDY_
BURST_EN
REQUEST
POLARITY
RSVD
DMA2ECC_
R RSVD0
ABORT_
WAIT_
MODE
ABORT_WAIT_FOR_
RDN_DELAY
READY_CHANNEL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
HW_GPMI_CTRL1 field descriptions

Field Description
RSVD2
24 Decouple Chip Select from DMA Channel. Setting this bit to 1 will allow a DMA channel to specify any value
DECOUPLE_CS in the CTRL0_CS register field. Software can use one DMA channel to access all 8 Nand devices.
23–22 Since the GPMI write strobe (WRN) is a fast clock pin, the delay on this signal can be programmed to match
WRN_DLY_SEL the load on this pin.
0 = 4ns to 8ns; 1 = 6ns to 10ns; 2 = 7ns to 12ns; 3 = no delay.
21 Always write zeroes to this bit field.

RSVD1
20 Setting this bit to 1 will enable timeout IRQ for WAIT_FOR_READY commands in Nand mode. The
TIMEOUT_IRQ_ Device_Busy_Timeout value is used for this timeout.
EN
19 Set this bit to 1 will force all Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0. This will
GANGED_ free up all, except one, RDY_BUSY input pins.
RDYBUSY
18 This bit selects which error correction unit will access GPMI. This bit must always be set to 1, since only the
BCH_MODE BCH unit is available in this design.
17 Set this bit to 1 to enable the GPMI DLL. This is required for fast NAND reads (above 30MHz read strobe).
DLL_ENABLE
After setting this bit, wait 64 GPMI clock cycles for the DLL to lock before performing a NAND read.
16 Set this bit to 1 if the GPMI clock period is greater than 16ns for proper DLL operation. DLL_ENABLE must
HALF_PERIOD be zero while changing this field.
15–12 This variable is a factor in the calculated delay to apply to the internal read strobe for correct read data
RDN_DELAY sampling.
The applied delay (AD) is between 0 and 1.875 times the reference period (RP). RP is one half of the GPMI
clock period if HALF_PERIOD=1
otherwise it is the full GPMI clock period. The equation is: AD = RDN_DELAY x 0.125 x RP. This value must
not exceed 16ns.
This variable is used to achieve faster NAND access. For example if the Read Strobe is asserted from time
0 to 13ns but the read access time is 20ns,
then choose AD=12ns will cause the data to be sampled at time 25ns (13+12) giving a 5ns data setup time.
If RP=13ns then RDN_DELAY = 12/(0.125 x 13ns)
= 7.38 (0111b). DLL_ENABLE must be zero while changing this field.

HW_GPMI_CTRL1 field descriptions (continued)

Field Description
11 This is mainly for testing HWECC without involving the Nand device. Setting this bit will cause DMA write
DMA2ECC_ data to redirected to HWECC module (instead of Nand Device) for encoding or decoding.
MODE
10 Always write zeros to this bit field.
RSVD
9 This bit is set when a timeout occurs using the Device_Busy_Timeout value. Write 0 to clear.
TIMEOUT_IRQ
8 When set to 1 each DMA request will generate a 4-transfer burst on the APB bus.
BURST_EN
7 Request to abort the wait for ready command on the channel indicated by
ABORT_WAIT_ ABORT_WAIT_FOR_READY_CHANNEL. Hardware clears this bit when the abort is done.
REQUEST
6–4 Abort a wait for ready command on selected channel. Set the ABORT_WAIT_REQUEST to kick of operation.
ABORT_WAIT_
FOR_READY_
CHANNEL
3 Nand Flash write protection control.
DEV_RESET
0x0 ENABLED — enable write protection for all Nand devices.
0x1 DISABLED — disable write protection for all Nand devices.
2 Always set this bit to 1.
ATA_IRQRDY_
POLARITY
1 Always write zeros to this bit field.
RSVD0
0 0= NAND mode.
GPMI_MODE
This bit should be 0 only.
15.4.8 GPMI Timing Register 0 (HW_GPMI_TIMING0)

The GPMI timing register 0 specifies the timing parameters that are used by the cycle state
machine to guarantee the various setup, hold and cycle times for the external media type.
Address: HW_GPMI_TIMING0 – 8000_C000h base + 70h offset = 8000_C070h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD0
ADDRESS_SETUP DATA_HOLD DATA_SETUP
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1
set

HW_GPMI_TIMING0 field descriptions

Field Description
RSVD0
23–16 Number of GPMICLK cycles that the CE/ADDR signals are active before a strobe is asserted. A value of
ADDRESS_ zero is interpreted as 0.
SETUP
15–8 Data bus hold time in GPMICLK cycles. Also the time that the data strobe is de-asserted in a cycle. A value
DATA_HOLD of zero is interpreted as 256.
7–0 Data bus setup time in GPMICLK cycles. Also the time that the data strobe is asserted in a cycle. A value
DATA_SETUP of zero is interpreted as 256.
15.4.9 GPMI Timing Register 1 (HW_GPMI_TIMING1)

The GPMI timing register 1 specifies the timeouts used when monitoring the NAND READY
pin and IOWAIT signals.
Address: HW_GPMI_TIMING1 – 8000_C000h base + 80h offset = 8000_C080h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD0
DEVICE_BUSY_TIMEOUT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_GPMI_TIMING1 field descriptions

Field Description
31–16 Timeout waiting for NAND Ready/Busy. Used in WAIT_FOR_READY mode. This value is the number of
DEVICE_BUSY_ GPMI_CLK cycles multiplied by 4096.
TIMEOUT
RSVD0
15.4.10 GPMI DMA Data Transfer Register (HW_GPMI_DATA)

The GPMI DMA data transfer register is used by the DMA to read or write data to or from
the NAND control state machine.

Address: HW_GPMI_DATA – 8000_C000h base + A0h offset = 8000_C0A0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DATA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_GPMI_DATA field descriptions

Field Description
31–0 In 8-bit mode, one, two, three or four bytes can can be accessed to send the same number of bus cycles.
DATA
15.4.11 GPMI Status Register (HW_GPMI_STAT)

The GPMI control and status register provides a read back path for various operational
states of the GPMI controller.
Address: HW_GPMI_STAT – 8000_C000h base + B0h offset = 8000_C0B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R READY_BUSY RDY_TIMEOUT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESENT
ERROR
ERROR
ERROR
ERROR
ERROR
ERROR
ERROR
ERROR
BUFFER_
EMPTY
INVALID_
DEV7_
DEV6_
DEV5_
DEV4_
DEV3_
DEV2_
DEV1_
DEV0_
GPMI_
FIFO_
FIFO_
RDY1
FULL
MASK
R RSVD0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
HW_GPMI_STAT field descriptions

Field Description
31–24 Read-only view of NAND Ready_Busy Input pins.
READY_BUSY
23–16 State of the RDY/BUSY Timeout Flags. When any bit is set to '1' in this field, it indicates that a time out
RDY_TIMEOUT
has occurred while waiting for the ready state of the requested NAND device. Multiple bits may be set
simultaneously.

HW_GPMI_STAT field descriptions (continued)

Field Description
When HW_GPMI_CTRL1_DECOUPLE_CS = 0, RDY_TIMEOUT[n] is associated with the NAND device on
chip_select[n].
When HW_GPMI_CTRL1_DECOUPLE_CS = 1, these flags become associated to a DMA channel instead
of a NAND device.
For example if DMA channel 6 sends a WAIT_FOR_READY command for NAND Device 2, and a timeout
occured on READY_BUSY2,
then READY_TIMEOUT[6] will be set instead of READY_TIMEOUT[2].
15 0= No error condition present on NAND Device accessed by DMA channel 7.

DEV7_ERROR
1= An Error has occurred on NAND Device accessed by DMA channel 7 (Timeout or compare failure,
depending on COMMAND_MODE).

DEV6_ERROR

DEV5_ERROR

DEV4_ERROR

DEV3_ERROR

DEV2_ERROR

DEV1_ERROR
1= An Error has occurred onNAND Device accessed by DMA channel 1 (Timeout or compare failure,

DEV0_ERROR

RSVD0
4 Status of theGPMI_RDY1 input pin.
GPMI_RDY1
3 0= ECC Buffer Mask is not invalid.
INVALID_
1= ECC Buffer Mask is invalid.
BUFFER_MASK

HW_GPMI_STAT field descriptions (continued)

Field Description
2 0= FIFO is not empty.
FIFO_EMPTY
1= FIFO is empty.
0x0 NOT_EMPTY — FIFO is not empty.
0x1 EMPTY — FIFO is empty.
1 0= FIFO is not full.
FIFO_FULL
1= FIFO is full.
0x0 NOT_FULL — FIFO is not full.
0x1 FULL — FIFO is full.
0 0= GPMI is not present in this product.
PRESENT
1= GPMI is present is in this product.
0x0 UNAVAILABLE — GPMI is not present in this product.
0x1 AVAILABLE — GPMI is present in this product.
15.4.12 GPMI Debug Information Register (HW_GPMI_DEBUG)

The GPMI debug information register provides a read back path for diagnostics to determine
the current operating state of the GPMI controller.
Address: HW_GPMI_DEBUG – 8000_C000h base + C0h offset = 8000_C0C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R WAIT_FOR_READY_END DMA_SENSE DMAREQ CMD_END

W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_GPMI_DEBUG field descriptions

Field Description
31–24 Read Only view of the Wait_For_Ready End toggle signals to DMA. One per channel
WAIT_FOR_
READY_END
23–16 Read-only view of sense state of the 8 DMA channels. A value of 1 in any bit position indicates that a read
DMA_SENSE and compare command failed or a timeout occured for the corresponding channel.
15–8 Read-only view of DMA request line for 8 DMA channels. A toggle on any bit position indicates a DMA
DMAREQ request for the corresponding channel.
7–0 Read Only view of the Command End toggle signals to DMA. One per channel
CMD_END

15.4.13 GPMI Version Register (HW_GPMI_VERSION)

This register reflects the version number for the GPMI.
Address: HW_GPMI_VERSION – 8000_C000h base + D0h offset = 8000_C0D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MAJOR MINOR STEP

W
Re- 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_GPMI_VERSION field descriptions

Field Description
MAJOR
MINOR
STEP

Chapter 16
20-BIT Correcting ECC Accelerator (BCH)
16.1 BCH Overview

The hardware ECC accelerator provides a forward error-correction function for improving
the reliability of various storage media that may be attached to the device. For example,
modern high-density NAND flash devices presume the existence of forward error-correction
algorithms to correct some soft and/or hard bit errors within the device, allowing for higher
device yields and, therefore, lower NAND device costs.
The Bose, Ray-Chaudhuri, Hocquenghem (BCH) Encoder and Decoder module is capable
of correcting from 2 to 20 single bit errors within a block of data no larger than about 900
bytes (512 bytes is typical) in applications such as protecting data and resources stored on
modern NAND flash devices. The correction level in the BCH block is programmable to
provide flexibility for varying applications and configurations of flash page size. The design
can be programmed to encode protection of 2, 4, 6, 8, 10, 12, 14, 16, 18, or 20 bit errors
when writing flash and to correct the corresponding number of errors on decode. The
correction level when decoding MUST be programmed to the same correction level as was
used during the encode phase.
BCH-codes are a type of block-code, which implies that all error-correction is performed
over a block of N-symbols. The BCH operation will be performed over GF(213 = 8192),
which is the Galois Field consisting of 8191 one-bit symbols. BCH-encoding (or encode
for any block-code) can be performed by two algorithms: systematic encoding or
multiplicative encoding. Systematic encoding is the process of reading all the symbols
which constitute a block, dividing continuously these symbols by the generator polynomial
for the GF(8192) and appending the resulting t parity symbols to the block to create a BCH
codeword (where t is the number of correctable bits).
The BCH encode process creates t 13-bit parity symbols for each data block when the data
is written to the flash device. The parity symbols are written to the flash device after the
corresponding data block, and together these are collectively called the codeword. The
codeword can be used during the decode process to correct errors that occur in either the
data or parity blocks.

BCH Overview
The BCH decoder processes code words in a 4-step fashion:

1. Syndrome Calculation (SC): This is the process of reading in all of the symbols of the
codeword and continuously dividing by the generator polynomial for the field. 2*t
syndromes must be calculated for each codeword and inspection of the syndromes
determines if there are errors: a non-zero set of syndromes indicates one or more errors.
This process is implemented parallel hardware to minimize processing time since it
must be done every time the decode is performed.
2. Key Equation Solver (KES): The syndromes represent 2t-linear equations with
2t-unknown variables. The process of solving these equations and selecting from the
numerous solutions constitutes the KES module. When the KES block completes its
operations, it generates an error locator polynomial (sigma) that is used in the proceeding
block to determine the locations and values of the errors.
3. Chien Search (CS): This block takes input from the KES block and uses the Chien
Algorithm for finding the locations of the errors based on the error locator polynomial.
The method basically involves substituting all 8191 symbols from the GF(8192) into
the locator polynomial. All evaluations that produce a zero solution indicate locations
of the various errors. Since each located error corresponds to a single bit, the bit in the
original data may be corrected by simply flipping the polarity of the incorrect location.
4. Correction: this block has to convert the symbol index and mask information to memory
byte indexes and masks.
The BCH block, shown in the figure, was designed to operate in a pipelined fashion to
maximize throughput. Aside from the initial latency to fill the pipeline stages, the BCH
throughput is faster than the fastest GPMI read rate of 2 cycles/byte. Thus, the bottleneck
in performing NAND reads and error corrections is the GPMI read rate. Current GPMI read
rates are approximately 3 cycles/byte for the current generation of NAND flash. The CPU
is not directly involved in generating parity symbols, checking for errors, or correcting
them.

Chapter 16 20-BIT Correcting ECC Accelerator (BCH)
AXI
APBH APBH Bridge/DMA
BCH Engine
BCH
GPMI Programmable
Registers
Transfer Controls
Write Data Parity Write Data

Generation
GPMI
NAND synpar AXI
CONTROLLER master
Syndrome
Read Data Read Data &
Calculation
transfer
syndromes FSM
Key
Equation
Solver
error-locator polynomial
Chien corrections
Search
GPMI clock domain
Figure 16-1. Hardware BCH Accelerator
16.2 Operation
Before performing any NAND flash read or write operations, software should first program
the BCH's flash layout registers (see Flash Page Layout) to specify how data is to be
formatted on the flash device. The BCH hardware allows full programmability over the
flash page layout to enable users flexibility in balancing ECC correction levels and
ever-changing flash page sizes.
To initiate a NAND Flash write, software will program a GPMI DMA operation. The DMA
need only program the GPMI control registers (and handle the requisite flash addressing
handshakes) since the BCH will handle all data operations using its AXI bus interface. The
BCH will then send the data to the GPMI controller to be written to flash as it computes
the parity symbols. At the end of each data block the BCH will insert the parity symbols
into the data stream so that the GPMI sees only a continuous stream of data to be written.
NAND Flash read operations operate in a similar manner. As the GPMI controller reads
the device, all data is sent to the BCH hardware for error detection/correction. The BCH
controller writes all incoming read data to system memory and in parallel computes the
syndromes used to detect bit errors. If errors are detected within a block, the BCH hardware

Operation
activates the error correction logic to determine where bit errors have occurred and ultimately
correct them in the data buffer in system memory. After an entire flash page has been read
and corrected, the BCH will signal an interrupt to the CPU.
Figure 16-2 indicates how data read from the GPMI is operated on within the BCH hardware.
As the BCH receives data from the GPMI (top row), it is written to memory by the BCH's
Bus Interface Unit (BIU) (second row). For blocks requiring correction, the KES logic will
be activated after the entire block has been received. Once the error locator polynomial has
been computed, the corrections are determined by the Chien Search and fed back to the
BIU, which performs a read, modify, write operation on the buffer in memory to correct
the data.
ECC Done
GPMI/ Read Read Read Read Read Read Read Read Interrupt
Syndrome Block 0 Block 1 Block 2 Block 3 Block 4 Block 5 Block 6 Block 7
Write Write Write Write Write Write Write Write

Block 0 Block 1 Block 2 / Block 3 / Block 4 / Block 5 / Block 6 / Block 7 /
BIU
Correct Correct Correct Correct Correct Correct Correct Correct
Block 0 Block 1 Block 2 Block 3 Block 4 Block 5 Block 6 Block 7
KES KES KES KES KES KES KES KES

KES
CS CS CS CS CS CS CS CS
Chien Search
Figure 16-2. Block Pipeline while Reading Flash
16.2.1 BCH Limitations and Assumptions

• The BCH is programmable to support 2, 4, 6, 8, 10, 12, 14, 16, 18, and 20 bit error
correction. ECC0 is supported as a passthrough, non-correcting mode.
• Data block sizes must be a multiple of 4 bytes and be aligned in system memory.
• The BCH supports a programmable number of metadata/auxiliary data bytes, from 0
to 255.
• Metadata will be written at the beginning of the flash page to facilitate fast access for
filesystem operations.
• Metadata may be treated as an independent block for ECC purposes or combined with
the first data block to conserve bits in the flash.
• The BCH does not support a partial page write (this can be accomplished by
programming the BCH layout registers such that the BCH only sees a portion of the
page).

• Flash read operations can read the entire page or the first block on the page.
• The BCH also supports a memory-to-memory mode of operation that does not require
the use of DMA or the GPMI.
16.2.2 Flash Page Layout

The BCH supports a fully programmable flash page layout. The BCH maintains four
independent layout registers that can describe four completely different NAND devices or
layouts. When the BCH initiates an operation, it selects one of the layouts by using the chip
select as an index into the HW_BCH_LAYOUTSELECT register the determines which
layout should be used for the operation.
Three possible (generic) flash layout schemes are supported, as indicated in Figure 16-3.
(In each case, the metadata size may also be programmed to 0 bytes). Metadata may either
be combined with the first block of data or the size of the first data block can be programmed
to 0 to allow the metadata to be protected by its own ECC parity bits.
Separate ECC over Metadata
parity
parity
parity
parity
parity
parity
meta d0 d1 d2 dn-1 dn
10B 512B 512B 512B 512B 512B
Block 0 Block 1 Block 2

Size=10B Size=512B Size=512B
ECC=4 ECC=14 ECC=14
Combined Metadata & Block 0, unbalanced ECC coverage

parity
parity
parity
parity
parity
meta d0 d1 d2 dn-1 dn
10B 512B 512B 512B 512B 512B

ECC=16 ECC=16 ECC=16
Combined Metadata & Block 0, balanced ECC coverage

parity
parity
parity
parity
parity
meta d0 d1 d2
2 dn-1 dn
32B 484B 516B 516B 516B 516B

ECC=14 ECC=14 ECC=14
Figure 16-3. FLASH Page Layout Options
Each layout is determined by a pair of registers that define the following parameters:
• DATA0_SIZE: Indicates the number of data bytes in the first block on the page (this
should not include parity or metadata bytes). This should be set to 0 when the metadata
is to be covered separately with its own ECC. This must be a multiple of 4 bytes.

Operation
• ECC0: Indicates the ECC level to be used for the first block on the flash
(data0+metadata).
• META_SIZE: Indicates the number of bytes (from 0-255) that are stored as metadata.
• NBLOCKS: Indicates the number of subsequent DATAN blocks on the flash, or the
number of blocks following the DATA0 block.
• DATAN_SIZE: Indicates the number of data bytes in all subsequent data blocks. This
MUST be a multiple of 4 bytes.
• ECCN: Indicates the ECC level to be used for the subsequent data blocks.
• PAGE_SIZE: Indicates the total number of bytes available per page on the physical
flash device. This includes the spare area and is typically 4096+128, 4096+218, or
2048+64 bytes.
16.2.3 Determining the ECC layout for a device

Since the BCH is programmable, a system can trade off ECC levels for flash size and layout
configurations. The following examples indicate how to determine a valid layout based on
the required storage space and flash size. For all cases, the size of the parity will be 13*ECC
level bits-- so for ECC8, 13 bytes are required (per block).
16.2.3.1 4K+218 flash, 10 bytes metadata, 512 byte data blocks, separate
metadata
In this case, we have 8 data blocks each consisting of 512 bytes. Since the flash has 218
spare bytes (1744 bits), first estimate an ECC level for the data blocks by first subtracting
the number of metadata bytes from the spare bytes (218 – 10 = 208 bytes = 1664 bits) then
dividing the number of bits by 8 (number of blocks) and then by 13 (bits per ECC level).
1664
(218 − 10) × 8 = 13(8) = 16
Therefore all the data blocks could be covered by ECC16 if the metadata had no parity.
This isn't acceptable, so assume ECC14 for all the data blocks. Now calculate the number
of free bits for the metadata parity as
1664 - (14) x 13 x 8 = 208
Therefore, 208 bits remain for metadata parity. Dividing by 13 (bits/ECC) gives 16, so the
metadata can be covered with ECC16. The settings for this device would then be

Table 16-1. Settings for 4K+218 FLASH

Setting Value
PAGE_SIZE 4096+218=4314=0x10DA
META_SIZE 10=0x0A
DATA0_SIZE 0
ECC0 16=0x10
DATAN_SIZE 512=0x200
ECCN 14=0x0E
NBLOCKS 8
16.2.3.2 4K+128 flash, 10 bytes metadata, 512 byte data blocks, separate
metadata
This flash will have 118 bytes available for ECC (after subtracting the metadata size),
therefore, 994 bits. Dividing by 8*13 (number of blocks * ECC level) we get 9.07, therefore
we can support ECC8 on the data blocks. The number of free spare bits becomes
944-8*8*13=944-832=112, divided by 13 = 8.6, therefore the metadata can be also covered
by ECC8.
Table 16-2. Settings for 4K+128 FLASH
Setting Value
PAGE_SIZE 4096+128=4224=0x1080
META_SIZE 10=0x0A
DATA0_SIZE 0
ECC0 8
DATAN_SIZE 512=0x200
ECCN 8
NBLOCKS 8
In this case, there will be additional unused spare bits, with the BCH will pad out with zeros.

Operation
16.2.4 Data Buffers in System Memory

While the data on the flash is interleaved with parity symbols, the BCH assumes that the
data buffers in memory are contiguous. Metadata read from the flash will be stored to the
location pointed to by the HW_GPMI_AUXILIARY register and data will be written to
the address specified in the HW_GPMI_PAYLOAD register as is shown in Figure 16-4.
Since the number of blocks on a flash page is programmable, the BCH also writes individual
block correction status to the auxiliary pointer at the word-aligned address following the
end of the metadata. Optionally, the computed syndromes may also be written to the auxiliary
area if the DEBUGSYNDROME bit is set in the control register.
As blocks complete processing, the bus master will accumulate the status for each block
and write it to the auxiliary data buffer following the metadata. The metadata area will be
padded with 0's until the next word boundary and the status for blocks 0-3 will be written
to the next word. The status for subsequent blocks will then be written to the buffer. The
status for the first block (metadata block) is also stored in the STATUS_BLK0 register in
the BCH_STATUS register. The completion codes for the blocks are indicated in the Table
16-3. Note that the definition of the bytes and their ordering in the auxiliary and payload
storage areas are user defined. When this data is read back from the flash and put into
memory, it will resemble the original buffer that was written out to the flash.

Minimum System Memory Footprint:
512 byte Payload A
HW_GPMI_PAYLOAD
512 byte Payload B
512 byte Payload C
512 byte Payload D
META_SIZE bytes of auxiliary storage

(programmable – block is padded w/ 0's to word
HW_GPMI_AUXILIARY
boundary)
Status for each block.
(Optional n bytes syndromes for Payload A)

(Optional n bytes syndrome for Payload B)
(Optional n bytes syndrome for Payload C)
(Optional n bytes syndrome for Payload D)
Computed syndrome area consists of 2*t 13-bit

symbols written as 16-bit halfwords.
Figure 16-4. BCH Data Buffers in Memory
Table 16-3. Status Block Completion Codes

Code Description
0xFF Block is erased
0xFE Block is uncorrectable
0x00 No errors found
0x01-0x14 Number of errors corrected
The following figure shows the layout of the bytes within the status field.

Memory to Memory (Loopback) Operation
3 2 1 0
Metadata
0 0
Block 3 Block 2 Block 1 block 0

Status Status Status Status

Status Status Status Status
Block 8
0 0 0
Status
Status bytes are allocated based on the NBLOCKS programmed into the
flash format register. The number of status bytes will be computed by the
NBLOCKS+1. The status area will be padded with zeros to the next word
boundary.
Syndrome data written for debug purposes will follow the

end of the status block.
Figure 16-5. Memory-to-Memory Operations
16.3 Memory to Memory (Loopback) Operation

The BCH supports a memory-to-memory mode of operation where both the encoded and
decoded buffers reside in system memory. This can be useful for applications where data
must be protected by ECC, but the storage device does not reside on the GPMI bus.
The BCH operation in memory to memory mode is much simpler than in GPMI mode since
DMAs are not required to manage the operation. Instead, software simply writes the
HW_BCH_DATAPTR and HW_BCH_METAPTR with the addresses of the data and
metadata (auxiliary) buffers and the HW_BCH_ENCODEPTR with the address of the buffer
for encoded data. To initiate the operation, software simply sets the M2M_ENCODE and
M2M_ENABLE bits in the control register. The BCH can be programmed to either issue
an interrupt at the end of the operation or software may poll the status bits for completion.
Memory to memory decode operations work in a similar manner. The encoded data address
is written to the HW_BCH_ENCODEPTR and the data and meta pointers are written to
buffers that correspond to the desired decoded data addresses. To initiate a decode, software
must set the M2M_ENCODE bit to 0 while writing the M2M_ENABLE bit. Note that the
addresses written to the HW_BCH_DATAPTR, HW_BCH_METAPTR and
HW_BCH_ENCODEPTR registers should always be aligned on a 4 byte boundary. In other
words, the 2 lower bits of the address should always be written with zeros.

16.4 Programming the BCH/GPMI Interfaces

Programming the BCH for NAND operations consists largely of disabling the soft reset
and clock bits (SFTRST and CLKGATE) from the HW_BCH_CTRL register and then
programming the flash layout registers to correspond to the format of the attached NAND
device(s). The HW_BCH_LAYOUTSELECT register should also be programmed to map
the chip select of each attached device into one of the four layout registers.
The bulk of the programming is actually applied to the GPMI through PIO operations
embedded in DMA command structures. The DMA will perform all the requisite handshaking
with the GPMI interface to negotiate the address portion of the transfer, then the BCH will
handle all the movement of data from memory to the GPMI (writes) or the GPMI to memory
(reads). The BCH will direct all data blocks to the buffer pointed to by the
PAYLOAD_BUFFER and the metadata will be written to the AUXILIARY_BUFFER.
Both of these registers are located in the GPMI PIO data space and are communicated to
the BCH hardware at the beginning of the transfer. Thus, the normal multi-NAND DMA
based device interleaving is preserved, that is, four NANDs on four separate chip selects
can be scheduled for read or write operations using the BCH. Whichever channel finishes
its ready wait first and enters the DMA arbiter with its lock bit set owns the GPMI command
interface and through it owns the BCH resources for the duration of its processing.
16.4.1 BCH Encoding for NAND Writes

The BCH encoder flowchart in Figure 16-6 shows the detailed steps involved in programming
and using the BCH encoder. This flowchart shows how to use the BCH block with the
GPMI.
To use the BCH encoder with the GPMI's DMA, create a DMA command chain containing
ten descriptor structures, as shown in Figure 16-8 and detailed in the DMA structure code
example that follows it in DMA Structure Code Example. The ten descriptors perform the
following tasks:
1. Disable the BCH block (in case it was enabled) and issue NAND write setup command
byte (under CLE) and address bytes (under ALE).
2. Configure and enable the BCH and GPMI blocks to perform the NAND write.
3. Disable the BCH block and issue NAND write execute command byte (under CLE).
4. Wait for the NAND device to finish writing the data by watching the ready signal.
5. Check for NAND timeout through PSENSE.

Programming the BCH/GPMI Interfaces
6. Issue NAND status command byte (under CLE).

7. Read the status and compare against expected.
8. If status is incorrect or incomplete, branch to error handling descriptor chain.
9. Otherwise, write is complete and emit GPMI interrupt.
BCH ENCODE &

WRITE NAND
Run the prescribe initialization sequence.
Point the GPMI DMA channel 4 (or 5 or 6 or 7) at

the prescribed static DMA sequence.
Start the DMA.
Return and wait for DMA channel 4 (or 5 or 6 or 7)

command complete interrupt.
STOP
APBH DMA CH4 Command

Complete ISR Must use SCT clear
HW_APBH_CTRL1_CH0_CMDCMPLT_IRQ = 0
Start GPMI DMA chain for next write or read transfer.
STOP
Figure 16-6. BCH Encode Flowchart

Descriptor Legend
NEXT CMD ADDR
CMD <= xfer_count cmdwords wait4endcmd semaphore nandwait4ready nandlock irqoncmplt chain command
BUFFER ADDR
HW_GPMI_CTRL0 <= command_mode word_length lock_cs CS address address_increment xfer_count
HW_GPMI_COMPARE <= mask reference
HW_GPMI_ECCCTRL <= ecc_cmd enable_ecc buffer_mask
HW_GPMI_ECCCOUNT
HW_GPMI_PAYLOAD
HW_GPMI_AUXILIARY
Figure 16-7. BCH DMA Descriptor Legend

Descriptor 1: Disable BCH engine and issue NAND write set-up command and address (CLE/ALE).
NEXT CMD ADDR
CMD <= 1+5 3 1 0 0 1 0 1 DMA_READ
BUFFER ADDR 1 Byte NAND CMD
HW_GPMI_CTRL0 <= write 8_bit enabled 2 NAND_CLE 1 1+5
5 Byte ADDR
HW_GPMI_COMPARE <= null null
HW_GPMI_ECCCTRL <= disable
NOTE: No DMA
Descriptor 2: Enable the BCH engine and write the data payload.
data transferred to
NEXT CMD ADDR GPMI when using
CMD <= 0 4 1 0 0 1 0 1 NO_DMA_XFER BCH
BUFFER ADDR
HW_GPMI_CTRL0 <= write 8_bit enabled 2 NAND_DATA 0 0
HW_GPMI_ECCCTRL <= encode_8_bit enable 0x1FF
8*512 Byte Data
HW_GPMI_ECCCOUNT<= 4096+218 (flash page size)
Payload Buffer
HW_GPMI_PAYLOAD
HW_GPMI_AUXILIARY
Auxiliary Payload
Buffer
Descriptor 3: Disable BCH engine and issue NAND write execute command (CLE).
NEXT CMD ADDR
CMD <= 1 3 1 0 0 1 0 1 DMA_READ
BUFFER ADDR
1 Byte NAND CMD
HW_GPMI_CTRL0 <= write 8_bit enabled 2 NAND_CLE 0 1
HW_GPMI_ECCCTRL <= ---- disable ----
Descriptor 4: Wait for NAND ready.

NEXT CMD ADDR
CMD <= 0 1 1 0 1 0 0 1 NO_DMA_XFER
BUFFER ADDR
HW_GPMI_CTRL0 <= wait_for_ready 8_bit disabled 2 NAND_DATA 0 0
Descriptor 5: PSENSE compare for time-out.

NEXT CMD ADDR
CMD <= 0 0 0 0 0 0 0 1 DMA_SENSE DMA Error
BUFFER ADDR Descriptor Chain
Descriptor 6: Disable BCH engine (if enabled by another thread) and issue NAND status command (CLE).
NEXT CMD ADDR
CMD <= 1 3 1 0 0 1 0 1 DMA_READ
HW_GPMI_CTRL0 <= write 8_bit enabled 2 NAND_CLE 0 1
Descriptor 7: Read the NAND status and compare against expected value.
NEXT CMD ADDR
CMD <= 0 2 1 0 0 1 0 1 NO_DMA_XFER
BUFFER ADDR
HW_GPMI_CTRL0 <= read_and_compare 8_bit disabled 2 NAND_DATA 0 1
HW_GPMI_COMPARE <= <mask_value> <reference_value>
Descriptor 8: PSENSE compare for status comparison check.

NEXT CMD ADDR
CMD <= 0 0 0 0 0 0 0 1 DMA_SENSE
BUFFER ADDR
Descriptor 9: Emit GPMI DMA interrupt.

NEXT CMD ADDR
CMD <= 0 0 0 0 0 0 1 0 NO_DMA_XFER
BUFFER ADDR
Figure 16-8. BCH Encode DMA Descriptor Chain

16.4.1.1 DMA Structure Code Example

The following code sample illustrates the coding for one write transaction involving 4096
bytes of data payload (eight 512-byte blocks) and 10 bytes of auxiliary payload (also referred
to as metadata) to a 4K NAND page sitting on GPMI CS2.
//----------------------------------------------------------------------------
// generic DMA/GPMI/ECC descriptor struct, order sensitive!
//----------------------------------------------------------------------------
typedef struct {
// DMA related fields
unsigned int dma_nxtcmdar;
unsigned int dma_cmd;
unsigned int dma_bar;
// GPMI related fields
unsigned int gpmi_ctrl0;
unsigned int gpmi_compare;
unsigned int gpmi_eccctrl;
unsigned int gpmi_ecccount;
unsigned int gpmi_data_ptr;
unsigned int gpmi_aux_ptr;
} GENERIC_DESCRIPTOR;
//----------------------------------------------------------------------------
// allocate 10 descriptors for doing a NAND ECC Write
//----------------------------------------------------------------------------
GENERIC_DESCRIPTOR write[10];
//----------------------------------------------------------------------------
// DMA descriptor pointer to handle error conditions from psense checks
//----------------------------------------------------------------------------
unsigned int * dma_error_handler;
//----------------------------------------------------------------------------
// 8 byte NAND command and address buffer
// any alignment is ok, it is read by the GPMI DMA
// byte 0 is write setup command
// bytes 1-5 is the NAND address
// byte 6 is write execute command
// byte 7 is status command
//----------------------------------------------------------------------------
unsigned char nand_cmd_addr_buffer[8];
//----------------------------------------------------------------------------
// 4096 byte payload buffer used for reads or writes
// needs to be word aligned
//----------------------------------------------------------------------------
unsigned int write_payload_buffer[(4096/4)];
//----------------------------------------------------------------------------
// 65 byte meta-data to be written to NAND
//----------------------------------------------------------------------------
unsigned int write_aux_buffer[65];
//----------------------------------------------------------------------------
// Descriptor 1: issue NAND write setup command (CLE/ALE)
//----------------------------------------------------------------------------
write[0].dma_nxtcmdar = &write[1]; // point to the next descriptor
write[0].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (1 + 5)| // 1 byte command, 5 byte address
BF_APBH_CHn_CMD_CMDWORDS (3) | // send 3 words to the GPMI
BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // wait for command to finish before
// continuing
BF_APBH_CHn_CMD_SEMAPHORE (0) |
BF_APBH_CHn_CMD_NANDWAIT4READY(0) |
BF_APBH_CHn_CMD_NANDLOCK (1) | // prevent other DMA channels from
// taking over

BF_APBH_CHn_CMD_IRQONCMPLT (0) |
BF_APBH_CHn_CMD_CHAIN (1) | // follow chain to next command
BV_FLD(APBH_CHn_CMD, COMMAND, DMA_READ); // read data from DMA, write to NAND
write[0].dma_bar = &nand_cmd_addr_buffer; // byte 0 write setup, bytes 1 - 5 NAND
address
// 3 words sent to the GPMI
write[0].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, WRITE) | // write to the NAND
BV_FLD(GPMI_CTRL0, WORD_LENGTH, 8_BIT) |
BV_FLD(GPMI_CTRL0, LOCK_CS, ENABLED) |
BF_GPMI_CTRL0_CS (2) | // must correspond to NAND CS used
BV_FLD(GPMI_CTRL0, ADDRESS, NAND_CLE) |

BF_GPMI_CTRL0_ADDRESS_INCREMENT (1) | // send command and address
BF_GPMI_CTRL0_XFER_COUNT (1 + 5); // 1 byte command, 5 byte address

write[0].gpmi_compare = NULL; // field not used but necessary to set
eccctrl
write[0].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, DISABLE); // disable the ECC block
//----------------------------------------------------------------------------
// Descriptor 2: write the data payload (DATA)
//----------------------------------------------------------------------------
write[1].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0)| // NOTE: No DMA data transfer
BF_APBH_CHn_CMD_CMDWORDS (4)| // send 4 words to the GPMI
BF_APBH_CHn_CMD_WAIT4ENDCMD (1)| // Wait to end
BF_APBH_CHn_CMD_SEMAPHORE (0)|
BF_APBH_CHn_CMD_NANDWAIT4READY (0)|
BF_APBH_CHn_CMD_NANDLOCK (1)| // maintain resource lock
BF_APBH_CHn_CMD_IRQONCMPLT (0)|
BF_APBH_CHn_CMD_CHAIN (1)| // follow chain to next command
BV_FLD(APBH_CHn_CMD, COMMAND, DMA_NO_XFER); // No data transferred
write[1].dma_bar = &write_payload_buffer; // pointer for the 4K byte data
area
BF_GPMI_CTRL0_CS (2) | // must correspond to NAND CS
used
BV_FLD(GPMI_CTRL0, ADDRESS, NAND_DATA)|
BF_GPMI_CTRL0_ADDRESS_INCREMENT (0) |
BF_GPMI_CTRL0_XFER_COUNT (0); // NOTE: this field contains
// the total amount

// DMA transferred to GPMI via DMA (0)!
write[1].gpmi_compare = NULL; // field not used but necessary to
set eccctrl
write[1].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ECC_CMD, ENCODE_8_BIT) | // specify t = 8 mode
BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, ENABLE) | // enable ECC module

BF_GPMI_ECCCTRL_BUFFER_MASK (0x1FF); // write all 8 data blocks
// and 1 aux block

write[1].gpmi_ecccount = BF_GPMI_ECCCOUNT_COUNT(4096+218); // specify number of bytes
// written to NAND
write[1].gpmi_data_pointer = &write_payload_pointer; // data buffer address
write[1].gpmi_aux_pointer = &write_aux_pointer; // metadata pointer
//----------------------------------------------------------------------------
// Descriptor 3: issue NAND write execute command (CLE)
//----------------------------------------------------------------------------
write[2].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (1) | // 1 byte command
// continuing

BF_APBH_CHn_CMD_NANDLOCK (1) | // maintain resource lock
write[2].dma_bar = &nand_cmd_addr_buffer[6]; // point to byte 6, write execute
command

BF_GPMI_CTRL0_XFER_COUNT (1); // 1 byte command
eccctrl
//----------------------------------------------------------------------------
// Descriptor 4: wait for ready (CLE)
//----------------------------------------------------------------------------
write[3].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | // no dma transfer

BF_APBH_CHn_CMD_CMDWORDS (1) | // send 1 word to the GPMI
// continuing
BF_APBH_CHn_CMD_NANDWAIT4READY(1) | // wait for nand to be ready
BF_APBH_CHn_CMD_NANDLOCK (0) | // relinquish nand lock
BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER); // no dma transfer
write[3].dma_bar = NULL; // field not used
// 1 word sent to the GPMI
write[3].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, WAIT_FOR_READY) | // wait for NAND ready

BV_FLD(GPMI_CTRL0, LOCK_CS, DISABLED) |
BV_FLD(GPMI_CTRL0, ADDRESS, NAND_DATA) |

BF_GPMI_CTRL0_XFER_COUNT (0);
//----------------------------------------------------------------------------
// Descriptor 5: psense compare (time out check)
//----------------------------------------------------------------------------
BF_APBH_CHn_CMD_CMDWORDS (0) | // no words sent to GPMI
BF_APBH_CHn_CMD_WAIT4ENDCMD (0) | // do not wait to continue
BF_APBH_CHn_CMD_NANDLOCK (0) |
BV_FLD(APBH_CHn_CMD, COMMAND, DMA_SENSE); // perform a sense check
write[4].dma_bar = dma_error_handler; // if sense check fails, branch to error
handler
//----------------------------------------------------------------------------
// Descriptor 6: issue NAND status command (CLE)
//----------------------------------------------------------------------------
write[5].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (1) | // 1 byte command

continuing
taking over
write[5].dma_bar = &nand_cmd_addr_buffer[7]; // point to byte 7, status command
eccctrl

//----------------------------------------------------------------------------
// Descriptor 7: read status and compare (DATA)
//----------------------------------------------------------------------------
// continuing
BF_APBH_CHn_CMD_NANDLOCK (1) | // maintain resource lock
write[6].dma_bar = NULL; // field not used
write[6].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, READ_AND_COMPARE) | // read from the
// NAND and
// // compare to expect

write[6].gpmi_compare = <MASK_AND_REFERENCE_VALUE>; // NOTE: mask and reference values are
NAND
// SPECIFIC to evaluate the NAND
status
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
write[7].dma_bar = dma_error_handler; // if sense check fails, branch to error
handler
//----------------------------------------------------------------------------

// Descriptor 9: emit GPMI interrupt

//----------------------------------------------------------------------------
write[8].dma_nxtcmdar = NULL; // not used since this is last
descriptor
BF_APBH_CHn_CMD_IRQONCMPLT (1) | // emit GPMI interrupt
BF_APBH_CHn_CMD_CHAIN (0) | // terminate DMA chain processing
16.4.1.2 Using the BCH Encoder

To use the BCH encoder, first turn off the module-wide soft reset bit in both the GPMI and
BCH blocks before starting any DMA activity. Turning off the soft reset must take place
by itself, prior to programming the rest of the control registers. Turn off the BCH bus master
soft reset bit (bit 29). Turn off the clock gate bits.
Program the remainder of the GPMI, BCH and APBH DMA as follows:
// bring APBH out of reset
HW_APBH_CTRL0_CLR(BM_APBH_CTRL0_SFRST);
HW_APBH_CTRL0_CLR(BM_APBH_CTRL0_CLKGATE);
// bring BCH out of reset
HW_BCH_CTRL_CLR(BM_BCH_CTRL_SFTRST);
HW_BCH_CTRL_CLR(BM_BCH_CTRL_CLKGATE);
// bring gpmi out of reset
HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_SFTRST);
HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_CLKGATE);
HW_GPMI_CTRL1_SET(BM_GPMI_CTRL1_DEV_RESET | // deassert reset
BM_GPMI_CTRL1_BCH_MODE ); // enable BCH mode
// enable pinctrl
HW_PINCTRL_CTRL_WR(0x00000000);
// enable GPMI through alt pin wiring
HW_PINCTRL_MUXSEL0_CLR(0xff000000);
HW_PINCTRL_MUXSEL0_SET(0xaa000000);
// to use the primary pins do the following
// HW_PINCTRL_MUXSEL4_CLR(0xff000000);
// HW_PINCTRL_MUXSEL4_SET(0x55000000);
// enable gpmi pins
HW_PINCTRL_MUXSEL0_CLR(0x0000ffff); // data bits
HW_PINCTRL_MUXSEL1_CLR(0x000fffff); // control bits
Note that for writing NANDs (ECC encoding), only GPMI DMA command complete
interrupts are used. The BCH engine is used for writing to the NAND but may optionally
produces an interrupt. From the sample code in DMA Structure Code Example:
• DMA descriptor 1 prepares the NAND for data write by using the GPMI to issue a
write setup command byte under CLE, then sends a 5-byte address under ALE. The
BCH engine is disabled and not used for these commands.

• DMA descriptor 2 enables the BCH engine for encoding to begin the initial writing of
the NAND data by specifying where the data and auxiliary payload are coming from
in system memory.
• DMA descriptor 3 issues the write commit command byte under CLE to the NAND.
• DMA descriptor 4 waits for the NAND to complete the write commit/transfer by
watching the NAND's ready line status. This descriptor relinquishes the NANDLOCK
on the GPMI to enable the other DMA channels to initiate NAND transactions on
different NAND CS lines.
• DMA descriptor 6 issues a NAND status command byte under "CLE" to check the
status of the NAND device following the page write.
• DMA descriptor 7 reads back the NAND status and compares the status with an expected
value. If there are differences, then the DMA processing engine follows an error-handling
DMA descriptor path.
• DMA descriptor 8 disables the BCH engine and emits a GPMI interrupt to indicate that
the NAND write has been completed.
16.4.2 BCH Decoding for NAND Reads

When a page is read from NAND flash, BCH syndromes will be computed and, if correctable
errors are found, they will be corrected on a per block basis within the NAND page. This
decoding process is fully overlapped with other NAND data reads and with CPU execution.
The BCH decoder flowchart in Figure 16-9 shows the steps involved in programming the
decoder. The hardware flow of reading and decoding a 4096-byte page is shown in Figure
16-10.

Read NAND &

BCH Decode
Run the prescribe initialization Sequence
Point the GPMI DMA channel 4 (or 5 or 6 or 7) at

the prescribed static DMA sequence
Start the DMA
Return and wait for DMA channel 4 (or 5 or 6 or 7)

command complete interrupt.
STOP
APBH DMA CH4 Command

Complete ISR Must use SCT clear
HW_APBH_CTRL1_CH0_CMDCMPLT_IRQ = 0
Start GPMI DMA chain for next write or read transfer
STOP
BCH Complete ISR
Read status regs and store for processing
Must use SCT clear
HW_BCH_CTRL_COMPLETE_IRQ = 0
STOP
Figure 16-9. BCH Decode Flowchart
Conceptually, an APHB DMA Channel 4, 5, 6, or 7 command chain with seven command

structures linked together is used to perform the BCH decode operation (as shown in Figure
16-10).
Note
The GPMI's DMA command structures controls the BCH decode
operation.
To use the BCH decoder with the GPMI's DMA, create a DMA command chain containing
seven descriptor structures, as shown in Figure 16-10 and detailed in the DMA structure
code example that follows it in DMA Structure Code Example. The seven DMA descriptors
perform the following tasks:
1. Issue NAND read setup command byte (under "CLE") and address bytes (under "ALE").
2. Issue NAND read execute command byte (under "CLE").

3. Wait for the NAND device to complete accessing the block data by watching the ready
signal.
4. Check for NAND timeout through "PSENSE".
5. Configure and enable the BCH block and read the NAND block data.
6. Disable the BCH block.
7. Descriptor NOP to allow NANDLOCK in the previous descriptor to the thread-safe.

Descriptor 1: Disable BCH engine and issue NAND read set-up command and address (CLE/ALE).
NEXT CMD ADDR

CMD <= 1+5 3 1 0 0 1 0 1 DMA_READ
HW_GPMI_CTRL0 <= write 8_bit enabled 2 NAND_CLE 1 1+5
5 Byte ADDR
Descriptor 2: NAND read execute command (CLE).
NEXT CMD ADDR

CMD <= 1 1 1 0 0 1 0 1 DMA_READ
HW_GPMI_CTRL0 <= write 8_bit disabled 2 NAND_CLE 0 1
Descriptor 3: Wait for NAND ready.
NEXT CMD ADDR

CMD <= 0 1 1 0 1 0 0 1 NO_DMA_XFER
BUFFER ADDR
HW_GPMI_CTRL0 <= wait_for_ready 8_bit disabled 2 NAND_DATA 0 0
Descriptor 4: PSENSE compare for time-out.
NEXT CMD ADDR

DMA Error
CMD <= 0 0 0 0 0 0 0 1 DMA_SENSE Descriptor Chain
BUFFER ADDR
Descriptor 5: Enable BCH engine and read NAND data.
NEXT CMD ADDR

CMD <= 0 6 1 0 0 1 0 1 NO_DMA_XFER
BUFFER ADDR
HW_GPMI_CTRL0 <= read 8_bit disabled 2 NAND_DATA 0 4096+218
HW_GPMI_ECCCTRL <= decode_8_bit enable 0x1FF
8*512 Byte Data
HW_GPMI_ECCCOUNT<= 4096+218 (flash page size) Payload Buffer
HW_GPMI_PAYLOAD
HW_GPMI_AUXILIARY
412 Byte Auxiliary
Payload Buffer
Descriptor 6: Disable BCH engine (wait for ready is a NOP here).
NEXT CMD ADDR

CMD <= 0 3 1 0 1 1 0 1 NO_DMA_XFER
BUFFER ADDR
HW_GPMI_CTRL0 <= wait_for_ready 8_bit
_ disabled 0 NAND_DATA 0 0
Descriptor 7: NOP to ensure NANDLOCK in previous descriptor .
NEXT CMD ADDR

CMD <= 0 0 0 0 0 0 0 0 NO_DMA_XFER
BUFFER ADDR
Figure 16-10. BCH Decode DMA Descriptor Chain
16.4.2.1 DMA Structure Code Example

The following sample code illustrates the coding for one read transaction, consisting of a
seven DMA command structure chain for reading all 4096 bytes of payload data (eight
512-byte blocks) and 65 bytes of metadata with the associative parity bytes (8 * (18) + 9)
from a 4K NAND page sitting on GPMI CS2.
//----------------------------------------------------------------------------

// generic DMA/GPMI/ECC descriptor struct, order sensitive!

//----------------------------------------------------------------------------
typedef struct {
// DMA related fields
unsigned int dma_nxtcmdar;
unsigned int dma_cmd;
unsigned int dma_bar;
// GPMI related fields
unsigned int gpmi_ctrl0;
unsigned int gpmi_compare;
unsigned int gpmi_eccctrl;
unsigned int gpmi_ecccount;
unsigned int gpmi_data_ptr;
unsigned int gpmi_aux_ptr;
} GENERIC_DESCRIPTOR;
//----------------------------------------------------------------------------
// allocate 7 descriptors for doing a NAND ECC Read
//----------------------------------------------------------------------------
GENERIC_DESCRIPTOR read[7];
//----------------------------------------------------------------------------
// DMA descriptor pointer to handle error conditions from psense checks
//----------------------------------------------------------------------------
unsigned int * dma_error_handler;
//----------------------------------------------------------------------------
// 7 byte NAND command and address buffer
// any alignment is ok, it is read by the GPMI DMA
// byte 0 is read setup command
// bytes 1-5 is the NAND address
// byte 6 is read execute command
//----------------------------------------------------------------------------
unsigned char nand_cmd_addr_buffer[7];
//----------------------------------------------------------------------------
// 4096 byte payload buffer used for reads or writes
//----------------------------------------------------------------------------
unsigned int read_payload_buffer[(4096/4)];
//----------------------------------------------------------------------------
// 412 byte auxiliary buffer used for reads
//----------------------------------------------------------------------------
unsigned int read_aux_buffer[(412/4)];
//----------------------------------------------------------------------------
// Descriptor 1: issue NAND read setup command (CLE/ALE)
//----------------------------------------------------------------------------
read[0].dma_nxtcmdar = &read[1]; // point to the next descriptor
read[0].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (1 + 5) | // 1 byte command, 5 byte address
BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // wait for command to finish
// before continuing
// taking over
BV_FLD(APBH_CHn_CMD, COMMAND, DMA_READ); // read data from DMA, write to
NAND
read[0].dma_bar = &nand_cmd_addr_buffer; // byte 0 read setup, bytes 1 - 5 NAND
address
read[0].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, WRITE) | // write to the NAND
BF_GPMI_CTRL0_CS (2) | // must correspond to NAND
CS used
BF_GPMI_CTRL0_ADDRESS_INCREMENT (1) | // send command and address
BF_GPMI_CTRL0_XFER_COUNT (1 + 5); // 1 byte command, 5 byte

address
read[0].gpmi_compare = NULL; // field not used but necessary to set
eccctrl
read[0].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, DISABLE); // disable the ECC block
//----------------------------------------------------------------------------
// Descriptor 2: issue NAND read execute command (CLE)
//----------------------------------------------------------------------------
read[1].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (1) | // 1 byte read command
BF_APBH_CHn_CMD_CMDWORDS (1) | // send 1 word to GPMI
// continuing
// taking over
BV_FLD(APBH_CHn_CMD, COMMAND, DMA_READ); // read data from DMA, write to
NAND
read[1].dma_bar = &nand_cmd_addr_buffer[6]; // point to byte 6, read execute
command
read[1].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, WRITE) | // write to the NAND
CS used
//----------------------------------------------------------------------------
// Descriptor 3: wait for ready (DATA)
//----------------------------------------------------------------------------
read[2].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | // no dma transfer
BF_APBH_CHn_CMD_CMDWORDS (1) | // send 1 word to GPMI
// continuing
read[2].dma_bar = NULL; // field not used
read[2].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, WAIT_FOR_READY) | // wait for NAND ready

BF_GPMI_CTRL0_CS (2) | // must correspond to
NAND CS used
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------

BF_APBH_CHn_CMD_CHAIN (1) | // follow chain to next
command
read[3].dma_bar = dma_error_handler; // if sense check fails, branch to
error handler
//----------------------------------------------------------------------------
// Descriptor 5: read 4K page plus 65 byte meta-data Nand data
// and send it to ECC block (DATA)
//----------------------------------------------------------------------------
BF_APBH_CHn_CMD_CMDWORDS (6) | // send 6 words to GPMI
// continuing
taking over
BF_APBH_CHn_CMD_IRQONCMPLT (0) | // ECC block generates BCH interrupt
// on completion
BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER); // no DMA transfer,
// ECC block handles transfer
read[4].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, READ) | // read from the NAND
CS used
BF_GPMI_CTRL0_XFER_COUNT (4096+218); // eight 512 byte data
blocks
// metadata, and parity

eccctrl
// GPMI ECCCTRL PIO This launches the 4K byte transfer through BCH's
// bus master. Setting the ECC_ENABLE bit redirects the data flow
// within the GPMI so that read data flows to the BCH engine instead
// of flowing to the GPMI's DMA channel.
read[4].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ECC_CMD, DECODE_8_BIT) | // specify t = 8
mode
BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, ENABLE) | // enable ECC module
BF_GPMI_ECCCTRL_BUFFER_MASK (0X1FF); // read all 8 data blocks and

1 aux block
read[4].gpmi_ecccount = BF_GPMI_ECCCOUNT_COUNT(4096+218); // specify number of bytes
// read from NAND
read[4].gpmi_data_ptr = &read_payload_buffer; // pointer for the 4K byte
// data area
read[4].gpmi_aux_ptr = &read_aux_buffer; // pointer for the 65 byte
aux area +
// parity and syndrome bytes
for both
// data and aux blocks.
//----------------------------------------------------------------------------
// Descriptor 6: disable ECC block
//----------------------------------------------------------------------------
BF_APBH_CHn_CMD_CMDWORDS (3) | // send 3 words to GPMI
// continuing


BF_APBH_CHn_CMD_NANDLOCK (1) | // need nand lock to be
// thread safe while turn-off BCH
read[5].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, READ) |
CS used
eccctrl
read[5].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, DISABLE); // disable the ECC block
//----------------------------------------------------------------------------
// Descriptor 7: deassert nand lock
//----------------------------------------------------------------------------
read[6].dma_nxtcmdar = NULL; // not used since this is last
descriptor
// continuing
BF_APBH_CHn_CMD_IRQONCMPLT (0) | // BCH engine generates interrupt
BF_APBH_CHn_CMD_CHAIN (0) | // terminate DMA chain processing
16.4.2.2 Using the Decoder

As illustrated in Figure 16-10 and the sample code in DMA Structure Code Example:
• DMA descriptor 1 prepares the NAND for data read by using the GPMI to issue a
NAND read setup command byte under CLE, then sends a 5-byte address under ALE.
The BCH engine is not used for these commands.
• DMA descriptor 2 issues a one-byte read execute command to the NAND device that
triggers its read access. The NAND then goes not ready.
• DMA descriptor 3 performs a wait for ready operation allowing the DMA chain to
remain dormant until the NAND device completes its read access time.
• DMA descriptor 5 handles the reading and error correction of the NAND data. This
command's PIOs activate the BCH engine to write the read NAND data to system
memory and to process it for any errors that need to be corrected. This DMA descriptor
contains two PIO values that are system memory addresses pointing to the PAYLOAD
data area and to the AUXILIARY data area. These addresses are used by the BCH
engine's AHB master to move data into system memory and to correct it. While this

example is reading an entire 4K page—payload plus metadata—it is equally possible

to read just one 512-byte payload block or just the uniquely protected metadata block
in a single 7 DMA structure transfer.
• DMA descriptor 6 disables the BCH engine with the NANDLOCK asserted. This is
necessary to ensure that the GPMI resource is not arbitrated to another DMA channel
when multiple DMA channels are active concurrently.
• DMA descriptor 7 deasserts the NANDLOCK to free up the GPMI resource to another
channel.
As the BCH block receives data from the GPMI:

• The decoder transforms the read NAND data block into a BCH code word and computes
the codeword syndrome.
• If no errors are present, then the BCH block can immediately report back to firmware.
This report is passed as the HW_BCH_CTRL_COMPLETE_IRQ interrupt status bit
and the associated status registers in HW_BCH_STATUS0/1 registers.
• If an error is present, then the BCH block corrects the necessary data block or parity
block bytes, if possible (not all errors are correctable).
As the BCH decoder reads the data and parity blocks, it records a special condition, i.e.,
that all of the bits of a payload data block or metadata block are one, including any associated
parity bytes. The all-ones case for both parity and data indicates an erased block in the
NAND device.
The HW_BCH_STATUS0 register contains a 4-bit field that indicates the final status of
the auxiliary block. A value of 0x0 indicates no errors found for a block.
• A value of 1 to 20 inclusive indicates that many correctable errors were found and fixed.
• A value of 0xFE indicates uncorrectable errors detected on the block.
• A value of 0xFF indicates that the block was in the special ALL ONES state and is
therefore considered to be an ERASED block.
• All other values are disallowed by the hardware design.
Recall that up to four NAND devices can have DMA chains in-flight at once, i.e. they can
all be contending for access to the GPMI data bus. It is impossible to predict which NAND
device will enter the BCH engine with a transfer first, because each chain includes a
wait4ready command structure. As a result, firmware should look at the
HW_BCH_STATUS0_COMPLETED_CE bit field to determine which block is being

reported in the status register. There is also a 16-bit HANDLE field in the
HW_GPMI_ECCCTRL register that is passed down the pipeline with each transaction.
This handle field can be used to speed firmware's detection of which transaction is being
reported.
These examples of reading and writing have focused on full page transfers of 4K page
NAND devices. Other device configurations can be specified by changing the ECCOUNT
field in the GPMI registers and reprogramming the BCH's HW_FLASHnLAYOUTm
registers.
The BCH and GPMI blocks are designed to be very efficient at reading single 512-byte
pages in one transaction. With no errors, the transaction takes less than 20 HCLKs longer
than the time to read the raw data from the NAND.
To summarize, the APBH DMA command chain for a BCH decode operation is shown in
Figure 16-10. Seven DMA command structures must be present for each NAND read
transaction decoded by the BCH. The seven DMA command structures for multiple NAND
read transaction blocks can be chained together to make larger units of work for the BCH,
and each will produce an appropriate error report in the BCH PIO space. Multiple NAND
devices can have such multiple chains scheduled. The results can come back out of order
with respect to the multiple chains.
16.4.3 Interrupts
There are two interrupt sources used in processing BCH protected NAND read and write
transfers. Since all BCH operations are initiated by GPMI DMA command structures, the
DMA completion interrupt for the GPMI is an important ISR. Both of the flow charts of
Figure 16-6 and Figure 16-9 show the GPMI DMA complete ISR skeleton. In both reads
and writes, the GPMI DMA completion interrupt is used to schedule work INTO the error
correction pipeline. As the front end processing completes, the DMA interrupt is generated
and additional work, such as DMA chains, are passed to the GPMI DMA to keep it fed. For
write operations, this is the only interrupt that is generated for processing the NAND write
transfer.
For reads, however, two interrupts are needed. Every read is started by a GPMI DMA
command chain and the front end queue is fed as described above. The back end of the read
pipeline is drained by monitoring the BCH completion interrupt found int
HW_BCH_CTRL_COMPLETE_IRQ.
An BCH transaction consists of reading or writing all of the blocks requested in the
HW_GPMI_ECCCTRL_BUFFER_MASK bit field. As every read transaction completes,
it posts the status of all of the blocks to the HW_BCH_STATUS0 and HW_BCH_STATUS1
registers and sets the completion interrupt. The five stages of the BCH read pipeline
completes, one in the GPMI and four in the BCH, are independently stalled as they complete
and try to deliver to the next stage in the data flow. Several of these stages can be skipped
if no-errors are found or once an uncorrectable error is found in a block.
In any case, the final stage will stall if the status register is busy waiting for the CPU to take
status register results. The hardware monitors the state of the
HW_BCH_CTRL_COMPLETE_IRQ bit. If it is still set when the last pipeline stage is
ready to post data, then the stage will stall. It follows that the next previous stage will stall
when it is ready to hand off work to the final stage, and so on up the pipeline.
CAUTION
It is important that firmware read the STATUS0/1 results and
save them before clearing the interrupt request bit. Otherwise, a
transaction and its results could be completely lost.

CLKGATE when setting SFTRST. The reset process gates the clocks automatically.

BCH Hardware Register Format Summary
HW_BCH memory map
Absolute
Width Section/
(in bits) page
(hex)
8000_A000 Hardware BCH ECC Accelerator Control Register 32 R/W 00E0_0000_ 16.6.1/1288
(HW_BCH_CTRL) 0000h
8000_A010 Hardware ECC Accelerator Status Register 0 32 R 0000_0010h 16.6.2/1290
(HW_BCH_STATUS0)
8000_A020 Hardware ECC Accelerator Mode Register (HW_BCH_MODE) 32 R/W 0000_0000h 16.6.3/1292
8000_A030 Hardware BCH ECC Loopback Encode Buffer Register 32 R/W 0000_0000h 16.6.4/1293
(HW_BCH_ENCODEPTR)
8000_A040 Hardware BCH ECC Loopback Data Buffer Register 32 R/W 0000_0000h 16.6.5/1293
(HW_BCH_DATAPTR)
8000_A050 Hardware BCH ECC Loopback Metadata Buffer Register 32 R/W 0000_0000h 16.6.6/1294
(HW_BCH_METAPTR)
8000_A070 Hardware ECC Accelerator Layout Select Register 32 R/W E4E4_E4E4h 16.6.7/1294
(HW_BCH_LAYOUTSELECT)

HW_BCH memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
8000_A080 Hardware BCH ECC Flash 0 Layout 0 Register 32 R/W 070A_8200h 16.6.8/1296
(HW_BCH_FLASH0LAYOUT0)
8000_A090 Hardware BCH ECC Flash 0 Layout 1 Register 32 R/W 10DA_8200h 16.6.9/1297
8000_A0A0 Hardware BCH ECC Flash 1 Layout 0 Register 32 R/W 070A_8200h 16.6.10/1298
8000_A0B0 Hardware BCH ECC Flash 1 Layout 1 Register 32 R/W 10DA_8200h 16.6.11/1299
8000_A0C0 Hardware BCH ECC Flash 2 Layout 0 Register 32 R/W 070A_8200h 16.6.12/1300
8000_A0D0 Hardware BCH ECC Flash 2 Layout 1 Register 32 R/W 10DA_8200h 16.6.13/1302
8000_A0E0 Hardware BCH ECC Flash 3 Layout 0 Register 32 R/W 070A_8200h 16.6.14/1303
8000_A0F0 Hardware BCH ECC Flash 3 Layout 1 Register 32 R/W 10DA_8200h 16.6.15/1304
8000_A100 Hardware BCH ECC Debug Register0 (HW_BCH_DEBUG0) 32 R/W 0000_0000h 16.6.16/1305
8000_A110 KES Debug Read Register (HW_BCH_DBGKESREAD) 32 R 0000_0000h 16.6.17/1307
8000_A120 Chien Search Debug Read Register 32 R 0000_0000h 16.6.18/1308
(HW_BCH_DBGCSFEREAD)
8000_A130 Syndrome Generator Debug Read Register 32 R 0000_0000h 16.6.19/1308
(HW_BCH_DBGSYNDGENREAD)
8000_A140 Bus Master and ECC Controller Debug Read Register 32 R 0000_0000h 16.6.20/1309
(HW_BCH_DBGAHBMREAD)
8000_A150 Block Name Register (HW_BCH_BLOCKNAME) 32 R 2048_4342h 16.6.21/1309
8000_A160 BCH Version Register (HW_BCH_VERSION) 32 R 0100_0000h 16.6.22/1310
16.6.1 Hardware BCH ECC Accelerator Control Register

(HW_BCH_CTRL)
The BCH CTRL provides overall control of the hardware ECC accelerator
HW_BCH_CTRL: 0x000
HW_BCH_CTRL_SET: 0x004
HW_BCH_CTRL_CLR: 0x008
HW_BCH_CTRL_TOG: 0x00C
EXAMPLE

Address: HW_BCH_CTRL – 8000_A000h base + 0h offset = 8000_A000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DEBUGSYNDROME
M2M_ENCODE
M2M_ENABLE
R RSVD5 RSVD4
CLKGATE
SFTRST
M2M_
LAYOUT
W
Reset 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEBUG_STALL_IRQ_
COMPLETE_IRQ_EN
DEBUG_STALL_IRQ
RSVD2
RSVD0
BM_ERROR_IRQ
COMPLETE_IRQ
R RSVD3 EN RSVD1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_BCH_CTRL field descriptions

Field Description
31 Set this bit to zero to enable normal BCH operation. Set this bit to one (default) to disable clocking with
SFTRST the BCH and hold it in its reset (lowest power) state. This bit can be turned on and then off to reset the
BCH block to its default state. This bit resets all state machines except for the AHB master state machine
0x0 RUN — Allow BCH to operate normally.
0x1 RESET — Hold BCH in reset.
CLKGATE
0x0 RUN — Allow BCH to operate normally.
0x1 NO_CLKS — Do not clock BCH gates in order to minimize power consumption.
29–23 Reserved, always set this bit to zero.
RSVD5
22 (For debug purposes only). Enable write of computed syndromes to memory on BCH decode operations.
DEBUGSYNDROME Computed syndromes will be written to the auxiliary buffer after the status block. Syndromes will be
written as padded 16-bit values.
21–20 Reserved, always set these bits to zero.

RSVD4
19–18 Selects the flash page format for memory-to-memory operations.
M2M_LAYOUT
17 Selects encode (parity generation) or decode (correction) mode for memory-to-memory operations.
M2M_ENCODE
16 NOTE! WRITING THIS BIT INITIATES A MEMORY-TO-MEMORY OPERATION. The BCH module must
M2M_ENABLE be inactive (not processing data from the GPMI) when this bit is set. The M2M_ENCODE and
M2M_LAYOUT bits as well as the ENCODEPTR, DATAPTR, and METAPTR registers are used for
memory-to-memory operations and must be correctly programmed before writing this bit.

HW_BCH_CTRL field descriptions (continued)

Field Description
RSVD3
10 1 = interrupt on debug stall mode is enabled. The irq is raised on every block
DEBUG_STALL_
IRQ_EN
9 Reserved, always set these bits to zero.
RSVD2
8 1 = interrupt on completion of correction is enabled.
COMPLETE_IRQ_EN
RSVD1
3 AHB Bus interface Error Interrupt Status. Write a one to the SCT clear address to clear the interrupt
BM_ERROR_IRQ status bit.
2 DEBUG STALL Interrupt Status. Write a one to the SCT clear address to clear the interrupt status bit.
DEBUG_STALL_IRQ
1 Reserved, always set these bits to zero.
RSVD0
0 This bit indicates the state of the external interrupt line. Write a one to the SCT clear address to clear
COMPLETE_IRQ the interrupt status bit. NOTE: subsequent ECC completions will be held off as long as this bit is set. Be
sure to read the data from HW_BCH_STATUS0,1 before clearing this interrupt bit.
16.6.2 Hardware ECC Accelerator Status Register 0

(HW_BCH_STATUS0)
The BCH STAT register provides visibility into the run-time status of the BCH and status
information when processing is complete.
EXAMPLE

Address: HW_BCH_STATUS0 – 8000_A000h base + 10h offset = 8000_A010h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R HANDLE COMPLETED_CE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNCORRECTABLE
CORRECTED
ALLONES
R STATUS_BLK0 RSVD1 RSVD0
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
HW_BCH_STATUS0 field descriptions

Field Description
31–20 Software supplies a 12 bit handle for this transfer as part of the GPMI DMA PIO operation that started
HANDLE the transaction. That handle passes down the pipeline and ends up here at the time the BCH interrupt is
signaled.
19–16 This is the chip enable number corresponding to the NAND device from which this data came.
COMPLETED_CE
15–8 Count of symbols in error during processing of first block of flash (metadata block). The number of errors
STATUS_BLK0 reported will be in the range of 0 to the ECC correction level for block 0.
0x00 ZERO — No errors found on block.
0x01 ERROR1 — One error found on block.
0x02 ERROR2 — One errors found on block.
0xFE UNCORRECTABLE — Block exhibited uncorrectable errors.
0xFF ERASED — Page is erased.

HW_BCH_STATUS0 field descriptions (continued)

Field Description
RSVD1
4 1 = All data bits of this transaction are ONE.
ALLONES
3 1 = At least one correctable error encountered during last processing cycle.
CORRECTED
2 1 = Uncorrectable error encountered during last processing cycle.
UNCORRECTABLE
RSVD0
16.6.3 Hardware ECC Accelerator Mode Register (HW_BCH_MODE)

The BCH MODE register provides additional mode controls.
Contains additional global mode controls for the BCH engine.
EXAMPLE
Address: HW_BCH_MODE – 8000_A000h base + 20h offset = 8000_A020h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD
ERASE_THRESHOLD
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_BCH_MODE field descriptions

Field Description
RSVD
7–0 This value indicates the maximum number of zero bits on a flash page for it to be considered erased. For
ERASE_ SLC NAND devices, this value should be programmed to 0 (meaning that the entire page should consist of
THRESHOLD bytes of 0xFF. For MLC NAND devices, bit errors may occur on reads (even on blank pages), so this threshold
can be used to tune the erased page checking algorithm.

16.6.4 Hardware BCH ECC Loopback Encode Buffer Register

(HW_BCH_ENCODEPTR)
When performing memory to memory operations, indicates the address of the encode buffer.
This register should be programmed before writing a 1 to the M2M_ENABLE bit in the
CTRL register.
For memory to memory operations, this register is used as the pointer to the encoded data,
which is an output when encoding and an input while decoding.
EXAMPLE
Address: HW_BCH_ENCODEPTR – 8000_A000h base + 30h offset = 8000_A030h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_BCH_ENCODEPTR field descriptions

Field Description
31–0 Address pointer to encode buffer. This is the source for decode operations and the destination for encode
ADDR operations. This value must be aligned on a 4 byte boundary.
16.6.5 Hardware BCH ECC Loopback Data Buffer Register

(HW_BCH_DATAPTR)
When performing memory to memory operations, indicates the address of the data buffer.
For memory to memory operations, this register is used as the pointer to the data to encode
or the destination buffer for decode operations.
EXAMPLE
Address: HW_BCH_DATAPTR – 8000_A000h base + 40h offset = 8000_A040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

HW_BCH_DATAPTR field descriptions

Field Description
31–0 Address pointer to data buffer. This is the source for encode operations and the destination for decode
ADDR operations. This register should be programmed before writing a 1 to the M2M_ENABLE bit in the CTRL
register. This value must be aligned on a 4 byte boundary.
16.6.6 Hardware BCH ECC Loopback Metadata Buffer Register

(HW_BCH_METAPTR)
When performing memory to memory operations, indicates the address of the metadata
buffer.
For memory to memory operations, this register is used as the pointer to the metadata to
encode or the extracted metadata for decode operations.
EXAMPLE
Address: HW_BCH_METAPTR – 8000_A000h base + 50h offset = 8000_A050h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_BCH_METAPTR field descriptions

Field Description
31–0 Address pointer to metadata buffer.This is the source for encode metadata read operations and the destination
ADDR for metadata decode operations. This register should be programmed before writing a 1 to the M2M_ENABLE
bit in the CTRL register. This value must be aligned on a 4 byte boundary.
16.6.7 Hardware ECC Accelerator Layout Select Register

(HW_BCH_LAYOUTSELECT)
The BCH LAYOUTSELECT register provides a mapping of chip selects to layout registers.
When the BCH engine receives a request to process a data block from the GPMI interface,
it will use this register to map the incoming chip select to one of the four possible flash
layout registers
EXAMPLE

Address: HW_BCH_LAYOUTSELECT – 8000_A000h base + 70h offset = 8000_A070h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SELECT
SELECT
SELECT
SELECT
SELECT
SELECT
SELECT
SELECT
SELECT
SELECT
SELECT
SELECT
SELECT
SELECT
SELECT
SELECT
CS15_
CS14_
CS13_
CS12_
CS11_
CS10_
CS9_
CS8_
CS7_
CS6_
CS5_
CS4_
CS3_
CS2_
CS1_
CS0_
W
Re- 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0
set
HW_BCH_LAYOUTSELECT field descriptions

Field Description
31–30 Selects which layout is used for chip select 15.
CS15_SELECT
CS14_SELECT
CS13_SELECT
CS12_SELECT
CS11_SELECT
CS10_SELECT
CS9_SELECT
CS8_SELECT
CS7_SELECT
CS6_SELECT
CS5_SELECT
CS4_SELECT
CS3_SELECT
CS2_SELECT
CS1_SELECT
CS0_SELECT

16.6.8 Hardware BCH ECC Flash 0 Layout 0 Register

The flash format register contains a description of the logical layout of data on the flash
device. This register is used in conjuction with the FLASH0LAYOUT1 register to control
the format for the devices selecting layout 0 in the LAYOUTSELECT register.
Each pair of layout registers describes one of four supported flash configurations. Software
should program the LAYOUTSELECT register for each supported GPMI chip select to
select from one of the fourlayout values. Each pair of registers contains settings that are
used by the BCH block while reading/writing the flash page to control data, metadata, and
flash page sizes as well as the ECC correction level. The first block written to flash can be
programmed to have different ECC, metadata, and data sizes from subsequent data blocks
on the device. In addition, the number of blocks stored on a page of flash is not fixed, but
instead is determined by the number of bytes consumed by the initial (block 0) and
subsequent data blocks. See the BCH programming reference manual for more information
on setting up the flash layout registers.
EXAMPLE
HW_BCH_FLASH0LAYOUT0_WR(0x020C8000);
HW_BCH_FLASH0LAYOUT1_WR(0x04408200);
Address: HW_BCH_FLASH0LAYOUT0 – 8000_A000h base + 80h offset = 8000_A080h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
NBLOCKS META_SIZE ECC0 DATA0_SIZE
W
Re- 0 0 0 0 0 1 1 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
set
HW_BCH_FLASH0LAYOUT0 field descriptions

Field Description
31–24 Number of subsequent blocks on the flash page (excluding the data0 block). A value of 0 indicates that only
NBLOCKS the DATA0 block is present and a value of 8 indicates that 8 subsequent blocks are present for a total of 9
blocks on the flash (including the DATA0 block). Any values from 0 to 255 are supported by the hardware.
23–16 Indicates the size of the metadata (in bytes) to be stored on a flash page. The BCH design support from 0
META_SIZE to 255 bytes for metadata -- if set to zero, no metadata will be stored. Metadata is stored before the associated
data in block 0. If the DATA0_SIZE field is programmed to a zero, then metadata effectively be stored with
its own parity. When both the metadata and data0 fields are programmed with non-zero values, the first
block will contain both portions of data and will be covered by a single parity block.
15–12 Indicates the ECC level for the first block on the flash page. The first block covers metadata plus the
ECC0 associated data from the DATA0_SIZE field.
0x0 NONE — No ECC to be performed

HW_BCH_FLASH0LAYOUT0 field descriptions (continued)

Field Description
0x1 ECC2 — ECC 2 to be performed

0xA ECC20 — ECC 20 to be performed
11–0 Indicates the size of the data 0 block (in bytes) to be stored on the flash page. The data size MUST be a
DATA0_SIZE multiple of four bytes. If set to zero, the first block will only contain metadata.

the format for the device selecting layout 0 in the LAYOUTSELECT register.
EXAMPLE
Address: HW_BCH_FLASH0LAYOUT1 – 8000_A000h base + 90h offset = 8000_A090h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PAGE_SIZE ECCN DATAN_SIZE
W
Re- 0 0 0 1 0 0 0 0 1 1 0 1 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
set

Field Description
31–16 Indicates the total size of the flash page (in bytes). This should be set to the page size including spare area.
PAGE_SIZE The page size is programmable to accomodate different flash configurations that may be available in the
future.
15–12 Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n). Subsequent blocks only
ECCN contain data (no metadata).


Field Description

11–0 Indicates the size of the subsequent data blocks (in bytes) to be stored on the flash page. The data size
DATAN_SIZE MUST be a multiple of four bytes. The size of subsequent data blocks does not have to match the data size
for block 0, which is important when metadata is stored separately or for balancing the amount of data stored
in each block.

EXAMPLE

Address: HW_BCH_FLASH1LAYOUT0 – 8000_A000h base + A0h offset = 8000_A0A0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Re- 0 0 0 0 0 1 1 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
set

Field Description

EXAMPLE

Address: HW_BCH_FLASH1LAYOUT1 – 8000_A000h base + B0h offset = 8000_A0B0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Re- 0 0 0 1 0 0 0 0 1 1 0 1 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
set

Field Description
future.
in each block.


EXAMPLE
Address: HW_BCH_FLASH2LAYOUT0 – 8000_A000h base + C0h offset = 8000_A0C0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Re- 0 0 0 0 0 1 1 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
set

Field Description


EXAMPLE
Address: HW_BCH_FLASH2LAYOUT1 – 8000_A000h base + D0h offset = 8000_A0D0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Re- 0 0 0 1 0 0 0 0 1 1 0 1 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
set

Field Description
future.
in each block.


EXAMPLE
Address: HW_BCH_FLASH3LAYOUT0 – 8000_A000h base + E0h offset = 8000_A0E0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Re- 0 0 0 0 0 1 1 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
set

Field Description


Field Description


EXAMPLE
Address: HW_BCH_FLASH3LAYOUT1 – 8000_A000h base + F0h offset = 8000_A0F0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Re- 0 0 0 1 0 0 0 0 1 1 0 1 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
set

Field Description
future.


Field Description

in each block.
16.6.16 Hardware BCH ECC Debug Register0 (HW_BCH_DEBUG0)

The hardware BCH accelerator internal state machines and signals can be seen in the ECC
debug register.
HW_BCH_DEBUG0: 0x100
HW_BCH_DEBUG0_SET: 0x104
HW_BCH_DEBUG0_CLR: 0x108
HW_BCH_DEBUG0_TOG: 0x10C
The HW_BCH_DEBUG0 register provides access to various internal state information
which might prove useful during hardware debug and validation.
EXAMPLE
// perform BIST operation

HW_BCH_DEBUG0_SET(BM_BCH_DEBUG0_ROM_BIST_ENABLE); // enable BIST operation
// poll until BIST_DONE

while( (HW_BCH_DEBUG0_RD() & BM_BCH_DEBUG0_ROM_BIST_COMPLETE) == 0 );
i=HW_BCH_DBGKESREAD();
if(HW_BCH_DBGKESREAD_RD() != 0x7AA3792F) {
// BIST FAILED
err++;
}
HW_BCH_DEBUG0_CLR(BM_BCH_DEBUG0_ROM_BIST_ENABLE | BM_BCH_DEBUG0_ROM_BIST_COMPLETE); // clear
bist status

Address: HW_BCH_DEBUG0 – 8000_A000h base + 100h offset = 8000_A100h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ROM_BIST_
R RSVD1
ROM_BIST_
COMPLETE
ENABLE
KES_DEBUG_SYNDROME_SYMBOL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KES_STANDALONE
BM_KES_TEST_
PAYLOAD_FLAG
KES_DEBUG_
KES_DEBUG_
KES_DEBUG_
KES_DEBUG_
KES_DEBUG_
KES_DEBUG_
SHIFT_SYND
R RSVD0
MODE4K
BYPASS
STALL
STEP
KICK
DEBUG_REG_SELECT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_BCH_DEBUG0 field descriptions

Field Description
RSVD1
26 Software may initiate a ROM BIST operation by toggling this bit from a zero to a one. When the operation
ROM_BIST_ is complete, the ROM_BIST_COMPLETE bit will be set and the ROM's CRC value will be available in the
ENABLE DEBUG data register.
25 This bit will be set after a BIST operation completes, at which time the ROM CRC is available in the
ROM_BIST_ DBGKESREAD register. The CRC value will be cleared after the BIST_ENABLE bit is cleared.
COMPLETE
24–16 The 9 bit value in this bit field will be shifted into the syndrome register array at the input of the KES engine
KES_DEBUG_ whenever HW_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled.
SYNDROME_
0x0 NORMAL — Bus master address generator for synd_gen writes operates normally.
SYMBOL
0x1 TEST_MODE — Bus master address generator always addresses last four bytes in Auxilliary block.
15 Toggling this bit causes the value in HW_BCH_DEBUG0_KES_SYNDROME_SYMBOL to be shift into the
KES_DEBUG_ syndrome register array at the input to the KES engine. After shifting in 16 symbols, one can kick off both
SHIFT_SYND KES and CF cycles by toggling HW_BCH_DEBUG0_KES_DEBUG_KICK. Be sure to set
KES_BCH_DEBUG0_KES_STANDALONE mode to 1 before kicking.
14 When running the stand alone debug mode on the error calculator, the state of this bit is presented to the
KES_DEBUG_ KES engine as the input payload flag.
PAYLOAD_FLAG
0x1 DATA — Payload is set for 512 byte data block.
0x1 AUX — Payload is set for 65 or 19 byte auxilliary block.
13 When running the stand alone debug mode on the error calculator, the state of this bit is presented to the
KES_DEBUG_ KES engine as the input mode (4K or 2K pages).
MODE4K
0x1 4k — Mode is set for 4K NAND pages.
0x1 2k — Mode is set for 2K NAND pages.

HW_BCH_DEBUG0 field descriptions (continued)

Field Description
12 Toggling causes KES engine FSM to start as if kick by the Bus Master. This allows stand alone testing of
KES_DEBUG_ the KES and Chien Search engines. Be sure to set KES_BCH_DEBUG0_KES_STANDALONE mode to 1
KICK before kicking.
11 Set to one to cause the KES engine to suppress toggling the KES_BM_DONE signal to the bus master and
KES_ to suppress toggling the CF_BM_DONE signal by the CF engine.
STANDALONE
10 Toggling this bit causes the KES FSM to skip passed the stall state if it is in DEBUG_STALL mode and it
KES_DEBUG_ has completed processing a block.
STEP
9 Set to one to cause KES FSM to stall after notifying Chien search engine to start processing its block but
KES_DEBUG_ before notifying the bus master that the KES computation is complete. This allows a diagnostic to stall the
STALL FSM after each blocks key equations are solved. This also has the effect of stalling the CSFE search engine
so it's state can be examined after it finishes processing the KES stalled block.
0x0 NORMAL — KES FSM proceeds to next block supplied by bus master.
0x1 WAIT — KES FSM waits after current equations are solved and the search engine is started.
8 1 = Point all synd_gen writes to dummy area at the end of the AUXILLIARY block so that diagnostics can
BM_KES_TEST_ preload all payload, parity bytes and computed syndrome bytes for test the KES engine.
BYPASS
RSVD0
5–0 The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien
DEBUG_REG_ search engine.
SELECT
16.6.17 KES Debug Read Register (HW_BCH_DBGKESREAD)

The hardware BCH ECC accelerator key equation solver internal state machines and signals
can be seen in the ECC debug registers.
EXAMPLE
Address: HW_BCH_DBGKESREAD – 8000_A000h base + 110h offset = 8000_A110h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VALUES
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

HW_BCH_DBGKESREAD field descriptions

Field Description
31–0 This register will return the ROM BIST CRC value after a BIST test.
VALUES
16.6.18 Chien Search Debug Read Register (HW_BCH_DBGCSFEREAD)

The hardware BCH ECC accelerator Chien Search internal state machines and signals can
be seen in the ECC debug registers.
EXAMPLE
Address: HW_BCH_DBGCSFEREAD – 8000_A000h base + 120h offset = 8000_A120h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VALUES
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_BCH_DBGCSFEREAD field descriptions

Field Description
31–0 Reserved
VALUES
16.6.19 Syndrome Generator Debug Read Register

(HW_BCH_DBGSYNDGENREAD)
The hardware BCH ECC accelerator syndrome generator internal state machines and signals
can be seen in the ECC debug registers.
EXAMPLE
Address: HW_BCH_DBGSYNDGENREAD – 8000_A000h base + 130h offset = 8000_A130h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VALUES
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

HW_BCH_DBGSYNDGENREAD field descriptions

Field Description
31–0 Reserved
VALUES
16.6.20 Bus Master and ECC Controller Debug Read Register

(HW_BCH_DBGAHBMREAD)
The hardware BCH ECC accelerator bus master and ecc controller internal state machines
and signals can be seen in the ECC debug registers.
EXAMPLE
Address: HW_BCH_DBGAHBMREAD – 8000_A000h base + 140h offset = 8000_A140h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VALUES
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_BCH_DBGAHBMREAD field descriptions

Field Description
31–0 Reserved
VALUES
16.6.21 Block Name Register (HW_BCH_BLOCKNAME)

Read only view of the block name string BCH.
Fixed pattern read only value for test puposes. Can be read as an ASCII string with the zero
termination coming from the first byte of the BLOCKVERSION register.
EXAMPLE
char *cp = ((char *)HW_BCH_BLOCKNAME_ADDR); reads back "BCH ".

Address: HW_BCH_BLOCKNAME – 8000_A000h base + 150h offset = 8000_A150h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R NAME
W
Re- 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 1 0 0 0 0 1 0
set
HW_BCH_BLOCKNAME field descriptions

Field Description
31–0 Should be the ASCII characters BCH (0x20, H, C, B).
NAME
16.6.22 BCH Version Register (HW_BCH_VERSION)

of the block.
EXAMPLE
if (HW_BCH_VERSION.B.MAJOR != 1) Error();
Address: HW_BCH_VERSION – 8000_A000h base + 160h offset = 8000_A160h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MAJOR MINOR STEP

W
Re- 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_BCH_VERSION field descriptions

Field Description
MAJOR
MINOR
STEP

Chapter 17
Synchronous Serial Ports (SSP)
17.1 Overview
The Synchronous Serial Port is a host controller which provides a flexible interface for
inter-IC and removable media control and communication. The SSP supports MMC/SD/SDIO
1-bit, 4-bit, and 8-bit modes; SPI master and slave modes; and Texas Instruments SSI mode.
The SSP is fully compliant with the eMMC 4.4 standard. Specifically, it supports Power-on
and alternate boot mode and is designed to perform both SDR and DDR operations at the
maxinum speed of 52 MHz. In SPI mode, the SSP has enhancements to support 1-bit legacy
MMC cards, and SPI master dual (2-bit) and quad (4-bit) read modes are also supported.
The SSP has a dedicated DMA channel in the bridge and can also be controlled directly by
the CPU through PIO registers.Figure 17-1 illustrates one of the four SSP ports included
on the i.MX28. Each SSP is independent of the other and can have separate SSPCLK
frequencies.
Figure 17-1. Synchronous Serial Port Block Diagram

Overview
ARM Core SRAM
System Clock
Generator
AHB
AHB Slave AHB Master AHB-to-APBH Bridge
DMA Controller
DMA Request
SSPCLK
HCLK
APBH Master
APBH
SPI TI SSI 8-Bit SD/SDIO/MMC

Modes
Synchronous Serial Port
GPIO
SSP/GPIO Pin
MUX
Pins

Chapter 17 Synchronous Serial Ports (SSP)
17.2 External Pins

#id-54331/id-33763 lists the SSP pin placements for all supported modes.
Table 17-1. SSP Pin Matrix
MOTOROLASPI WinBONDSPI
Pin Name TI SSIMode SD/SDIO/MMC/ Modes
Mode Mode
SSP_SCK SCK CLK CLK CLK
SSP_CMD MOSI DI (IO0) MOSI CMD
SSP_DATA0 MISO DO (IO1) MISO DATA0
SSP_DATA1 WPn (IO2) DATA1/IRQ
SSP_DATA2 HOLDn (IO3) DATA2
SSP_DATA3 SSn0 SSn0 SSn DATA3
SSP_DATA4 SSn1 SSn1 DATA4
SSP_DATA5 SSn2 SSn2 DATA5
SSP_DATA6 DATA6
SSP_DATA7 DATA7
SSP_DETECT CARD_DETECT
The pin control interface on the i.MX28 provides all digital pins with selectable output drive
strengths. In addition, all SSP data pins have selectable 47-KΩ pullup resistors, and SSP
command pins have 10-KΩ pullups. Configuring the SSP_CMD pad to connect to the
internal 10-KΩ pullup is recommended for SD/SDIO/MMC modes during the Card_ID
phase. After the Card_ID phase, the 10-KΩ pullup should be disabled, and the weaker
external 47-KΩ pullup takes over. The SSP_DATA pads also can be configured to connect
to an internal 47-KΩ pullup, which is required for SD/SDIO/MMC modes.
17.3 Bit Rate Generation

The serial bit rate is derived by dividing down the internal clock SSPCLK. The clock is
first divided by an even prescale value, CLOCK_DIVIDE, from 2 to 254, which is
programmed in HW_SSP_TIMING. The clock is further divided by a value from 1 to 256,
which is 1 + CLOCK_RATE, where CLOCK_RATE is the value programmed in
HW_SSP_TIMING.

Frame Format for SPI and SSI
The frequency of the output signal bit clock SSP_SCK is defined as follows:
SSPCLK
SSP _ SCK = CLOCK DIVIDE × (1 + CLOCK _ RATE)
For example, if SSPCLK is 3.6864 MHz, and CLOCK_DIVIDE = 2, then SSP_SCK has
a frequency range from 7.2 KHz to 1.8432 MHz. See Clock Generation and Control
(CLKCTRL) Overview for more clock details.
17.4 Frame Format for SPI and SSI

Each data frame is between 4 and 16 bits long, depending on the size of data programmed,
and is transmitted starting with the MSB. Two basic frame types can be selected:
• Motorola SPI
• Texas Instruments Synchronous Serial Interface (SSI)
For both formats, the serial clock (SSP_SCK) is held inactive while the SSP is idle and
transitions at the programmed frequency only during active transmissions or reception of
data. The idle state of SSP_SCK is used to provide a receive time-out indication, which
occurs when FIFO still contains data after a time-out period.
For Motorola SPI frame format, the serial frame (SSn) pin is active low and is asserted
(pulled down) during the entire transmission of the frame.
For Texas Instruments synchronous serial interface (SSI) frame format, the SSn pin is pulsed
for one serial clock period starting at its rising edge, prior to the transmission of each frame.
For this frame format, both the SSP and the off-chip slave device drive their output on data
on the rising edge of SSP_SCK, and latch data from the other device on the falling edge.
The SSP master supports up to three combinations of SPI and SSI slave devices connected.
Three SSn pins are provided but only one can be active at a time.
17.5 Motorola SPI Mode

The SPI mode is used for general inter-component communication and legacy 1-bit MMC
cards.

17.5.1 SPI DMA Mode

The SPI bus is inherently a full-duplex bidirectional interface. However, as most applications
only require half-duplex data transmission, the i.MX28 has a single DMA channel for the
SSP. It can be configured for either transmit or receive. In DMA receive mode, the SPI
continuously repeats the word written to its data register. In DMA transmit mode, the SPI
ignores the incoming data.
17.5.2 Motorola SPI Frame Format

The Motorola SPI interface is a four-wire interface where the SSn signal behaves as a slave
select. The main feature of the Motorola SPI format is that the inactive state and phase of
SSP_SCK signal are programmable through the polarity and phase bits within the
HW_SSP_CTRL1.
17.5.2.1 Clock Polarity

• When the clock polarity control bit is low, it produces a steady-state low value on the
SSP_SCK pin.
• When the clock polarity control bit is high, a steady-state high value is placed on the
SSP_SCK pin when data is not being transferred.
17.5.2.2 Clock Phase

The phase control bit selects the clock edge that captures data and allows it to change state.
It has the most impact on the first bit transmitted, by either allowing or not allowing a clock
transition before the first data-capture edge.
• When the phase control bit is low, data is captured on the first clock-edge transition.
• When the clock phase control bit is high, data is captured on the second clock-edge
transition.
17.5.3 Motorola SPI Format with Polarity=0, Phase=0

Single and continuous transmission signal sequences for Motorola SPI format with
POLARITY=0, PHASE=0 are shown in Figure 17-2 and Figure 17-3.

Motorola SPI Mode
SSP_SCK
SSn
MISO MSB LSB Q

4 to 16 bits
MSB LSB
MOSI
Figure 17-2. Motorola SPI Frame Format (Single Transfer) with POLARITY=0 and PHASE=0
SSP_SCK
SSn
MOSI/MISO LSB MSB LSB MSB
4 to 16 bits
Figure 17-3. Motorola SPI Frame Format with POLARITY=0 and PHASE=0
In this configuration, during idle periods:

• The SSP_SCK signal is forced low.
• SSn is forced high.
• The Transmit data line MOSI is arbitrarily forced low.
• When the SSP is configured as a master, SSP_SCK is an output.
• When the SSP is configured as a slave, SSP_SCK is an input.
If the SSP is enabled and there is valid data within the FIFO, the start of the transmission
is signified by the SSn master signal being low. This causes slave data to be enabled onto
the MISO input line of the master, and enables the master MOSI output pad.
One-half SSP_SCK period later, valid master data is transferred to the MOSI pin. Now that
both the master and slave data have been set, the SSP_SCK master clock pin goes high after
one further half SSP_SCK period.
The data is now captured on the rising and propagated on the falling edges of the SSP_SCK
signal.
In the case of a single word transmission, after all bits of the data word have been transferred,
the SSn line is returned to its idle high state one SSP_SCK period after the last bit has been
captured.
However, in the case of continuous back-to-back transmissions, the SSn signal must be
pulsed high between each data word transfer. This is because the slave select pin freezes
the data in its serial peripheral register and does not allow it to be altered if the PHASE bit
is logic 0. Therefore, the master device must raise the SSn pin of the slave device between

each data transfer to enable the serial peripheral data write. On completion of the continuous
transfer, the SSn pin is returned to its idle state one SSP_SCK period after the last bit has
been captured.

The transfer signal sequence for Motorola SPI format with POLARITY=0 and PHASE=1
is shown in Figure 17-4, which covers both single and continuous transfers.
SSP_SCK
SSn
MISO Q MSB LSB Q

4 to 16 bits
MOSI MSB LSB
Figure 17-4. Motorola SPI Frame Format (Continuous Transfer) with POLARITY=0 and
PHASE=1

• The SSP_SCK signal is forced low.
• When the SSP is configured as a master, the SSP_SCK pad is an output.
• When the SSP is configured as a slave, the SSP_SCK is an input.
If the SSP is enabled and there is valid data within the FIFO, the start of the transmission
is signified by the SSn master signal being low. After a further one-half SSP_SCK period,
both master and slave valid data are enabled with a rising-edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the SSP_SCK
signal.
In the case of a single word transfer, after all bits have been transferred, the SSn line is
returned to its idle high state one SSP_SCK period after the last bit has been captured.
For continuous back-to-back transfers, SSPFSOUT (the SSn pin in master mode) is held
low between successive data words and termination is the same as that of a single word
transfer.

Motorola SPI Mode

Single and continuous transmission signal sequences for Motorola SPI format with
POLARITY=1 and PHASE=0 are shown in Figure 17-5 and Figure 17-6.
SSP_SCK
SSn
MISO MSB LSB Q

4 to 16 bits
MSB LSB
MOSI
Figure 17-5. Motorola SPI Frame Format (Single Transfer) with POLARITY=1 and PHASE=0
Note
In Figure 17-5, Q is an undefined signal.
SSP_SCK
SSn
MOSI/MISO LSB MSB LSB MSB
4 to 16 bits
Figure 17-6. Motorola SPI Frame Format (Continuous Transfer) with POLARITY=1 and
PHASE=0

• The SSP_SCK signal is forced high.
If the SSP is enabled and there is valid data within the FIFO, the start of transmission is
signified by the SSn master signal being driven low, which causes slave data to be
immediately transferred onto the MISO line of the master, and enabling the master MOSI
output pad.

One half-period later, valid master data is transferred to the MOSI line. Now that both
master and slave data have been set, the SSP_SCK master clock pin becomes low after one
further half SSP_SCK period. This means that data is captured on the falling edges and
propagated on the rising edges of the SSP_SCK signal.
In the case of a single word transmission, after all bits of the data word are transferred, the
SSn line is returned to its idle high state one SSP_SCK period after the last bit has been
captured.
However, in the case of continuous back-to-back transmissions, the SSn signal must be
pulsed high between each data word transfer. This is because the slave select pin freezes
the data in its serial peripheral register and does not allow it to be altered if the PHASE bit
is logic 0. Therefore, the master device must raise SSPSFSSIN (the SSn pin in slave mode)
of the slave device between each data transfer to enable the serial peripheral data write. On
completion of the continuous transfer, the SSn pin is returned to its idle state one SSP_SCK
period after the last bit has been captured.

The transfer signal sequence for Motorola SPI format with POLARITY=1 and PHASE=1
is shown in Figure 17-7, which covers both single and continuous transfers.
SSP_SCK
SSn
MISO Q MSB LSB Q

4 to 16 bits
MSB LSB
MOSI
Figure 17-7. Motorola SPI Frame Format with POLARITY=1 and PHASE=1
Note
In Figure 17-7, Q is an undefined signal.
• The SSP_SCK signal is forced high.

Winbond SPI Mode
If the SSP is enabled and there is valid data within the FIFO, the start of transmission is
signified by the SSn master signal being driven low, and MOSI output is enabled. After a
further one-half SSP_SCK period, both master and slave are enabled onto their respective
transmission lines. At the same time, the SSP_SCK is enabled with a falling edge transition.
Data is then captured on the rising edge and propagated on the falling edges of the SSP_SCK
signal.
After all bits have been transferred, in the case of a single word transmission, the SSn line
is returned to its idle high state one SSP_SCK period after the last bit has been captured.
For continuous back-to-back transmissions, the SSn pin remains in its active low state, until
the final bit of the last word has been captured, and then returns to its idle state as described
above.
For continuous back-to-back transfers, the SSn pin is held low between successive data
words and termination is same as that of a single word transfer.
17.6 Winbond SPI Mode

The Winbond SPI mode is similar to Motorola's SPI mode when POLARITY = PHASE,
where data is sampled on the rising edge. In addition to serial 1-bit reads and writes, 2-bit
(dual) and 4-bit (quad) reads are supported. Only 8-bit word length is supported for dual
and quad read modes. See Figure 17-8. The numbers in the IO signal waveform correspond
to the bit position in the byte being transferred.
CLK
CLK
IO0 SwitchesfromInput to Out
IO0 Switches from Input to Output
IO0 4 0 4 0 4 0 4 0
IO0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
IO1 5 1 5 1 5 1 5 1
IO1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1
* Data Out 2
* Data Out 3 Data Out 4
Data Out 1
IO2 6 2 6 2 6 2 6 2
IO3 7 3 7 3 7 3 7 3
Byte 1 Byte 2 Byte 3 Byte 4
Figure 17-8. Fast Read Dual and Quad Output Diagram
17.7 Texas Instruments Synchronous Serial Interface (SSI)

Mode
Figure 17-9 shows the Texas Instruments synchronous serial frame format for a single
transmitted frame.

SSP_SCK
SSn
MOSI/MISO MSB LSB
4 to 16 bits
Figure 17-9. Texas Instruments Synchronous Serial Frame Format (Single Transfer)
In this mode, SSP_SCK and SSn are forced low, and the transmit data line MOSI is
three-stated whenever the SSP is idle. Once the bottom entry of the FIFO contains data,
SSn is pulsed high for one SSP_SCK period. The value to be transmitted is also transferred
from the FIFO to the serial shift register of the transmit logic. On the next rising edge of
SSP_SCK, the MSB of the 4-to-16-bit data frame is shifted out on the SSPRXD pin by the
off-chip serial slave device.
Both the SSP and the off-chip serial slave device then clock each data bit into their serial
shifter on the falling edge of each SSP_SCK. The received data is transferred from the serial
shifter to the FIFO on the first rising edge of SSP_SCK after the LSB has been latched.
Figure 17-10 shows the Texas Instrument synchronous serial frame format when back-to-back
frames are transmitted.
SSP_SCK
SSn
MSB LSB
MOSI/MISO
4 to 16 bits
Figure 17-10. Texas Instruments Synchronous Serial Frame Format (Continuous Transfer)
17.8 SD/SDIO/MMC Mode

This mode is used to provide high performance with SD, SDIO, MMC, and high-speed
(4-bit and 8-bit) MMC cards. When running 4-bit and 8-bit modes, the SSP has the capability
of SDR and DDR operations. Power-on and alternate boot operations are also supported.
SD/MMC mode supports simultaneous command and data transfers. Commands are sent
to the card and responses are returned to the host on the CMD line. Register data, such as
card information, is sent as a command response and is therefore on the CMD line. Block
data read from or written to the card's flash is transferred on the DAT line(s). The SSP also
supports the SDIO IRQ.

SD/SDIO/MMC Mode
The SSP's SD/MMC controller can automatically perform a single block read/write or card
register operation with a single PIO setup and RUN. For example, the SD/MMC controller
can perform these steps with a single write to the PIO registers:
• Send command to the card.
• Receive response from the card.
• Check response for errors (and assert a CPU IRQ if there is an error).
• Wait for the DAT line(s) to be ready to transfer data (while counting for time-out).
• Transfer multiple blocks of data to/from the card.
• Check the CRC or CRC status of received/sent data (and assert IRQ if there is an error).
The SD/MMC controller is generally used with the DMA. Each DMA descriptor is set up
the SD/MMC controller to perform a single complex operation as exemplified above.
Multiple DMA descriptors can be chained to perform multiple card block transfers without
CPU intervention. A single DMA descriptor can also perform multiple card block transfers.
17.8.1 SD/MMC Command/Response Transfer

SD/MMC commands are written to the HW_SSP_CMDn registers and sent on the CMD
line. Command tokens consist of a start bit (0), a source bit (1), the actual command, which
is padded to 38 bits, a 7-bit CRC and a stop bit (1). The command token format is shown
in Table 17-2.
Table 17-2. SD/MMC Command/Response Transfer
Line Start Source Data CRC End
CMD 0 1 (Host) 38-bit Command CRC7 1
SD/MMC cards transmit command words with the most significant bit first. After the card
receives the command, it checks for CRC errors or invalid commands. If an error occurs,
the card withholds the usual response to the command.
After transmitting the end bit, the SSP releases the CMD line to the high-impedance state.
A pullup resistor on the CMD node keeps it at the 1 state until the response packet is received.
The slave waits to issue a reply until the SCK line is clocking again.
After the SSP sends an SD/MMC command, it optionally starts looking for a response from
the card. It waits for the CMD line to go low, indicating the start of the response token.
Once the SSP has received the Start and Source bits, it begins shifting the response content
into the receive shift register. The SSP calculates the CRC7 of the incoming data.
If the card fails to start sending an expected response packet within 64 SCK cycles, then an
error occurrs; the command may be invalid or have a bad CRC. After the SSP detects a
time-out, it stops any DMA request activity and sets the RESP_TIMEOUT flag. If
RESP_TIMEOUT_IRQ_EN is set, then a CPU IRQ is asserted.
The SSP calculates the CRC of the received response and compares it to the CRC received
from the card. If they do not match, then the SSP sets the RESP_ERR status flag. If
RESP_ERR_IRQ_EN is set, then a CPU IRQ is asserted on a command response CRC
mismatch.
The SSP can also compare the 32-bit card status word, known as response R1, against a
reference to check for errors. If CHECK_RESP in HW_SSP_CTRL0 is set, then the SSP
XORs the response with the XOR field in the HW_SSP_COMPREF register. It then masks
the results with the MASK field in the HW_SSP_COMPMASK register. If there are any
differences between the masked response and the reference, then an error will occur. The
CPU asserts the RESP_ERR status flag. If RESP_ERR_IRQ_EN is set, then the
RESP_ERR_IRQ is asserted. In the ISR, the CPU can read the status word to see which
error flags are set.
The regular and long response tokens are shown in Table 17-3 and Table 17-4:
Table 17-3. SD/MMC Command Regular Response Token
CMD 0 0 (Card) 38-bit Response CRC7 1
Table 17-4. SD/MMC Command Regular Long Response Token

CMD 0 0 (Card) 117-bit response CRC16 1
17.8.2 SD/MMC Data Block Transfer

Block data is transferred on the DATA0 pin. In 1-bit I/O mode, the block data is formatted
as shown in Table 17-5. Block data transfers typically have 512 bytes of payload, plus a
16-bit CRC, a Start bit, and an End bit. The block size is programmable with the
XFER_COUNT field in the HW_SSP_XFER_SIZE register. In SD/MMC mode,
WORD_LENGTH in the HW_SSP_CTRL1 register field should always be set to 8 bits.
Data is always sent Most Significant Bit of the Least Significant Byte first.
The SSP is designed to support block transfer modes only. Streaming modes may not be
supported. Figure 17-11 shows a flowchart of SD/MMC block read and write transfers.

SD/SDIO/MMC Mode
In block write mode, the card holds the DATA0 line low while it is busy. SSP must wait
for the DATA0 line to be high for one clock cycle before starting to write to a block.
In block read mode, the card begins sending the data when it is ready. The first bit transmitted
by the card is a Start bit 0. Prior to the 0 Start Bit, the DATA0 bus is high. After the Start
bit is received, data is shifted in. The SSP bus width is set using the BUS_WIDTH bit in
the HW_SSP_CTRL0 register.
In 1-bit bus mode, the block data is formatted as shown in Table 17-5.
Table 17-5. SD/MMC Data Block Transfer 1-Bit Bus Mode
Line Start Data Data Data CRC End
DATA0 0 Data Bit 7 Byte 0 ... Data Bit 0 Byte 511 CRC16 1
In 4-bit I/O mode, the block data is formatted as shown in Table 17-6.
In 8-bit bus mode, the block data is formatted as shown in Table 17-7.
DATA2 0 Data Bit 2Byte 0 ... Data Bit 2 Byte 511 CRC16 1

17.8.2.1 SD/MMC Multiple Block Transfers

The SSP supports SD/MMC multiple block transfers. The CPU or DMA will configure the
SD/MMC controller to issue a Multi-Block Read or Write command. If DMA is used, then
the first descriptor issues the multi-block read/write command and receives/sends the first
block (512 bytes) of data. Subsequent DMA descriptors only receive/send blocks of data
and do not issue new SD/MMC commands. If the card is configured for an open-ended
multi-block transfer, then the last DMA descriptor needs to issue a STOP command to the
card. Multiple blocks can also be transferred with a single DMA descriptor.
After each block of data has been transferred, the SSP sends/receives the CRC and checks
the CRC or the CRC token. If the CRC is correct, then the SSP signals the DMA that it is
completed.
The SSP supports transferring multiple SD/MMC blocks per DMA descriptor. The SSP
state machine needs to know the number of blocks and the size of a block. When
HW_SSP_BLOCK_SIZE_BLOCK_COUNT is non-zero, the actual block size is:
0x1 shiftleft BLOCK_SIZE
For example, setting a value of 9 will result in a block size of 512 bytes. When
BLOCK_COUNT is 0, BLOCK_SIZE is ignored and the bit field
HW_SSP_XFER_SIZE_XFER_COUNT represents the single block size or the number of
byte to transfer. This must satisfy the equation:
HW_SSP_XFER_SIZE_XFER_COUNT = (0x1 shiftleft BLOCK_SIZE) x
(BLOCK_COUNT+1)
for BLOCK_COUNT greater than 0.
17.8.2.2 eMMC DDR operation

When performing a single block or multiple block transfer, the SSP has an option of using
DDR operation by setting DBL_DATA_RATE_EN bit in HW_SSP_CMD0 register. When
performing a DDR operation, the timing relationship between SCK and DATA can be
programmed to suit different needs. The highly recommended settings are in the following
(but not necessary):

SD/SDIO/MMC Mode
• To set TXCLK_DELAY_TYPE of HW_SSP_DDR_CTRL register allows SCK to

have a 1/4 SCK delay and to switch approximately at the center of each TX DATA
period.
• Turn on the DLL by setting ENABLE bit of HW_SSP_DLL_CTRL registerr. This
generates a precisive clock delay relative to SCK (input version), which is used to
sample RX DATA. Program the value of 4'd7 to DLV_DLY_TARGET field of
HW_SSP_DLL_CTRL register, and this specifies the clock delay to be 1/4 of SCK
period.
To boost the performance of SSP running in DDR mode and at the maximum frequency,
the DMA interface allows a burst of 4 or 8 32-bit APB transfers per DMA request.
17.8.2.3 SD/MMC Block Transfer CRC Protection

The block of data transferred over the data bus is protected by CRC16. For reads, the SSP
calculates the CRC of the incoming data and compares it to the CRC16 reference that is
provided by the card at the end of the block. In DDR mode, two sets of CRC16s are
calculated for both the rising edge sampled data and the falling edge sampled data. If any
CRC mismatch occurs, then the block asserts the DATA_CRC_ERR status flag. If
DATA_CRC_IRQ_EN is set, then a CPU IRQ is asserted.
For block write operations, the card determines if a CRC error has occurred. After the SSP
has sent a block of data, it transmits the reference CRC16. In DDR mode, two sets of
reference CRC16s are transmitted. The card compares that(those) to its calculated CRC16(s).
The card then sends a CRC status token on the DATA bus. It sends a positive status ('010')
if the transfer was good, and a negative status ('101') if the CRC16(s) did not match. If the
SSP receives a CRC bad token, it sets the DATA_CRC_ERROR in the HW_SSP_STATUS
register, and then it indicates it to the CPU if DATA_CRC_IRQ_EN is set.
17.8.3 eMMC Boot Operation

In boot operation mode, the SSP can read boot data from the slave (MMC device) by keeping
SSP_CMD line low using PRIM_BOOT_OP_EN bit, or sending CMD0 with argument =
0xFFFFFFFA, before issuing CMD1. User can terminate the boot operation by setting
SOFT_TERMINATE bit in HW_SSP_CMD0 register when using primary boot method,
or send a CMD0 command when using the alternate boot method. Boot acknowledge is
also supported by setting BOOT_ACK_EN bit in HW_SSP_CMD0 register. The boot mode
supports DDR operations as specified in eMMC 4.4 standard.

17.8.4 SDIO Interrupts

The SSP supports SDIO interrupts. When the SSP is in SD/MMC mode and the SDIO_IRQ
bit in the HW_SSP_CTRL0 register is set, the SSP looks for interrupts on DATA1 during
the valid IRQ periods. The valid IRQ periods are defined in the SDIO specification. If the
card asserts an interrupt and SDIO_IRQ_EN is set, then the SSP sets the SDIO_IRQ status
bit and asserts a CPU IRQ. Other than detecting when card IRQs are valid, the SDIO IRQ
function operates independently from the rest of the SSP. After the CPU receives an IRQ,
it should monitor the SSP and DMA status to determine when it should send commands to
the SDIO card to handle the interrupt.
17.8.5 SD/MMC Mode Error Handling

There are several errors that can occur during the SD/MMC operation. These errors can be
caused by normal unexpected events, such as having a card removed or unusual events such
as a card failure. The detected error cases are listed below. Please note that in all the cases
below, a CPU IRQ is only asserted if DATA_CRC_IRQ_EN is set in HW_SSP_CTRL1
register.
• Data Receive CRC Error—Detected by the SSP after a block receive. If this occurs,
the SSP will not indicate to DMA that the transfer is complete. It will set the
DATA_CRC_ERR status flag and assert a CPU IRQ. The ISR should reset the SSP
DMA channel and instruct the DMA to re-try the block read operation.
• Data Transmit CRC Error—Transmit CRC error token is received from the SD/MMC
card on the DAT line after a block transmit. If this occurs, the SSP will not indicate to
DMA that the transfer is complete. It will set the DATA_CRC_ERR status flag and
assert a CPU IRQ. The ISR should reset the SSP DMA channel and instruct the DMA
to re-try the block write operation.

SD/SDIO/MMC Mode
SD/MMC Block Read SD/MMC Block Write

Example Example
DMA PIO cycle: DMA PIO cycle:
SD/MMC mode SD/MMC mode
Read Mode Write Mode
XFER_COUNT=512 XFER_COUNT=512
Write the BLOCK_READ Write the BLOCK_WRITE
command to SDCTRLx. command to SDCTRLx.
DMA sets SSP Run bit. DMA sets SSP Run bit.
SSP sends out the MMC

SSP sends out the MMC Block Write Command and
Block Read Command begins looking at the DAT
and begins looking at the line for Busy Condition.
DAT line for a Start Bit. SSP will start issuing DMA
requests to fill the transmit
After the Block Read FIFO.
command is sent, SSP
looks at the CMD line for a After the Block Write
Response. command is sent, SSP
looks at the CMD line for a
Response.
When the response is sent When the response is sent

by the MMC card, the SSP by the MMC card, the SSP
will place the response in will place the response in
the RESP register. the RESP register.
The SSP will check the The SSP will check the
CRC7 of the response CRC7 of the response
packet against the packet against the
received CRC7. If there is received CRC7. If there is
an error, it will assert a an error, it will assert a
CPU IRQ. CPU IRQ.
When the Data is ready,

the MMC will send the When the Data line is no
start bit and the SSP will longer busy, the SSP will
put the data into the start sending data. The
receive FIFO and start transmitted data will also
asserting DMA request. have CRC16 calculated
The received data will also and transmitted after the
be checked for CRC16. If data. If the card indicates
there is a CRC error, the a CRC error, the SSP will
SSP will assert a CPU assert a CPU IRQ.
IRQ.
After the block has been After the block has been
read and the CRC sent and the CRC
checked, the SSP will checked, the SSP will
indicate to the DMA that it indicate to the DMA that it
is done. The DMA can is done. The DMA can
then issue a new then issue a new
command sequence, or command sequence or tell
tell the CPU that it is done. the CPU that it is done.
Figure 17-11. SD/MMC Block Transfer Flowchart
• Data Time-Out Error—The SSP TIMEOUT counter is used to detect a time-out

condition during data write or read operations. The time-out counts any time that the
SSP is waiting on a busy DAT bus. For read operations, the DAT line(s) indicate busy
before the card sends the start bit. For write operations, the DAT line(s) may indicate
busy after the block has been sent to the card. If the time-out counter expires before
the DAT line(s) become ready, the SSP stops any DMA requests, sets the
DATA_TIMEOUT status flag, and asserts a CPU IRQ. The ISR should check the status
register to see that a data time-out has occurred. It can then reset the DMA channel and
the SSP to re-try the operation.

• DMA Overflow/Underflow—The SSP should stop SCK if the FIFO is full or the FIFO
is empty during data transfer. So, a DMA underflow or overflow should not occur.
However, if it does due to some unforeseen problem, the FIFO_OVRFLW or
FIFO_UNDRFLW status bit is set in the SSP Status Register and asserts a CPU IRQ.
• Command Response Error—The SD/MMC card returns a R1 status response after
most commands. The SSP can compare the R1 response against a mask/reference pair.
If any of the enabled bits are set, then an error will occur. The SSP stops requesting
any DMAs, sets the RESP_ERR status flag, and asserts a CPU IRQ. The CPU can read
the SSP Status Register to see the RESP_ERR flag and read the HW_SSP_SDRESP0
register to get the actual response from the SD/MMC card. That response contains the
specific error information. Once the error is understood, the CPU can reset the DMA
channel and the SSP and re-try the operation or take some other action to recover or
inform the user of a non-recoverable error.
• Command Response Time-Out—If an expected response is not received within 64
SCK cycles, then the command response has timed out. If this occurs, the SSP stops
any DMA requests, stops transferring data to the card, sets the RESP_TIME-OUT status
flag, and asserts the RESP_TIME-OUT_IRQ. The ISR should read the status register
to find that a command response time-out has occurred. It can then decide to reset the
DMA channel and SSP and re-try the operation.
17.8.6 SD/MMC Clock Control

• When SD/MMC block is idle, the serial clock (SCK) toggling will be based on the
value of CONT_CLKING_EN and SLOW_CLKING_EN. See HW_SSP_CMD0 register
description.
• SCK runs any time that RUN is set and a data or command is active or pending. If a
command has been sent and a response is expected, then SCK continues to run until
the response is received. If a data operation is active or if the DAT line is busy, then
SCK runs.
• If CONT_CLKING_EN=0, SCK stops running if received command response status
R1 indicates an error.
• If CONT_CLKING_EN=0, SCK stops running if a data operation has timed out or a
CRC error has occurred.
• If CONT_CLKING_EN=0, SCK stops running after all pending commands and data
operations have completed. SCK restarts when a new command or data operation has
been requested.


CLKGATE bit fields.

SSP Hardware Register Format Summary
SSP0 base address is 0x80010000; SSP1 base address is 0x80012000; SSP2 base address
is 0x80014000; SSP3 base address is 0x80016000
HW_SSP memory map
Absolute
Width Section/
(in bits) page
(hex)
8001_0000 SSP Control Register 0 (HW_SSP_CTRL0) 32 R/W C000_0000h 17.10.1/1331
8001_0010 SD/MMC Command Register 0 (HW_SSP_CMD0) 32 R/W 0000_0000h 17.10.2/1333
8001_0020 SD/MMC Command Register 1 (HW_SSP_CMD1) 32 R/W 0000_0000h 17.10.3/1336
8001_0030 Transfer Count Register (HW_SSP_XFER_SIZE) 32 R/W 0000_0001h 17.10.4/1336
8001_0040 SD/MMC BLOCK SIZE and COUNT Register 32 R/W 0000_0000h 17.10.5/1337
(HW_SSP_BLOCK_SIZE)
8001_0050 SD/MMC Compare Reference (HW_SSP_COMPREF) 32 R/W 0000_0000h 17.10.6/1337
8001_0060 SD/MMC compare mask (HW_SSP_COMPMASK) 32 R/W 0000_0000h 17.10.7/1338
8001_0070 SSP Timing Register (HW_SSP_TIMING) 32 R/W 0000_0000h 17.10.8/1338
8001_0080 SSP Control Register 1 (HW_SSP_CTRL1) 32 R/W 0000_0080h 17.10.9/1339
8001_0090 SSP Data Register (HW_SSP_DATA) 32 R/W 0000_0000h 17.10.10/1342
8001_00A0 SD/MMC Card Response Register 0 (HW_SSP_SDRESP0) 32 R 0000_0000h 17.10.11/1342
8001_00B0 SD/MMC Card Response Register 1 (HW_SSP_SDRESP1) 32 R 0000_0000h 17.10.12/1342
8001_00C0 SD/MMC Card Response Register 2 (HW_SSP_SDRESP2) 32 R 0000_0000h 17.10.13/1343
8001_00D0 SD/MMC Card Response Register 3 (HW_SSP_SDRESP3) 32 R 0000_0000h 17.10.14/1343
8001_00E0 SD/MMC Double Data Rate Control Register 32 R/W 0000_0000h 17.10.15/1344
(HW_SSP_DDR_CTRL)
8001_00F0 SD/MMC DLL Control Register (HW_SSP_DLL_CTRL) 32 R 0000_0000h 17.10.16/1345
8001_0100 SSP Status Register (HW_SSP_STATUS) 32 R E000_0020h 17.10.17/1346
8001_0110 SD/MMC DLL Status Register (HW_SSP_DLL_STS) 32 R 0000_0000h 17.10.18/1348
8001_0120 SSP Debug Register (HW_SSP_DEBUG) 32 R 0000_0000h 17.10.19/1349

HW_SSP memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
8001_0130 SSP Version Register (HW_SSP_VERSION) 32 R 0400_0000h 17.10.20/1350
17.10.1 SSP Control Register 0 (HW_SSP_CTRL0)

SSP Control Register 0
HW_SSP_CTRL0: 0x000
HW_SSP_CTRL0_SET: 0x004
HW_SSP_CTRL0_CLR: 0x008
HW_SSP_CTRL0_TOG: 0x00C
This is the most frequently changed fields.
Address: HW_SSP_CTRL0 – 8001_0000h base + 0h offset = 8001_0000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LONG_RESP
WAIT_FOR_
WAIT_FOR_
DATA_XFER
SDIO_IRQ_
LOCK_CS
IGNORE_
CHECK_
CLKGATE
ENABLE
SFTRST
CHECK
READ
RESP
CMD
CRC
GET_
RUN BUS_WIDTH IRQ
RESP
W
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_SSP_CTRL0 field descriptions

Field Description
31 SSP Reset - 0: SSP is not Reset. 1: SSP Held in Reset.
SFTRST
After Reset, all registers are returned to their reset state. This will not work if the CLKGATE bit is already
set to \'1\'.
CLKGATE must be cleared to \'0\' before issuing a soft reset. Also the SSPCLK must be running for this to
work properly.
30 Gate SSP Clocks - 0: SSP Clocks not gated. 1: SSP Clocks are gated. Set this to save power while the SSP
CLKGATE is not actively being used. Configuration state is kept while the clock is gated.
29 SSP Run. 0: SSP is not running. 1: SSP is running. Automatically set during DMA operation.
RUN

HW_SSP_CTRL0 field descriptions (continued)

Field Description
28 In SD/MMC mode: SDIO IRQ: 1= Enable checking for SDIO Card IRQ.
SDIO_IRQ_
CHECK
27 In SPI mode: This affects the SSn output.
LOCK_CS
When set to 1, SSn will be asserted throughout the current command. SSn will remain asserted after the
command if IGNORE_CRC = 0.
SSn will deassert at the end of the next command that has IGNORE_CRC = 1.
In SD/MMC mode:
0= Look for a CRC status token from the card on DATA0 after a block write.
1= Ignore the CRC status response on DATA0 after a write operation.
Note that the SD/MMC function should be used when performing MMC BUSTEST_W operation.
26 Ignore CRC - In SD/MMC.

IGNORE_CRC
In SPI/SSI modes: When set to 1, deassert the chip select (SSn) pin after the command is executed.
25 Read Mode - When this and DATA_XFER are set, the SSP will read data from the device. If this is not set,
READ then the SSP will write data to the device.
24 Data Transfer Mode - When set, transfer XFER_COUNT bytes of data. When not set, the SSP will not
DATA_XFER transfer any data (command or Wait for IRQ only).
23–22 Data Bus Width - SD/MMC modes supports all widths, SSI mode supports only 1-bit bus width.
BUS_WIDTH
In SPI mode 1, 2, and 4-bit bus widths are supported. In SPI mode the Data Bus Width field is redefined: 0
means 1-bit; 1 means 2-bit; 2 means 4-bit.
0x0 ONE_BIT — SD/MMC data bus is 1-bit wide
0x1 FOUR_BIT — SD/MMC data bus is 4-bits wide
0x2 EIGHT_BIT — SD/MMC data bus is 8-bits wide
21 Wait for IRQ
WAIT_FOR_IRQ
In SD/MMC mode this signal means wait for MMC ready before sending command. (MMC is busy when
databit0 is low.)
In SPI/SSI mode this bit and WAIT_FOR_CMD bit select which SSn output to assert:
(WAIT_FOR_IRQ,WAIT_FOR_CMD) =
b00: SSn0 will assert during access (SSn2, SSn1 inactive); b01: SSn1 will assert during access (SSn2,
SSn0 inactive); b10: SSn2 will assert during access (SSn1, SSn0 inactive).
20 Wait for Data Done - SD/MMC - 0: Send commands immediately after they are written.
WAIT_FOR_CMD
1: Wait to send command until after the CRC-checking phase of a data transfer has completed successfully.
This delays sending a command until a block of data is transferred. This can be used to send a STOP
command during an SD/MMC multi-block read.
In SD/MMC mode this signal means wait for MMC ready before sending command. (MMC is busy when
databit0 is low.)
In SPI/SSI mode this bit and WAIT_FOR_IRQ bit select which SSn output to assert:
(WAIT_FOR_IRQ,WAIT_FOR_CMD) =
b00: SSn0 will assert during access (SSn2, SSn1 inactive); b01: SSn1 will assert during access (SSn2,
SSn0 inactive); b10: SSn2 will assert during access (SSn1, SSn0 inactive).


Field Description
19 Get Long Response - SD/MMC - 0: The card response will be short. 1: The card will provide a 136-bit
LONG_RESP response. Only valid if GET_RESP is set. A long response cannot be checked using CHECK_RESP.
18 Check Response - SD/MMC. If this bit is set, the SSP will XOR the result with the REFERENCE field and
CHECK_RESP then mask the incoming status word with the MASK field in the COMPARE register. If there is a mismatch,
then the SSP will set the RESP_ERR status bit, and, if enabled, the RESP_ERR_IRQ. This should not be
used with LONG_RESP.
17 Get Response - SD/MMC - 0: Do not wait for a response from the card. 1: This command should receive a
GET_RESP response from the card.
16 Command Transmit Enable - SD/MMC - 0: Commands are not enabled. 1: Data in Command registers will
ENABLE be sent. This is normally enabled in SD/MMC.
15–0 Reserved
RSVD0
17.10.2 SD/MMC Command Register 0 (HW_SSP_CMD0)

SD/MMC Command Index and control register
HW_SSP_CMD0: 0x010
HW_SSP_CMD0_SET: 0x014
HW_SSP_CMD0_CLR: 0x018
HW_SSP_CMD0_TOG: 0x01C
This is the command code for the SD/MMC devices. See device specification for details.
For eMMC Alternate boot operation, Command and RX data phases must be executed
together (HW_SSP_CTRL0_ENABLE=1 and HW_SSP_CTRL0_DATA_XFER=1) so that
SSP does not miss the boot ack or boot data phases.
Address: HW_SSP_CMD0 – 8001_0000h base + 10h offset = 8001_0010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BOOT_ACK_
CLKING_EN
CLKING_EN
DBL_DATA_
BOOT_OP_
APPEND_
RATE_EN
RSVD0 RSVD1[19:16]
TERMINATE
R
SLOW_
CONT_
PRIM_
8CYC
SOFT_
EN
EN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1[15:8]
CMD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_SSP_CMD0 field descriptions

Field Description
31–27 Reserved
RSVD0
26 Setting this bit to 1 causes the current operation to terminate itself under normal condition. This signal is
SOFT_ used as edge-sensitive, so in order to create a subsequent termanation, SOFT_TERMINATE must be taken
TERMINATE low and then asserted again.
25 This bit enables the Double Data Rate operation. The DDR operation only applies in 4-bit or 8-bit data
DBL_DATA_ transfers.
RATE_EN
24 Enable the primary method of Boot Operation where the SSP_CMD output is driven low for the entire boot
PRIM_BOOT_ operation.
OP_EN
In primary Boot Operation mode, program the SSP to read one or more 512 byte blocks of data, and ensure
command is dissabled (HW_SSP_CTRL0_ENABLE=0). Do not set this bit for the Alternate Boot Operation
mode;
instead, program the SSP to send command zero (with no response) and read one or more 512 byte blocks
of boot data. Enabling the BOOT_ACK is optional.
23 Enable Boot Acknowledge reception from the slave during primary or alternate boot operation.
BOOT_ACK_EN
For eMMC Alternate boot operation, Command and RX data phases must be executed together
(HW_SSP_CTRL0_ENABLE=1 and HW_SSP_CTRL0_DATA_XFER=1)
so that SSP does not miss the boot ack or boot data phases. This bit must be zero for non-boot operations.
22 Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring
SLOW_CLKING_ command and data. This field is ignored when CONT_CLKING is zero.
EN
21 Set this bit to enable Continous clocking of SCK when no SD/MMC command/reaponse or data transfer is
CONT_CLKING_ active. This is used in SD/MMC mode. When set to zero, SCK is idle when no transfer is taking place.
EN
20 Append 8 SCK cycles. This is used in SD/MMC mode. When set to one, the SCK will toggle for 8 more
APPEND_8CYC cycles before going idle. When set to zero SCK will toggle up to 4 cycles before going idle. This should be
set to one at the end of a single or multiple block transfer.
19–8 Reserved
RSVD1
7–0 SD/MMC Command Index (uses 5:0) to be sent to card. This is also SPI/SSI control word[7:0] for RX
CMD transfers.
0x00 MMC_GO_IDLE_STATE —
0x01 MMC_SEND_OP_COND —
0x02 MMC_ALL_SEND_CID —
0x03 MMC_SET_RELATIVE_ADDR —
0x04 MMC_SET_DSR —

HW_SSP_CMD0 field descriptions (continued)

Field Description
0x05 MMC_RESERVED_5 —
0x06 MMC_SWITCH —
0x07 MMC_SELECT_DESELECT_CARD —
0x08 MMC_SEND_EXT_CSD —
0x09 MMC_SEND_CSD —
0x0A MMC_SEND_CID —
0x0B MMC_READ_DAT_UNTIL_STOP —
0x0C MMC_STOP_TRANSMISSION —
0x0D MMC_SEND_STATUS —
0x0E MMC_BUSTEST_R —
0x0F MMC_GO_INACTIVE_STATE —
0x10 MMC_SET_BLOCKLEN —
0x11 MMC_READ_SINGLE_BLOCK —
0x12 MMC_READ_MULTIPLE_BLOCK —
0x13 MMC_BUSTEST_W —
0x14 MMC_WRITE_DAT_UNTIL_STOP —
0x17 MMC_SET_BLOCK_COUNT —
0x18 MMC_WRITE_BLOCK —
0x19 MMC_WRITE_MULTIPLE_BLOCK —
0x1A MMC_PROGRAM_CID —
0x1B MMC_PROGRAM_CSD —
0x1C MMC_SET_WRITE_PROT —
0x1D MMC_CLR_WRITE_PROT —
0x1E MMC_SEND_WRITE_PROT —
0x23 MMC_ERASE_GROUP_START —
0x24 MMC_ERASE_GROUP_END —
0x26 MMC_ERASE —
0x27 MMC_FAST_IO —
0x28 MMC_GO_IRQ_STATE —
0x2A MMC_LOCK_UNLOCK —
0x37 MMC_APP_CMD —
0x38 MMC_GEN_CMD —
0x00 SD_GO_IDLE_STATE —
0x02 SD_ALL_SEND_CID —
0x03 SD_SEND_RELATIVE_ADDR —
0x04 SD_SET_DSR —
0x05 SD_IO_SEND_OP_COND —
0x07 SD_SELECT_DESELECT_CARD —
0x09 SD_SEND_CSD —
0x0A SD_SEND_CID —
0x0C SD_STOP_TRANSMISSION —
0x0D SD_SEND_STATUS —
0x0F SD_GO_INACTIVE_STATE —
0x10 SD_SET_BLOCKLEN —
0x11 SD_READ_SINGLE_BLOCK —
0x12 SD_READ_MULTIPLE_BLOCK —
0x18 SD_WRITE_BLOCK —

HW_SSP_CMD0 field descriptions (continued)

Field Description
0x19 SD_WRITE_MULTIPLE_BLOCK —
0x1B SD_PROGRAM_CSD —
0x1C SD_SET_WRITE_PROT —
0x1D SD_CLR_WRITE_PROT —
0x1E SD_SEND_WRITE_PROT —
0x20 SD_ERASE_WR_BLK_START —
0x21 SD_ERASE_WR_BLK_END —
0x23 SD_ERASE_GROUP_START —
0x24 SD_ERASE_GROUP_END —
0x26 SD_ERASE —
0x2A SD_LOCK_UNLOCK —
0x34 SD_IO_RW_DIRECT —
0x35 SD_IO_RW_EXTENDED —
0x37 SD_APP_CMD —
0x38 SD_GEN_CMD —
17.10.3 SD/MMC Command Register 1 (HW_SSP_CMD1)

SD/MMC Command Argument Register
Address: HW_SSP_CMD1 – 8001_0000h base + 20h offset = 8001_0020h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMD_ARG
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_SSP_CMD1 field descriptions

Field Description
31–0 SD/MMC Command Argument. See SSP_CTRL0_DATA_XFER bit description.
CMD_ARG
17.10.4 Transfer Count Register (HW_SSP_XFER_SIZE)

Transfer Count Register.

Address: HW_SSP_XFER_SIZE – 8001_0000h base + 30h offset = 8001_0030h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
XFER_COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
set
HW_SSP_XFER_SIZE field descriptions

Field Description
31–0 Number of words to transfer, as referenced in WORD_LENGTH in HW_SSP_CTRL1. The run bit and DMA
XFER_COUNT request will clear after this many words have been transferred. In SD/MMC, this should be a multiple of the
block size.
17.10.5 SD/MMC BLOCK SIZE and COUNT Register

(HW_SSP_BLOCK_SIZE)
SD/SDIO/MMC Multiple Block Size and Count Register.
Address: HW_SSP_BLOCK_SIZE – 8001_0000h base + 40h offset = 8001_0040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD0
BLOCK_COUNT BLOCK_SIZE
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_SSP_BLOCK_SIZE field descriptions

Field Description
31–28 Reserved
RSVD0
27–4 SD/MMC block count. This value one less than the number of blocks to transfer. For example setting a value
BLOCK_COUNT of one will transfer two blocks. This must satisfy equation HW_SSP_XFER_SIZE_XFER_COUNT = (1
shiftleft BLOCK_SIZE) x (BLOCK_COUNT+1) for BLOCK_COUNT greater than zero. This is also SPI/SSI
control word[15:8] for RX transfers.
3–0 SD/MMC block size encode. When BLOCK_COUNT is nonzero, the actual block size is (1 shiftleft
BLOCK_SIZE BLOCK_SIZE). For example setting a value of 9 will result in a block size of 512 bytes. When BLOCK_COUNT
is zero, BLOCK_SIZE is ignored and HW_SSP_XFER_SIZE_XFER_COUNT represents the single block
size or the number of byte to transfer. This must satisfy equation HW_SSP_XFER_SIZE_XFER_COUNT =
(1 shiftleft BLOCK_SIZE) x (BLOCK_COUNT+1) for BLOCK_COUNT greater than zero.
17.10.6 SD/MMC Compare Reference (HW_SSP_COMPREF)

SD/MMC status can be compared with a reference value.
Address: HW_SSP_COMPREF – 8001_0000h base + 50h offset = 8001_0050h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
REFERENCE
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_SSP_COMPREF field descriptions

Field Description
31–0 SD/MMC Compare mode reference. If CHECK_RESP is set, the response will be XOR'd with this value.
REFERENCE The results will be masked by the MASK bitfield. If there are any differences, then the SSP will indicate an
error state to the DMA.
17.10.7 SD/MMC compare mask (HW_SSP_COMPMASK)

A mask allows the comparison of one or more bit fields in the reference value.
Address: HW_SSP_COMPMASK – 8001_0000h base + 60h offset = 8001_0060h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MASK
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_SSP_COMPMASK field descriptions

Field Description
31–0 SD/MMC Compare mode Mask. If CHECK_RESP is set, the response is compared to REFERENCE, and
MASK the results are masked by this bitfield.
17.10.8 SSP Timing Register (HW_SSP_TIMING)

SSP Timing Config Register
The Timeout field and the clock dividers are contained in this register.
Address: HW_SSP_TIMING – 8001_0000h base + 70h offset = 8001_0070h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TIMEOUT CLOCK_DIVIDE CLOCK_RATE
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

HW_SSP_TIMING field descriptions

Field Description
31–16 Timeout counter. This specifies the number of SCK cycles multiplied by 4096, to wait before asserting the
TIMEOUT DATA TIMEOUT IRQ. It is used during timeout is used for data transfer/write operations in SD/MMC modes.
15–8 Clock Pre-Divider. CLOCK_DIVIDE must be an even value from 2 to 254.

CLOCK_DIVIDE
7–0 Serial Clock Rate. The value CLOCK_RATE is used to generate the transmit and receive bit rate of the
CLOCK_RATE SSP. The bit rate is SSPCLK / (CLOCK_DIVIDE x (1+ CLOCK_RATE)). CLOCK_RATE is a value from 0
to 255.
17.10.9 SSP Control Register 1 (HW_SSP_CTRL1)

Control Register 1.
HW_SSP_CTRL1: 0x080
HW_SSP_CTRL1_SET: 0x084
HW_SSP_CTRL1_CLR: 0x088
HW_SSP_CTRL1_TOG: 0x08C
This contains interrupt status and enable fields.
Address: HW_SSP_CTRL1 – 8001_0000h base + 80h offset = 8001_0080h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RECV_TIMEOUT_
RECV_TIMEOUT_
RESP_TIMEOUT_
RESP_TIMEOUT_
RESP_ERR_IRQ_
UNDERRUN_IRQ
DATA_TIMEOUT_
DATA_TIMEOUT_
DATA_CRC_IRQ_
RESP_ERR_IRQ
UNDERRUN_EN
DATA_CRC_IRQ
RSVD2
RSVD1
SDIO_IRQ_EN
SDIO_IRQ
R
IRQ_EN
IRQ_EN
IRQ_EN
FIFO_
FIFO_
IRQ
IRQ
IRQ
EN
EN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFO_OVERRUN_
FIFO_OVERRUN_
RSVD0
DMA_ENABLE
SLAVE_MODE
SLAVE_OUT_
POLARITY
R
DISABLE
IRQ_EN
PHASE
IRQ
WORD_LENGTH SSP_MODE
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

HW_SSP_CTRL1 field descriptions

Field Description
31 If this is set, an SDIO card interrupt has occurred and an IRQ, if enabled, has been sent to the ICOLL. Write
SDIO_IRQ a one to the SCT Clear address to reset this interrupt request status bit.
30 SDIO Card Interrupt IRQ Enable. 0: SDIO card IRQs masked. 1: SDIO card IRQs will be sent to the ICOLL.
SDIO_IRQ_EN
29 When the CHECK_RESP bit in CTRL0 is set, if an unexpected response (or response CRC) is received
RESP_ERR_IRQ from the card, this bit will be set. Write a one to the SCT Clear address to reset this interrupt request status
bit.
28 SD/MMC Card Error IRQ Enable. 0: Card Error IRQ is Masked. 1: Card Error IRQ is enabled. When set to
RESP_ERR_ 1, if an SD/MMC card indicates a card error (bit is set in both the SD/MMC Error Mask and R1 Card Status
IRQ_EN response), then a CPU IRQ will be asserted.
27 If this is set, a command response timeout has occurred, and an IRQ, if enabled, has been sent to the IRQ
RESP_ Collector. This is used for SD/MMC response timeout. Write a one to the SCT Clear address to reset this
TIMEOUT_IRQ interrupt request status bit.
26 SD/MMC Card Command Respone Timeout Error IRQ Enable. 0: Response Timeout IRQ is Masked. 1:
RESP_ Response Timeout IRQ is enabled. When set to 1, if an SD/MMC card does not respond to a command
TIMEOUT_IRQ_ within 64 cycles, then this CPU IRQ will be asserted.
EN
25 Data Transmit/Receive Timeout Error IRQ. If the timeout counter expires before the DAT bus is ready for
DATA_ write or sends read data, then a data timeout has occurred. Only Valid For SD/MMC Modes. Write a one to
TIMEOUT_IRQ the SCT Clear address to reset this interrupt request status bit.
24 Data Transmit/Receive Timeout Error IRQ Enable. If the timeout counter expires before the DAT bus is
DATA_ ready for write or sends read data, then a data timeout has occurred. Only Valid For SD/MMC Modes.
TIMEOUT_IRQ_
EN
23 Data Transmit/Receive CRC Error IRQ. Only valid for SD/MMC Modes. Write a one to the SCT Clear address
DATA_CRC_IRQ to reset this interrupt request status bit.
22 Data Transmit/Receive CRC Error IRQ Enable. Only valid for SD/MMC Modes.
DATA_CRC_
IRQ_EN
21 FIFO Underrun Interrupt. If the FIFO is read when it is empty this bit will be set. Write a one to the SCT Clear
FIFO_ address to reset this interrupt request status bit.
UNDERRUN_IRQ
20 FIFO Underrun IRQ Enable. If set and the FIFO_UNDERRUN_IRQ bit is asserted, an IRQ will be generated.
FIFO_
UNDERRUN_EN
19 Reserved
RSVD2
18 Reserved
RSVD1
17 Data Timeout Interrupt. If enabled and the FIFO is not empty, an IRQ will be generated if 128 HCLK Cycles
RECV_ Pass before the DATA register is read. This is supported for SPI modes only (Modes 0,1,2). Write a one to
TIMEOUT_IRQ the SCT Clear address to reset this interrupt request status bit.


Field Description
16 Receive Timeout. If set and the FIFO is not empty, an IRQ will be generated if 128 HCLK Cycles Pass before
RECV_ the DATA register is read.
TIMEOUT_IRQ_
EN
15 FIFO Overrun Interrupt. Indicated that the FIFO has been written to while full. Write a one to the SCT Clear
FIFO_ address to reset this interrupt request status bit.
OVERRUN_IRQ
14 FIFO Overrun Interrupt Enable. If set, an IRQ will be generated if the FIFO is written to while full.
FIFO_
OVERRUN_IRQ_
EN
13 DMA Enable. This signal enables DMA request and DMA Command End signals to be asserted.
DMA_ENABLE
12 Reserved
RSVD0
11 Slave Output Disable. 0: SSP can drive MISO in Slave Mode. 1: SSP does not drive MISO in slave mode.
SLAVE_OUT_
DISABLE
10 Serial Clock Phase. For SPI mode only.
PHASE
9 Serial Clock Polarity. In SD/MMC mode, 0: Command and TX data change after rising edge of SCK. In SPI
POLARITY mode, 0: Steady-state '0' on SCK when data is not being transferred. 1: Steady-state '1' on SCK when data
is not being transferred.
8 Slave Mode. 0: SSP is in Master Mode. 1: SSP is in Slave Mode. Set to zero for SD/MMC modes.
SLAVE_MODE
7–4 Word Length in bits per word. 0x0 to 0x2 are Reserved and Undefined. 0x3 is 4-bits per word...0xF is 16-bits
WORD_LENGTH per word. Always use 8 bits per word in SD/MMC Modes.
0x0 RESERVED0 — 0x0 is Reserved and Undefined
0x3 FOUR_BITS — use 4-bits per word
0x7 EIGHT_BITS — use 8-bits per word
0xF SIXTEEN_BITS — use 16-bits per word
3–0 Operating Mode. 0x0 = Motorola and Winbond SPI Mode, 0x1 = TI syncronous serial mode, 0x3 = SD/MMC
SSP_MODE Card. All other values are undefined. Before changing ssp_mode, a softreset must be issued to clear the
FIFO.
0x0 SPI — Motorola and Winbond SPI mode
0x1 SSI — Texas Instruments SSI mode
0x3 SD_MMC — SD/MMC mode
—

17.10.10 SSP Data Register (HW_SSP_DATA)

The HW_SSP_DATA register allows user access to the SSP FIFO.
This register is the gateway for data transfer to and from the attached device.
Address: HW_SSP_DATA – 8001_0000h base + 90h offset = 8001_0090h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DATA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_SSP_DATA field descriptions

Field Description
31–0 Data Register. Holds one, two, three, or four words, depending on the WORD_LENGTH. If WORD_LENGTH
DATA is not 8, 16, or 32, the words are padded to those lengths.
Data is right justified. When the run bit is set reads will cause the FIFO read pointer to increment and writes
will cause the FIFO write pointer to increment.
17.10.11 SD/MMC Card Response Register 0 (HW_SSP_SDRESP0)

SD/SDIO/MMC Card Response Register 0.
Address: HW_SSP_SDRESP0 – 8001_0000h base + A0h offset = 8001_00A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RESP0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_SSP_SDRESP0 field descriptions

Field Description
31–0 SD/MMC Response Status Bits[31:0].
RESP0
See SSP_CTRL0_DATA_XFER bit description.


Address: HW_SSP_SDRESP1 – 8001_0000h base + B0h offset = 8001_00B0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RESP1
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 SD/MMC Long Response [63:32]
RESP1

Address: HW_SSP_SDRESP2 – 8001_0000h base + C0h offset = 8001_00C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RESP2
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RESP2

Address: HW_SSP_SDRESP3 – 8001_0000h base + D0h offset = 8001_00D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RESP3
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
RESP3
17.10.15 SD/MMC Double Data Rate Control Register

(HW_SSP_DDR_CTRL)
SD/MMC Double Data Rate Control Register.
This register provides programmability in DDR mode for data output timing and data
formats.
Address: HW_SSP_DDR_CTRL – 8001_0000h base + E0h offset = 8001_00E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R DMA_ RSVD0[29:16]
BURST_
W TYPE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NIBBLE_POS
R RSVD0[15:2]
TXCLK_
DELAY_
TYPE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_SSP_DDR_CTRL field descriptions

Field Description
31–30 The field controls the number of APB transfers per DMA request. 2'b00: select one APB transfer per DMA
DMA_BURST_ request
TYPE
2'b01: select 4 APB transfers per DMA request. 2'b10: select 8 APB transfers per DMA request. 2'b11:
reserved
29–2 Reserved
RSVD0
1 This bit only applies in MMC 4-bit DDR transfers. 0: The two high nibbles of two odd and even bytes are
NIBBLE_POS sent/received on a cycle(both edges), then the low nibbles of the odd and even bytes are sent/received on
the next cycle.
1: Two nibbles of every bytes are sent/received on a cycle.
0 This field specifies two delay methods of delaying SCK related to SSP TX data to serve the purpose of
TXCLK_DELAY_ obtaining better TX data setup time. Set this bit to 0 to choose the pre-set gate delay, which is approximately
TYPE 5ns; set this bit to 1 to choose the SCK-coupled delay, which is 1/4 of SCK period.

17.10.16 SD/MMC DLL Control Register (HW_SSP_DLL_CTRL)

SD/MMC Delay Loop Lock Control Register.
This register provides programmability in DDR mode for data input timing and data formats.
Address: HW_SSP_DLL_CTRL – 8001_0000h base + F0h offset = 8001_00F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD1
REF_UPDATE_INT SLV_UPDATE_INT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FORCE_UPD
OVERRIDE
R RSVD0
ENABLE
UPDATE
RESET
GATE_
SLV_
SLV_
SLV_OVERRIDE_VAL SLV_DLY_TARGET
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_SSP_DLL_CTRL field descriptions

Field Description
31–28 This field allows the user to add additional delay cycles to the DLL control loop (reference delay line control).
REF_UPDATE_ By default, the DLL control loop shall update every two SSPCLK cycles. Programming this field results in a
INT DLL control loop update interval of (2 + REF_UPDATE_INT) * SSPCLK. It should be noted that increasing
the reference delay-line update interval reduces the ability of the DLL to adjust to fast changes in conditions
that may effect the delay (such as voltage and temperature)
27–20 Setting a value greater than 0 in this field, shall over-ride the default slave delay-line update interval of 256
SLV_UPDATE_ SSPCLK cycles. A value of 0 results in an update interval of 256 SSPCLK cycles (default setting). A value
INT of 0x0f results in 15 cycles and so on. Note that software can always cause an update of the slave-delay
line using the SLV_FORCE_UPDATE register. Note that the slave delay line will also update automatically
when the reference DLL transitions to a locked state (from an un-locked state).
19–16 Reserved
RSVD1
15–10 When SLV_OVERRIDE=1 This field is used to select 1 of 64 physical taps manually. A value of 0 selects
SLV_ tap 1, and a value of 0x3f selects tap 64.
OVERRIDE_VAL
9 Set this bit to 1 to Enable manual override for slave delay chain using SLV_OVERRIDE_VAL; to set 0 to
SLV_OVERRIDE disable manual override. This feature does not require the DLL to tbe enabled using the ENABLE bit. In fact
to reduce power, if SLV_OVERRIDE is used, it is recommended to disable the DLL with ENABLE=0
8 Reserved
RSVD0
7 Setting this bit to 1, forces the slave delay line not update
GATE_UPDATE

HW_SSP_DLL_CTRL field descriptions (continued)

Field Description
6–3 The delay target for the SSP read clock is can be programmed in 1/16th increments of an SSPCLK half-period.
SLV_DLY_ So the input read-clock can be delayed relative input data from (SSPCLK/2)/16 to SSPCLK/2.
TARGET
2 Setting this bit to 1, forces the slave delay line to update to the DLL calibrated value immediately. The slave
SLV_FORCE_ delay line shall update automatically based on the SLV_UPDATE_INT interval or when a DLL lock condition
UPD is sensed. Subsequent forcing of the slave-line update can only occur if SLV_FORCE_UP is set back to 0
and then asserted again (edge triggered).
1 Setting this bit to 1 force a reset on DLL. This will cause the DLL to lose lock and re-calibrate to detect an
RESET SSPCLK half period phase shift. This signal is used by the DLL as edge-sensitive, so in order to create a
subsequent reset, RESET must be taken low and then asserted again.
0 Set this bit to 1 to enable the DLL and delay chain; otherwise; set to 0 to bypasses DLL. Note that using the
ENABLE slave delay line override feature with SLV_OVERRIDE and SLV_OVERRIDE VAL, the DLL does not need
to be enabled.
17.10.17 SSP Status Register (HW_SSP_STATUS)

SSP Read Only Status Registers.
Various SSP status fields are provided in this register.
Address: HW_SSP_STATUS – 8001_0000h base + 100h offset = 8001_0100h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESP_CRC_
SDIO_IRQ
PRESENT
PRESENT
DMATERM
DMAREQ
DMASENSE
DMABURST
DMAEND
DETECT
CARD_
RSVD4
ERR
SD_
R RSVD3
Reset 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFO_EMPTY
DATA_CRC_
DATA_BUSY
CMD_BUSY
RESP_ERR
FIFO_FULL
TIMEOUT_
UNDRFLW
OVRFLW
TIMEOUT
TIMEOUT
RSVD2
RSVD0
RECV_
RESP_
FIFO_
FIFO_
ERR
STAT
R RSVD1 BUSY
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

HW_SSP_STATUS field descriptions

Field Description
31 SSP Present Bit. 0: SSP is not present in this product. 1: SSP is present.
PRESENT
30 Reserved
RSVD4
29 SD/MMC Controller Present bit. 0: SD/MMC controller is not present in this product. 1: SD/MMC controller
SD_PRESENT is present.
28 Reflects the state of the SSP_DETECT input pin.

CARD_DETECT
27–23 Reserved
RSVD3
22 Reflects the state of the ssp_dmaburst output port.
DMABURST
21 Reflects the state of the ssp_dmasense output port. It indicates a DMA error (Timeout or CRC) when asserted
DMASENSE high at the end of a DMA command.
20 Reflects the state of the ssp_dmaterm output port. This is a toggle signal.
DMATERM
19 Reflects the state of the ssp_dmareq output port. This is a toggle signal.
DMAREQ
18 Reflects the state of the ssp_dmaend output port. This is a toggle signal.
DMAEND
17 SDIO IRQ has been detected.
SDIO_IRQ
16 SD/MMC Response failed CRC check. This bit is cleared with soft reset or the rising edge of
RESP_CRC_ HW_SSP_CTRL0_RUN.
ERR
15 SD/MMC Card Responsed to Command with an Error Condition. This bit is cleared with soft reset or the
RESP_ERR rising edge of HW_SSP_CTRL0_RUN.
14 SD/MMC Card Expected Command Response not received within 64 CLK cycles. This indicates a card
RESP_TIMEOUT error, bad command, or command that failed CRC check. This bit is cleared with soft reset or the rising edge
of HW_SSP_CTRL0_RUN.
13 Data CRC Error. This bit is cleared with soft reset or the rising edge of HW_SSP_CTRL0_RUN.
DATA_CRC_
ERR
12 SD/MMC - timeout counter expired before data bus was ready. This bit is cleared with soft reset or the rising
TIMEOUT edge of HW_SSP_CTRL0_RUN.
11 Raw Receive Timeout Status. Indicates that no read has occurred to non-empty receive data FIFO for 128
RECV_ cycles
TIMEOUT_STAT
10 Reserved
RSVD2
9 FIFO Overflow Interrupt.
FIFO_OVRFLW

HW_SSP_STATUS field descriptions (continued)

Field Description
8 FIFO FULL
FIFO_FULL
7–6 Reserved
RSVD1
5 FIFO Empty.
FIFO_EMPTY
4 FIFO Underflow has occurred.
FIFO_UNDRFLW
3 SD/MMC command controller is busy sending a command or receiving a response
CMD_BUSY
2 SD/MMC command controller is busy transferring data.
DATA_BUSY
1 Reserved
RSVD0
0 SSP State Machines are Busy.
BUSY
17.10.18 SD/MMC DLL Status Register (HW_SSP_DLL_STS)

SSP Read Only Status Registers.
SSP DLL status fields are provided in this register.
Address: HW_SSP_DLL_STS – 8001_0000h base + 110h offset = 8001_0110h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD0[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REF_ SLV_
R RSVD0[15:14] REF_SEL SLV_SEL
LOCK LOCK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_SSP_DLL_STS field descriptions

Field Description
31–14 Reserved
RSVD0

HW_SSP_DLL_STS field descriptions (continued)

Field Description
13–8 Reference delay line select status.
REF_SEL
7–2 Slave delay line select status
SLV_SEL
1 Reference DLL lock status. This signifies that the DLL has detected and locked to a half-phase SSPCLK
REF_LOCK shift, allowing the slave delay-line to perform programmed clock delays.
0 Slave delay-line lock status. This signifies that a valid calibration has been set to the slave-delay line and
SLV_LOCK that the slave-delay line is implementing the programmed delay value.
17.10.19 SSP Debug Register (HW_SSP_DEBUG)

SSP Read Only Debug Registers.
Debug Register provide access to State machines.
Address: HW_SSP_DEBUG – 8001_0000h base + 120h offset = 8001_0120h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA_ CMD_
R DATACRC_ERR DAT_SM RSVD1 DMA_SM
STALL OE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSP_ SSP_
R MMC_SM CMD_SM SSP_RXD
CMD RESP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_SSP_DEBUG field descriptions

Field Description
31–28 Data CRC error
DATACRC_ERR
27 MMC mode: FIFO transfer not ready
DATA_STALL
26–24 MMC dataxfer state machine
DAT_SM
0x0 DSM_IDLE —
0x2 DSM_WORD —
0x3 DSM_CRC1 —
0x4 DSM_CRC2 —
0x5 DSM_END —

HW_SSP_DEBUG field descriptions (continued)

Field Description
23–20 Reserved
RSVD1
19 Enable for SSP_CMD
CMD_OE
18–16 DMA state machine
DMA_SM
0x0 DMA_IDLE —
0x1 DMA_DMAREQ —
0x2 DMA_DMAACK —
0x3 DMA_STALL —
0x4 DMA_BUSY —
0x5 DMA_DONE —
0x6 DMA_COUNT —
15–12 MMC_state machine
MMC_SM
0x0 MMC_IDLE —
0x1 MMC_CMD —
0x2 MMC_TRC —
0x3 MMC_RESP —
0x4 MMC_RPRX —
0x5 MMC_TX —
0x6 MMC_CTOK —
0x7 MMC_RX —
0x8 MMC_CCS —
0x9 MMC_PUP —
0xA MMC_WAIT —
11–10 MMC command_state machine
CMD_SM
0x0 CSM_IDLE —
0x1 CSM_INDEX —
0x2 CSM_ARG —
0x3 CSM_CRC —
9 SSP_CMD
SSP_CMD
8 SSP_RESP
SSP_RESP
7–0 SSP_RXD.
SSP_RXD
17.10.20 SSP Version Register (HW_SSP_VERSION)

This register reflects the version number for the SSP.

Address: HW_SSP_VERSION – 8001_0000h base + 130h offset = 8001_0130h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MAJOR MINOR STEP

W
Re- 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_SSP_VERSION field descriptions

Field Description
MAJOR
MINOR
STEP


Chapter 18
18.1 Boundary Scan Interface

This chapter describes the boundary scan feature that has been implemented on the i.MX28.
This feature is provided to enable board level testing.
There are five pins on the device which are used to implement the IEEE 1149.1 boundary
scan protocol. In order to make use of the boundary scan functionality, an extra pin called
DEBUG must be tied to low. The following table shows the pin information that is used to
implement boundary scan.
Table 18-1. Boundary Scan Pin Functions
Name of Pin Function Direction
TCK This is the clock that is used to serially shift data in to the part. Input
TMS This signal is used to select the test mode. Input
TDI This is the serial data that is used to shift in data into the boundary scan register. Input
It is also be used to shift in instructions into the instruction register and data into
the I/O configuration register.
TRST_N This is the reset signal for the block. Input
TDO This is the output of the boundary scan chain. Output
DEBUG This is the selection for the JTAG interface. Input

DEBUG=0: JTAG interface works for boundary scan.
DEBUG=1: JTAG interface works for ARM debugging. This chapter does not
cover ARM Debugging.
There are six instructions implemented in the boundary scan design. The following table
describes these instructions:

Table 18-2. Boundary Scan Instruction Set

Instruction Code Description
EXTEST 0000 This instruction places the IC into an external boundary-test mode and selects the boundary-scan
register to be connected between TDI and TDO. During this instruction, the boundary-scan register
is accessed to drive test data off-chip through the boundary outputs and receive test data off-chip
through the boundary inputs.
SAMPLE/PRELOAD 0001 This instruction takes the data on the I/O pad and latches it into the boundary scan register.
BYPASS 1111 This instruction is used to bypass the chip during board testing.
IDCODE 0010 This instruction allows a code to be serially read from the component. The Chip level JTAG ID
Code of i.MX28 is 0x0882401D.
HIGHZ 0011 This instruction places the component in a state, in which all of its system logic outputs are placed
in an inactive drive state.
IOCFG 0101 This user-defined instruction is used to program the voltage level of pins.
There is a special instruction which is called IOCFG that is implemented to load the I/O
configuration register. The I/O configuration register is used to program the voltage levels
of pins. It has 126 bits, corresponding to the 126 GPIO pins in the device. If there is a 0 in
a certain bit location, then the GPIO corresponding to that location will be programmed to
a 1.8 V level. The default value, which is 1, corresponds to a pin being programmed to a
3.3 V level. This register is provided so that the pins that are connected to 1.8 V peripherals
can be programmed to the correct voltage level before running the board level tests.
The customer will be provided a BSDL file which is in a format that is used by the board
tester. This file will detail the sequence of the pad connection in the boundary scan chain,
and the properties of the pads. This is used by the board level tester to develop the tests for
connectivity of the chip.

Chapter 19
Digital Control (DIGCTL) and On-Chip RAM
19.1 Overview
The digital control block provides overall control of various items within the top digital
block of the chip, including:
• Default first-level page table (DFLPT) controls
• HCLK performance counter
• Free-running microseconds counter
• Entropy control
• BIST controls for ARM Core and On-Chip RAM
• Chip Revision register
• USB loop back congtrol
• Other miscellaneous controls
The detailed diagram is shown below.

SRAM Controls
ARM Core SRAM EMI
AXIS
AHB Bridge
APB Bridge AHB
Shared APBX DMA
APBH Master AHB-to-APBH Bridge

APBH
Revision
On-Chip
PIO Programmable Registers OTP
Controller
Default First-
Performance Entropy
Level Page
Monitos
DIGCTL Table
AHB Arbiter PSWITCH OCRAM_CTRL
Figure 19-1. Digital Control (DIGCTL) Block Diagram
19.2 SRAM Controls

The on-chip 128 KB RAM is comprised of four physical banks of 8Kx32-bit each. The
architecture requires a 4-port, word interleaved topology to maximize the performance in
a multi-layer bus system. A diagrammatic representation of the word-interleaving is shown
below.

Chapter 19 Digital Control (DIGCTL) and On-Chip RAM
31 0
0x0000_0000
0x0000_0010
.
. Bank 3
.
.
0x0000_0004
0x0000_0014
.
. Bank 2
.
.
0x0000_0008
0x0000_0018
.
. Bank 1
.
.
0x0000_000C
0x0000_001C
.
. Bank 0
.
.
Figure 19-2. On-Chip RAM Partitioning
A 32-bit AHB address is arranged as shown below.

Table 19-1. On-Chip RAM Address Bits
AHB ADDR
BITS USAGE DESCRIPTION
16:4 Address Selects one of 8 K words in a bank.
3:2 Bank Address Selects 1 of 4 physical 32 KB banks.
1:0 Byte Address Selects/masks out specific bytes within a word.
The on-chip RAM and controller work at full CLK_H frequency without additional wait
states. There is no memory repair for the SRAM.
19.3 Miscellaneous Controls

The digital control block also contains a number of other miscellaneous functions, as detailed
in this section.
19.3.1 Performance Monitoring

The digital control block contains several registers for system bus performance monitoring,
including HW_DIGCTL_HCLKCOUNT, which counts HCLK rising edges. This register
counts at a variable rate as HW_CLKCTRL_HBUS_AUTO_SLOW_ MODE is enabled.
In addition, there exists a performance monitoring register for each AHB layer (L0–L3).
The HW_DIGCTL_L(n)_AHB_DATA_STALLED and
HW_DIGCTL_L(n)_AHB_ACTIVE_CYCLES registers can be used to measure AHB bus
utilization. The Stalled register counts all cycles in which any device has an outstanding

and unfulfilled bus operation in flight. The Active Cycles register counts the number of
data transfer cycles. Subtract cycles from stalls to determine under utilized bus cycles. These
counters can be used to tune the performance of the HCLK frequency for specific activities.
In addition, these monitors can be forced to focus on specific masters (which connect to
that layer). See the HW_DIGCTL_AHB_STATS_SELECT bit description for details.
19.3.2 High-Entropy PRN Seed

A 32-bit entropy register begins running a pseudo-random number algorithm from the time
reset is removed until the PSWITCH is released by the user. This high-entropy value can
be used as the seed for other pseudo-random number generators.
19.3.3 Write-Once Register

A 32-bit write-once register holds a runtime-derived locked seed. Once written, it cannot
be changed until the next chip wide reset event. The contents of this register are frequently
derived from the entropy register.
19.3.4 Microseconds Counter

A 32-bit free-running microseconds counter provides fine-grain real-time control. Its period
is determined by dividing the 24.0-MHz crystal oscillator by 24. Therefore, its frequency
does not change as HCLK, XCLK, and the processor clock frequency are changed.

DIGCTL Register Format Summary
HW_DIGCTL memory map
Absolute
Width Section/
(in bits) page
(hex)
8001_C000 DIGCTL Control Register (HW_DIGCTL_CTRL) 32 R/W 0001_0004h 19.4.1/1361
8001_C010 DIGCTL Status Register (HW_DIGCTL_STATUS) 32 R FF00_0000h 19.4.2/1364
8001_C020 Free-Running HCLK Counter Register 32 R 0000_0000h 19.4.3/1366
(HW_DIGCTL_HCLKCOUNT)
8001_C030 On-Chip RAM Control Register (HW_DIGCTL_RAMCTRL) 32 R/W 0000_0000h 19.4.4/1367
8001_C040 EMI Status Register (HW_DIGCTL_EMI_STATUS) 32 R 0000_0000h 19.4.5/1368
8001_C050 On-Chip Memories Read Margin Register 32 R/W 0000_0002h 19.4.6/1369
(HW_DIGCTL_READ_MARGIN)

HW_DIGCTL memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
8001_C060 Software Write-Once Register (HW_DIGCTL_WRITEONCE) 32 R/W A5A5_A5A5h 19.4.7/1369
8001_C070 BIST Control Register (HW_DIGCTL_BIST_CTL) 32 R/W 4000_0000h 19.4.8/1370
8001_C080 DIGCTL Status Register (HW_DIGCTL_BIST_STATUS) 32 R 0000_0000h 19.4.9/1372
8001_C090 Entropy Register (HW_DIGCTL_ENTROPY) 32 R 0000_0000h 19.4.10/1375
8001_C0A0 Entropy Latched Register 32 R 0000_0000h 19.4.11/1376
(HW_DIGCTL_ENTROPY_LATCHED)
8001_C0C0 Digital Control Microseconds Counter Register 32 R/W 0000_0000h 19.4.12/1376
(HW_DIGCTL_MICROSECONDS)
8001_C0D0 Digital Control Debug Read Test Register 32 R 789A_BCDEh 19.4.13/1377
(HW_DIGCTL_DBGRD)
8001_C0E0 Digital Control Debug Register (HW_DIGCTL_DBG) 32 R 8765_4321h 19.4.14/1377
8001_C100 USB LOOP BACK (HW_DIGCTL_USB_LOOPBACK) 32 R/W 0000_0000h 19.4.15/1378
8001_C110 SRAM Status Register 0 (HW_DIGCTL_OCRAM_STATUS0) 32 R 0000_0000h 19.4.16/1380
8001_C1A0 SRAM Status Register 9 (HW_DIGCTL_OCRAM_STATUS9) 32 R 0000_0000h 19.4.25/1386
8001_C1B0 SRAM Status Register 10 32 R 0000_0000h 19.4.26/1387
(HW_DIGCTL_OCRAM_STATUS10)
8001_C1C0 SRAM Status Register 11 32 R 0000_0000h 19.4.27/1388
8001_C1D0 SRAM Status Register 12 32 R 0000_0000h 19.4.28/1389
8001_C1E0 SRAM Status Register 13 32 R 0000_0000h 19.4.29/1390
8001_C280 Digital Control Scratch Register 0 (HW_DIGCTL_SCRATCH0) 32 R/W 0000_0000h 19.4.30/1391
8001_C290 Digital Control Scratch Register 1 (HW_DIGCTL_SCRATCH1) 32 R/W 0000_0000h 19.4.31/1392
8001_C2A0 Digital Control ARM Cache Register 32 R/W 0000_0000h 19.4.32/1392
(HW_DIGCTL_ARMCACHE)
8001_C2B0 Debug Trap Control and Status for AHB Layer 0 and 3 32 R/W 0000_0000h 19.4.33/1393
(HW_DIGCTL_DEBUG_TRAP)


Absolute
Width Section/
(in bits) page
(hex)
8001_C2C0 Debug Trap Range Low Address for AHB Layer 0 32 R/W 0000_0000h 19.4.34/1395
(HW_DIGCTL_DEBUG_TRAP_L0_ADDR_LOW)
8001_C2D0 Debug Trap Range High Address for AHB Layer 0 32 R/W 0000_0000h 19.4.35/1396
(HW_DIGCTL_DEBUG_TRAP_L0_ADDR_HIGH)
8001_C2E0 Debug Trap Range Low Address for AHB Layer 3 32 R/W 0000_0000h 19.4.36/1396
8001_C2F0 Debug Trap Range High Address for AHB Layer 3 32 R/W 0000_0000h 19.4.37/1397
8001_C300 Freescale Copyright Identifier Register (HW_DIGCTL_FSL) 32 R 6565_7246h 19.4.38/1397
8001_C310 Digital Control Chip Revision Register (HW_DIGCTL_CHIPID) 32 R 2800_0000h 19.4.39/1398
8001_C330 AHB Statistics Control Register 32 R/W 0000_0000h 19.4.40/1399
(HW_DIGCTL_AHB_STATS_SELECT)
8001_C370 AHB Layer 1 Transfer Count Register 32 R/W 0000_0000h 19.4.41/1400
(HW_DIGCTL_L1_AHB_ACTIVE_CYCLES)
8001_C380 AHB Layer 1 Performance Metric for Stalled Bus Cycles 32 R/W 0000_0000h 19.4.42/1401
Register (HW_DIGCTL_L1_AHB_DATA_STALLED)
8001_C390 AHB Layer 1 Performance Metric for Valid Bus Cycles Register 32 R/W 0000_0000h 19.4.43/1401
(HW_DIGCTL_L1_AHB_DATA_CYCLES)
8001_C3A0 AHB Layer 2 Transfer Count Register 32 R/W 0000_0000h 19.4.44/1402
8001_C3B0 AHB Layer 2 Performance Metric for Stalled Bus Cycles 32 R/W 0000_0000h 19.4.45/1403
8001_C3C0 AHB Layer 2 Performance Metric for Valid Bus Cycles Register 32 R/W 0000_0000h 19.4.46/1403
8001_C3D0 AHB Layer 3 Transfer Count Register 32 R/W 0000_0000h 19.4.47/1404
8001_C3E0 AHB Layer 3 Performance Metric for Stalled Bus Cycles 32 R/W 0000_0000h 19.4.48/1405
8001_C3F0 AHB Layer 3 Performance Metric for Valid Bus Cycles Register 32 R/W 0000_0000h 19.4.49/1406
8001_C500 Default First Level Page Table Movable PTE Locator 0 32 R/W 0000_0000h 19.4.50/1406
(HW_DIGCTL_MPTE0_LOC)
8001_C510 Default First-Level Page Table Movable PTE Locator 1 32 R/W 0000_0001h 19.4.51/1407


Absolute
Width Section/
(in bits) page
(hex)
8001_C5A0 Default First-Level Page Table Movable PTE Locator 10 32 R/W 0000_000Ah 19.4.60/1415
8001_C5B0 Default First-Level Page Table Movable PTE Locator 11 32 R/W 0000_000Bh 19.4.61/1416
8001_C5C0 Default First-Level Page Table Movable PTE Locator 12 32 R/W 0000_000Ch 19.4.62/1416
8001_C5D0 Default First-Level Page Table Movable PTE Locator 13 32 R/W 0000_000Dh 19.4.63/1417
8001_C5E0 Default First-Level Page Table Movable PTE Locator 14 32 R/W 0000_000Eh 19.4.64/1418
8001_C5F0 Default First-Level Page Table Movable PTE Locator 15 32 R/W 0000_000Fh 19.4.65/1419
19.4.1 DIGCTL Control Register (HW_DIGCTL_CTRL)

The DIGCTL Control Register provides overall control of various functions throughout the
digital portion of the chip.
HW_DIGCTL_CTRL: 0x000
HW_DIGCTL_CTRL_SET: 0x004
HW_DIGCTL_CTRL_CLR: 0x008
HW_DIGCTL_CTRL_TOG: 0x00C
EXAMPLE
HW_DIGCTL_CTRL_CLR(BM_DIGCTL_CTRL_USB_CLKGATE); // enable USB clock

Address: HW_DIGCTL_CTRL – 8001_C000h base + 0h offset = 8001_C000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OVERCURRENT_POL
OVERCURRENT_POL
USB1_CLKGATE
XTAL24M_GATE
RSVD3
OVERCURRENT_
OVERCURRENT_
TESTMODE
TESTMODE
TESTMODE
TESTMODE
RSVD2
ANALOG_
R
DIGITAL_
USB1_
USB0_
ENABLE
ENABLE
USB1_
USB0_
USB1_
USB0_
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEBUG_DISABLE
SAIF_LOOPBACK
USB0_CLKGATE
RSVD1
JTAG_SHIELD
LOOPBACK
LOOPBACK
AUART01_
RSVD0
ENTROPY
R
DUART_
LATCH_
SAIF_
CLKMUX_
SEL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
HW_DIGCTL_CTRL field descriptions

Field Description
31 Reserved.
RSVD3
30 If set to 1, disable the Digital Control Microseconds counter, STRB1MHZ. If set to 0, enable the Digital
XTAL24M_GATE Control Microseconds counter..
29–25 Reserved.
RSVD2
24 0 - Disable the overcurrent detection logic (default)
USB1_
1 - Enable the overcurrent detection logic
OVERCURRENT_
ENABLE
23 0 - Disable the overcurrent detection logic (default)
USB0_
1 - Enable the overcurrent detection logic
OVERCURRENT_
ENABLE
22 0 - The external Over Current indicator signal is high active.(default)
USB1_
1 - The external Over Current indicator signal is low active.
OVERCURRENT_
POL
21 0 - The external Over Current indicator signal is high active.(default)
USB0_
1 - The external Over Current indicator signal is low active.
OVERCURRENT_
POL
20 Set this bit to get into USB1 test mode
USB1_
TESTMODE
19 Set this bit to get into USB0 test mode
USB0_
TESTMODE

HW_DIGCTL_CTRL field descriptions (continued)

Field Description
18 Set this bit to get into analog test mode
ANALOG_
TESTMODE
17 Set this bit to get into digital test mode
DIGITAL_
TESTMODE
16 This bit must be cleared to 0 for normal operation of the USB controller. When set to 1, it gates off the
USB1_CLKGATE clocks to the USB controller. USB_CLKGATE can be set during suspend to gate the USB clock during
suspend. If this is gated, then the USB controller Reset Received bit (HW_USBCTRL_USBSTS_URI)
should be not be polled for reset during suspend; use the HW_USBPHY_CTRL_RESUME_IRQ bit instead.
This bit can be hardware auto cleared when wakeup from suspend happens
0x0 RUN — Allow USB to operate normally.
0x1 NO_CLKS — Do not clock USB gates in order to minimize power consumption.
15 Set this bit to one to loop SAIF0 to SAIF1 and SAIF1 to SAIF0. To use SAIF loopback the user must
SAIF_LOOPBACK configure one SAIF for transmit and the other for receive. Because this bit connects SAIF0's output to
SAIF1's input, and SAIF1's output to SAIF0's input it doesn't matter which of the two ports is configured for
TX and the other for RX, either configuration will produce an internal TX to RX loopback.
0x0 NORMAL — No loopback.
0x1 LOOPIT — Loop SAIF0 and SAIF1 back to each other.
14 Set this bit to one to loop the debug UART's RX and TX signals back on themselves in a null modem
DUART_ configuration.
LOOPBACK
0x1 LOOPIT — Loop debug UART TX and RX together.
13 Set this bit to one to loop application UARTs 0 and 1 back on themselves in a null modem configuration.
AUART01_
LOOPBACK
0x1 LOOPIT — Loop application UART 0 and 1 together.
12 Reserved.
RSVD1
11–10 Selects the source of the SAIF0 and SAIF1 input bit clock (BITCLK), and input left/right sample clock
SAIF_CLKMUX_ (LRCLK).
SEL
0x0 DIRECT — SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1 clock pins selected for
SAIF1 input clocks.
0x1 CROSSINPUT — SAIF1 clock inputs selected for SAIF0 input clocks, and SAIF0 clock inputs selected
for SAIF1 input clocks. This is the cross input mode.
0x2 CLKSRCSAIF0PIN — SAIF0 clock pin selected for both SAIF0 and SAIF1 input clocks.
0x3 CLKSRCSAIF1PIN — SAIF1 clock pin selected for both SAIF0 and SAIF1 input clocks.
9–4 Reserved.
RSVD0
3 Set this bit to disable the ARM core's debug logic (for power savings). This bit must remain 0 following
DEBUG_DISABLE power-on reset for normal JTAG debugger operation of the ARM core. When set to 1, it gates off the clocks
to the ARM core's debug logic. Once this bit is set, the part must undergo a power-on reset to re-enable
debug operation. Manually clearing this bit through a write after it has been set produces unknown results.

HW_DIGCTL_CTRL field descriptions (continued)

Field Description
2 This bit must be cleared to 0 for normal operation of the USB controller. When set to 1, it gates off the
USB0_CLKGATE clocks to the USB controller. USB_CLKGATE can be set during suspend to gate the USB clock during
suspend. If this is gated, then the USB controller Reset Received bit (HW_USBCTRL_USBSTS_URI)
should be not be polled for reset during suspend; use the HW_USBPHY_CTRL_RESUME_IRQ bit instead.
This bit can be hardware auto cleared when wakeup from suspend happens
0x0 RUN — Allow USB to operate normally.
0x1 NO_CLKS — Do not clock USB gates in order to minimize power consumption.
1 0 = The JTAG debugger is enabled.
JTAG_SHIELD
1 = The JTAG debugger is disabled.
0x0 NORMAL — JTAG debugger enabled.
0x1 SHIELDS_UP — JTAG debugger disabled.
0 Setting this bit latches the current value of the entropy register into HW_DIGCTL_ENTROPY_VALUE. This
LATCH_ can be used get a stable value on players that do not deassert the PSWITCH while powered up.
ENTROPY
19.4.2 DIGCTL Status Register (HW_DIGCTL_STATUS)

The DIGCTL Status Register provides a read-only view to various input conditions and
internal states.
HW_DIGCTL_STATUS: 0x010
HW_DIGCTL_STATUS_SET: 0x014
HW_DIGCTL_STATUS_CLR: 0x018
HW_DIGCTL_STATUS_TOG: 0x01C
EXAMPLE
if(HW_DIGCTL_STATUS.PACKAGE_TYPE)
{
// do 100-pin package things
}

Address: HW_DIGCTL_STATUS – 8001_C000h base + 10h offset = 8001_C010h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USB0_OTG_
USB1_OTG_
USB0_HS_
USB1_HS_
PRESENT
PRESENT
PRESENT
PRESENT
PRESENT
PRESENT
PRESENT
PRESENT
DEVICE_
DEVICE_
HOST_
HOST_
USB0_
USB0_
USB1_
USB1_
R RSVD0[23:16]
Reset 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JTAG_IN_
WRITTEN
USE
R RSVD0[15:5] PACKAGE_TYPE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_DIGCTL_STATUS field descriptions

Field Description
31 This read-only bit returns a 1 when USB high-speed mode is present.
USB0_HS_
PRESENT
30 This read-only bit returns a 1 when USB on-the-go (OTG) functionality is present.
USB0_OTG_
PRESENT
29 This read-only bit returns a 1 when USB host functionality is present.
USB0_HOST_
PRESENT
28 This read-only bit returns a 1 when USB device functionality is present.
USB0_DEVICE_
PRESENT
27 This read-only bit returns a 1 when USB high-speed mode is present.
USB1_HS_
PRESENT
26 This read-only bit returns a 1 when USB on-the-go (OTG) functionality is present.
USB1_OTG_
PRESENT
25 This read-only bit returns a 1 when USB host functionality is present.
USB1_HOST_
PRESENT
24 This read-only bit returns a 1 when USB device functionality is present.
USB1_DEVICE_
PRESENT

HW_DIGCTL_STATUS field descriptions (continued)

Field Description
23–5 Reserved.
RSVD0
4 This read-only bit is a 1 if JTAG debugger usage has been detected.
JTAG_IN_USE
3–1 This read-only bit field returns the pin count and package type. 000=289BGA, 001-111=Reserved.
PACKAGE_TYPE
0 Set to 1 by any successful write to the HW_DIGCTL_WRITEONCE register.
WRITTEN
19.4.3 Free-Running HCLK Counter Register

(HW_DIGCTL_HCLKCOUNT)
The Free-Running HCLK Counter Register is available for performance metrics. This
counter increments once per HCLK rising edge.
HW_DIGCTL_HCLKCOUNT: 0x020
HW_DIGCTL_HCLKCOUNT_SET: 0x024
HW_DIGCTL_HCLKCOUNT_CLR: 0x028
HW_DIGCTL_HCLKCOUNT_TOG: 0x02C
EXAMPLE
StartTime = HW_DIGCTL_HCLKCOUNT;
// Do something you want timed here
EndTime = HW_DIGCTL_HCLKCOUNT;
Duration = EndTime - StartTime; // make sure to handle rollover in a real application
Address: HW_DIGCTL_HCLKCOUNT – 8001_C000h base + 20h offset = 8001_C020h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_DIGCTL_HCLKCOUNT field descriptions

Field Description
31–0 This counter counts up from reset using HCLK. The count is valid for HCLK frequencies greater than 2 MHz.
COUNT

19.4.4 On-Chip RAM Control Register (HW_DIGCTL_RAMCTRL)

The On-Chip RAM Control Register holds on-chip SRAM control bit fields. This register
controls various parts of the on-chip RAM, including the speed select configuration.
HW_DIGCTL_RAMCTRL: 0x030
HW_DIGCTL_RAMCTRL_SET: 0x034
HW_DIGCTL_RAMCTRL_CLR: 0x038
HW_DIGCTL_RAMCTRL_TOG: 0x03C
EXAMPLE
HW_DIGCTL_RAMCTRL_SET(BM_DIGCTL_RAMCTRL_REPAIR_TRANSMIT); // Start the efuse state

machine
Address: HW_DIGCTL_RAMCTRL – 8001_C000h base + 30h offset = 8001_C030h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD2[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD2
R RSVD0
DEBUG_
ENABLE
RSVD1
[15:15]
DEBUG_CODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_DIGCTL_RAMCTRL field descriptions

Field Description
31–15 Reserved.
RSVD2
RSVD1
13 Debug enable for on chip sram. Set DEBUG_CODE field for different debug mode.
DEBUG_ENABLE
12–8 Debug code for 8x32 OCRAM instances. Recommended value is 0x0. Used to change different data access
DEBUG_CODE time. These bits are ignored if debug enable is low.
0x0 NORMAL — Normal functional mode.
0x4 DELAY1 — Normal functional mode.

HW_DIGCTL_RAMCTRL field descriptions (continued)

Field Description

7–0 Reserved.
RSVD0
19.4.5 EMI Status Register (HW_DIGCTL_EMI_STATUS)

The EMI Status Register indicates the low power mode of the EMI and provides state data
that is not available in the EMI controller.
HW_DIGCTL_EMI_STATUS: 0x040
HW_DIGCTL_EMI_STATUS_SET: 0x044
HW_DIGCTL_EMI_STATUS_CLR: 0x048
HW_DIGCTL_EMI_STATUS_TOG: 0x04C
EXAMPLE
NA
Address: HW_DIGCTL_EMI_STATUS – 8001_C000h base + 40h offset = 8001_C040h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD0 POWER_MODE
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_DIGCTL_EMI_STATUS field descriptions

Field Description
31–5 Reserved.
RSVD0
4–0 A detail description of the low power modes can be found in the EMI documentation. This register provides
POWER_MODE a port with which to read the power mode status since this capability is not inherent in the block itself.
0x2 PM4 — Power mode 4 is active.
0x0 NORMAL — Normal operation, low power modes are not active.

19.4.6 On-Chip Memories Read Margin Register

(HW_DIGCTL_READ_MARGIN)
The On-Chip Memories Read Margin Register provide speed select settings for numerous
memories.
HW_DIGCTL_READ_MARGIN: 0x050
HW_DIGCTL_READ_MARGIN_SET: 0x054
HW_DIGCTL_READ_MARGIN_CLR: 0x058
HW_DIGCTL_READ_MARGIN_TOG: 0x05C
This register controls various parts of the on-chip RAM and ROM, including the sense amp
configuration.
Address: HW_DIGCTL_READ_MARGIN – 8001_C000h base + 50h offset = 8001_C050h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD0
ROM
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
set
HW_DIGCTL_READ_MARGIN field descriptions

Field Description
31–4 Reserved.
RSVD0
3–0 This field is used for setting the read margin for the On-Chip ROM. It programs the sense amp differential
ROM setting and allows the trade off between speed and robustness. This field should not be changed unless
instructed by Freescale.
19.4.7 Software Write-Once Register (HW_DIGCTL_WRITEONCE)

The Software Write-Once Register hold the value used in software certification management.
This register is used to hold a portion of a certificate that is not mutable after software
initialization.
EXAMPLE
HW_DIGCTL_WRITEONCE.U = my_certificate;

Address: HW_DIGCTL_WRITEONCE – 8001_C000h base + 60h offset = 8001_C060h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Re- 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1
set
HW_DIGCTL_WRITEONCE field descriptions

Field Description
31–0 This field can be written only one time. The contents are not used by hardware.
BITS
19.4.8 BIST Control Register (HW_DIGCTL_BIST_CTL)

The BIST Control Register provides the BIST control of all the blocks.
HW_DIGCTL_BIST_CTL: 0x070
HW_DIGCTL_BIST_CTL_SET: 0x074
HW_DIGCTL_BIST_CTL_CLR: 0x078
HW_DIGCTL_BIST_CTL_TOG: 0x07C
EXAMPLE
HW_DIGCTL_BIST_CTL(); //
Address: HW_DIGCTL_BIST_CTL – 8001_C000h base + 70h offset = 8001_C070h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD0[26:16]
BIST_RESUME
BIST_CHECKB
BIST_DEBUGZ
BIST_RESETN
BIST_TESTMODE
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIST_DONE
OCRAM_BIST_
BIST_PASS
BIST_FAIL
RETENTION
OCRAM_
OCRAM_
OCRAM_
OCRAM_BIST_START
CACHE_BIST_START
LCDIF_BIST_START
DMA1_BIST_START
DMA0_BIST_START
ENET_BIST_START
USB1_BIST_START
USB0_BIST_START
DCP_BIST_START
CAN_BIST_START
PXP_BIST_START
RSVD0
R
[15:15]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_DIGCTL_BIST_CTL field descriptions

Field Description
31 bist test mode, open clock gatings
BIST_
TESTMODE
30 bist reset.
BIST_RESETN
29 enable bist debug
BIST_DEBUGZ
28 use checkboard algorithm with retention
BIST_CHECKB
27 resume with bist for retention test
BIST_RESUME
26–15 Reserved.
RSVD0
14 This read-only bit is a 1 if the OCRAM BIST test has been enabled waiting for a resume.
OCRAM_BIST_
RETENTION
13 This read-only bit is a 1 if the OCRAM BIST pass.
OCRAM_BIST_
PASS
12 This read-only bit is a 1 if the OCRAM BIST test returns a failure.
OCRAM_BIST_
FAIL
11 This read-only bit is a 1 if the OCRAM BIST test has completed.
OCRAM_BIST_
DONE
10 Set this bit to start the OCRAM BIST.
OCRAM_BIST_
START
9 Set this bit to start the PXP BIST.
PXP_BIST_
START
8 Set this bit to start the LCDIF BIST.
LCDIF_BIST_
START

HW_DIGCTL_BIST_CTL field descriptions (continued)

Field Description
7 Set this bit to start the DCP BIST.
DCP_BIST_
START
6 Set this bit to start the ENET BIST.
ENET_BIST_
START
5 Set this bit to start the USB1 BIST.
USB1_BIST_
START
4 Set this bit to start the USB0 BIST.
USB0_BIST_
START
3 Set this bit to start the DMA1 BIST.
DMA1_BIST_
START
2 Set this bit to start the DMA0 BIST.
DMA0_BIST_
START
1 Set this bit to start the CACHE BIST.
CACHE_BIST_
START
0 Set this bit to start the CAN BIST.
CAN_BIST_
START
19.4.9 DIGCTL Status Register (HW_DIGCTL_BIST_STATUS)

The DIGCTL Status Register reports status for the digital control block.
HW_DIGCTL_BIST_STATUS: 0x080
HW_DIGCTL_BIST_STATUS_SET: 0x084
HW_DIGCTL_BIST_STATUS_CLR: 0x088
HW_DIGCTL_BIST_STATUS_TOG: 0x08C
EXAMPLE
HW_DIGCTL_BIST_STATUS();

Address: HW_DIGCTL_BIST_STATUS – 8001_C000h base + 80h offset = 8001_

C080h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCDIF_BIST_
ENET_BIST_
DCP_BIST_
PXP_BIST_
CACHE_BIST_
LCDIF_BIST_
DMA1_BIST_
DMA0_BIST_
ENET_BIST_
USB1_BIST_
USB0_BIST_
RETENTION
RETENTION
RETENTION
RETENTION
RETENTION
RETENTION
RETENTION
RETENTION
RETENTION
RETENTION
DCP_BIST_
CAN_BIST_
PXP_BIST_
FAIL
FAIL
FAIL
FAIL
R RSVD0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCDIF_BIST_
DMA1_BIST_
DMA0_BIST_
DMA1_BIST_
DMA0_BIST_
ENET_BIST_
USB1_BIST_
USB0_BIST_
USB1_BIST_
USB0_BIST_
BIST_DONE
CAN_BIST_
DCP_BIST_
CAN_BIST_
PXP_BIST_
BIST_FAIL
CACHE_
CACHE_
DONE
DONE
DONE
DONE
DONE
DONE
DONE
DONE
DONE
FAIL
FAIL
FAIL
FAIL
FAIL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_DIGCTL_BIST_STATUS field descriptions

Field Description
31–30 Reserved.
RSVD0
29 This read-only bit is a 1 if the PXP BIST test has been enabled waiting for a resume.
PXP_BIST_
RETENTION
28 This read-only bit is a 1 if the LCDIF BIST test has been enabled waiting for a resume.
LCDIF_BIST_
RETENTION
27 This read-only bit is a 1 if the DCP BIST test has been enabled waiting for a resume.
DCP_BIST_
RETENTION
26 This read-only bit is a 1 if the ENET BIST test has been enabled waiting for a resume.
ENET_BIST_
RETENTION
25 This read-only bit is a 1 if the USB1 BIST test has been enabled waiting for a resume.
USB1_BIST_
RETENTION
24 This read-only bit is a 1 if the USB0 BIST test has been enabled waiting for a resume.
USB0_BIST_
RETENTION

HW_DIGCTL_BIST_STATUS field descriptions (continued)

Field Description
23 This read-only bit is a 1 if the DMA1 BIST test has been enabled waiting for a resume.
DMA1_BIST_
RETENTION
22 This read-only bit is a 1 if the DMA0 BIST test has been enabled waiting for a resume.
DMA0_BIST_
RETENTION
21 This read-only bit is a 1 if the CACHE BIST test has been enabled waiting for a resume.
CACHE_BIST_
RETENTION
20 This read-only bit is a 1 if the CAN BIST test has been enabled waiting for a resume.
CAN_BIST_
RETENTION
19 This read-only bit is a 1 if the PXP BIST test returns a failure.
PXP_BIST_FAIL
18 This read-only bit is a 1 if the LCDIF BIST test returns a failure.
LCDIF_BIST_
FAIL
17 This read-only bit is a 1 if the DCP BIST test returns a failure.
DCP_BIST_FAIL
16 This read-only bit is a 1 if the ENET BIST test returns a failure.
ENET_BIST_
FAIL
15 This read-only bit is a 1 if the USB1 BIST test returns a failure.
USB1_BIST_
FAIL
14 This read-only bit is a 1 if the USB0 BIST test returns a failure.
USB0_BIST_
FAIL
13 This read-only bit is a 1 if the DMA1 BIST test returns a failure.
DMA1_BIST_
FAIL
12 This read-only bit is a 1 if the DMA0 BIST test returns a failure.
DMA0_BIST_
FAIL
11 This read-only bit is a 1 if the CACHE BIST test returns a failure.
CACHE_BIST_
FAIL
10 This read-only bit is a 1 if the CAN BIST test returns a failure.
CAN_BIST_FAIL
9 This read-only bit is a 1 if the PXP BIST test has completed.
PXP_BIST_
DONE
8 This read-only bit is a 1 if the LCDIF BIST test has completed.
LCDIF_BIST_
DONE

HW_DIGCTL_BIST_STATUS field descriptions (continued)

Field Description
7 This read-only bit is a 1 if the DCP BIST test has completed.
DCP_BIST_
DONE
6 This read-only bit is a 1 if the ENET BIST test has completed.
ENET_BIST_
DONE
5 This read-only bit is a 1 if the USB1 BIST test has completed.
USB1_BIST_
DONE
4 This read-only bit is a 1 if the USB0 BIST test has completed.
USB0_BIST_
DONE
3 This read-only bit is a 1 if the DMA1 BIST test has completed.
DMA1_BIST_
DONE
2 This read-only bit is a 1 if the DMA0 BIST test has completed.
DMA0_BIST_
DONE
1 This read-only bit is a 1 if the CACHE BIST test has completed.
CACHE_BIST_
DONE
0 This read-only bit is a 1 if the CAN BIST test has completed.
CAN_BIST_
DONE
19.4.10 Entropy Register (HW_DIGCTL_ENTROPY)

The Entropy register is a read-only test value register.
EXAMPLE
while(HW_DIGCTL_STATUS.PSWITCH != 0)
{
//wait for pswitch to go away
}
HW_DIGCTL_WRITEONCE.BITS = rand(HW_DIGCTL_ENTROPY.VALUE);
Address: HW_DIGCTL_ENTROPY – 8001_C000h base + 90h offset = 8001_C090h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VALUE
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

HW_DIGCTL_ENTROPY field descriptions

Field Description
31–0 This read-only bit field always reads back the results of an entropy calculation. It is used to randomize the
VALUE seeds for random number generators.
19.4.11 Entropy Latched Register (HW_DIGCTL_ENTROPY_LATCHED)

The Entropy Latched Register is a read-only test value register.
Address: HW_DIGCTL_ENTROPY_LATCHED – 8001_C000h base + A0h offset = 8001_
C0A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VALUE
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_DIGCTL_ENTROPY_LATCHED field descriptions

Field Description
31–0 When the LATCH_ENTROPY bit in the HW_DIGCTL_CTRL register is set to 1, the value of the
VALUE HW_DIGCTL_ENTROPY register is latched into this register. This can be used to latch a stable random
value on players where the PSWITCH is not deasserted after power-up.
19.4.12 Digital Control Microseconds Counter Register

(HW_DIGCTL_MICROSECONDS)
The Digital Control Microseconds Counter Register is a read-only test value register.
HW_DIGCTL_MICROSECONDS: 0x0C0
HW_DIGCTL_MICROSECONDS_SET: 0x0C4
HW_DIGCTL_MICROSECONDS_CLR: 0x0C8
HW_DIGCTL_MICROSECONDS_TOG: 0x0CC
This fixed-rate timer always increments at 24.0 MHz divided by 24 or 1.0 MHz. It does not
generate an interrupt.
EXAMPLE
StartTime = HW_DIGCTL_MICROSECONDS_RD();
EndTime = HW_DIGCTL_MICROSECONDS_RD();

ElapsedTime = StartTime - EndTime; // WARNING, handle rollover in real software
Address: HW_DIGCTL_MICROSECONDS – 8001_C000h base + C0h offset = 8001_C0C0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
VALUE
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_DIGCTL_MICROSECONDS field descriptions

Field Description
31–0 This register maintains a 32-bit counter that increments at a 1-microsecond rate. The 1-MHz clock driving
VALUE this counter is derived from the 24.0-MHz crystal oscillator. The count value is not preserved over
power-downs. The 32-bit value wraps in less than two hours.
19.4.13 Digital Control Debug Read Test Register (HW_DIGCTL_DBGRD)

The Digital Control Debug Read Test Register is a read-only test value register.
This register is used for debugging purposes.
EXAMPLE
debug_value = HW_DIGCTL_DBGRD_RD();
Address: HW_DIGCTL_DBGRD – 8001_C000h base + D0h offset = 8001_C0D0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R COMPLEMENT
W
Re- 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0
set
HW_DIGCTL_DBGRD field descriptions

Field Description
31–0 This read-only bit field always reads back the one's complement of the value in HW_DIGCTL_DBG.
COMPLEMENT
19.4.14 Digital Control Debug Register (HW_DIGCTL_DBG)

The Digital Control Debug Register is a read-only test value register.

This register is used for debugging purposes.

EXAMPLE
debug_value = HW_DIGCTL_DBG_RD();
Address: HW_DIGCTL_DBG – 8001_C000h base + E0h offset = 8001_C0E0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VALUE
W
Re- 1 0 0 0 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1
set
HW_DIGCTL_DBG field descriptions

Field Description
31–0 This read-only bit field always reads back the fixed value 0x87654321.
VALUE
19.4.15 USB LOOP BACK (HW_DIGCTL_USB_LOOPBACK)

This register used to control the USB test mode for loopback tests.
HW_DIGCTL_USB_LOOPBACK: 0x100
HW_DIGCTL_USB_LOOPBACK_SET: 0x104
HW_DIGCTL_USB_LOOPBACK_CLR: 0x108
HW_DIGCTL_USB_LOOPBACK_TOG: 0x10C
This register contains controls for the USB loop back
Address: HW_DIGCTL_USB_LOOPBACK – 8001_C000h base + 100h offset = 8001_
C100h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USB1_TST_START
R RSVD0
TSTI1_TX_LS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIG_TST1
DIG_TST0
DIG_TST1
DIG_TST0
USB0_TST_START
UTMO1_
UTMO1_
UTMO0_
UTMO0_
UTMI1_DIG_TST1
UTMI1_DIG_TST0
UTMI0_DIG_TST1
UTMI0_DIG_TST0
TSTI1_TX_HIZ
TSTI0_TX_HIZ
TSTI1_TX_HS
TSTI1_TX_EN
TSTI0_TX_HS
TSTI0_TX_EN
TSTI0_TX_LS
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_DIGCTL_USB_LOOPBACK field descriptions

Field Description
RSVD0
17 This bit enables the USB loopback test.
USB1_TST_
START
16 Set to 1 to choose LS, set to 0 to choose HS or FS mode which defined by TSTI1_TX_HS.
TSTI1_TX_LS
15 chooses HS or FS mode.
TSTI1_TX_HS
14 eanbles TX
TSTI1_TX_EN
13 makes TX HIZ
TSTI1_TX_HIZ
12 control for mode
UTMI1_DIG_
TST1
11 control for mode
UTMI1_DIG_
TST0
10 This bit enables the USB loopback test.
USB0_TST_
START
9 Set to 1 to choose LS, set to 0 to choose HS or FS mode which defined by TSTI1_TX_HS.
TSTI0_TX_LS
8 chooses HS or FS mode.
TSTI0_TX_HS
7 enables TX
TSTI0_TX_EN
6 makes TX HIZ
TSTI0_TX_HIZ
5 control for mode
UTMI0_DIG_
TST1

HW_DIGCTL_USB_LOOPBACK field descriptions (continued)

Field Description
4 control for mode
UTMI0_DIG_
TST0
3 This read-only bit is a status bit for USB1 LB = 1 is pass
UTMO1_DIG_
TST1
UTMO1_DIG_
TST0
UTMO0_DIG_
TST1
UTMO0_DIG_
TST0
19.4.16 SRAM Status Register 0 (HW_DIGCTL_OCRAM_STATUS0)

The SRAM Status Register 0 is a read-only fail data register.
HW_DIGCTL_OCRAM_STATUS0: 0x110
HW_DIGCTL_OCRAM_STATUS0_SET: 0x114
HW_DIGCTL_OCRAM_STATUS0_CLR: 0x118
HW_DIGCTL_OCRAM_STATUS0_TOG: 0x11C
This register contains fail data for the first fail .
EXAMPLE
fail_data = HW_DIGCTL_OCRAM_STATUS0_RD();
Address: HW_DIGCTL_OCRAM_STATUS0 – 8001_C000h base + 110h offset = 8001_

C110h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R FAILDATA00
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

HW_DIGCTL_OCRAM_STATUS0 field descriptions

Field Description
31–0 This read-only bit field contains the fail data for the first fail .
FAILDATA00

The SRAM Status Register 1 is a read-only fail data register.
This register contains fail data for the second fail .
EXAMPLE

C120h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R FAILDATA01
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 This read-only bit field contains the fail data for the second fail .
FAILDATA01

SRAM Status Register 2 is a read-only fail data register.

This register contains fail data for the third fail .
EXAMPLE

C130h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R FAILDATA10
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 This read-only bit field contains the fail data for the third fail .
FAILDATA10

RAM Status Register 3 is a read-only fail data register.
This register contains fail data for the 4th fail .
EXAMPLE


C140h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R FAILDATA11
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 This read-only bit field contains the fail data for the 4th fail .
FAILDATA11

EXAMPLE

C150h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R FAILDATA20
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
FAILDATA20


EXAMPLE

C160h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R FAILDATA21
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
FAILDATA21

EXAMPLE

C170h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R FAILDATA30
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
FAILDATA30

EXAMPLE

C180h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R FAILDATA31
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
FAILDATA31

SRAM Status Register 8 is a read-only fail address register.
This register contains fail address for the first and second failures .
EXAMPLE

C190h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R FAILADDR01 FAILADDR00
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–16 This read-only bit field contains the failing address for the second fail .
FAILADDR01
15–0 This read-only bit field contains the failing address for the first fail .
FAILADDR00

HW_DIGCTL_OCRAM_STATUS9: 0x1A0

HW_DIGCTL_OCRAM_STATUS9_SET: 0x1A4
HW_DIGCTL_OCRAM_STATUS9_CLR: 0x1A8
HW_DIGCTL_OCRAM_STATUS9_TOG: 0x1AC
This register contains fail address for the third and 4th failures .
EXAMPLE
Address: HW_DIGCTL_OCRAM_STATUS9 – 8001_C000h base + 1A0h offset = 8001_

C1A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–16 This read-only bit field contains the failing address for the 4th fail .
FAILADDR11
15–0 This read-only bit field contains the failing address for the third fail .
FAILADDR10

HW_DIGCTL_OCRAM_STATUS10: 0x1B0
HW_DIGCTL_OCRAM_STATUS10_SET: 0x1B4
HW_DIGCTL_OCRAM_STATUS10_CLR: 0x1B8
HW_DIGCTL_OCRAM_STATUS10_TOG: 0x1BC
This register contains fail address for the 5th and 6th failures .
EXAMPLE

Address: HW_DIGCTL_OCRAM_STATUS10 – 8001_C000h base + 1B0h offset = 8001_

C1B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
FAILADDR21
FAILADDR20

HW_DIGCTL_OCRAM_STATUS11: 0x1C0
HW_DIGCTL_OCRAM_STATUS11_SET: 0x1C4
HW_DIGCTL_OCRAM_STATUS11_CLR: 0x1C8
HW_DIGCTL_OCRAM_STATUS11_TOG: 0x1CC
This register contains fail address for the 7th and 8th failures .
EXAMPLE
Address: HW_DIGCTL_OCRAM_STATUS11 – 8001_C000h base + 1C0h offset = 8001_

C1C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
FAILADDR31

HW_DIGCTL_OCRAM_STATUS11 field descriptions (continued)

Field Description
FAILADDR30

SRAM Status Register 12 is a read-only fail state register.
HW_DIGCTL_OCRAM_STATUS12: 0x1D0
HW_DIGCTL_OCRAM_STATUS12_SET: 0x1D4
HW_DIGCTL_OCRAM_STATUS12_CLR: 0x1D8
HW_DIGCTL_OCRAM_STATUS12_TOG: 0x1DC
This register contains fail state for the first, second, third and 4th failures .
EXAMPLE
Address: HW_DIGCTL_OCRAM_STATUS12 – 8001_C000h base + 1D0h offset =

8001_C1D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD3 FAILSTATE11 RSVD2 FAILSTATE10
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
31 This field is unused.
RSVD3
30–24 This read-only bit field contains the failing state for the 4th fail .
FAILSTATE11

HW_DIGCTL_OCRAM_STATUS12 field descriptions (continued)

Field Description
RSVD2
FAILSTATE10
RSVD1
14–8 This read-only bit field contains the failing state for the second fail .
FAILSTATE01
RSVD0
6–0 This read-only bit field contains the failing state for the first fail .
FAILSTATE00

SRAM Status Register 13 is a read-only fail state register.
HW_DIGCTL_OCRAM_STATUS13: 0x1E0
HW_DIGCTL_OCRAM_STATUS13_SET: 0x1E4
HW_DIGCTL_OCRAM_STATUS13_CLR: 0x1E8
HW_DIGCTL_OCRAM_STATUS13_TOG: 0x1EC
This register contains fail state for the 5th, 6th, 7th, and 8th failures .
EXAMPLE
Address: HW_DIGCTL_OCRAM_STATUS13 – 8001_C000h base + 1E0h offset =

8001_C1E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSVD3
FAILSTATE31
RSVD2
FAILSTATE30
RSVD1
FAILSTATE21
RSVD0
FAILSTATE20
19.4.30 Digital Control Scratch Register 0 (HW_DIGCTL_SCRATCH0)

Digital control scratch pad
Scratch Pad Register 0.
EXAMPLE
scratch_pad = (*void)HW_DIGCTL_SCRATCH0.PTR;
Address: HW_DIGCTL_SCRATCH0 – 8001_C000h base + 280h offset = 8001_C280h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PTR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

HW_DIGCTL_SCRATCH0 field descriptions

Field Description
31–0 Digital control scratch pad
PTR
19.4.31 Digital Control Scratch Register 1 (HW_DIGCTL_SCRATCH1)

Scratch Pad Register 1.
EXAMPLE
scratch_pad = (*void)HW_DIGCTL_SCRATCH1.PTR;
Address: HW_DIGCTL_SCRATCH1 – 8001_C000h base + 290h offset = 8001_C290h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PTR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_DIGCTL_SCRATCH1 field descriptions

Field Description
31–0 Digital control scratch pad
PTR
19.4.32 Digital Control ARM Cache Register (HW_DIGCTL_ARMCACHE)

This register provides the ARM cache RAM controls.
ARM Cache Control Register.
EXAMPLE
cache_timing = HW_DIGCTL_ARMCACHE.CACHE_SS;

Address: HW_DIGCTL_ARMCACHE – 8001_C000h base + 2A0h offset = 8001_

C2A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD4
VALID_SS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DRTY_SS CACHE_SS DTAG_SS ITAG_SS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_DIGCTL_ARMCACHE field descriptions

Field Description
31–18 Reserved.
RSVD4
17–16 Timing control for 64x24x1 RAMs (both instruction and data cache_valid arrays).
VALID_SS
15–14 Reserved.
RSVD3
13–12 Timing control for 128x8x1 RAM (DDRTY).
DRTY_SS
11–10 Reserved.
RSVD2
9–8 Timing Control for 1024x32x4 RAMs (both instruction and data cache arrays).
CACHE_SS
7–6 Reserved.
RSVD1
5–4 Timing Control for 256x22x4 RAM (DTAG).
DTAG_SS
3–2 Reserved.
RSVD0
1–0 Timing Control for 128x22x4 RAM (ITAG).
ITAG_SS
19.4.33 Debug Trap Control and Status for AHB Layer 0 and 3
(HW_DIGCTL_DEBUG_TRAP)
The Debug Trap Register provides control and status information for the trap functionality.
HW_DIGCTL_DEBUG_TRAP: 0x2B0

HW_DIGCTL_DEBUG_TRAP_SET: 0x2B4
HW_DIGCTL_DEBUG_TRAP_CLR: 0x2B8
HW_DIGCTL_DEBUG_TRAP_TOG: 0x2BC
This register sets the lower address that defines the debug trap function. When this function
is enabled, any active AHB cycle on either Layer 0 or Layer 0 which accesses this range
will trigger an interrupt to the ARM core.
EXAMPLE
Address: HW_DIGCTL_DEBUG_TRAP – 8001_C000h base + 2B0h offset = 8001_
C2B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD2[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRAP_L0_ TRAP_L3_MASTER_
TRAP_L3_
TRAP_L0_
TRAP_IN_
R RSVD2[15:12] RSVD1 RSVD0
ENABLE
RANGE
TRAP_
MASTER_ID ID
IRQ
IRQ
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_DIGCTL_DEBUG_TRAP field descriptions

Field Description
31–12 Reserved.
RSVD2
11–10 Reserved.
RSVD1
9–8 ID of master on AHB Layer 0 that triggered the TRAP_L0_IRQ. The value in this bitfield is updated when
TRAP_L0_ TRAP_L0_IRQ is set.
MASTER_ID
0x0 PXP — PXP
0x1 LCDIF — LCDIF
0x2 BCH — BCH
0x3 DCP — DCP
7 Reserved.
RSVD0
6–4 ID of master on AHB Layer 3 that triggered the TRAP_L3_IRQ. The value in this bitfield is updated when
TRAP_L3_ TRAP_L3_IRQ is set.
MASTER_ID
0x0 APBH_BRIDE_DMA — APBH Bridge DMA
0x1 APBX_BRIDE_DMA — APBX Bridge DMA
0x2 USB0 — USB0

HW_DIGCTL_DEBUG_TRAP field descriptions (continued)

Field Description
0x3 USB1 — USB1

0x4 ENET_M0 — ENET_M0
0x5 ENET_M1 — ENET_M1
3 This bit is set when an AHB access occurs to the range defined by the TRAP_ADDR registers below and
TRAP_L3_IRQ the trap function is enabled with the TRAP_ENABLE bit.
2 This bit is set when an AHB access occurs to the range defined by the TRAP_ADDR registers below and
TRAP_L0_IRQ the trap function is enabled with the TRAP_ENABLE bit.
1 Determines whether the debug trap function causes a match when the master address is inside (low-address
TRAP_IN_ <= current-address <= high-address) the specified range.
RANGE
0 = The trap occurs when the master address falls outside of the range.
1 = The check is inside the range.
0 Enables the AHB arbiter debug trap functions. When a trap occurs and this bit is set, an interrupt is sent to
TRAP_ENABLE the ARM core.
19.4.34 Debug Trap Range Low Address for AHB Layer 0

The Debug Trap Range Low Address Register defines the lower bound for an address range
that can be enabled to trigger an interrupt to the ARM core when an AHB cycle occurs
within this range. This register applies only to AHB Layer 0.
is enabled, any active AHB cycle on Layer 0 which accesses this range will trigger an
interrupt to the ARM core.
EXAMPLE
Address: HW_DIGCTL_DEBUG_TRAP_L0_ADDR_LOW – 8001_C000h base + 2C0h offset
= 8001_C2C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_DIGCTL_DEBUG_TRAP_L0_ADDR_LOW field descriptions

Field Description
31–0 This field contains the 32-bit lower address for the debug trap range.
ADDR

19.4.35 Debug Trap Range High Address for AHB Layer 0

The Debug Trap Range High Address Register defines the upper bound for an address range
This register sets the upper address that defines the debug trap function. When this function
EXAMPLE
Address: HW_DIGCTL_DEBUG_TRAP_L0_ADDR_HIGH – 8001_C000h base + 2D0h
offset = 8001_C2D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_DIGCTL_DEBUG_TRAP_L0_ADDR_HIGH field descriptions

Field Description
31–0 This field contains the 32-bit upper address for the debug trap range.
ADDR
19.4.36 Debug Trap Range Low Address for AHB Layer 3

EXAMPLE

Address: HW_DIGCTL_DEBUG_TRAP_L3_ADDR_LOW – 8001_C000h base + 2E0h offset

= 8001_C2E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_DIGCTL_DEBUG_TRAP_L3_ADDR_LOW field descriptions

Field Description
ADDR
19.4.37 Debug Trap Range High Address for AHB Layer 3

The Debug Trap Range High Address Register defines the upper bound for an address range
This register sets the upper address that defines the debug trap function. When this function
EXAMPLE
Address: HW_DIGCTL_DEBUG_TRAP_L3_ADDR_HIGH – 8001_C000h base + 2F0h offset
= 8001_C2F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_DIGCTL_DEBUG_TRAP_L3_ADDR_HIGH field descriptions

Field Description
ADDR
19.4.38 Freescale Copyright Identifier Register (HW_DIGCTL_FSL)

Read-only Freescale Copyright Identifier Register.

This register provides read-only access to the zero-terminated twelve-byte Freescale copyright
identification string. This register behaves somewhat differently from all other APB registers
in that it provides different read-back values at its three successive SCT bus addresses. The
following binary values are read back at 0x300, 0x304, and 0x308 respectively: 0x65657246
e,e,r,F at 0x300 0x6c616373 l,a,c,e at 0x304 0xAEA92d65 0x00, Registered Trademark
(®), Copyright (©), hyphen (-), e at 0x308 The debugger does a string compare on these
12 successive little endian bytes. Any chip that reads back these values is either a Freescale
chip or it is a competitors chip that is violating Freescale registered trademarks and or
copyrights.
EXAMPLE
printf("%s", (char *)HW_DIGCTL_SGTL_ADDR);
Address: HW_DIGCTL_FSL – 8001_C000h base + 300h offset = 8001_C300h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R COPYRIGHT
W
Re- 0 1 1 0 0 1 0 1 0 1 1 0 0 1 0 1 0 1 1 1 0 0 1 0 0 1 0 0 0 1 1 0
set
HW_DIGCTL_FSL field descriptions

Field Description
31–0 This read-only bit field contains the four bytes of the Freescale Copyright Identification String.
COPYRIGHT
19.4.39 Digital Control Chip Revision Register (HW_DIGCTL_CHIPID)

Read-only chip revision register.
This register is for Chip Revision
EXAMPLE
FormatAndPrintChipID(HW_DIGCTL_CHIPID_PRODUCT_CODE,HW_DIGCTL_CHIPID_REVISION
);

Address: HW_DIGCTL_CHIPID – 8001_C000h base + 310h offset = 8001_C310h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PRODUCT_CODE RSVD0 REVISION

W
Re- 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_DIGCTL_CHIPID field descriptions

Field Description
31–16 This read-only bit field returns 0x2800, which identifies the generation from which the part is derived.
PRODUCT_
CODE
15–8 Reserved.
RSVD0
7–0 This read-only bit field always reads back the mask revision level of the chip.
REVISION
19.4.40 AHB Statistics Control Register

(HW_DIGCTL_AHB_STATS_SELECT)
The AHB Statistics Control Register selects which AHB Masters on each Layer of the AHB
subsystem are enabled to contribute to the statistics calculations.
This register is to enable performance monitoring for the corresponding AHB master in
layers
EXAMPLE
Address: HW_DIGCTL_AHB_STATS_SELECT – 8001_C000h base + 330h offset = 8001_
C330h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD0
L3_MASTER_SELECT L2_MASTER_SELECT L1_MASTER_SELECT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_DIGCTL_AHB_STATS_SELECT field descriptions

Field Description
31–24 Reserved.
RSVD0
23–16 Set various bits of this bit field to one to enable performance monitoring in the AHB Layer 3 arbiter for the
L3_MASTER_ corresponding AHB master. Bits [7:6] are currently reserved and should not be set
SELECT
0x1 APBHDMA — Select APBH DMA Master.
0x2 APBXDMA — Select APBX DMA Master.

HW_DIGCTL_AHB_STATS_SELECT field descriptions (continued)

Field Description
0x4 USB0 — Select USB0 Master.

0x8 USB1 — Select USB1 Master.
0x10 UDMA0 — Select UDMA0 Master.
0x20 UDMA1 — Select UDMA1 Master.
SELECT
0x1 ARMD — Select ARM DATA Master.
SELECT
0x1 ARMI — Select ARM Instruction Master.
19.4.41 AHB Layer 1 Transfer Count Register

The AHB Layer 1 Transfer Count Register counts the number of AHB bus cycles during
which a transfer is active on AHB Layer 0.
This field counts the number of AHB cycles in which a master was requesting a transfer,
and the slave had not responded. This includes cycles in which it was requesting transfers
but was not granted them, as well as cycles in which it was granted and driving the bus but
the targeted slave was not ready. The master selects in
HW_DIGCTL_CTRL_MASTER_SELECT are used in the arbiter to mask which master\'s
cycles are actually recorded here.
EXAMPLE
NumberCycles = HW_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT_RD();
Address: HW_DIGCTL_L1_AHB_ACTIVE_CYCLES – 8001_C000h base + 370h offset =

8001_C370h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_DIGCTL_L1_AHB_ACTIVE_CYCLES field descriptions

Field Description
31–0 This field contains the count of AHB bus cycles during which a master was active on the AHB Layer 1.
COUNT

(HW_DIGCTL_L1_AHB_DATA_STALLED)
Used for AHB bus utilization measurements, the AHB Performance Metric for Stalled Bus
Cycles Register counts the number of stalled AHB cycles.
This counter increments on a data-phase of the AHB in which the HREADY signal is low,
indicating a stalled data transfer.
EXAMPLE
NumberStalledCycles = HW_DIGCTL_L1_AHB_DATA_STALLED_COUNT_RD();
Address: HW_DIGCTL_L1_AHB_DATA_STALLED – 8001_C000h base + 380h offset =

8001_C380h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_DIGCTL_L1_AHB_DATA_STALLED field descriptions

Field Description
31–0 This field counts the number of AHB cycles in which a master was stalled.
COUNT
Used for AHB bus utilization measurements, the AHB Performance Metric for Valid Bus
Cycles Register counts the number of actual AHB cycles in which a data transfer is
completed.
This field counts the number of AHB cycles in which a master completed a data transfer (a
data-phase in which HREADY is high).
EXAMPLE
StartTime = HW_DIGCTL_HCLKCOUNT_RD();
while(HW_DIGCTL_L1_AHB_DATA_CYCLES.COUNT less than 1000000)
{
// wait for a specific number of xfers
}

ElapsedTime = HW_DIGCTL_HCLKCOUNT_RD() - StartTime;
Address: HW_DIGCTL_L1_AHB_DATA_CYCLES – 8001_C000h base + 390h offset =

8001_C390h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_DIGCTL_L1_AHB_DATA_CYCLES field descriptions

Field Description
31–0 This field contains the count of AHB bus cycles during which data was actually transferred from a master
COUNT to a slave or from a slave to a master.

EXAMPLE
Address: HW_DIGCTL_L2_AHB_ACTIVE_CYCLES – 8001_C000h base + 3A0h offset =

8001_C3A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
COUNT
EXAMPLE
Address: HW_DIGCTL_L2_AHB_DATA_STALLED – 8001_C000h base + 3B0h offset =

8001_C3B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
COUNT
completed.

EXAMPLE
{
}
Address: HW_DIGCTL_L2_AHB_DATA_CYCLES – 8001_C000h base + 3C0h offset =

8001_C3C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description

EXAMPLE

Address: HW_DIGCTL_L3_AHB_ACTIVE_CYCLES – 8001_C000h base + 3D0h offset =

8001_C3D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
COUNT
EXAMPLE
Address: HW_DIGCTL_L3_AHB_DATA_STALLED – 8001_C000h base + 3E0h offset =

8001_C3E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
COUNT

completed.
EXAMPLE
{
}
Address: HW_DIGCTL_L3_AHB_DATA_CYCLES – 8001_C000h base + 3F0h offset =

8001_C3F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
19.4.50 Default First Level Page Table Movable PTE Locator 0

This register is used by the DFLPT to set the location for MPTE0.
When using the hardware-based Default First-Level Page Table (DFLPT), program this
value to set the location for Movable PTE (MPTE0) to any of the 4096 sections.

Address: HW_DIGCTL_MPTE0_LOC – 8001_C000h base + 500h offset = 8001_C500h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1 RSVD0
DIS
SPAN LOC
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_DIGCTL_MPTE0_LOC field descriptions

Field Description
31 Setting this bit to 1 disables the MPTE. A disabled MPTE cannot be bound to the page table and cannot be
DIS modified.
30–27 Reserved.
RSVD1
26–24 This bit-field allows this PTE to span a larger than 1MB section of memory. Specifically 1MB * (2^SPAN).
SPAN Care must be taken to make sure that spanned regions do not overlap in the page table, since the DFLPT
does not provide any correction mechanism in an overlapped scenario. Because only one value can be set
for the MPTE base-address section entry, the DFLPT assumes linear physical 1 MB addressing within a
SPAN. For example, assuming a value N for LOC and SPAN=2, the DFLPT assumes the value of LOC,
LOC+1, LOC+2 and LOC+3 for the 4-values within that span; that is, all base addresses within a span are
contiguous.
23–12 Reserved.
RSVD0
11–0 Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT.Note that when the
LOC SPAN field is used, any MPTE can cover up to 128MB. Do not program to 0x800 (fixed PIO entry). No two
HW_DIGCTL_MPTEn_LOC registers can have the same value, and care must be taken to not create overlap
when using the SPAN feature. Doing so will result in non-deterministic behavior of the DFLPT.
19.4.51 Default First-Level Page Table Movable PTE Locator 1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1 RSVD0
DIS
SPAN LOC
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
set


Field Description
DIS modified.
30–27 Reserved.
RSVD1
contiguous.
23–12 Reserved.
RSVD0

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1 RSVD0
DIS
SPAN LOC
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
set

Field Description
DIS modified.
30–27 Reserved.
RSVD1

HW_DIGCTL_MPTE2_LOC field descriptions (continued)

Field Description
for the MPTE base-address section entry, the DFLPT assumes linear physical 1MB addression within a
contiguous.
23–12 Reserved.
RSVD0

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1 RSVD0
DIS
SPAN LOC
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
set

Field Description
DIS modified.
30–27 Reserved.
RSVD1
contiguous.


Field Description
23–12 Reserved.
RSVD0

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1 RSVD0
DIS
SPAN LOC
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
set

Field Description
DIS modified.
30–27 Reserved.
RSVD1
contiguous.
23–12 Reserved.
RSVD0


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1 RSVD0
DIS
SPAN LOC
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
set

Field Description
DIS modified.
30–27 Reserved.
RSVD1
LOC+1, LOC+2 and LOC+3 for the four values within that span; that is, all base addresses within a span
are contiguous.
23–12 Reserved.
RSVD0



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1 RSVD0
DIS
SPAN LOC
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
set

Field Description
DIS modified.
30–27 Reserved.
RSVD1
are contiguous.
23–12 Reserved.
RSVD0

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1 RSVD0
DIS
SPAN LOC
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
set


Field Description
DIS modified.
30–27 Reserved.
RSVD1
are contiguous.
23–12 Reserved.
RSVD0

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1 RSVD0
DIS
SPAN LOC
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
set

Field Description
DIS modified.
30–27 Reserved.
RSVD1


Field Description
are contiguous.
23–12 Reserved.
RSVD0

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1 RSVD0
DIS
SPAN LOC
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1
set

Field Description
DIS modified.
30–27 Reserved.
RSVD1
are contiguous.


Field Description
23–12 Reserved.
RSVD0

Address: HW_DIGCTL_MPTE10_LOC – 8001_C000h base + 5A0h offset = 8001_C5A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1 RSVD0
DIS
SPAN LOC
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
set

Field Description
DIS modified.
30–27 Reserved.
RSVD1
are contiguous.
23–12 Reserved.
RSVD0


Address: HW_DIGCTL_MPTE11_LOC – 8001_C000h base + 5B0h offset = 8001_C5B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1 RSVD0
DIS
SPAN LOC
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1
set

Field Description
DIS modified.
30–27 Reserved.
RSVD1
are contiguous.
23–12 Reserved.
RSVD0


Address: HW_DIGCTL_MPTE12_LOC – 8001_C000h base + 5C0h offset = 8001_C5C0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1 RSVD0
DIS
SPAN LOC
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
set

Field Description
DIS modified.
30–27 Reserved.
RSVD1
are contiguous.
23–12 Reserved.
RSVD0

Address: HW_DIGCTL_MPTE13_LOC – 8001_C000h base + 5D0h offset = 8001_C5D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1 RSVD0
DIS
SPAN LOC
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
set


Field Description
DIS modified.
30–27 Reserved.
RSVD1
are contiguous.
23–12 Reserved.
RSVD0

Address: HW_DIGCTL_MPTE14_LOC – 8001_C000h base + 5E0h offset = 8001_C5E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1 RSVD0
DIS
SPAN LOC
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
set

Field Description
DIS modified.
30–27 Reserved.
RSVD1


Field Description
are contiguous.
23–12 Reserved.
RSVD0

Address: HW_DIGCTL_MPTE15_LOC – 8001_C000h base + 5F0h offset = 8001_C5F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1 RSVD0
DIS
SPAN LOC
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
set

Field Description
DIS modified.
30–27 Reserved.
RSVD1
are contiguous.


Field Description
23–12 Reserved.
RSVD0

Chapter 20
On-Chip OTP (OCOTP) Controller
20.1 OCOTP Overview

The on-chip OTP controller (OCOTP) provides the following functions:
• Full memory-mapped (restricted) read access of 1.25 Kbit of on-chip OTP ROM.
• Data-register programming interface for the 1.25 Kbit of OTP.
• Generation of the chip hardware capability bus.
• Sources of two security keys that are supplied automatically to the DCP block through
private internal busses.
• Chip-level pin access to nonrestricted portions of OTP.
The OCOTP is connected to the APBH system peripheral bus and is accessible through the
ARM core. Read accesses can be performed at the maximum HCLK frequency.
Programming/writes can be performed at 24 MHz. There are two security encription keys
that are supplied to the DCP block. The first is the Crypto key which is made up of the 128
bits from registers HW_OCOTP_CRYPTO0 through HW_OCOTP_CRYPTO3. The least
significant bits are in register 0. The Unique key is made up of the 64 bits from registers
HW_OCOTP_OPS2 and HW_OCOTP_UN2. The least significant bits are contained in the
OPS2 register. The system diagram for the OCOTP is shown below.

Operation
OCOTP
APB Interface
APBH
HW_OCOTP_CTRL
S
HW_OCOTP_DATA
_
HW/SW
/ Capability, LOCK and
ROM Shadow Regs
HW Capability Bus
All
Blocks
OTP Controller/State Machine To

Crypto Keys
DCP
Test /Pin
Interface
256x1 OTP
256x1 OTP
256x1 OTP
256x1 OTP
256x1 OTP
Figure 20-1. On-Chip OTP (OCOTP) Controller Block Diagram
20.2 Operation
The APB interface of the OCOTP provides two functions:
• Programmer-model access to registers (see Programmable Registers for register details).
These operations require a bank opening sequence through
HW_OCOTP_CTRL_RD_BANK_OPEN.
• Restricted 32-bit word write/program access to the 1.25 Kbit OTP.
The OTP is divided into 32-bit words (40 in total). All of the 40 words are memory-mapped
to APBH addresses (for reads only). Writes require the use of HW_OCOTP_CTRL_ADDR.
The high-level OTP allocation for i.MX28 is shown below.

Chapter 20 On-Chip OTP (OCOTP) Controller
HW_OCOTP_CTRL_ADDR
0x27 SRK
0x26 SRK
0x25 SRK
0x24 SRK
0x23 SRK OTP Bank 4
0x22 SRK
0x21 SRK
0x20 SRK
Shadow
Regs
0x1F ROM Use
0x1E ROM Use
0x1D ROM Use
0x1C ROM Use
OTP Bank 3
0x1B ROM Use
0x1A ROM Use
0x19 ROM Use
0x18 ROM Use
Pin
Access
0x17 OPS6
0x16 OPS5
0x15 OPS4
0x14 OPS3
OTP Bank 2
0x13 OPS2
0x12 OPS1
0x11 OPS0
0x10 LOCK
0x0F CUSTCap
0x0E SWCap
0x0D HWCap5
Shadow
Regs 0x0C HWCap4
OTP Bank 1
0x0B HWCap3
0x0A HWCap2
0x09 HWCap1
0x08 HWCap0
0x07 CRYPTO KEY

0x06 CRYPTO KEY
0x05 CRYPTO KEY
0x04 CRYPTO KEY
OTP Bank 0
0x03 Customer
0x02 Customer
0x01 Customer
0x00 Customer
Figure 20-2. OCOTP Allocation-Internal View
OTP reads and writes can be performed on 32-bit words only. For writes, the 32-bit word
reflects the write mask, such that bit fields with 0 will not be programmed and bit fields
with 1 will be programmed.
For OTP random access, the programming interface consists of:

Operation
• HW_OCOTP_DATA—Data register (32- bit) for OTP programming (writes).

• HW_OCOTP_CTRL_ADDR—Address register (6-bit) for OTP programming (writes).
• HW_OCOTP_CTRL_BUSY—Programming/write request/status handshake bit.
• HW_OCOTP_CTRL_ERROR—Read/write access error status.
• HW_OCOTP_CTRL_RD_BANK_OPEN—Status of OTP read availability (reads).
20.2.1 Software Read Sequence

Reading OTP contents is relatively simple, because all OTP words are memory-mapped on
the APB space (see Programmable Registers for details). These registers are read-only,
except for the HW/SW capability, CUSTCAP, ROM and SRK shadow registers, which are
writable until the appropriate LOCK bit in OTP is set.
Due to the fuse-read architecture, the OTP banks must be open before they can be read.
This is accomplished as follows (the following does not apply to shadow registers, which
can be read at any time).
1. Program the HCLK to a frequency up to the maximum allowable HCLK frequency.
Note that this cannot exceed 200 MHz.
2. Check that HW_OCOTP_CTRL_BUSY and HW_OCOTP_CTRL_ERROR are clear.
3. Set HW_OCOTP_CTRL_RD_BANK_OPEN. This will kick the controller to put the
fuses into read mode. The controller will set HW_OCOTP_CTRL_BUSY until the
OTP contents are readable. Note that if there was a pending write (holding
HW_OCOTP_CTRL_BUSY) and HW_OCOTP_CTRL_RD_BANK_OPEN was set,
the controller would complete the write and immediately move into read operation
(keeping HW_OCOTP_CTRL_BUSY set while the banks are being opened).
4. Poll for HW_OCOTP_CTRL_BUSY clear. When HW_OCOTP_CTRL_BUSY is clear
and HW_OCOTP_CTRL_RD_BANK_OPEN is set, read the data from the appropriate
memory-mapped address. Note that this is not necessary for registers that are shadowed.
Reading before HW_OCOTP_CTRL_BUSY is cleared by the controller, will return
0xBADA_BADA and will result in the setting of HW_OCOTP_CTRL_ERROR.
Because opening banks takes approximately 33 HCLK cycles, immediate polling for
BUSY is not recommended.
5. Once accesses are complete, clear HW_OCOTP_CTRL_RD_BANK_OPEN. Leaving
the banks open will cause current drain.

If data is accessed from a protected region (such as the crypto key, once a read LOCK bit
has been set), the controller returns 0xBADA_BADA. In addition
HW_OCOTP_CTRL_ERROR is set. It must be cleared by the software before any new
write access can be issued. Subsequent reads to unrestricted mapped OTP locations will
still work successfully assuming that HW_OCOTP_CTRL_RD_BANK_OPEN is set and
HW_OCOTP_CTRL_BUSY is clear.
It should be noted that after opening the banks, read latencies to OTP are instant (meaning
they behave like regular reads from hardware registers), since parallel loading is used.
It should also be noted that setting HW_OCOTP_CTRL_RELOAD_SHADOWS to reload
shadow registers does not set HW_OCOTP_CTRL_RD_BANK_OPEN.
HW_OCOTP_CTRL_RD_BANK_OPEN can only be set and cleared by software. Forced
reloading of shadows is covered in Shadow Registers and Hardware Capability Bus.
20.2.2 Software Write Sequence

In order to avoid erroneous code performing erroneous writes to OTP, a special unlocking
sequence is required for writes.
1. Program HCLK to 24 MHz. OTP writes do not work at frequencies above 24 MHz.
2. Set the VDDIO voltage to 2.8 V (using HW_POWER_VDDIOCTRL_TRG). The
VDDIO voltage is used to program OTP. Incorrect voltage and frequency settings will
result in the OTP being programmed with incorrect values.
3. Check that HW_OCOTP_CTRL_BUSY and HW_OCOTP_CTRL_ERROR are clear.
Overlapped accesses are not supported by the controller. Any pending write must be
completed before a write access can be requested. In addition, the banks cannot be open
for reading, so HW_OCOTP_CTRL_RD_BANK_OPEN must also be clear. If the write
is done following a previous write, the postamble wait period of 2 μs must be followed
after clearing the HW_OCOTP_CTRL_BUSY (see Write Postamble).
4. Write the requested address to HW_OCOTP_CTRL_ADDR and program the unlock
code into HW_OCOTP_CTRL_WR_UNLOCK. This must be programmed for each
write access. The lock code is documented in the register description. Both the unlock
code and address can be written in the same operation.
5. Write the data to HW_OCOTP_DATA. This automatically sets
HW_OCOTP_CTRL_BUSY and clears HW_OCOTP_CTRL_WR_UNLOCK. In this
case, the data is a programming mask. Bit fields with ones will result in that OTP bit
being set. Only the controller can clear HW_OCOTP_CTRL_BUSY. The controller
will use the mask to program a 32-bit word in the OTP per the address in ADDR. At
the same time that the write is accepted, the controller makes an internal copy of
Operation
HW_OCOTP_CTRL_ADDR that cannot be updated until the next write sequence is

initiated. This copy guarantees that erroneous writes to HW_OCOTP_CTRL_ADDR
will not affect an active write operation. It should also be noted that, during
programming, HW_OCOTP_DATA will shift right (with zero fill). This shifting is
required to program the OTP serially. During the write operation, HW_OCOTP_DATA
cannot be modified.
6. Once complete, the controller clears BUSY. Beyond this, the 2-μs postamble requirement
must be met before submitting any further OTP operations (see Write Postamble). A
write request to a protected region will result in no OTP access and no setting of
HW_OCOTP_CTRL_BUSY. In addition, HW_OCOTP_CTRL_ERROR will be set.
It must be cleared by software before any new write access can be issued.
It should be noted that write latencies to OTP are in the order of 10s to 100s of microseconds
per word. Write latencies will vary based on the location of the word within the OTP bank.
Once a write is initiated, HW_OCOTP_DATA is shifted one bit per every 32 HCLK cycles.
Given:
8 words per OTP bank
32 bits per word
tHCLK is the HCLK clock period
n word locations (where 0 ≤ n ≤ 7)
Then, the approximate write latency for a given word is:
tHCLK * 32 * 32 * n
In addition to this latency, software must allow for the 2-μs postamble (using
HW_DIGCTL_MICROSECONDS), as described in Write Postamble
20.2.3 Write Postamble

Due to internal electrical characteristics of the OTP during writes, all OTP operations
following a write must be separated by 2 μs after the clearing of HW_OCOTP_CTRL_BUSY
following the write. This guarantees programming voltages on-chip to reach a steady state
when exiting a write sequence. This includes reads, shadow reloads, or other writes. A
recommended software sequence to meet the postamble requirements is as follows:
1. Issue the write and poll for BUSY (as per Software Write Sequence).
2. Once BUSY is clear, use HW_DIGCTL_MICROSECONDS to wait 2 μs.
3. Perform the next OTP operation.

20.2.4 Shadow Registers and Hardware Capability Bus

The on-chip hardware capability bus is generated using a direct connection to the shadow
registers HW_OCOTP_HWCAP0–5 and HW_OCOTP_HWSWCAP. The bits are copied
from the OTP on reset. They can be modified until either
HW_OCOTP_LOCK_HWSW_SHADOW or
HW_OCOTP_LOCK_HWSW_SHADOW_ALT is set. In addition, HW_OCOTP_SWCAP
and HW_OCOTP_LOCK are also shadowed into physical registers immediately after reset.
The user can force a reload of the shadow registers (including HW_OCOTP_LOCK) without
having to reset the device, which is useful for debugging code. To force a reload:
• Set HW_OCOTP_CTRL_RELOAD_SHADOWS.
• Wait for HW_OCOTP_CTRL_BUSY and HW_OCOTP_CTRL_RELOAD_SHADOWS
to be cleared by the controller.
• Attempting to write to the shadow registers while the shadows are being reloaded will
result in the setting of HW_OCOTP_CTRL_ERROR. In addition, the register will not
take the attempted write (yielding to the reload instead).
• Attempting to write to a shadow register that is locked will result in the setting of
HW_OCOTP_CTRL_ERROR.
HW_OCOTP_CTRL_RELOAD_SHADOWS can be set at any time. There is no need to

wait for HW_OCOTP_CTRL_BUSY or HW_OCOTP_CTRL_ERROR to be clear.
• In the case of HW_OCOTP_CTRL_BUSY being set due to an active write, the controller
will perform the bank opening and shadow reloading immediately after the completion
of the write.
• In the case where HW_OCOTP_CTRL_RD_BANK_OPEN is set, the shadow reload
will be performed immediately after the banks are closed by the software (by clearing
HW_OCOTP_CTRL_RD_BANK_OPEN). It should be noted that BUSY will take
approximately 33 HCLK cycles to clear, so polling for HW_OCOTP_CTRL_BUSY
immediately after clearing HW_OCOTP_CTRL_RD_BANK_OPEN is not
recommended.
• In all cases, the controller will clear HW_OCOTP_CTRL_RELOAD_SHADOWS after
the successful completion of the operation.


The OCOTP is always active. The shadow registers described in Programmable Registers
automatically load the appropriate OTP contents after reset is deasserted. During this
load-time HW_OCOTP_CTRL_BUSY is set. The load time is approximately 32 HCLK
cycles after the deassertion of reset. These shadow registers can be reloaded as described
in Shadow Registers and Hardware Capability Bus.

OCOTP Hardware Register Format Summary
HW_OCOTP memory map
Absolute
Width Section/
(in bits) page
(hex)
8002_C000 OTP Controller Control Register (HW_OCOTP_CTRL) 32 R/W 0000_0000h 20.4.1/1430
8002_C010 OTP Controller Write Data Register (HW_OCOTP_DATA) 32 R/W 0000_0000h 20.4.2/1432
8002_C020 Value of OTP Bank0 Word0 (Customer) 32 R 0000_0000h 20.4.3/1432
(HW_OCOTP_CUST0)
(HW_OCOTP_CUST1)
(HW_OCOTP_CUST2)
(HW_OCOTP_CUST3)
8002_C060 Value of OTP Bank0 Word4 (Crypto Key) 32 R 0000_0000h 20.4.7/1434
(HW_OCOTP_CRYPTO0)
(HW_OCOTP_CRYPTO1)
(HW_OCOTP_CRYPTO2)
(HW_OCOTP_CRYPTO3)
8002_C0A0 HW Capability Shadow Register 0 (HW_OCOTP_HWCAP0) 32 R/W 0000_0000h 20.4.11/1436
8002_C0B0 HW Capability Shadow Register 1 (HW_OCOTP_HWCAP1) 32 R/W 0000_0000h 20.4.12/1437
8002_C0C0 HW Capability Shadow Register 2 (HW_OCOTP_HWCAP2) 32 R/W 0000_0000h 20.4.13/1437
8002_C0D0 HW Capability Shadow Register 3 (HW_OCOTP_HWCAP3) 32 R/W 0000_0000h 20.4.14/1438
8002_C0E0 HW Capability Shadow Register 4 (HW_OCOTP_HWCAP4) 32 R/W 0000_0000h 20.4.15/1438
8002_C0F0 HW Capability Shadow Register 5 (HW_OCOTP_HWCAP5) 32 R/W 0000_0000h 20.4.16/1439
8002_C100 SW Capability Shadow Register (HW_OCOTP_SWCAP) 32 R/W 0000_0000h 20.4.17/1439

HW_OCOTP memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
8002_C110 Customer Capability Shadow Register 32 R/W 0000_0000h 20.4.18/1440
(HW_OCOTP_CUSTCAP)
8002_C120 LOCK Shadow Register OTP Bank 2 Word 0 32 R 0000_0000h 20.4.19/1441
(HW_OCOTP_LOCK)
8002_C130 Value of OTP Bank2 Word1 (Freescale OPS0) 32 R 0000_0000h 20.4.20/1443
(HW_OCOTP_OPS0)
(HW_OCOTP_OPS1)
(HW_OCOTP_OPS2)
(HW_OCOTP_OPS3)
8002_C170 Value of OTP Bank2 Word5 (Unassigned0) 32 R 0000_0000h 20.4.24/1445
(HW_OCOTP_UN0)
(HW_OCOTP_UN1)
(HW_OCOTP_UN2)
8002_C1A0 Shadow Register for OTP Bank3 Word0 (ROM Use 0) 32 R/W 0000_0000h 20.4.27/1447
(HW_OCOTP_ROM0)
8002_C1B0 Shadow Register for OTP Bank3 Word1 (ROM Use 1) 32 R/W 0000_0000h 20.4.28/1449
(HW_OCOTP_ROM1)
8002_C1C0 Shadow Register for OTP Bank3 Word2 (ROM Use 2) 32 R/W 0000_0000h 20.4.29/1451
(HW_OCOTP_ROM2)
8002_C1D0 Shadow Register for OTP Bank3 Word3 (ROM Use 3) 32 R/W 0000_0000h 20.4.30/1452
(HW_OCOTP_ROM3)
8002_C1E0 Shadow Register for OTP Bank3 Word4 (ROM Use 4) 32 R/W 0000_0000h 20.4.31/1453
(HW_OCOTP_ROM4)
8002_C1F0 Shadow Register for OTP Bank3 Word5 (ROM Use 5) 32 R/W 0000_0000h 20.4.32/1454
(HW_OCOTP_ROM5)
8002_C200 Shadow Register for OTP Bank3 Word6 (ROM Use 6) 32 R/W 0000_0000h 20.4.33/1454
(HW_OCOTP_ROM6)
8002_C210 Shadow Register for OTP Bank3 Word7 (ROM Use 7) 32 R/W 0000_0000h 20.4.34/1455
(HW_OCOTP_ROM7)
8002_C220 Shadow Register for OTP Bank4 Word0 (Data Use 0) 32 R/W 0000_0000h 20.4.35/1457
(HW_OCOTP_SRK0)
(HW_OCOTP_SRK1)
(HW_OCOTP_SRK2)
(HW_OCOTP_SRK3)

HW_OCOTP memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
(HW_OCOTP_SRK4)
(HW_OCOTP_SRK5)
(HW_OCOTP_SRK6)
(HW_OCOTP_SRK7)
8002_C2A0 OTP Controller Version Register (HW_OCOTP_VERSION) 32 R 0105_0000h 20.4.43/1461
20.4.1 OTP Controller Control Register (HW_OCOTP_CTRL)

The OCOTP Control and Status Register specifies the copy state, as well as the control
required for random access of the OTP memory
HW_OCOTP_CTRL: 0x000
HW_OCOTP_CTRL_SET: 0x004
HW_OCOTP_CTRL_CLR: 0x008
HW_OCOTP_CTRL_TOG: 0x00C
The OCOTP Control and Status Register provides the necessary software interface for
performing read and write operations to the On-Chip OTP (One-Time Programmable ROM).
The control fields such as WR_UNLOCK, ADDR and BUSY/ERROR may be used in
conjunction with the HW_OCOTP_DATA register to perform write operations. Read
operations are performed through the direct memory mapped registers. In the cases where
OTP values are shadowed into local memory storage, the memory mapped location can be
read directly. In the cases where the OTP values are not shadowed into local memory, the
read-preparation sequence involving RD_BANK_OPEN and BUSY/ERROR fields must
be used before performing the read.
Address: HW_OCOTP_CTRL – 8002_C000h base + 0h offset = 8002_C000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_UNLOCK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD_BANK_
SHADOWS
R RSRVD2 RSRVD1 BUSY RSRVD0
RELOAD_
ERROR
OPEN
ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_OCOTP_CTRL field descriptions

Field Description
31–16 Write 0x3E77 to enable OTP write accesses. NOTE: This register must be unlocked on a write-by-write
WR_UNLOCK basis (a write is initiated when HW_OCOTP_DATA is written), so the UNLOCK bitfield must contain the
correct key value during all writes to HW_OCOTP_DATA, otherwise a write shall not be initiated. This field
is automatically cleared after a successful write completion (clearing of BUSY).
0x3E77 KEY — Key needed to unlock HW_OCOTP_DATA register.
15–14 These bits always read back zero.
RSRVD2
13 Set to force re-loading the shadow registers (HW/SW capability and LOCK). This operation will automatically
RELOAD_ open banks (but will not set RD_BANK_OPEN) and set BUSY. Once the shadow registers have been
SHADOWS re-loaded, BUSY and RELOAD_SHADOWS are automatically cleared by the controller. There is no need
to set RD_BANK_OPEN to force the reload. If RD_BANK_OPEN is already set, its still possible to set
RELOAD_SHADOWS. In this case, the shadow registers will only be updated upon the clearing of
RD_BANK_OPEN.
12 Set to open the all the OTP banks for reading. When set, the controller sets BUSY to allow time for the banks
RD_BANK_ to become available (approximately 32 HCLK cycles later at which time the controller will clear BUSY). Once
OPEN BUSY is clear, the various OTP words are accessible through their memory mapped address. Note that
OTP words which are shadowed, can be read at anytime and will not be affected by RD_BANK_OPEN. This
bit must be cleared after reading is complete. Keeping the OTP banks open causes additional current draw.
BUSY must be clear before this setting will take affect. If there is a write transaction pending (holding BUSY),
then the bank opening sequence will begin automatically upon the previous transaction clears BUSY. Note
that if a read is performed from non-shadowed locations without RD_BANK_OPEN, ERROR will be set

RSRVD1
9 Set by the controller when either an access to a locked region is requested or a read is requested from
ERROR non-shadowed efuse locations without the banks being open. Must be cleared before any further write access
can be performed. This bit can only be set by the controller. This bit is also set if the Pin interface is active
and software requests an access to the OTP. In this instance, the ERROR bit cannot be cleared until the
Pin interface access has completed. Reset this bit by writing a one to the SCT clear address space and not
by a general write.
8 OTP controller status bit. When active, no new write access or bank open operations (including
BUSY RELOAD_SHADOWS) can be performed. Cleared by controller when access complete (for writes), or the
banks are open (for reads). After reset (or after setting RELOAD_SHADOWS), this bit is set by the controller
until the HW/SW and LOCK registers are successfully copied, after which time it is automatically cleared by
the controller.

RSRVD0
5–0 OTP write access address register. Specifies one of 40 word address locations (0x00 - 0x27). If a valid write
ADDR is accepted by the controller (see HW_OCOTP_DATA for details on what constitutes a valid write), the
controller makes an internal copy of this value (to avoid the OTP programming being corrupted). This internal
copy will not update until the write access is complete.

20.4.2 OTP Controller Write Data Register (HW_OCOTP_DATA)

The OCOTP Data Register is used for OTP Programming
This register is used in conjunction with HW_OCOTP_CTRL to perform one-time writes
to the OTP. See the Software Write Sequence section for operating details.
Address: HW_OCOTP_DATA – 8002_C000h base + 10h offset = 8002_C010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DATA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_OCOTP_DATA field descriptions

Field Description
31–0 Used to initiate a write to OTP. To blow a fuse bit, the "1" shall be written through this data register
DATA
20.4.3 Value of OTP Bank0 Word0 (Customer) (HW_OCOTP_CUST0)

OTP banks must be open through HW_OCOTP_CTRL[RD_BANK_OPEN] before reading
this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN]
set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR]
being set and 0xBADA_BADA being returned.
Non-shadowed memory mapped access to OTP Bank 0, word 0 (ADDR = 0x00).
Address: HW_OCOTP_CUST0 – 8002_C000h base + 20h offset = 8002_C020h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_OCOTP_CUST0 field descriptions

Field Description
31–0 Reflects value of OTP Bank 0, word 0 (ADDR = 0x00)
BITS


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
BITS

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
BITS


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
BITS
20.4.7 Value of OTP Bank0 Word4 (Crypto Key) (HW_OCOTP_CRYPTO0)

OTP banks must be open via HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this
register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN]
Address: HW_OCOTP_CRYPTO0 – 8002_C000h base + 60h offset = 8002_C060h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_OCOTP_CRYPTO0 field descriptions

Field Description
31–0 Reflects value of OTP Bank 0, word 4 (ADDR = 0x04). If HW_OCOTP_LOCK[CRYPTOKEY] is set, returns
BITS 0xBADA_BADA and sets HW_OCOTP_CTRL[ERROR]


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description

OTP banks must be open via HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this
register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN]
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description

20.4.10 Value of OTP Bank0 Word7 (Crypto Key)

(HW_OCOTP_CRYPTO3)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
20.4.11 HW Capability Shadow Register 0 (HW_OCOTP_HWCAP0)

Copied from the OTP automatically after reset. Can be re-loaded by setting
HW_OCOTP_CTRL[RELOAD_SHADOWS]
Shadowed memory mapped access to OTP bank 1, word 0 (ADDR = 0x08).
Address: HW_OCOTP_HWCAP0 – 8002_C000h base + A0h offset = 8002_C0A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_OCOTP_HWCAP0 field descriptions

Field Description
31–0 Shadow register for HW capability bits 31:0 (copy of OTP bank 1, word 0 (ADDR = 0x08)). These bits become
BITS read-only after the HW_OCOTP_LOCK[HWSW_SHADOW] or HW_OCOTP_LOCK[HWSW_SHADOW_ALT]
bit is set.


Address: HW_OCOTP_HWCAP1 – 8002_C000h base + B0h offset = 8002_C0B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Shadow register for HW capability bits 63:32 (copy of OTP bank 1, word 1 (ADDR = 0x09)). These bits
BITS become read-only after the HW_OCOTP_LOCK[HWSW_SHADOW] or
HW_OCOTP_LOCK[HWSW_SHADOW_ALT] bit is set.

Shadowed memory mapped access to OTP bank 1, word 2 (ADDR = 0x0A).
Address: HW_OCOTP_HWCAP2 – 8002_C000h base + C0h offset = 8002_C0C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Shadow register for HW capability bits 95:64 (copy of OTP bank 1, word 2 (ADDR = 0x0A)). These bits


Shadowed memory mapped access to OTP bank 1, word 3 (ADDR = 0x0B).
Address: HW_OCOTP_HWCAP3 – 8002_C000h base + D0h offset = 8002_C0D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Shadow register for HW capability bits 127:96 (copy of OTP bank 1, word 3 (ADDR = 0x0B)). These bits

Shadowed memory mapped access to OTP bank 1, word 4 (ADDR = 0x0C).
Address: HW_OCOTP_HWCAP4 – 8002_C000h base + E0h offset = 8002_C0E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Shadow register for HW capability bits 159:128 (copy of OTP bank 1, word 4 (ADDR = 0x0C)). These bits


Shadowed memory mapped access to OTP bank 1, word 5 (ADDR = 0x0D).
Address: HW_OCOTP_HWCAP5 – 8002_C000h base + F0h offset = 8002_C0F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Shadow register for HW capability bits 191:160 (copy of OTP bank 1, word 5 (ADDR = 0x0D)). These bits
20.4.17 SW Capability Shadow Register (HW_OCOTP_SWCAP)

Shadowed memory mapped access to OTP bank 1, word 6 (ADDR = 0x0E).
Address: HW_OCOTP_SWCAP – 8002_C000h base + 100h offset = 8002_C100h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_OCOTP_SWCAP field descriptions

Field Description
31–0 Shadow register for SW capability bits 31:0 (copy of OTP bank 1, word 6 (ADDR = 0x0E)). These bits become
BITS read-only after the HW_OCOTP_LOCK[HWSW_SHADOW] or HW_OCOTP_LOCK[HWSW_SHADOW_ALT]
bit is set.

20.4.18 Customer Capability Shadow Register (HW_OCOTP_CUSTCAP)

Shadowed memory mapped access to OTP bank 1, word 7 (ADDR = 0x0F).
Address: HW_OCOTP_CUSTCAP – 8002_C000h base + 110h offset = 8002_C110h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTC_XTAL_32768_
RTC_XTAL_32000_
RSRVD0
R RSRVD1[15:3]
PRESENT
PRESENT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_OCOTP_CUSTCAP field descriptions

Field Description
31–3 Reserved - do not blow these bits.
RSRVD1
2 Blow to indicate the presence of an optional 32.768KHz off-chip oscillator.
RTC_XTAL_
32768_PRESENT
1 Blow to indicate the presence of an optional 32.000KHz off-chip oscillator.
RTC_XTAL_
32000_PRESENT
0 Reserved - do not blow these bits.
RSRVD0

20.4.19 LOCK Shadow Register OTP Bank 2 Word 0

(HW_OCOTP_LOCK)
Shadow register for OCOTP Lock Status Value (ADDR = 0x10). Copy of the state of the
OTP lock regions. Copied from the OTP upon reset. Can be re-loaded by setting
Address: HW_OCOTP_LOCK – 8002_C000h base + 120h offset = 8002_C120h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SHADOW_ALT
CRYPTODCP_ALT
CRYPTOKEY_ALT
HWSW_
ROM7
ROM6
ROM5
ROM4
ROM3
ROM2
ROM1
ROM0
R PIN OPS UN2 UN1 UN0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRK_SHADOW
CRYPTODCP
CRYPTOKEY
CUSTCAP_
CUSTCAP
SHADOW
SHADOW
SHADOW
HWSW_
HWSW
CUST3
CUST2
CUST1
CUST0
ROM_
R SRK UNALLOCATED
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_OCOTP_LOCK field descriptions

Field Description
31 Status of ROM use region write lock bits (ADDR = 0x1F). When set, word 0x1F in the ROM region is locked.
ROM7
30 Status of ROM use region write lock bits (ADDR = 0x1E). When set, word 0x1E in the ROM region is locked.
ROM6
29 Status of ROM use region write lock bits (ADDR = 0x1D). When set, word 0x1D in the ROM region is locked.
ROM5
28 Status of ROM use region write lock bits (ADDR = 0x1C). When set, word 0x1C in the ROM region is locked.
ROM4

HW_OCOTP_LOCK field descriptions (continued)

Field Description
27 Status of ROM use region write lock bits (ADDR = 0x1B). When set, word 0x1B in the ROM region is locked.
ROM3
26 Status of ROM use region write lock bits (ADDR = 0x1A). When set, word 0x1A in the ROM region is locked.
ROM2
25 Status of ROM use region write lock bits (ADDR = 0x19). When set, word 0x19 in the ROM region is locked.
ROM1
24 Status of ROM use region write lock bits (ADDR = 0x18). When set, word 0x18 in the ROM region is locked.
ROM0
23 Status of alternate bit for HWSW_SHADOW lock
HWSW_
SHADOW_ALT
22 Status of alternate bit for CRYPTODCP lock
CRYPTODCP_
ALT
21 Status of alternate bit for CRYPTOKEY lock
CRYPTOKEY_
ALT
20 Status of Pin access lock bit. When set, pin access is disabled.
PIN
19 Status of OPS region (ADDR = 0x11-0x14) write lock bit. When set, region is locked.
OPS
18 Status of un-assigned (ADDR = 0x17) write-lock bit. When set, un-asigned word at OTP address 0x17 is
UN2 locked.
UN1 locked.
UN0 locked.
15 Status of SRK bank (ADDR = 0x20-0x27) write-lock bit. When set, the 8 words (bank4) at OTP addresses
SRK 0x20-0x27 are locked.
14–12 Value of un-used portion of LOCK word

UNALLOCATED
11 Status of SRK region shadow register lock. When set, over-ride of DATA-region shadow bits is blocked.
SRK_SHADOW
10 Status of ROM region shadow register lock. When set, over-ride of ROM-region shadow bits is blocked.
ROM_SHADOW
9 Status of Customer Capability region (ADDR = 0x0F) write lock bit. When set, region is locked.
CUSTCAP
8 Status of HW/SW region (ADDR = 0x08-0x0E) write lock bit. When set, region is locked.
HWSW
7 Status of Customer Capability shadow register lock. When set, over-ride of customer capabality shadow
CUSTCAP_ bits is blocked.
SHADOW

HW_OCOTP_LOCK field descriptions (continued)

Field Description
6 Status of HW/SW Capability shadow register lock. When set, over-ride of HW/SW capabality shadow bits
HWSW_ is blocked.
SHADOW
5 Status of read lock bit for DCP APB crypto access. When set, the DCP will disallow reads of its crypto keys
CRYPTODCP through its APB interface.
4 Status of crypto key region (ADDR = 0x04-0x07) read/write lock bit. When set, region is locked.
CRYPTOKEY
3 Status of customer region word (ADDR = 0x03) write lock bit. When set, the region is locked.
CUST3
CUST2
CUST1
CUST0
20.4.20 Value of OTP Bank2 Word1 (Freescale OPS0)

(HW_OCOTP_OPS0)
Shadowed memory mapped access to OTP Bank 2, word 1 (ADDR = 0x11).
Address: HW_OCOTP_OPS0 – 8002_C000h base + 130h offset = 8002_C130h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_OCOTP_OPS0 field descriptions

Field Description
BITS


(HW_OCOTP_OPS1)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
BITS

(HW_OCOTP_OPS2)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
BITS

(HW_OCOTP_OPS3)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Reflects value of OTP Bank 2, word 4 (ADDR = 0x14), it is used to form the least significant bits of the unique
BITS key.
20.4.24 Value of OTP Bank2 Word5 (Unassigned0) (HW_OCOTP_UN0)


Address: HW_OCOTP_UN0 – 8002_C000h base + 170h offset = 8002_C170h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_OCOTP_UN0 field descriptions

Field Description
BITS

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
BITS



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Reflects value of OTP Bank 2, word 7 (ADDR = 0x17) . It is used to form the unique key
BITS
20.4.27 Shadow Register for OTP Bank3 Word0 (ROM Use 0)

(HW_OCOTP_ROM0)
HW_OCOTP_CTRL[RELOAD_SHADOWS].
Address: HW_OCOTP_ROM0 – 8002_C000h base + 1A0h offset = 8002_C1A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SD_MMC_ SD_POWER_ SD_POWER_UP_DELAY

BOOT_MODE
MODE GATE_GPIO [19:16]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOT_SERIAL_NUM
DISABLE_SPI_NOR_
UNENCRYPTED_BOOT
RECOVERY_MODE
RSRVD0
EMMC_USE_DDR
ENABLE_USB_
FAST_READ
R
DISABLE_
ENABLE_
SD_POWER_ USE_ALT_
SD_BUS_
UP_DELAY SSP_SCK_INDEX DEBUG_
WIDTH
[15:14] UART_PINS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_OCOTP_ROM0 field descriptions

Field Description
31–24 Encoded boot mode.
BOOT_MODE

HW_OCOTP_ROM0 field descriptions (continued)

Field Description
23–22 SD/MMC BOOT MODE
SD_MMC_MODE
00 MBR BOOT
01 Reserved
10 eMMC 4.3 Fast Boot
11 eSD2.1 Fast Boot
21–20 SD card power gate GPIO pin select: 00 - PWM3, 01 - PWM4, 10 - LCD_DOTCLK, 11 - NO_GATE.
SD_POWER_
GATE_GPIO
19–14 SD card power up delay required after enabling GPIO power gate: 000000 - 0 ms, 000001 - 10 ms, 000010
SD_POWER_UP_ - 20 ms, 111111 - 630 ms.
DELAY
13–12 SD card bus width: 00 - 4-bit, 01 - 1-bit, 10 - 8-bit, 11 - reserved.
SD_BUS_WIDTH
11–8 Index to the SSP clock speed
SSP_SCK_INDEX
0000 - invalid
0001 - 240kHz
0010 - 1Mhz
0011 - 2Mhz
0100 - 4Mhz
0101 - 6Mhz
0110 - 8Mhz
0111 - 10Mhz
1000 - 12Mhz
1001 - 16Mhz
1010 - 20Mhz
1011 - 30Mhz
1100 - 40Mhz
1101 - 48Mhz
1110 - 51.4Mhz (Max Frequency)
1111 - invalid
7 Blow to operate eMMC4.4 card in DDR mode.

EMMC_USE_DDR
6 Blow to disable SPI NOR fast reads which are used by default.
DISABLE_SPI_
NOR_FAST_
READ
5 Blow to enable USB boot serial number.
ENABLE_USB_
BOOT_SERIAL_
NUM


Field Description
4 Blow to enable unencrypted boot modes.
ENABLE_
UNENCRYPTED_
BOOT
3 Reserved - do not blow this bit.
RSRVD0
2 Blow to disable recovery boot mode.
DISABLE_
RECOVERY_
MODE
1–0 00-PWM; 01-AUART0; 10-I2C0; 11-Reserved;
USE_ALT_
DEBUG_UART_
PINS

(HW_OCOTP_ROM1)
Address: HW_OCOTP_ROM1 – 8002_C000h base + 1B0h offset = 8002_C1B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENABLE_NAND7_CE_RDY_
SD_INCREASE_INIT_SEQ_
SSP3_EXT_PULLUP
SSP2_EXT_PULLUP
SSP1_EXT_PULLUP
SSP0_EXT_PULLUP
UNTOUCH_INTERNAL_
R RSRVD2
SSP_PULLUP
PULLUP
PULLUP
PULLUP
PULLUP
PULLUP
PULLUP
PULLUP
PULLUP
TIME
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SD_CMD0_DISABLE
RSRVD1
RSRVD0
SD_INIT_SEQ_2_
SD_INIT_SEQ_1_
R
DISABLE
ENABLE
NUMBER_OF_
BOOT_SEARCH_COUNT BOOT_SEARCH_STRIDE
NANDS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Field Description
31–30 Reserved - do not blow this bit.
RSRVD2
29 Blow to indicate external pull-ups implemented for SSP3.
SSP3_EXT_
PULLUP
SSP2_EXT_
PULLUP
27 If the bit is blown then ROM NAND driver will enable internal pull-up for GPMI_CE7 and GPMI_RDY7 pins.
ENABLE_
NAND7_CE_
RDY_PULLUP
ENABLE_
NAND6_CE_
RDY_PULLUP
ENABLE_
NAND5_CE_
RDY_PULLUP
ENABLE_
NAND4_CE_
RDY_PULLUP
ENABLE_
NAND3_CE_
RDY_PULLUP
ENABLE_
NAND2_CE_
RDY_PULLUP
ENABLE_
NAND1_CE_
RDY_PULLUP
ENABLE_
NAND0_CE_
RDY_PULLUP
19 If this bit is blown then internal pull-ups for SSP are neither enabled nor disabled. This bit is used only if
UNTOUCH_ external pull-ups are implemented and ROM1:18 and/or ROM1:17 are blown.
INTERNAL_SSP_
PULLUP
SSP1_EXT_
PULLUP


Field Description
SSP0_EXT_
PULLUP
16 Blow to increase the SD card initialization sequence time from 1ms (default) to 4ms.
SD_INCREASE_
INIT_SEQ_TIME
15 Blow to enable the second initialization sequence for SD boot.
SD_INIT_SEQ_
2_ENABLE
14 Cmd0 (reset cmd) is called by default to reset the SD card during startup. Blow this bit to not reset the card
SD_CMD0_ during SD boot.
DISABLE
13 Blow to disable the first initialization sequence for SD.
SD_INIT_SEQ_
1_DISABLE
RSRVD1
11–8 Number of 64 page blocks that should be read by the boot loader.
BOOT_
SEARCH_
COUNT
7–4 the value of these bits is multiplied by 64 to get boot search stride. The default is 1 boot search stride, i.e.
BOOT_ 64 pages.
SEARCH_
STRIDE
RSRVD0
2–0 Encoded value indicates number of external NAND devices (0 to 7). Zero indicates ROM will probe for the
NUMBER_OF_ number of NAND devices connected in the system.
NANDS

(HW_OCOTP_ROM2)
Shadowed memory mapped access to OTP Bank 3, word 2 (ADDR = 0x1A).

Address: HW_OCOTP_ROM2 – 8002_C000h base + 1C0h offset = 8002_C1C0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
USB_VID USB_PID
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–16 USB Vendor ID.
USB_VID
15–0 USB Product ID
USB_PID

(HW_OCOTP_ROM3)
Shadowed memory mapped access to OTP Bank 3, word 3 (ADDR = 0x1B).
Address: HW_OCOTP_ROM3 – 8002_C000h base + 1D0h offset = 8002_C1D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD1[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOT_ACK
ALT_FAST_
FAST_
BOOT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD1
11 Enable the fast boot acknowledge.
FAST_BOOT_
ACK


Field Description
10 Enable the alternative fast boot mode.
ALT_FAST_
BOOT
RSRVD0

(HW_OCOTP_ROM4)
Shadowed memory mapped access to OTP Bank 3, word 4 (ADDR = 0x1C).
Address: HW_OCOTP_ROM4 – 8002_C000h base + 1E0h offset = 8002_C1E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MARKER_RESERVE
NAND_BADBLOCK_
R RSRVD0
NAND_READ_CMD_CODE2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
NAND_COLUMN_ NAND_ROW_ADDRESS_
NAND_READ_CMD_CODE1
ADDRESS_BYTES BYTES
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
31 If this bit is blown, the factory bad block marker preservation will be disabled.
NAND_
BADBLOCK_
MARKER_
RESERVE
RSRVD0
23–16 NAND flash read command confirm code.
NAND_READ_
CMD_CODE2


Field Description
15–8 NAND flash read command setup code.
NAND_READ_
CMD_CODE1
7–4 NAND flash column address cycles.
NAND_
COLUMN_
ADDRESS_
BYTES
3–0 NAND flash row address cycles.
NAND_ROW_
ADDRESS_
BYTES

(HW_OCOTP_ROM5)
Shadowed memory mapped access to OTP Bank 3, word 5 (ADDR = 0x1D).
Address: HW_OCOTP_ROM5 – 8002_C000h base + 1F0h offset = 8002_C1F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Shadow register for ROM-use word5 (Copy of OTP Bank 3, word 5 (ADDR = 0x1D)). These bits become
BITS read-only after the HW_OCOTP_LOCK[ROM_SHADOW] bit is set.

(HW_OCOTP_ROM6)
Shadowed memory mapped access to OTP Bank 3, word 6 (ADDR = 0x1E).

Address: HW_OCOTP_ROM6 – 8002_C000h base + 200h offset = 8002_C200h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Shadow register for ROM-use word6 (Copy of OTP Bank 3, word 6 (ADDR = 0x1E)). These bits become
BITS read-only after the HW_OCOTP_LOCK[ROM_SHADOW] bit is set.

(HW_OCOTP_ROM7)
Shadowed memory mapped access to OTP Bank 3, word 7 (ADDR = 0x1F).
Address: HW_OCOTP_ROM7 – 8002_C000h base + 210h offset = 8002_C210h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARM_PLL_DISABLE
FORCE_RECOVERY_
R RSRVD2
DISABLE
HAB_ RECOVERY_BOOT_MODE
CONFIG [19:16]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENABLE_SSP_12MA_
ENABLE_PIN_BOOT_
RESET_USB_PHY_
RSRVD1
I2C_USE_400KHZ
ENABLE_ARM_
MMU_DISABLE
HAB_DISABLE
AT_STARTUP
R RSRVD0
ICACHE
CHECK
DRIVE
RECOVERY_BOOT_MODE
[15:12]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Field Description
RSRVD2
23 0 - Force Recovery Enable
FORCE_
1 - Force Recovery Disable
RECOVERY_
DISABLE
22 0 - Not disabled : ARM core will run at 240MHz for high speed boot
ARM_PLL_
1 - Disabled : ARM core will run at xtal 24MHz for boot
DISABLE
21–20 00 - HAB_FAB : Blank out of FAB
HAB_CONFIG
01 - HAB_OPEN : For non-secure shipping products, or secure products under development., the ROM will
boot the image even if the HAB authentication fails.
Other - HAB_CLOSED : For the end product, the ROM will not boot unless the image passes the HAB
authentication.
19–12 If USB is not desirable for recovery boot mode then these bits can be blown to have the ROM boot from a
RECOVERY_ non-USB device in recovery mode.
BOOT_MODE
11 0 - HAB is enabled in default
HAB_DISABLE
1 - HAB is disabled

RSRVD1
9 Blow to reset the USBPHY at startup This bit will be listed as Reserved in the Data Sheet.
RESET_USB_
PHY_AT_
STARTUP
8 Blow to force SSP pins to drive 12mA, default is 4mA.
ENABLE_SSP_
12MA_DRIVE
RSRVD0
3 Blow to force the I2C to be programmed by the boot loader to run at 400KHz, 100KHz is the default.
I2C_USE_
400KHZ
2 Blow to enable the ARM 926 ICache during boot.
ENABLE_ARM_
ICACHE
1 0 - MMU and D-Cache are enabled during boot.
MMU_DISABLE
1 - MMU and D-Cache are disabled during boot.
0 Blow to enable boot loader to first test the LCD_RS pin to determine if pin boot mode is enabled. If this bit
ENABLE_PIN_ is blown, and LCD_RS is pulled high, then boot mode is determined by the state of LCD_D[5:0] pins. If this
BOOT_CHECK bit is not blown, skip testing the LCD_RS pin and go directly to determining boot mode by reading the state
of LCD_D[5:0].

20.4.35 Shadow Register for OTP Bank4 Word0 (Data Use 0)

(HW_OCOTP_SRK0)
Address: HW_OCOTP_SRK0 – 8002_C000h base + 220h offset = 8002_C220h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_OCOTP_SRK0 field descriptions

Field Description
31–0 Shadow register for the hash of the Super Root Key word0. If HAB is not required, these fuses can be used
BITS for other purposes (Copy of OTP Bank 4, word 0 (ADDR = 0x20)). These bits become read-only after the
HW_OCOTP_LOCK[SRK_SHADOW] bit is set.

(HW_OCOTP_SRK1)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description


(HW_OCOTP_SRK2)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description

(HW_OCOTP_SRK3)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description


(HW_OCOTP_SRK4)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description

(HW_OCOTP_SRK5)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description


(HW_OCOTP_SRK6)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description

(HW_OCOTP_SRK7)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description

20.4.43 OTP Controller Version Register (HW_OCOTP_VERSION)

of the block.
Address: HW_OCOTP_VERSION – 8002_C000h base + 2A0h offset = 8002_C2A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MAJOR MINOR STEP

W
Re- 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_OCOTP_VERSION field descriptions

Field Description
MAJOR
MINOR
STEP


Chapter 21
Performance Monitor (PERFMON)
21.1 Overview
The i.MX28 implements a real time systerm performance monitor, it provides the following
functions:
• Real-time performance statistics collection on AXI buses.
• Single or multiple master transactions monitoring.
• Various interrupts support: address trap, latency threshold, and so on.
• AXI protocol and out-of-order sequence support.
The performance monitor is illustrated in Figure 21-1.
Performance
Monitor M
LCDIF
Axi0 - 200MHz (PL301)
64
AHB_ARB1
AHB_ARB2
AHB_ARB3
M
PXP
64
M
DCP
64
M
BCH
64
SYNC/
ASYNC
EMI – DDR2-400, LV-DDR2-400, LP-DDR1-400
Figure 21-1. Block diagram of PerfMon

Operation
21.2 Operation
The role of the performance monitor in an AXI system is to collect real time bus transaction
statistics, including transaction average and maximum latency, total data bandwidth, and
total active cycles. The statistics collection can be configured for single master or multiple
masters on the same AXI bus, and can be enabled for either read or write transactions.
There is one AXI bus in the i.MX28 system which has DCP, PXP, LCDIF and BCH.
AXI protocol supports out-of-order transaction completion. In i.MX28, out-of-order
transaction is programmable in EMI. Tag ID is used to trace each transaction and match
the data phase with the correct address phase. Performance Monitor supports out-of-order
transactions. AXI protocol separates the address/control phase and data phase, and has the
ability to issue multiple outstanding addresses. It gives an ID tag to every transaction across
the interface, which consists 4-bit master ID and 4-bit subID. Every master has its own
unique master ID, and each master could have up to 16 sub IDs, which means up to 16
outstanding address phases.
PerfMon collects the accumulated latency on cycle counts and number of transfers, the
average latency can be calculated by dividing the total latency over number of transfers.
Since the AXI protocol separates the address and data phases, the address and data phases
could be overlapped, and individual data phase could overlap with multiple address phase.
Statistics on total cycles, total data transfer in bytes will be collected as well. All statistics
are collected for either read or write transactions, which could be switched by the enable
bit in the control register.
To calculate the maximum latency and support out-of-order transaction, PerfMon needs to
cache the tag ID for all the outstanding requests. The potential number of outstanding
requests depends on how deep the command queue in the memory controller(EMI) which
includes two level of command queues. A scoreboard will be implemented to match the tag
ID of the ongoing data phase with the ID from the outstanding requests. PerfMon snapshots
the master ID(8 bits), burst length(4 bits), burst type(2 bits), burst size(3 bits) for the content
register of maximum latency, but no transfer address(32 bits).
Registers in PerfMon are accessible through APBH bridge, and PerfMon registers sits on
APBH clock domain. Shade registers are added for the coherence among statistics/status
registers, and the snapshot bit in PerfMon control register will trigger the shade register
being filled at the same cycle for these registers: total transfers, total latency, maximum
latency, content register for max_latency, total data bytes, total active cycles, and total
cycles.
Various interrupts supported in this module are as follows:

Chapter 21 Performance Monitor (PERFMON)
1. Address trap IRQ. IRQ will be asserted if any transaction address hit within the
pre-configured address range.
2. Address range inversion IRQ. IRQ will be asserted if any transaction address hit outside
the pre-configured address range.
3. Max latency threshold IRQ: IRQ will be asserted if maximum latency is above the value
defined in the threshold register.
4. Bus error IRQ: IRQ will be asserted if any AXI transaction triggers an error response.

PERFMON Hardware Register Format Summary
HW_PERFMON memory map
Absolute
Width Section/
(in bits) page
(hex)
8000_6000 PerfMon Control Register (HW_PERFMON_CTRL) 32 R/W C000_0000h 21.3.1/1466
8000_6010 PerfMon Master Enable Register 32 R/W 0000_0000h 21.3.2/1468
(HW_PERFMON_MASTER_EN)
8000_6020 PerfMon Trap Range Low Address Register 32 R/W 0000_0000h 21.3.3/1469
(HW_PERFMON_TRAP_ADDR_LOW)
8000_6030 PerfMon Trap Range High Address Register 32 R/W 0000_0000h 21.3.4/1469
(HW_PERFMON_TRAP_ADDR_HIGH)
8000_6040 PerfMon Latency Threshold Register 32 R/W 0000_0000h 21.3.5/1470
(HW_PERFMON_LAT_THRESHOLD)
8000_6050 PerfMon AXI Active Cycle Count Register 32 R 0000_0000h 21.3.6/1470
(HW_PERFMON_ACTIVE_CYCLE)
8000_6060 PerfMon Transfer Count Register 32 R 0000_0000h 21.3.7/1471
(HW_PERFMON_TRANSFER_COUNT)
8000_6070 PerfMon Total Latency Count Register 32 R 0000_0000h 21.3.8/1472
(HW_PERFMON_TOTAL_LATENCY)
8000_6080 PerfMon Total Data Count Register 32 R 0000_0000h 21.3.9/1472
(HW_PERFMON_DATA_COUNT)
8000_6090 PerfMon Maximum Latency Register 32 R 0000_0000h 21.3.10/1473
(HW_PERFMON_MAX_LATENCY)
8000_60A0 PerfMon Debug Register (HW_PERFMON_DEBUG) 32 R/W 0000_0001h 21.3.11/1473
8000_60B0 PerfMon Version Register (HW_PERFMON_VERSION) 32 R 0100_0000h 21.3.12/1474

21.3.1 PerfMon Control Register (HW_PERFMON_CTRL)

The PerfMon Control Register specifies the reset state and the interrupt controls for the
Performance Monitor.
HW_PERFMON_CTRL: 0x000
HW_PERFMON_CTRL_SET: 0x004
HW_PERFMON_CTRL_CLR: 0x008
HW_PERFMON_CTRL_TOG: 0x00C
This register controls various funcitons of the systerm performance monitor.
EXAMPLE
// turn off soft reset and clock gating

HW_PERFMON_CTRL_CLR(BM_PERFMON_CTRL_SFTRST| BM_PERFMON_CTRL_CLKGATE);
Address: HW_PERFMON_CTRL – 8000_6000h base + 0h offset = 8000_6000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD2 IRQ_MID
CLKGATE
SFTRST
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LATENCY_IRQ
TRAP_IRQ_
TRAP_IRQ
TRAP_IN_
READ_EN
BUS_
LATENCY_
LATENCY_
R RSVD1
ENABLE
RANGE
ENABLE
BUS_
IRQ_EN
TRAP_
ERR_
EN
ERR_ CLR SNAP RUN

IRQ_
W IRQ
EN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_PERFMON_CTRL field descriptions

Field Description
31 Set to zero for normal operation. When this bit is set to one (default), then the entire block is held in its reset
SFTRST state.
0x0 RUN — Allow PerfMon to operate normally.
0x1 RESET — Hold PerfMon in reset.
CLKGATE
0x0 RUN — Allow PerfMon to operate normally.
0x1 NO_CLKS — Do not clock PerfMon gates in order to minimize power consumption.
29–24 Always set this bit field to zero.
RSVD2

HW_PERFMON_CTRL field descriptions (continued)

Field Description
23–16 This field contains the master ID and sub ID associated with the interrupt. If multiple IRQs, it is the ID
IRQ_MID associated the first IRQ transaction, and will not update until the IRQ being cleared.

RSVD1
12 This bit is set if there is error on any AXI transaction and the BUS_ERR_IRQ_EN bit is set.
BUS_ERR_IRQ
11 This status bit is set if maximum latency is above the value defined in the latency threshold register and the
LATENCY_IRQ LATENCY_ENABLE bit is set. Writing a one to its SCT clear address to clear it.
10 This status bit is set to indicate that an address trap occurs. This bit is cleared by software by writing a one
TRAP_IRQ to its SCT clear address. This bit is set if axi address is within the pre-configured address range and the trap
function is enabled with TRAP_ENABLE bit.
9 Enables the PerfMon AXI BUS ERROR IRQ. When an error occurs and this bit is set, an interrupt is sent to
BUS_ERR_IRQ_ the ARM core.
EN
8 Enables the PerfMon Latency threshold IRQ. When an error occurs and this bit is set, an interrupt is sent
LATENCY_IRQ_ to the ARM core.
EN
7 Enables the PerfMon Address Trap IRQ. When an trap occurs and this bit is set, an interrupt is sent to the
TRAP_IRQ_EN ARM core.
6 Enables the PerfMon AXI latency threshold functions. When a transfer latency larger than the threshold and
LATENCY_ this bit is set, the LATENCY_IRQ status bit will be set.
ENABLE
5 Determines whether the debug trap function causes a match when the master address is inside (low-address
TRAP_IN_ <= current-address <= high-address) the specified range.
RANGE
0 = The trap occurs when the master address falls outside of the range.
1 = The check is inside the range.
4 Enables the PerfMon AXI address trap functions. When a trap occurs and this bit is set, the TRAP_IRQ
TRAP_ENABLE status bit will be set.
3 Set this bit to One to monitor all Read transactions, set to zero to monitor all Write transactions.
READ_EN
0 = performance monitoring on all WRITE activities.
1 = performance monitoring on all READ activities.
2 Set this bit to clear all the PerfMon's statistics registers. This bit will be reset to 0 once the clear process is
CLR done.
1 Set this bit to snap shot PerfMon's statistics registers into the shadow registers for reads. PerfMon will
SNAP continue collecting and updating statistics registers. This bit will be reset to 0 once the snapshot processing
is done.
0 Set this bit to one to enable the PerfMon operation.

RUN
0x0 HALT — No PerfMon command in progress.
0x1 RUN — Process Performance monitoring.

21.3.2 PerfMon Master Enable Register (HW_PERFMON_MASTER_EN)

The Master Enable register defines single or multiple MasterIDs to be monitored by Perfmon.
The master ID of PXP is 0, LCDIF is 1, BCH is 2 and DCP is 3.
Address: HW_PERFMON_MASTER_EN – 8000_6000h base + 10h offset = 8000_6010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD0
MID15
MID14
MID13
MID12
MID11
MID10
MID9
MID8
MID7
MID6
MID5
MID4
MID3
MID2
MID1
MID0
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_PERFMON_MASTER_EN field descriptions

Field Description
RSVD0
15 Set to 1 to enable performancce monitoring and statistics collection on MasterID 15.
MID15
MID14
MID13
MID12
MID11
MID10
MID9
MID8
MID7
MID6
MID5
MID4
MID3

HW_PERFMON_MASTER_EN field descriptions (continued)

Field Description
MID2
MID1
MID0
21.3.3 PerfMon Trap Range Low Address Register

(HW_PERFMON_TRAP_ADDR_LOW)
that can be enabled to trigger an interrupt to the ARM core when an AXI cycle occurs within
this range.
Address: HW_PERFMON_TRAP_ADDR_LOW – 8000_6000h base + 20h offset = 8000_
6020h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_PERFMON_TRAP_ADDR_LOW field descriptions

Field Description
ADDR
21.3.4 PerfMon Trap Range High Address Register

(HW_PERFMON_TRAP_ADDR_HIGH)
The Trap Range High Address Register defines the upper bound for an address range that
can be enabled to trigger an interrupt to the ARM core when an AXI cycle occurs within
this range.

Address: HW_PERFMON_TRAP_ADDR_HIGH – 8000_6000h base + 30h offset = 8000_

6030h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ADDR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_PERFMON_TRAP_ADDR_HIGH field descriptions

Field Description
ADDR
21.3.5 PerfMon Latency Threshold Register

(HW_PERFMON_LAT_THRESHOLD)
The latency threshold Register defines the threshold for AXI transaction latency that can
be enabled to trigger an interrupt to the ARM core when an AXI transaction latency is above
this value.
Address: HW_PERFMON_LAT_THRESHOLD – 8000_6000h base + 40h offset = 8000_
6040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD0
VALUE
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_PERFMON_LAT_THRESHOLD field descriptions

Field Description
RSVD0
11–0 This field contains the 12-bit transaction latency threshold.
VALUE
21.3.6 PerfMon AXI Active Cycle Count Register

(HW_PERFMON_ACTIVE_CYCLE)
The active cycle count register counts the number of AXI cycles during which a transaction
is active on AXI bus.

This register counts the number of AXI cycles in which a master was requesting a transfer,
and the slave had not responded. This is including cycles in which it was requesting transfers
but was not accepted by slave yet. The master enable register
HW_PERFMON_MASTER_EN are used to mask which master(s) cycles are actually
recorded here.
Address: HW_PERFMON_ACTIVE_CYCLE – 8000_6000h base + 50h offset = 8000_6050h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_PERFMON_ACTIVE_CYCLE field descriptions

Field Description
31–0 This field contains the total active AXI cycle counts. If overflow, the value will be 0xFFFFFFFF.
COUNT
21.3.7 PerfMon Transfer Count Register

(HW_PERFMON_TRANSFER_COUNT)
The transfer count register defines the total number of transfers has been completed during
the whole monitoring period.
Divide the register HW_PERFMON_LATENCY_CYCLE value over this value of this
register will give the average latency for each transfer.
Address: HW_PERFMON_TRANSFER_COUNT – 8000_6000h base + 60h offset = 8000_
6060h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VALUE
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_PERFMON_TRANSFER_COUNT field descriptions

Field Description
31–0 This field contains the total amount transfers. If overflow, the value will be 0xFFFFFFFF.
VALUE

21.3.8 PerfMon Total Latency Count Register

(HW_PERFMON_TOTAL_LATENCY)
The transfer count register defines the total number of latency in cycles during the monitoring
period.
Divide the register value over value of register HW_PERFMON_TRANSFER_COUNT
will give the average latency for each transfer.
Address: HW_PERFMON_TOTAL_LATENCY – 8000_6000h base + 70h offset = 8000_
6070h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_PERFMON_TOTAL_LATENCY field descriptions

Field Description
31–0 This field contains the total latency in cycle counts. If overflow, the value will be 0xFFFFFFFF.
COUNT
21.3.9 PerfMon Total Data Count Register

(HW_PERFMON_DATA_COUNT)
The data count register defines the total number of data transfered in bytes during the
monitoring period.
Address: HW_PERFMON_DATA_COUNT – 8000_6000h base + 80h offset = 8000_6080h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_PERFMON_DATA_COUNT field descriptions

Field Description
31–0 This field contains the total bytes of data transfered. If overflow, the value will be 0xFFFFFFFF.
COUNT

21.3.10 PerfMon Maximum Latency Register

(HW_PERFMON_MAX_LATENCY)
The maximum latency register contains the maximum latency in cycles and control signals
for this transaction during the monitoring period.
Address: HW_PERFMON_MAX_LATENCY – 8000_6000h base + 90h offset = 8000_
6090h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R ABURST ALEN ASIZE TAGID[22:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAGID
R RSVD0 COUNT
[15:15]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_PERFMON_MAX_LATENCY field descriptions

Field Description
31–30 This field contains axi_aburst signal associated with the worst latency transaction.
ABURST
29–26 This field contains axi_alen signal associated with the worst latency transaction.
ALEN
25–23 This field contains axi_asize signal associated with the worst latency transaction.
ASIZE
22–15 This field contains the master id and sub id associated with the worst latency transaction.
TAGID
RSVD0
11–0 This field contains the worst transfer latency. If overflow, the value will be 0xFFF.
COUNT
21.3.11 PerfMon Debug Register (HW_PERFMON_DEBUG)

The debug register is for internal use only.
Divide the register HW_PERFMON_LATENCY_CYCLE value over this value of this
register will give the average latency for each transfer.

Address: HW_PERFMON_DEBUG – 8000_6000h base + A0h offset = 8000_60A0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD[15:2]
CLR_EN
CYCLE_
TOTAL_
ERR_
MID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
HW_PERFMON_DEBUG field descriptions

Field Description
RSVD
1 This field is for debug purpose. Set to 1 to clear the internal total cycle register no matter there is pending
TOTAL_CYCLE_ request or not when the clear bit in control register is set.
CLR_EN
0 This field is for debug purpose. Set to 0 will not record the MID for bus error irq.
ERR_MID
21.3.12 PerfMon Version Register (HW_PERFMON_VERSION)

This register always returns a known read value for debug purposes. It indicates the version
of the block.
EXAMPLE
if (HW_PERFMON_VERSION.B.MAJOR != 1) Error();
Address: HW_PERFMON_VERSION – 8000_6000h base + B0h offset = 8000_60B0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MAJOR MINOR STEP

W
Re- 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

HW_PERFMON_VERSION field descriptions

Field Description
MAJOR
MINOR
STEP


Chapter 22
Real-Time Clock Alarm Watchdog Persistent Bits
22.1 RTC Overview

The real-time clock (RTC) and alarm share a one-second pulse time domain. The watchdog
reset and millisecond counter run on a one-millisecond time domain. The RTC, alarm, and
persistent bits use persistent storage and reside in a special power domain (crystal domain)
that remains powered up even when the rest of the chip is in its powered-down state. Figure
22-1 illustrates this block.
Note
The term power-down, as used here, refers to a state in which the
DC-DC converter and various parts of the crystal power domain
are still powered up, but the rest of the chip is powered down. If
the battery is removed, then the persistent bits, the alarm value,
and the second counter value will be lost. The crystal power
domain powers both the 32-KHz and 24-MHz crystals.
Upon battery insertion, the crystals (32-KHz and 24-MHz) are in a quiescent state. The
activation of these crystals is under software control through the RTC persistent bits, as
described later in this chapter.
• The XTAL32KHZ_PWRUP bit in the Persistent Register 0 controls the activity of the
32-KHz crystal at all times (chip power on or off).
• The XTAL24MHZ_PWRUP bit in the Persistent Register 0 controls the behavior of
the 24-MHz crystal during the power-off state. (The 24-MHz crystal is always on when
the chip is powered up.)
The one-second time base is derived either from the 24.0-MHz crystal oscillator or a 32-KHz
crystal oscillator (which can be either exactly 32.0 KHz or 32.768 KHz), as controlled by
bits in Persistent Register 0. The time base thus generated is used to increment the value of

RTC Overview
the persistent seconds count register. Like the values of the other persistent registers, the
value of the persistent seconds count register is not lost across a power-down state and will
continue to count seconds during that time.
Contrary to the one-second time base, no record or count is made of the one-millisecond
time base in the crystal power domain. The one-millisecond time base is always derived
from the 24.0-MHz crystal oscillator, but is not available when the chip is powered down.
The real-time clock seconds counter, alarm functions, and persistent bit storage are kept in
the (always on) crystal power domain. Shadow versions of these values are maintained in
the CPU's power and APBX clock domain when the chip is in the power-up state. When
the chip transitions from power-off to power-on, the master values are copied to shadow
registers by the copy controller. Whenever software writes to a shadow register, then the
copy controller copies the new value into the master register in the crystal oscillator power
domain.
Some of the persistent bits are used to control features that can continue to operate after
power-down, such as the second counter and the alarm function and bits in the
HW_RTC_PERSISTENT0 register. The bits in registers HW_RTC_PERSISTENT1 through
HW_RTC_PERSISTENT5 are available to store application state information over
power-downs and are completely software-defined.

Chapter 22 Real-Time Clock Alarm Watchdog Persistent Bits
ARM Core SRAM
AHB
24-MHz
AHB Slave AHB Master Divide XTAL
by n Osc.
1/768 = 31250Hz
Shared DMA
AHB-to-APBX Bridge
APBX Master 32.768 or
32.000
kHz
XTAL
APBX
RTC/Watchdog/Alarm/ Copy Osc.1

Persistent I/O controller
32-Bit Shadow Persistent 0 32-Bit Master Persistent 0

32-Bit Alarm Shadow 32-Bit Alarm Master
Alarm Event
==
32-Bit RTC Shadow Counter 32-Bit RTC Seconds
1 Hz 1 Hz
Divide by appropriate value

Crystal Power and Clock Domain
1 kHz
fixed divide by 24000
Figure 22-1. RTC, Watchdog, Alarm, and Persistent Bits Block Diagram
Immediately after reset, it will take approximately three milliseconds for the copy controller
to complete the copy process from the analog domain to the digital domain. Software cannot
rely on the contents of the seconds counter, alarm, or persistent bits until this copy is
complete. Therefore, software must wait until all bits of interest in the
HW_RTC_STAT_STALE_REGS field have been reset to 0 by the copy controller before
reading the initial state of these values (see Figure 22-2). The order in which registers are
updated is Persistent 0, 1, 2, 3, 4, 5, Alarm, Seconds. (This list is in bitfield order, from LSB
to MSB, as they would appear in the STALE_REGS and NEW_REGS bitfields of the
HW_RTC_STAT register. For example, the Seconds register corresponds to STALE_REGS
or NEW_REGS containing 0x80.)
rtc_init Call during initialization
HW_RTC_CTRL_SFTRST_WRITE (BM_RTC_CTRL_SFTRST);
HW_RTC_CTRL_CLKGATE_WRITE (BM_RTC_CTRL_CLKGATE);
Remove soft reset and clock gate.
Return This releases the copy controller.
Figure 22-2. RTC Initialization Sequence

Programming and Enabling the RTC Clock
22.2 Programming and Enabling the RTC Clock

The RTC functions implemented in the crystal power domain are referred to as RTC analog
functions. The clock frequency and clock source for the RTC analog functions are
programmable. There are three possible clock options.
• If the HW_RTC_PERSISTENT0_CLOCKSOURCE bit is set to 0, these functions
operate on a clock domain derived from the 24.0-MHz crystal oscillator divided by 768
to yield 31.250 KHz.
• If the HW_RTC_PERSISTENT0_CLOCKSOURCE bit is 1 and the
HW_RTC_PERSISTENT0_XTAL32_FREQ bit is 0, then the optional external driving
crystal clock will be used and its frequency should be 32.768 KHz.
• However, if the HW_RTC_PERSISTENT0_CLOCKSOURCE is 1 and the
HW_RTC_PERSISTENT0_XTAL32_FREQ bit is also 1, then the external crystal
generated clock should be 32.000 KHz for correct operation.
Thus, the HW_RTC_PERSISTENT0_XTAL32_FREQ bit gives the systems designer some

flexibility as to which external crystal to use on the board.
Switching between these two clock domains is handled by a glitch-free clock mux and can
be done on the fly. The 1-Hz time base is derived by dividing either 32.768 KHz by 32768
or by dividing 31.250 KHz by 31,250, or by dividing 32.000 KHz by 32000.
By reading and examining the HW_RTC_STAT_XTAL32000_PRESENT and
HW_RTC_STAT_XTAL32768_PRESENT bits, software can discover if there is an optional
crystal clock present and the frequency at which it runs (32.768 KHz or 32.000 KHz). Only
one of these fuse bits will be asserted if there is such a crystal attached. If there is no crystal
present, both bits will be deasserted.
22.3 RTC Persistent Register Copy Control

The copying of a persistent shadow register (digital) to persistent master storage (analog)
occurs automatically. This automatic write-back that occurs for each register as the copy
controller services writes to the shadow registers can lead to some very long timing loops
if efficient write procedures are not used. Writing all eight shadow registers can take several
milliseconds to complete. Do not attempt to write to more than one shadow register
immediately before power down. Whenever possible, software should ensure that the
HW_RTC_STAT_NEW_REGS field is 0 before powering down the chip or setting the

HW_RTC_CTRL_SFTRST bit. Otherwise, some of the write data could be lost because
the shadow registers could be powered down/reset before the new values can be copied to
the persistent master storage.
Registers are copied between the digital and analog sides one by one and in 32-bit words.
There are no hardwired uses for any of the bits of Persistent registers 1 through 5. Therefore,
the bits in these registers can be defined and set by the software. Persistent Register 0 is
reserved for hardware programming and configuration.
Before a new value is written to a shadow register by the CPU, software must first confirm
that the corresponding bit of HW_RTC_STAT_NEW_REGS is 0. This ensures that a value
previously written to the register has been completely handled by the copy state machine.
Failure to obey this constraint could cause a newer updated value to be lost.
NOTE: The HW_RTC_CTRL_SUPPRESS_COPY2ANALOG diagnostic bit is never set
while any copy or update operation is underway. Doing so will result in undefined operation
of the copy controller.
Figure 22-3 shows the copy and test procedure for a single register. However, software can
write to any register whose HW_RTC_STAT_NEW_REGS bit is 0 even if the copy
controller is currently busy copying a different register. For example, if the copy controller
is busy copying Persistent Register 1 from a previous write, software can simultaneously
write to Persistent Register 0 during this copy. After the copy controller has finished copying
register 1, it will then, in turn, begin the copy process for the new value of Register 0.
Therefore, registers can thus be written in any order. Again, the main important rule that
must be followed is that the HW_RTC_STAT_NEW_REGS bit for a particular register
must be 0 before it can be written and is independent of the state of the
HW_RTC_STAT_NEW_REGS bits for the other registers.
How to write a master
register.
rtc_write2master
TestValue = HW_RTC_STAT _NEW_REGS
Extract corresponding bit.
NO
TestValue == 0 Wait for previous write
to this register to
YES complete.
HW_RTC_PERSISTENT2_WR(0xdeadbeef); Write new value to shadow

that will be automatically
copied to analog side. Use
this same technique for
TestValue =HW_RTC_STAT_NEW_REGS
milliseconds, alarm, or other
persistent registers.
NO
TestValue == 0
Return
Figure 22-3. RTC Writing to a Master Register from CPU

Real-Time Clock Function
The digital shadow registers will be updated (copied from analog to digital) with values
from their analog persistent counterparts under two conditions: first, whenever the chip is
powered on, and second, whenever the HW_RTC_CTRL_FORCE_UPDATE bit is set by
the software. Then, an update occurs, and all persistent registers are updated. Persistent
registers cannot be updated singly.
22.4 Real-Time Clock Function

The real-time clock is a CPU-accessible, continuously-running 32-bit counter that increments
every second and that can be derived from either the 24-MHz clock or the 32-KHz clock,
as determined by writable bit values in the RTC Persistent Register 0.
A 32-bit second counter has enough resolution to count up to 136 years with one-second
increments. The RTC can continue to count time as long as a voltage is applied to the BATT
pin, irrespective of whether the rest of the chip is powered up. The normal digital reset has
no effect on the master RTC registers located in the crystal power and clock domain. A
special first-power-on reset establishes the default value of the master RTC registers when
a voltage is first applied to the BATT pin (battery insertion).
For consistency across applications, it is recommended that the seconds timer should be
referenced to January 1, 1980 at a 32-bit value of 0 (same epoch reference as PC) in
applications that use it as a time-of-day clock. If the real-time clock function is not present
on a specific chip, as indicated in the control and status register
(HW_RTC_STAT_RTC_PRESENT), then no real-time epoch is maintained over
power-down cycles.
22.4.1 Behavior During Reset

CLKGATE bit fields.
22.5 Millisecond Resolution Timing Function

A millisecond counter facility is provided based on a 1-KHz signal derived from the 24-MHz
clock. The count value is neither maintained nor incremented during power-down cycles.
At each power-up, this register is set to its reset state. On each tick of the 1-KHz source,
the milliseconds counter increments. With a 32-bit counter, a kernel can run up to

4,294,967,294 milliseconds or 49.7 days before it must deal with a counter wrap. The
programmer can change the resolution of the millisecond counter to be 1, 2, 4, 8, or 16
milliseconds. This is programmed through bits in Persistent Register 0.
CAUTION: When the 32.768-KHz or 32.000-KHz crystal oscillator is selected as the
source for the seconds counter, an anomaly is created between the time intervals of the
millisecond counter and the seconds counter. That is, the manufacturing tolerance of the
two crystals are such that 1000 millisecond counter increments are not exactly one second
as measured by the real-time clock seconds counter.
22.6 Alarm Clock Function

The alarm clock function allows an application to specify a future instant at which the chip
should be awakened, that is, if powered down, it can be powered up. The alarm clock setting
is a CPU-accessible, 32-bit value that is continuously matched against the 32-bit real-time
clock seconds counter. When the two values are equal, an alarm event is triggered. Persistent
bits indicate whether an alarm event should power up the chip from its powered-down state.
In addition to or instead of powering up the chip, the alarm event can also cause a CPU
interrupt. Although these two functions can be enabled at the same time, one should
remember that the CPU will only be interrupted if the chip is powered up at the time of the
alarm event.
NOTE: If the alarm is set to power up the chip in the event of an alarm and such an event
occurs, then the only record of the cause of the wake-up is located in the analog side. At
power-up, the analog side registers are copied to the digital shadow registers and the
ALARM_WAKE bit in the Persistent register 0 is visible in the digital shadow register. If
an alarm wake event occurs while the chip is powered up, the ALARM_WAKE bit will not
be set in the persistent register because the chip was not woken up.
The alarm must be present on an actual chip to perform this function (see the
HW_RTC_STAT_ALARM_PRESENT bit description).
22.7 Watchdog Reset Function

The watchdog reset is a CPU-configurable device. It is programmed by software to generate
a chip-wide reset after HW_RTC_WATCHDOG milliseconds. The watchdog generates
this reset if software does not rewrite this register before this time elapses.

The watchdog timer decrements the register value once for every tick of the 1-KHz clock
supplied from the RTC analog section (see Figure 22-1). The reset generated by the watchdog
timer has no effect on the values retained in the master registers of the real-time clock
seconds counter, alarm, or persistent registers (analog persistent storage).
The watchdog timer is initially disabled and set to count 4,294,967,295 milliseconds before
generating a watchdog reset.
The watchdog timer does not run when the chip is in its powered-down state. Therefore,
there is no master/shadow register pairing for the watchdog timer, and it must be
reprogrammed after cycling power or resetting the block.
The watchdog timer must be "present" on an actual chip to perform this function (see the
HW_RTC_STAT_WATCHDOG_PRESENT bit description).

RTC Hardware Register Format Summary
HW_RTC memory map
Absolute
Width Section/
(in bits) page
(hex)
8005_6000 Real-Time Clock Control Register (HW_RTC_CTRL) 32 R/W C000_0020h 22.8.1/1485
8005_6010 Real-Time Clock Status Register (HW_RTC_STAT) 32 R E0FF_0000h 22.8.2/1486
8005_6020 Real-Time Clock Milliseconds Counter 32 R/W 0000_0000h 22.8.3/1488
(HW_RTC_MILLISECONDS)
8005_6030 Real-Time Clock Seconds Counter (HW_RTC_SECONDS) 32 R/W 0000_0000h 22.8.4/1489
8005_6040 Real-Time Clock Alarm Register (HW_RTC_ALARM) 32 R/W 0000_0000h 22.8.5/1490
8005_6050 Watchdog Timer Register (HW_RTC_WATCHDOG) 32 R/W FFFF_FFFFh 22.8.6/1491
8005_6060 Persistent State Register 0 (HW_RTC_PERSISTENT0) 32 R/W 0000_0100h 22.8.7/1492
8005_60A0 Persistent State Register 4 (HW_RTC_PERSISTENT4) 32 R/W 0000_0000h 22.8.11/1497
8005_60B0 Persistent State Register 5 (HW_RTC_PERSISTENT5) 32 R/W 0000_0000h 22.8.12/1497
8005_60C0 Real-Time Clock Debug Register (HW_RTC_DEBUG) 32 R/W 0000_0000h 22.8.13/1498
8005_60D0 Real-Time Clock Version Register (HW_RTC_VERSION) 32 R 0203_0000h 22.8.14/1499

22.8.1 Real-Time Clock Control Register (HW_RTC_CTRL)

HW_RTC_CTRL is the control register for the RTC.
HW_RTC_CTRL: 0x000
HW_RTC_CTRL_SET: 0x004
HW_RTC_CTRL_CLR: 0x008
HW_RTC_CTRL_TOG: 0x00C
The contents of this register control the operation of the RTC portions implemented as an
APBX peripheral running in the APBX clock domain. These functions only operate when
the chip is in its full power up state.
EXAMPLE
HW_RTC_CTRL_CLR(BM_RTC_CTRL_SFTRST); // remove the soft reset condition

HW_RTC_CTRL_CLR(BM_RTC_CTRL_CLKGATE); // enable clocks within the RTC
HW_RTC_CTRL_CLR(BM_RTC_CTRL_ALARM_IRQ); // reset the alarm interrupt by clearing
its status bit
Address: HW_RTC_CTRL – 8005_6000h base + 0h offset = 8005_6000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD0[29:16]
CLKGATE
SFTRST
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FORCE_UPDATE
ONEMSEC_IRQ_
ALARM_IRQ_EN
ONEMSEC_IRQ
COPY2ANALOG
ALARM_IRQ
WATCHDOGEN
R RSVD0[15:7]
SUPPRESS_
EN
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
HW_RTC_CTRL field descriptions

Field Description
31 1= Hold real time clock digital side in soft reset state. This bit has no effect on the RTC analog.
SFTRST
30 This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block. This
CLKGATE bit has no effect on RTC analog.

HW_RTC_CTRL field descriptions (continued)

Field Description
29–7 Reserved, write only zeroes.
RSVD0
6 This bit is used for diagnostic purposes. 1= suppress the automatic copy that normally occurs to the analog
SUPPRESS_ side, whenever a shadow register is written. 0= Normal operation. Use SCT writes to set, clear, or toggle.
COPY2ANALOG
5 This bit is how the software requests the update of the shadow registers from values in RTC analog. When
FORCE_UPDATE software sets this bit, all eight of the shadow registers are updated from the corresponding values in the
persistent registers in RTC analog. The state of this update operation is reflected on the STALEREGS bits
on the STAT register, which are set to all ones upon an update request and are cleared by hardware as the
update proceeds. Hardware clears this bit immediately after detecting it has been set. Software does not
need to clear. Software must NOT look to the state of this bit to determine the status of the update operation,
it must look to the STALEREG bits in the STAT register to determine when any given register has been
updated and/or when the update operation is complete. Notice that the default value of this bit is 1, so that
that a reset (either chip-wide or soft) always results in an update.
4 1= Enable Watchdog Timer to force chip wide resets. Use SCT writes to set, clear, or toggle.
WATCHDOGEN
3 1= one millisecond interrupt request status. Use SCT writes to clear this interrupt status bit.
ONEMSEC_IRQ
2 1= Alarm Interrupt Status. Use SCT writes to clear this interrupt status bit.
ALARM_IRQ
1 1= Enable one millisecond interrupt. Use SCT writes to set, clear, or toggle.
ONEMSEC_IRQ_
EN
0 1= Enable Alarm Interrupt. Use SCT writes to set, clear, or toggle.
ALARM_IRQ_EN
22.8.2 Real-Time Clock Status Register (HW_RTC_STAT)

HW_RTC_STAT is the status register for the RTC.
HW_RTC_STAT: 0x010
HW_RTC_STAT_SET: 0x014
HW_RTC_STAT_CLR: 0x018
HW_RTC_STAT_TOG: 0x01C
This register reflects the current state of the RTC in terms of its enabled capabilities and
the state of the persistent registers.
EXAMPLE
while(HW_RTC_STAT.STALE_REGS !=0)
{

printf(" something is stale in one of the digital side registers\n");

// the copy controller will copy analog registers to digtial registers as
required,
// turning off staleregs bits as it goes about its business.
}
if(HW_RTC_STAT.WATCHDOG_PRESENT != 0) // then you can use the watchdog timer on
this chip
Address: HW_RTC_STAT – 8005_6000h base + 10h offset = 8005_6010h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTC_PRESENT
WATCHDOG_
PRESENT
XTAL32000_
XTAL32768_
ALARM_
PRESENT
PRESENT
PRESENT
R RSVD1 STALE_REGS
Reset 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R NEW_REGS RSVD0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_RTC_STAT field descriptions

Field Description
31 This read-only bit reads back a one if the RTC is present in the device.
RTC_PRESENT
30 This read-only bit reads back a one if the Alarm function is present in the device.
ALARM_
PRESENT
29 This read-only bit reads back a one if the Watchdog Timer function is present in the device.
WATCHDOG_
PRESENT
28 This read-only bit reads back a one if the 32.000-kHz crystal oscillator function is present in the device.
XTAL32000_
PRESENT
27 This read-only bit reads back a one if the 32.768-kHz crystal oscillator function is present in the device.
XTAL32768_
PRESENT

HW_RTC_STAT field descriptions (continued)

Field Description
RSVD1
23–16 These read-only bits are set to one whenever the corresponding shadow register contents are older than
STALE_REGS the analog side contents. These bits are set by reset and cleared by the copy controller. They are also set
by writing a one to the FORCE_UPDATE bit.
15–8 These read-only bits are set to one whenever the corresponding shadow register contents are newer than
NEW_REGS the analog side contents. These bits are set by writing to the corresponding register and cleared by the copy
controller.

RSVD0
22.8.3 Real-Time Clock Milliseconds Counter

(HW_RTC_MILLISECONDS)
The millisecond count register provides a reliable elapsed time reference to the kernel with
millisecond resolution.
HW_RTC_MILLISECONDS: 0x020
HW_RTC_MILLISECONDS_SET: 0x024
HW_RTC_MILLISECONDS_CLR: 0x028
HW_RTC_MILLISECONDS_TOG: 0x02C
HW_RTC_MILLISECONDS provides access to the 32-bit millisecond counter. This counter
is not a shadow register, i.e., the contents of this register are not preserved over power-down
states. This counter increments once per millisecond based on a pulse from RTC analog
which is derived from the 24.0-MHz crystal clock. This 1-kHz source hence does not vary
as the APBX clock frequency is changed. The millisecond counter wraps at 4,294,967,294
milliseconds or 49.7 days.
EXAMPLE
HW_RTC_MILLISECONDS_WR(0); // write an initial starting value to the

milliseconds counter
Count = HW_RTC_MILLISECONDS_RD(); // read the current value of the milliseconds
counter.

Address: HW_RTC_MILLISECONDS – 8005_6000h base + 20h offset = 8005_6020h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_RTC_MILLISECONDS field descriptions

Field Description
31–0 32 bit milliseconds counter.
COUNT
22.8.4 Real-Time Clock Seconds Counter (HW_RTC_SECONDS)

The real-time clock seconds counter is used to maintain real time for applications, even
across certain chip power-down states.
HW_RTC_SECONDS: 0x030
HW_RTC_SECONDS_SET: 0x034
HW_RTC_SECONDS_CLR: 0x038
HW_RTC_SECONDS_TOG: 0x03C
HW_RTC_SECONDS provides access to the 32-bit real-time seconds counter. Both the
shadow register on the digital side and the analog side register update every second. When
the chip enters the power-down state, the shadow register is powered down and loses its
state value. When the chip powers up, the analog side register contents are automatically
copied to the shadow register. The reset value of 0x0 for the digital side register is only
visible until the copy controller overwrites with the value from the analog side. The analog
side register resets to zero only upon power-on reset (POR), i.e., when the battery is first
inserted or whenever a battery-less part is plugged into USB power or into a wall transformer.
Note that if a low frequency (32.000khz or 32.768khz) crystal is available in the system,
then the seconds count and the milliseconds count will be derived from different clocks.
Namely, the msec count is derived from the 24MHz crystal and the seconds count from the
low-frequency crystal. This limits the precision of the relation between these two clocks.
EXAMPLE
HW_RTC_SECONDS_WR(0); // write an initial value to the digital side.

This value will
// be automatically copied to the analog side
rt_clock = HW_RTC_SECONDS_RD(); // read the 32 seconds counter value

Address: HW_RTC_SECONDS – 8005_6000h base + 30h offset = 8005_6030h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_RTC_SECONDS field descriptions

Field Description
31–0 Increments once per second.
COUNT
22.8.5 Real-Time Clock Alarm Register (HW_RTC_ALARM)

The 32-bit alarm value is matched against the 32-bit seconds counter to detect an alarm
condition.
HW_RTC_ALARM: 0x040
HW_RTC_ALARM_SET: 0x044
HW_RTC_ALARM_CLR: 0x048
HW_RTC_ALARM_TOG: 0x04C
The 32-bit alarm value can be used to awaken the chip from a power-down state or simply
to cause an interrupt at a specific time. When the chip enters the power-down state, the
shadow register is powered down and loses its state value. When the chip powers up, the
analog side register contents are automatically copied to the shadow register. The reset
value of 0x0 for the digital side register is only visible until the copy controller overwrites
with the value from the analog side. The analog side register resets to zero only upon
power-on reset (POR), i.e., when the battery is first inserted or whenever a battery-less part
is plugged into a power USB or into a wall transformer.
EXAMPLE
HW_RTC_ALARM_WR(60); // generate rtc alarm after 60 seconds

Address: HW_RTC_ALARM – 8005_6000h base + 40h offset = 8005_6040h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
VALUE
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_RTC_ALARM field descriptions

Field Description
31–0 Seconds match-value used to trigger assertion of the RTC alarm.
VALUE
22.8.6 Watchdog Timer Register (HW_RTC_WATCHDOG)

The 32-bit watch dog timer can be used to reset the chip if enabled and not adequately
serviced.
HW_RTC_WATCHDOG: 0x050
HW_RTC_WATCHDOG_SET: 0x054
HW_RTC_WATCHDOG_CLR: 0x058
HW_RTC_WATCHDOG_TOG: 0x05C
The 32-bit watchdog timer will reset the chip upon decrementing to zero, if this function is
enabled and present on the chip. The 1-kHz source is based on a msec pulse from RTC
analog which is derived from the 24-MHz crystal oscillator and hence does not vary when
the APBX clock is changed.
EXAMPLE
HW_RTC_WATCHDOG_WR(10000); // reload the watchdog and keep it from resetting the

chip
Address: HW_RTC_WATCHDOG – 8005_6000h base + 50h offset = 8005_6050h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
COUNT
W
Re- 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
set

HW_RTC_WATCHDOG field descriptions

Field Description
31–0 If the watchdog timer decrements to zero and the watchdog timer reset is enabled, then the chip will be
COUNT reset.
The watchdog timer decrements once per millisecond, when enabled.
22.8.7 Persistent State Register 0 (HW_RTC_PERSISTENT0)

The 32-bit persistent registers are used to retain certain control states during chip wide
power-down states.
HW_RTC_PERSISTENT0: 0x060
HW_RTC_PERSISTENT0_SET: 0x064
HW_RTC_PERSISTENT0_CLR: 0x068
HW_RTC_PERSISTENT0_TOG: 0x06C
The general persistent bits are available for software use. The register initalizes to a known
reset pattern. The copy controller overwrites the digital reset values very soon after power
on, but not in zero time.
EXAMPLE
HW_RTC_PERSISTENT0_SET(BM_RTC_PERSISTENT0_ALARM_WAKE_EN); // wake up the chip if

the alarm event occurs
HW_RTC_PERSISTENT0_SET(BM_RTC_PERSISTENT0_CLOCKSOURCE); // select the 32KHz
oscillator as the source for the RTC analog clock
Address: HW_RTC_PERSISTENT0 – 8005_6000h base + 60h offset = 8005_6060h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DISABLE_PSWITCH
AUTO_RESTART
LRADC_PWRUP
EXTERNAL_RESET
THERMAL_RESET
R
ENABLE_
RSVD0
ADJ_POSLIMITBUCK RSVD1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALARM_WAKE_
ALARM_WAKE
XTAL32_FREQ
CLOCKSOURCE
XTAL24MHZ_
ALARM_EN
XTAL32KHZ_
R
DISABLE_
XTALOK
PWRUP
PWRUP
LCK_
EN
LOWERBIAS MSEC_RES
SECS
W
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
HW_RTC_PERSISTENT0 field descriptions

Field Description
31–28 This field can be used to allow dcdc startup with lower Liion battery voltages. With the default value of 0x0,
ADJ_ the dcdc converter will not startup below 2.83V, and increasing this value will lower the Liion startup voltage.
POSLIMITBUCK It is not recommended to set a value higher than 0x6. The value of this field effects the minimum startup
voltage as follows: 0x0=2.83V, 0x1=2.78V, 0x2=2.73V, 0x3=2.68V, 0x4=2.62V, 0x5=2.57V, 0x6=2.52V,
0x7-0xF=2.48V.
27–22 Reserved for special uses.

RSVD1
21 This bit is set by the analog hardware. On powerup, it indicate to software that that the chip had previously
EXTERNAL_ been powered down due to a reset event on the reset pin by an external source. This bit must be cleared
RESET by software. Note this bit is only valid when 32K XTAL is selected as the clock source of RTC, otherwise
the external reset event might not be correctly captured when the reset happens.
20 This bit is set by the analog hardware. On powerup, it indicate to software that that the chip had previously
THERMAL_ been powered down due to overheating. This bit must be cleared by software. This bit is analogous to the
RESET HW_POWER_STS_THERMAL_WARNING bit only in persistent storage. Note this bit is only valid when
32K XTAL is selected as the clock source of RTC, otherwise the thermal reset event might not be correctly
captured when the reset happens.
19 Reserved for special uses.

RSVD0
18 Set to one to enable a low voltage on LRADC0 to powerup the chip. This is to support powerup through
ENABLE_ open drain pulldowns connected to LRADC0. Ths requires external circuitry and this bit should not be set
LRADC_PWRUP unless the correct circuitry is present. Freescale will provide information on the external circuitry, if this
functionality is required.
17 Set to one to enable the chip to automatically power up approximately 180 ms after powering down.
AUTO_RESTART
16 Disables the pswitch pin startup functionality unless the voltage on the pswitch pin goes above the VDDXTAL
DISABLE_ pin voltage by a threshold voltage. Typically, this voltage is created by pulling pswitch up with a current
PSWITCH limiting resistor to a higher voltage, such as the Liion battery voltage.
15–14 Reduce bias current of 24mhz crystal.

LOWERBIAS
b00: nominal,
b01: -25%,
b10: -25%,
b11: -50%,
13 Set to one to disable the circuit that resets the chip if 24-MHz frequency falls below 2 MHz. The circuit
DISABLE_ defaults to enabled and will power down the device if the 24-MHz stop oscillating for any reason.
XTALOK

HW_RTC_PERSISTENT0 field descriptions (continued)

Field Description
12–8 This bit field encodes the value of the millisecond count resolution in a one-hot format. Resolutions supported
MSEC_RES are: 1, 2, 4, 8, and 16 msec. The bitfield directly gives the resolution without need for decode.
7 Set when the chip is powered up by an alarm event from rtc_ana. Can then be cleared by software as
ALARM_WAKE desired.
6 If CLOCKSOURCE (bit 0 of this register) is one, then this bit gives the exact frequency of the 32kHz crystal.
XTAL32_FREQ If this bit is zero, the frequency is 32.768kHZ, if it is one, the frequency is 32.000kHz. If CLOCKSOURCE
is zero, the value of this bit is immaterial.
5 Set to one to power up the 32kHz crystal oscillator. Set to zero to disable the oscillator. This bit controls the
XTAL32KHZ_ oscillator at all times (chip powered on or not).
PWRUP
4 Set to one to keep the 24.0-MHz crystal oscillator powered up while the chip is powered down. Set to zero
XTAL24MHZ_ to disable during chip power down. Note: The oscillator is always on while the chip is powered on.
PWRUP
3 Set to one to lock down the seconds count. Once this bit is written with a 1, the user will not be able to either
LCK_SECS write to the seconds register or to change this bit back to a zero -- except by removing the battery.
2 Set this bit to one to enable the detection of an alarm event. This bit must be turned on before an alarm
ALARM_EN event can awaken a powered-down device, or before it can generate an alarm interrupt to a powered-up
CPU. When the alarm is not present in the device (as indicated by the fuse bits) the copy of shadow0 to
persistent0 will not allow bit[2] to be written and persistent bit[2] will always read back 0, regardless of the
values in the shadow register.
1 This bit is set to one to upon the arrival of an alarm event that powers up the chip. ALARM_EN must be set
ALARM_WAKE_ to one to enable the detection of an alarm event.
EN
This bit is reset by writing a zero directly to the shadow register, which causes the copy controller to move
it across to the analog domain.
0 Set to one to select the 32-kHz crystal oscillator as the source for the 32-kHz clock domain used by the RTC
CLOCKSOURCE analog domain circuits. Set to zero to select the 24-MHz crystal oscillator as the source for generating the
32-kHz clock domain used by the RTC analog domain circuits.

The 32-bit persistent registers are used to retain certain control states during chip wide
power-down states.

The register initalizes to a known reset pattern. The copy controller overwrites this digital
reset value very soon after power on but not in zero time.
EXAMPLE
HW_RTC_PERSISTENT1_WR(0x12345678); // this write will ultimately push data to the

analog side via the copy controller

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
GENERAL
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 Firmware use, defined as follows:
GENERAL
0x1000 ENUMERATE_500MA_TWICE — Enumerate at 500mA twice before dropping back to 100mA.
0x0800 USB_BOOT_PLAYER_MODE — Boot to player when connected to USB.
0x0400 SKIP_CHECKDISK — Run Checkdisk flag.
0x0200 USB_LOW_POWER_MODE — USB Hi/Lo Current select.
0x0100 OTG_HNP_BIT — HNP has been required if set to one.
0x0080 OTG_ATL_ROLE_BIT — USB role.

The 32-bit persistent registers are used to retain certain control states during chip-wide
power-down states.
EXAMPLE


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
GENERAL
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
31–0 FIRMWARE/SOFTWARE
GENERAL

power-down states.
EXAMPLE


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
GENERAL
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
GENERAL

power-down states.
HW_RTC_PERSISTENT4: 0x0A0
HW_RTC_PERSISTENT4_SET: 0x0A4
HW_RTC_PERSISTENT4_CLR: 0x0A8
HW_RTC_PERSISTENT4_TOG: 0x0AC
EXAMPLE

Address: HW_RTC_PERSISTENT4 – 8005_6000h base + A0h offset = 8005_60A0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
GENERAL
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
GENERAL

power-down states.

HW_RTC_PERSISTENT5: 0x0B0
HW_RTC_PERSISTENT5_SET: 0x0B4
HW_RTC_PERSISTENT5_CLR: 0x0B8
HW_RTC_PERSISTENT5_TOG: 0x0BC
EXAMPLE

Address: HW_RTC_PERSISTENT5 – 8005_6000h base + B0h offset = 8005_60B0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
GENERAL
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
GENERAL
22.8.13 Real-Time Clock Debug Register (HW_RTC_DEBUG)

This 32-bit register provides debug read access to various internal states for diagnostic
purposes.
HW_RTC_DEBUG: 0x0C0
HW_RTC_DEBUG_SET: 0x0C4
HW_RTC_DEBUG_CLR: 0x0C8
HW_RTC_DEBUG_TOG: 0x0CC
Read-only view into the internals of the digital side of the RTC for diagnostic purposes.
EXAMPLE

DebugValue = HW_RTC_DEBUG_RD(); // read debug register value
Address: HW_RTC_DEBUG – 8005_6000h base + C0h offset = 8005_60C0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD0[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WATCHDOG_RESET_MASK
WATCHDOG_
RESET
R RSVD0[15:2]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_RTC_DEBUG field descriptions

Field Description
31–2 Debug read-only view of various state machine bits.
RSVD0
1 When set, mask the reset generation by the watchdog timer for testing purposes.
WATCHDOG_
RESET_MASK
0 Reflects the state of the watchdog reset. Used for testing purposes so the watchdog can be tested without
WATCHDOG_ resetting part. When set, Watchdog reset is asserted.
RESET
22.8.14 Real-Time Clock Version Register (HW_RTC_VERSION)

Version register.
EXAMPLE

VersionValue = HW_RTC_VERSION_RD(); // read debug register value
Address: HW_RTC_VERSION – 8005_6000h base + D0h offset = 8005_60D0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MAJOR MINOR STEP

W
Re- 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_RTC_VERSION field descriptions

Field Description
MAJOR
MINOR
STEP

Chapter 23
Timers and Rotary Decoder (TIMROT)
23.1 Timers and Rotary Decoder (TIMROT) Overview

The device implements four timers and a rotary decoder, as shown in Figure 23-1. The
timers and decoder can take their inputs from any of the pins defined for PWM, rotary
encoders, or certain divisions from the 32-KHz clock input. Therefore, the PWM pins can
be inputs or outputs, depending on the application.
ARM Core SRAM

24-MHz
XTAL
Osc.
AHB
AHB Slave AHB Master Divide

by n
Shared DMA
AHB-to-APBX Bridge
APBX Master
APBX
Timer/Rotary Decoder
PWM[0]
PWM[1] Timer 0 1/1, 1/ 2, 1/4, 1/8
PWM[2]
PWM[3] Timer 1 1/1, 1/ 2, 1/4, 1/8
PWM[4]
PWM[5] Timer 2 1/1, 1/ 2, 1/4, 1/8
PWM[6]
PWM[7]
Timer 3 1/1, 1/ 2, 1/4, 1/8
ROTARY_B
ROTARY_A
Rotary Up/Down Counter
32-kHz Osc.
Timers and Rotary Decoder
Figure 23-1. Timers and Rotary Decoder Block Diagram
The timer/rotary decoder block is a programmed I/O interface connected to the APBX bus.
Recall that the APBX typically runs at a divided clock rate from the 24-MHz crystal clock.
Each timer and rotary channel can sample at a rate that is further subdivided from the APBX
clock. Each timer can select a different pre-scaler value.

Timer
23.2 Timer
There are two running mode for each timer. One is fixed count mode and the other is match
count mode. By default Timer works in fixed count mode, and match count mode can be
enabled by writing 1'b1 to bit MATCH_MODE of register TIMERx Control and Status
Register (x = 0-3).
23.2.1 Fixed count mode

In this mode, the timer consists of a 32-bit fixed count value and a 32-bit free-running count
value. The free running count decrements until it reaches 0 where it sets an interrupt status
bit associated with the counter.
• If the RELOAD bit is set to 1, then the fixed count is automatically copied to the
free-running counter and the count continues.
• If the RELOAD bit is not set, the timer stalls when it reaches 0.
Figure 23-2 shows a detailed view of each timer in fixed count mode.
?
Timer I/O == match & match_mode
32-Bit Match Count 32-Bit Running Count
match_mode == 1
Mode
Controller
ALWAYS TICK
PWM[0]
PWM[1]
PWM[2]
PWM[3]
PWM[4]
PWM[5]
PWM[6] Tick
Edge
PWM[7] Detect
ROTARY_A
ROTARY_B
NEVER TICK
1, 4, 8, 32
Divide byy
32-kHz
24-MHz
Divide APBX clk Divide by Gated clk
XTAL
Input
Osc. by n 1, 2, 4, 8
Figure 23-2. Timer 0, Timer 1, Timer 2 or Timer 3 Detail

Chapter 23 Timers and Rotary Decoder (TIMROT)
Each timer has an UPDATE bit that controls whether the free-running counter is loaded at
the same time the fixed-count register is written from the CPU. The output of each timer's
source select has a polarity control that allows the timer to operate on either edge.
Table 23-1 lists the timer state machine transitions.
Table 23-1. Timer State Machine Transitions
UPDATE RELOAD RUNNING
0 0 PIO writes to the fixed-count bit field have no effect on the running count.
0 1 The value written to the fixed count is used to reload the running count the next time it reaches 0.
When the fixed count has been written with a value of 0 and the running count reaches 0, it continuously
copies the fixed count value to the running count. Therefore, writing a non-zero value to the fixed
count register kicks off a continuous count and update operation.
1 0 The value written to the fixed count bit field is copied, immediately to the running count, restarting any
existing running count operation. When the new running count reaches 0, it freezes.
1 1 The value written to the fixed count bit field is copied, immediately to the running count, restarting any
existing running count operation. When the new running count reaches 0, it is reloaded from the value
in the fixed count bit field, therefore running continuously using the newly supplied fixed count.
When generating a periodic timer interrupt using the RELOAD bit, the user must compute
proper fixed-count value (count_value) based on clock speeds and clock divider settings.
Note that, in this case, the actual value written to the FIXED_COUNT register field should
be count_value – 1. For one-shot interrupts (RELOAD bit not set), the value written should
be count_value.
Any timer interrupt can be programmed as an FIQ or as a regular IRQ. See Interrupt Collector
(ICOLL) Overview for programming details.
For proper detection of the input source signal, it should be much slower than the pre-scaled
APBX clock (not greater than one-third the frequency of the pre-scaled APBX clock).
Selecting the ALWAYS tick causes the timer to decrement continuously at the rate
established by the pre-scaled APBX clock. The NEVER TICK selection causes the timer
to stall. Setting the fixed-count to 0xFFFFFFFF and setting the RELOAD bit causes the
timer to operate continuously with a 4,294,967,296 count.
The state of the 32-bit free-running count can be read by the CPU for each timer.
23.2.2 Match count mode

In this mode, the timer consists of a 32-bit match count value and a 32-bit free-running
count value. This mode is enabled once MATCH MODE of Register TIMERx Control
and Status Register (x = 0-3) is written to 1. At the same time, the free-running count

Timer
returns to its default start value 0xFFFF_FFFF, then starts decrementing from 0xFFFF_FFFF
to 0. Every time it decreases to 0, it restores to 0xFFFF_FFFF and keeps decreasing
repeatedly. During this ceaseless decrement, interrupt is triggered every time free running
count equals match count.
Figure 23-3 shows a detailed view of each timer in match mode.
?
Timer I/O == match & match_mode
32-Bit Match Count 32-Bit Running Count
match_mode == 1
Mode
Controller
ALWAYS TICK
PWM[0]
PWM[1]
PWM[2]
PWM[3]
PWM[4]
PWM[5]
PWM[6] Tick
Edge
PWM[7] Detect
ROTARY_A
ROTARY_B
NEVER TICK
1, 4, 8, 32
Divide byy
32-kHz
24-MHz
Divide APBX clk Divide by Gated clk
XTAL
Input
Osc. by n 1, 2, 4, 8
Figure 23-3. Timer 0, Timer 1, Timer 2 or Timer 3 Detail
In match mode, period timer interrupt can be triggered by modifying the match register to
a proper value adequately smaller than the current value of the match register in every
interrupt service routine, which is usually calculated by subtracting a delta from the current
value of the match register. To get a group of interrupts with fixed interval, constant delta
is used, and to get interrupts with variable interval, variable delta is used.
Any timer interrupt can be programmed as a FIQ or as a regular IRQ. See Interrupt Collector
(ICOLL) Overview for programming details.
For proper detection of the input source signal, it should be much slower than the pre-scaled
APBX clock (not greater than one-third the frequency of the pre-scaled APBX clock).
Selecting the ALWAYS tick causes the timer to decrement continuously at the rate
established by the pre-scaled APBX clock. The NEVER TICK selection causes the timer
to stall.

The state of the 32-bit free-running count can be read by the CPU for each timer.
23.2.3 Using External Signals as Inputs

External signals can be used as inputs to the block. They can be used as either the test signal
or sampling input signals (duty cycle or normal timer mode). This can be accomplished by
using the rotary input pins or any unused PWM pins. If PWM pins are being used for this
purpose, conflicts with the PWM or other blocks that could drive the pins as outputs must
be avoided. In this case, the PWM pins being used should be programmed as GPIO inputs.
(See Pin Control and GPIO Overview for details.) Then, the external signal can be wired
to the pin, and the PWM number selected in the appropriate TIMROT registers.
23.2.4 Timer 3 and Duty Cycle Mode

Timer 3 can operate in the same modes as Timer 0, Timer 1, and Timer 2. However, it has
an additional duty cycle measurement mode. Figure 23-4 shows a detailed view of Timer
3 in duty cycle mode. This mode can be enabled by writing 1 to bit DUTY_CYCLE of
Register TIMER3 Control and Status Register. When this bit is set, no matter what value
MATCH MODE of Register TIMER3 Control and Status Register is, Timer 3 works
in duty cycle mode.

Timer
Timer I/O
32-Bit Low Count

32-Bit Fixed count 32-Bit Running Count
Hold, load, Hold, down,

copy load, copy
Mode
Controller
ALWAYS TICK
PWM[0]
PWM[1]
PWM[2]
PWM[3]
PWM[4]
PWM[5] Tick LVL
PWM[6] Edge
PWM[7] Detect
ROTARY_A
ROTARY_B
NEVER TICK
1, 4, 8, 32
Divide byy
32-kHz 24-MHz APBX clk Divide by

Divide Gated clk
Input XTAL
by n 1, 2, 4, 8
Osc.
Figure 23-4. Timer 3 Detail
In the duty cycle mode, Timer 3 samples the free-running counter at the rising and falling
edges of the input test signal, resetting the free-running counter on the same clock that is
sampled.
• On the rising edge of the test signal, the free-running count is copied to the
LOW_RUNNING_COUNT bit field of the HW_TIMROT_TIMCOUNT3 register.
• On the falling edge of the source clock, the free-running count is copied to the
HIGH_FIXED_COUNT bit field (as shown in Figure 23-5).
Low Count High Count
Input
Figure 23-5. Pulse-Width Measurement Mode
• Once duty cycle mode is programmed and the input signal is stable, software should
poll the DUTY_VALID bit in the HW_TIMROT_TIMCTRL3 register.
• This bit is automatically set and cleared by the hardware. When this bit is set, count
values in the HW_TIMROT_TIMCOUNT3 register are stable and ready to be read.

Refer to the Timer 3 control and status register, HW_TIMROT_TIMCTRL3, where the
DUTY_CYCLE bit controls whether HW_TIMROT_TIMCOUNT3 register's
LOW_RUNNING_COUNT bit field reads back the running count or the low count of a
duty cycle measurement. The DUTY_CYCLE bit also controls whether the
HIGH_FIXED_COUNT bit field reads back the fixed-count value used in normal timer
operations or the duty cycle high-time measurement.
It should be noted that for duty cycle mode to function properly, the timer tick source
selected (SELECT field of the HW_TIMROT_TIMCTRL3 register) should be an appropriate
frequency to sample the test signal. The NEVER_TICK value should never be used in this
mode, as it yields incorrect count results.
23.3 Rotary Decoder

The rotary decoder uses two input selectors and edge detectors, as shown in Figure 23-6.
It includes a debounce circuit for each input, as shown in Figure 23-7. This figure shows
the debounce circuit for input A, though the circuit is identical for input B.
Timer I/O
Signed 16-Bit Up/Down Count
32-kHz
Input
Hold, load,
inc/dec
Mode
Controller and
Debounce
Circuit
NEVER TICK
PWM[0]
PWM[1] ROT
PWM[2] SELA
PWM[3]
PWM[4]
Edge
PWM[5]
PWM[6] Detect
PWM[7]
ROTARY_A
ROTARY_B
NEVER TICK
PWM[0]
PWM[1] ROT
PWM[2] SELB
PWM[3]
PWM[4]
Edge
PWM[5]
PWM[6] Detect
PWM[7]
ROTARY_A APBX Clock
ROTARY_B
Figure 23-6. Detail of Rotary Decoder

Rotary Decoder
~oversamp_by_8
Adebounce
J Q
DQ DQ DQ DQ DQ DQ DQ DQ K Q*
*Q *Q *Q *Q *Q *Q *Q *Q
~oversamp_by_8
NEVER TICK Flip-flops sample and

PWM[0] advance at a divided
PWM[1] 32-kHz rate
PWM[2]
PWM[3]
PWM[4]
PWM[5]
PWM[6]
PWM[7]
ROTARY_A
ROTARY_B
Figure 23-7. Rotary Decoding Mode-Debouncing Rotary A and B Inputs
A state machine following rotary decoder transition is provided to detect the direction of
rotation and the time at which to increment or decrement the 16-bit signed counter in
HW_TIMROT_ROTCOUNT. The updown counter can be treated as either a relative count
or an absolute count, depending on the state of the HW_TIMROT_ROTCTRL_RELATIVE
bit. When set to the relative mode, each read of the counter has the side effect of resetting
it. The edge detectors respond to both edges of each input to determine the self-timed
transition inputs to the state machine (see Figure 23-8).
11 00 01
Input A inc 10
Input B 10 11
00 01
dec
Figure 23-8. Rotary Decoding Mode-Input Transitions
Figure 23-8 shows that each detected edge causes a transition in the decoder state machine.
Not all transitions are legal (see Table 23-2). For example, there is no legal way to transition
directly from state 11 to 00 using normal inputs. In the cases where this occurs, the state
machine goes to an alternate set of states and follows the input sequence until a valid
sequence leading to state 00 is detected. No increment or decrement action is taken from
the alternate state sequence.

Table 23-2. Rotary Decoder State Machine Transitions

CURRENT STATE INPUT BA=00 INPUT BA=01 INPUT BA=10 INPUT BA=11
00 00 01 10 error
01 00, dec 01 error 11
10 00, inc error 10 11
11 error 01 10 11
23.3.1 Behavior During Reset

CLKGATE bit fields.

i.MX28 TIMROT Hardware Register Format Summary
HW_TIMROT memory map
Absolute
Width Section/
(in bits) page
(hex)
8006_8000 Rotary Decoder Control Register (HW_TIMROT_ROTCTRL) 32 R/W FE00_0000h 23.4.1/1510
8006_8010 Rotary Decoder Up/Down Counter Register 32 R 0000_0000h 23.4.2/1513
(HW_TIMROT_ROTCOUNT)
8006_8020 Timer 0 Control and Status Register 32 R/W 0000_0000h 23.4.3/1513
(HW_TIMROT_TIMCTRL0)
8006_8030 Timer 0 Runing Count Register 32 R 0000_0000h 23.4.4/1515
(HW_TIMROT_RUNNING_COUNT0)
8006_8040 Timer 0 Fixed Count Register 32 R/W 0000_0000h 23.4.5/1516
(HW_TIMROT_FIXED_COUNT0)
8006_8050 Timer 0 Match Count Register 32 R/W 0000_0000h 23.4.6/1516
(HW_TIMROT_MATCH_COUNT0)
8006_8060 Timer 1 Control and Status Register 32 R/W 0000_0000h 23.4.7/1517
8006_8070 Timer 1 Runing Count Register 32 R 0000_0000h 23.4.8/1519
8006_8080 Timer 1 Fixed Count Register 32 R/W 0000_0000h 23.4.9/1519

HW_TIMROT memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
8006_80A0 Timer 2 Control and Status Register 32 R/W 0000_0000h 23.4.11/1520
8006_80B0 Timer 2 Runing Count Register 32 R 0000_0000h 23.4.12/1522
8006_80C0 Timer 2 Fixed Count Register 32 R/W 0000_0000h 23.4.13/1523
8006_80D0 Timer 2 Match Count Register 32 R/W 0000_0000h 23.4.14/1523
8006_80E0 Timer 3 Control and Status Register 32 R/W 0000_0000h 23.4.15/1524
8006_80F0 Timer 3 Running Count Register 32 R 0000_0000h 23.4.16/1526
8006_8100 Timer 3 Count Register (HW_TIMROT_FIXED_COUNT3) 32 R/W 0000_0000h 23.4.17/1527
8006_8120 TIMROT Version Register (HW_TIMROT_VERSION) 32 R 0200_0000h 23.4.19/1528
23.4.1 Rotary Decoder Control Register (HW_TIMROT_ROTCTRL)

The Rotary Decoder Control Register specifies the reset state and the source selection for
the rotary decoder. In addition, it specifies the polarity of any external input source that is
used. This register also contains some general block controls including soft reset, clock
gate, and present bits.
HW_TIMROT_ROTCTRL: 0x000
HW_TIMROT_ROTCTRL_SET: 0x004
HW_TIMROT_ROTCTRL_CLR: 0x008
HW_TIMROT_ROTCTRL_TOG: 0x00C
EXAMPLE
HW_TIMROT_ROTCTRL_WR(0x00000076); // Set up rotary control fields.

Address: HW_TIMROT_ROTCTRL – 8006_8000h base + 0h offset = 8006_8000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESENT
PRESENT
PRESENT
PRESENT
PRESENT
ROTARY_
TIM3_
TIM2_
TIM1_
TIM0_
R STATE
CLKGATE
SFTRST
DIVIDER
Reset 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVERSAMPLE
R RSRVD3
POLARITY_B
POLARITY_A
RELATIVE
SELECT_B SELECT_A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_TIMROT_ROTCTRL field descriptions

Field Description
31 This bit must be set to zero to enable operation of any timer or the rotary decoder. When set to one, it forces
SFTRST a block-level reset and gates off the clocks to the block.
30 This bit must be set to zero for normal operation. When set to one, it gates off the clocks to the block.
CLKGATE
29 0= Rotary decoder is not present in this product.
ROTARY_
1= Rotary decoder is present is in this product.
PRESENT
28 0= TIMER3 is not present in this product.
TIM3_PRESENT
1= TIMER3 is present is in this product.

TIM2_PRESENT

TIM1_PRESENT

TIM0_PRESENT
24–22 Read-only view of the rotary decoder transition detecting state machine.
STATE
21–16 This bit field determines the divisor used to divide the 32-kHz on chip clock rate for oversampling (debouncing)
DIVIDER the rotary A and B inputs. Note that the divider value is actually the (value of this field+1).

HW_TIMROT_ROTCTRL field descriptions (continued)

Field Description
RSRVD3
12 Set this bit to one to cause the rotary decoders updown counter to be reset to zero whenever it is read.
RELATIVE
11–10 This bit field determines the oversample rate to use in debouncing Rotary A and B inputs.
OVERSAMPLE
0x0 8X — 8x Oversample: 8 successive ones or zeroes to transition.
0x3 1X — 1x Oversample: Transition on each first input change.
9 Set this bit to one to invert the input to the edge detector.
POLARITY_B
POLARITY_A
7–4 Selects the source for the timer tick that increments the free-running counter that measures the A2B and
SELECT_B B2A overlap counts.
0x0 NEVER_TICK — SelectB: Never tick.
0x1 PWM0 — SelectB: Input from PWM0.
0x9 ROTARYA — SelectB: Input from Rotary A.
0xA ROTARYB — SelectB: Input from Rotary B.
3–0 Selects the source for the timer tick that increments the free-running counter that measures the A2B and
SELECT_A B2A overlap counts.
0x0 NEVER_TICK — SelectA: Never tick.
0x1 PWM0 — SelectA: Input from PWM0.
0x9 ROTARYA — SelectB: Input from Rotary A.
0xA ROTARYB — SelectB: Input from Rotary B.

23.4.2 Rotary Decoder Up/Down Counter Register

(HW_TIMROT_ROTCOUNT)
The Rotary Decoder Up/Down Counter Register contains the timer counter value that counts
up or down as the rotary encoder is rotated.
This register contains the read-only current count for the rotary decoder.
EXAMPLE
count = HW_TIMROT_ROTCTRL_RD(); // Read count
Address: HW_TIMROT_ROTCOUNT – 8006_8000h base + 10h offset = 8006_8010h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1 UPDOWN
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_TIMROT_ROTCOUNT field descriptions

Field Description
RSRVD1
15–0 At each edge of the Rotary A input, the Rotary B value is sampled, similarly at each edge of the Rotary B
UPDOWN input, the Rotary A input is sampled. These values drive a rotary decoder state machine that determines
when this counter is incremented or decremetned. When set in the RELATIVE mode, reads from this register
clear this register as a side effect. Counter values in this register are signed 16-bit values.
23.4.3 Timer 0 Control and Status Register (HW_TIMROT_TIMCTRL0)

The Timer 0 Control and Status Register specifies timer control parameters, as well as
interrupt status and the enable for Timer 0.
HW_TIMROT_TIMCTRL0: 0x020
HW_TIMROT_TIMCTRL0_SET: 0x024
HW_TIMROT_TIMCTRL0_CLR: 0x028
HW_TIMROT_TIMCTRL0_TOG: 0x02C
EXAMPLE

HW_TIMROT_TIMCTRLn_WR(0, 0x00000008); // Set up control fields for timer0
Address: HW_TIMROT_TIMCTRL0 – 8006_8000h base + 20h offset = 8006_8020h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD3
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD2 RSRVD1
POLARITY
R
RELOAD
MATCH_
UPDATE
MODE
IRQ_
IRQ PRESCALE SELECT
EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_TIMROT_TIMCTRL0 field descriptions

Field Description
RSRVD3
15 This bit is set to one when Timer 0 decrements to zero. Write a zero to clear it or use Clear SCT mode.
IRQ
14 Set this bit to one to enable the generation of a CPU interrupt when the count reaches zero in normal counter
IRQ_EN mode.

RSRVD2
11 Set this bit to one to enable timer match mode
MATCH_MODE
RSRVD1
POLARITY
0: Positive edge detection.
1: Negative edge detection.
7 Set this bit to one to cause the running count to be written from the CPU at the same time a new fixed count
UPDATE register value is written.
6 Set this bit to one to cause the timer to reload its current count from its fixed count value whenever the
RELOAD current count decrements to zero. When set to zero, the timer enters a mode that freezes at a count of zero.
When the fixed count is zero, setting this bit to one causes a continuous reload of the fixed count register
so that writting a non-zero value will start the timer.
5–4 Selects the divisor used for clock generation. The APBX clock is divided by the following amount. Note the
PRESCALE APBX clock itself is initially divided down from the 24.0-MHz crystal clock frequency.
0x0 DIV_BY_1 — PreScale: Divide the APBX clock by 1.

HW_TIMROT_TIMCTRL0 field descriptions (continued)

Field Description

3–0 Selects the source for the timer tick that decrements the free running counter. Note: programming an
SELECT undefined value will result in "always tick" behavior.
0x0 NEVER_TICK — Never tick.
0x1 PWM0 — Input from PWM0.
0x9 ROTARYA — Input from Rotary A.
0xA ROTARYB — Input from Rotary B.
0xB 32KHZ_XTAL — Input from 32-kHz crystal.
0xC 8KHZ_XTAL — Input from 8-kHz (divided from 32-kHz crystal).
0xD 4KHZ_XTAL — Input from 4-kHz (divided from 32-kHz crystal).
0xE 1KHZ_XTAL — Input from 1-kHz (divided from 32-kHz crystal).
0xF TICK_ALWAYS — Always tick.
23.4.4 Timer 0 Runing Count Register

The Timer 0 Running Count Register contains the timer running counter values for Timer
0.
Address: HW_TIMROT_RUNNING_COUNT0 – 8006_8000h base + 30h offset = 8006_
8030h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RUNNING_COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_TIMROT_RUNNING_COUNT0 field descriptions

Field Description
31–0 This bit field shows the current state of the running count as it decrements.
RUNNING_
COUNT

23.4.5 Timer 0 Fixed Count Register (HW_TIMROT_FIXED_COUNT0)

The Timer 0 Fixed Count Register contains the fixed timer counter values for Timer 0.
EXAMPLE
HW_TIMROT_FIXED_COUNTn_WR(0, 0x0000f0dd); // Set up timer fixed count
Address: HW_TIMROT_FIXED_COUNT0 – 8006_8000h base + 40h offset = 8006_8040h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
FIXED_COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_TIMROT_FIXED_COUNT0 field descriptions

Field Description
31–0 Software loads the fixed count bit field with the value to down count.
FIXED_COUNT
If the reload bit is set to one, then the new value will be loaded into the running count the next time it reaches
zero.
If the update bit is set to one, then the new value is also copied into the running count, immediately.
If both the reload and update bits are set to zero, then the new value is never picked up by the running count.
23.4.6 Timer 0 Match Count Register (HW_TIMROT_MATCH_COUNT0)

The Timer 0 Match Count Register contains the match timer counter values for Timer 0.
EXAMPLE
HW_TIMROT_MATCH_COUNTn_WR(0, 0x0000f0dd); // Set up timer match count
Address: HW_TIMROT_MATCH_COUNT0 – 8006_8000h base + 50h offset = 8006_8050h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MATCH_COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

HW_TIMROT_MATCH_COUNT0 field descriptions

Field Description
31–0 Software compares the match count bit field with the value to down count. If they equal to each other, interrupt
MATCH_COUNT is trigger.

HW_TIMROT_TIMCTRL1: 0x060
HW_TIMROT_TIMCTRL1_SET: 0x064
HW_TIMROT_TIMCTRL1_CLR: 0x068
HW_TIMROT_TIMCTRL1_TOG: 0x06C
EXAMPLE
Address: HW_TIMROT_TIMCTRL1 – 8006_8000h base + 60h offset = 8006_8060h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD3
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD2 RSRVD1
POLARITY
R
RELOAD
MATCH_
UPDATE
MODE
IRQ_
IRQ PRESCALE SELECT
EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD3
IRQ


Field Description
IRQ_EN mode.

RSRVD2
MATCH_MODE
RSRVD1
POLARITY
1: Invert to negative edge detection.


1.
Address: HW_TIMROT_RUNNING_COUNT1 – 8006_8000h base + 70h offset = 8006_
8070h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RUNNING_COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RUNNING_
COUNT

EXAMPLE

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
FIXED_COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
FIXED_COUNT
zero.


EXAMPLE

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MATCH_COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description

HW_TIMROT_TIMCTRL2: 0x0a0
HW_TIMROT_TIMCTRL2_SET: 0x0a4
HW_TIMROT_TIMCTRL2_CLR: 0x0a8
HW_TIMROT_TIMCTRL2_TOG: 0x0aC
EXAMPLE

Address: HW_TIMROT_TIMCTRL2 – 8006_8000h base + A0h offset = 8006_80A0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD3
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD2 RSRVD1
POLARITY
R
RELOAD
MATCH_
UPDATE
MODE
IRQ_
IRQ PRESCALE SELECT
EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD3
IRQ
IRQ_EN mode.

RSRVD2
MATCH_MODE
RSRVD1
POLARITY


Field Description

2.
Address: HW_TIMROT_RUNNING_COUNT2 – 8006_8000h base + B0h offset = 8006_
80B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RUNNING_COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
RUNNING_
COUNT


EXAMPLE
Address: HW_TIMROT_FIXED_COUNT2 – 8006_8000h base + C0h offset = 8006_80C0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
FIXED_COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
FIXED_COUNT
zero.

EXAMPLE
Address: HW_TIMROT_MATCH_COUNT2 – 8006_8000h base + D0h offset = 8006_80D0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MATCH_COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description

HW_TIMROT_TIMCTRL3: 0x0e0
HW_TIMROT_TIMCTRL3_SET: 0x0e4
HW_TIMROT_TIMCTRL3_CLR: 0x0e8
HW_TIMROT_TIMCTRL3_TOG: 0x0eC
EXAMPLE
Address: HW_TIMROT_TIMCTRL3 – 8006_8000h base + E0h offset = 8006_80E0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD2
TEST_SIGNAL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DUTY_
RSRVD1
POLARITY
R
RELOAD
MATCH_
UPDATE
CYCLE
DUTY_
MODE
VALID
IRQ_
IRQ PRESCALE SELECT
EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
RSRVD2
19–16 Selects the source of the signal to be measured in duty cycle mode.
TEST_SIGNAL
0x0 NEVER_TICK — Never tick. Freeze the count.


Field Description

IRQ
IRQ_EN mode.

RSRVD1
MATCH_MODE
10 This bit is set and cleared by the hardware. It is set only when in duty cycle measuring mode and the
DUTY_VALID HW_TIMROT_TIMCOUNT3 has valid duty cycle data to be read. This register will be cleared if not in duty
cycle mode or on writes to this register. In the case that it is written while in duty cycle mode, this bit will
clear but will again be set at the appropriate time for reading the count register.
9 Set this bit to one to cause the timer to operate in duty cycle measuring mode.
DUTY_CYCLE
POLARITY


Field Description

SELECT undefined value will result in "always tick" behavior. In duty cycle mode it increments the counter used to
calculate the high and low cycle counts.
0x0 NEVER_TICK — Never tick. Freeze the count.
23.4.16 Timer 3 Running Count Register

The Timer 3 Running Count Register contains the timer runningcounter values for Timer
3. NOTE: This timer can be put in a special duty cycle mode that will measure the duty
cycle of an input test signal.
The definitions of the fields change depending whether the timer is in normal or duty cycle
mode.
Address: HW_TIMROT_RUNNING_COUNT3 – 8006_8000h base + F0h offset = 8006_
80F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R LOW_RUNNING_COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set


Field Description
31–0 In duty cycle mode, this bit field is loaded from the running counter when it has just finished measuring the
LOW_RUNNING_ low portion of the duty cycle. In normal timer mode, it shows the running count as a read-only value.
COUNT
23.4.17 Timer 3 Count Register (HW_TIMROT_FIXED_COUNT3)

The Timer 3 fixed Count Register contains the timer fixed counter values for Timer 3.
NOTE: This timer can be put in a special duty cycle mode that will measure the duty cycle
of an input test signal.
The definitions of the fields change depending whether the timer is in normal or duty cycle
mode.
EXAMPLE

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
HIGH_FIXED_COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
HIGH_FIXED_
COUNT
zero.
In duty cycle mode, this bit field is loaded from the running counter when it has finished measuring the high
portion of the duty cycle.

EXAMPLE


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MATCH_COUNT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

Field Description
23.4.19 TIMROT Version Register (HW_TIMROT_VERSION)

of the block.
EXAMPLE
if (HW_TIMROT_VERSION.B.MAJOR != 1) Error();
Address: HW_TIMROT_VERSION – 8006_8000h base + 120h offset = 8006_8120h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MAJOR MINOR STEP

W
Re- 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_TIMROT_VERSION field descriptions

Field Description
MAJOR
MINOR
STEP

Chapter 24
Debug UART (DUART)
24.1 Debug UART Overview

The Debug UART performs:
• Serial-to-parallel conversion on data received from a peripheral device
• Parallel-to-serial conversion on data transmitted to the peripheral device
The CPU reads and writes data and control/status information through the APBX interface.
The transmit and receive paths are buffered with internal FIFO memories, enabling up to
32 bytes to be stored independently in both transmit and receive modes.
The Debug UART includes a programmable baud rate generator that creates a transmit and
receive internal clock from the 24-MHz UART internal reference clock input UARTCLK.
XCLK is not tied to the UARTCLK in the i.MX28.
It offers similar functionality to the industry-standard 16C550 UART device and supports
baud rates of up to 115 Kb/s. Figure 24-1 shows a block diagram of the Debug UART. The
Debug UART operation and baud rate values are controlled by the line control register
(HW_UARTDBGLCR_H, HW_UARTDBGIBRD, and HW_UARTDBGFBRD).
The Debug UART can generate a single combined interrupt, so output is asserted if any
individual interrupt is asserted and unmasked. Interrupt sources include the receive (including
timeout), transmit, modem status, and error conditions.
If a framing, parity, or break error occurs during reception, the appropriate error bit is set,
and is stored in the FIFO. If an overrun condition occurs, the overrun register bit is set
immediately, and FIFO data is prevented from being overwritten. You can program the
FIFOs to be one-byte deep, providing a conventional double-buffered UART interface.
The modem status input signal Clear To Send (CTS) and output modem control line Request
To Send (RTS) are supported. A programmable hardware flow control feature uses the
nUARTCTS input and the nUARTRTS output to automatically control the serial data flow.

Operation
Note
Names for the external pins used by the Debug UART begin with
"UART1". Pin names beginning with "UART2" are used by the
Application UART.
ARM Core SRAM
AHB
24-MHz
XTAL
XCLK Osc.
Divide
AHB Slave
by n
UARTCLK
XCLK
AHB-to-APBX Bridge
APBX Master
APBX
UART Programmable Registers

and FIFOs
UART1RXD RX FSM BAUDRATE

UART2RTS
UART2CTS
TX FSM
UART1TXD
UART
Figure 24-1. Debug UART Block Diagram
24.2 Operation
Control data is written to the Debug UART line control register. This register defines:
• Transmission parameters
• Word length
• Buffer mode
• Number of transmitted stop bits
• Parity mode

Chapter 24 Debug UART (DUART)
• Break generation
• Baud rate divisor
24.2.1 Fractional Baud Rate Divider

The baud rate divisor is calculated from the frequency of UARTCLK and the desired baud
rate by using the following formula:
divisor = (UARTCLK * 4) / baud rate, rounded to the nearest integer
The divisor must be between 0x00000040 and 0x003FFFC0, inclusive. Program the lowest
6 bits of the divisor into BAUD_DIVFRAC, and the next 16 bits of the divisor into
BAUD_DIVINT.
In the debug UART, HW_UARTDBGLCR_H, HW_UARTDBGIBRD, and
HW_UARTDBGFBRD form a single 30-bit wide register (UARTLCR) that is updated on
a single write strobe generated by an HW_UARTDBGLCR_H write. So, in order to internally
update the contents of HW_UARTDBGIBRD or HW_UARTDBGFBRD, a write to
HW_UARTDBGLCR_H must always be performed at the end.
24.2.2 UART Character Frame

Figure 24-2 illustrates the UART character frame.
UARTTXD
1–2
lsb msb stop bits
1
5–8 data bits
0
n
Parity bit
Start if enabled
Figure 24-2. Debug UART Character Frame
24.2.3 Data Transmission or Reception

Data received or transmitted is stored in two 32-byte FIFOs, though the receive FIFO has
an extra four bits per character for status information.
For transmission, data is written into the transmit FIFO. If the Debug UART is enabled, it
causes a data frame to start transmitting with the parameters indicated in UARTLCR_H.
Data continues to be transmitted until there is no data left in the transmit FIFO.
Operation
The BUSY signal goes HIGH as soon as data is written to the transmit FIFO (that is, the
FIFO is non-empty) and remains asserted HIGH while data is being transmitted. BUSY is
negated only when the transmit FIFO is empty and the last character has been transmitted
from the shift register, including the stop bits. BUSY can be asserted HIGH even though
the Debug UART might no longer be enabled.
For each sample of data, three readings are taken and the majority value is kept. In the
following paragraphs, the middle sampling point is defined and one sample is taken either
side of it.
• When the receiver is idle (UARTRXD continuously 1, in the marking state) and a LOW
is detected on the data input (a start bit has been received), the receive counter, with
the clock enabled by Baud16, begins running and data is sampled on the eighth cycle
of that counter in normal UART mode to allow for the shorter logic 0 pulses (half way
through a bit period).
• The start bit is valid if UARTRXD is still LOW on the eighth cycle of Baud16, otherwise
a false start bit is detected and it is ignored. If the start bit was valid, successive data
bits are sampled on every 16th cycle of Baud16 (that is, one bit period later) according
to the programmed length of the data characters. The parity bit is then checked, if parity
mode was enabled.
• Lastly, a valid stop bit is confirmed if UARTRXD is HIGH, otherwise a framing error
has occurred. When a full word is received, the data is stored in the receive FIFO, with
any error bits associated with that word (see Table 24-1).
24.2.4 Error Bits

Three error bits are stored in bits [10:8] of the receive FIFO and are associated with a
particular character. An additional error indicating an overrun error is stored in bit 11 of
the receive FIFO.
24.2.5 Overrun Bit

The overrun bit is not associated with the character in the receive FIFO. The overrun error
is set when the FIFO is full, and the next character is completely received in the shift register.
The data in the shift register is overwritten, but it is not written into the FIFO. When an
empty location is available in the receive FIFO, and another character is received, the state
of the overrun bit is copied into the receive FIFO along with the received character. The
overrun state is then cleared. Table 24-1 shows the bit functions of the receive FIFO.

Table 24-1. Receive FIFO Bit Functions

FIFO bit Function
11 Overrun indicator
10 Break error
9 Parity error
8 Framing error
7:0 Received data
24.2.6 Disabling the FIFOs

FIFOs can be disabled. In this case, the transmit and receive sides of the UART have one-byte
holding registers (the bottom entry of the FIFOs). The overrun bit is set when a word has
been received and the previous one was not yet read.
In this implementation, the FIFOs are not physically disabled, but the flags are manipulated
to give the illusion of a one-byte register.

UARTDBG Hardware Register Format Summary
HW_UARTDBG memory map
Absolute
Width Section/
(in bits) page
(hex)
8007_4000 UART Data Register (HW_UARTDBG_DR) 32 R/W 0000_0000h 24.3.1/1534
8007_4004 UART Receive Status Register (Read) / Error Clear Register 32 R/W 0000_0000h 24.3.2/1535
(Write) (HW_UARTDBG_ECR)
8007_4018 UART Flag Register (HW_UARTDBG_FR) 32 R 0000_0090h 24.3.3/1536
8007_4020 UART IrDA Low-Power Counter Register 32 R/W 0000_0000h 24.3.4/1537
(HW_UARTDBG_ILPR)
8007_4024 UART Integer Baud Rate Divisor Register 32 R/W 0000_0000h 24.3.5/1537
(HW_UARTDBG_IBRD)
8007_4028 UART Fractional Baud Rate Divisor Register 32 R/W 0000_0000h 24.3.6/1538
(HW_UARTDBG_FBRD)
8007_402C UART Line Control Register, HIGH Byte (HW_UARTDBG_H) 32 R/W 0000_0000h 24.3.7/1539
8007_4030 UART Control Register (HW_UARTDBG_CR) 32 R/W 0000_0300h 24.3.8/1539
8007_4034 UART Interrupt FIFO Level Select Register 32 R/W 0000_0012h 24.3.9/1541
(HW_UARTDBG_IFLS)

HW_UARTDBG memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
8007_4038 UART Interrupt Mask Set/Clear Register 32 R/W 0000_0000h 24.3.10/1542
(HW_UARTDBG_IMSC)
8007_403C UART Raw Interrupt Status Register (HW_UARTDBG_RIS) 32 R 0000_0000h 24.3.11/1543
8007_4040 UART Masked Interrupt Status Register (HW_UARTDBG_MIS) 32 R 0000_0000h 24.3.12/1545
8007_4044 UART Interrupt Clear Register (HW_UARTDBG_ICR) 32 R/W 0000_0000h 24.3.13/1546
8007_4048 UART DMA Control Register (HW_UARTDBG_DMACR) 32 R/W 0000_0000h 24.3.14/1547
24.3.1 UART Data Register (HW_UARTDBG_DR)

Debug Uart Data Register. For words to be transmitted: 1) If the FIFOs are enabled, data
written to this location is pushed onto the transmit FIFO 2) If the FIFOs are not enabled,
data is stored in the transmitter holding register (the bottom word of the transmit FIFO).
The write operation initiates transmission from the PrimeCell UART. The data is prefixed
with a start bit, appended with the appropriate parity bit (if parity is enabled), and a stop
bit. The resultant word is then transmitted. For received words: 1) If the FIFOs are enabled,
the data byte and the 4-bit status (break, frame, parity, and overrun) are pushed onto the
12-bit wide receive FIFO 2) If the FIFOs are not enabled, the data byte and status are stored
in the receiving holding register (the bottom word of the receive FIFO). The received data
byte is read by performing reads from the DR register along with the corresponding status
information. The status information can also be read by a read of the RSR_ECR register.
Address: HW_UARTDBG_DR – 8007_4000h base + 0h offset = 8007_4000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BE
PE
OE
FE
R UNAVAILABLE RESERVED
DATA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_UARTDBG_DR field descriptions

Field Description
31–16 The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are
UNAVAILABLE always unavailable.
15–12 This bitfield is reserved.

Reserved Reserved.
11 Overrun Error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to
OE 0 once there is an empty space in the FIFO and a new character can be written to it.

HW_UARTDBG_DR field descriptions (continued)

Field Description
10 Break Error. This bit is set to 1 if a break condition was detected, indicating that the received data input was
BE held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO
mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0
character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a
1 (marking state), and the next valid start bit is received.
9 Parity Error. When this bit is set to 1, it indicates that the parity of the received data character does not match
PE the parity selected as defined by bits 2 and 7 of the LCR_H register. In FIFO mode, this error is associated
with the character at the top of the FIFO.
8 Framing Error. When this bit is set to 1, it indicates that the received character did not have a valid stop bit
FE (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO.
7–0 Receive (read) data character. Transmit (write) data character.

DATA
24.3.2 UART Receive Status Register (Read) / Error Clear Register

(Write) (HW_UARTDBG_ECR)
The RSR_ECR register is the receive status register/error clear register. Receive status can
also be read from RSR_ECR. If the status is read from this register, then the status
information for break, framing and parity corresponds to the data character read from DR
prior to reading RSR_ECR. The status information for overrun is set immediately when an
overrun condition occurs. A write to RSR_ECR clears the framing, parity, break, and overrun
errors.
Address: HW_UARTDBG_ECR – 8007_4000h base + 4h offset = 8007_4004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R UNAVAILABLE OE
BE
PE
FE
EC
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_UARTDBG_ECR field descriptions

Field Description
7–4 Error Clear. Any write to this bitfield clears the framing, parity, break, and overrun errors. The value is
EC unpredictable when read.
3 Overrun Error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by
OE any write to RSR_ECR. The FIFO contents remain valid since no further data is written when the FIFO is
full, only the contents of the shift register are overwritten. The CPU must now read the data in order to empty
the FIFO.

HW_UARTDBG_ECR field descriptions (continued)

Field Description
2 Break Error.
BE
1 Parity Error.
PE
0 Framing Error.
FE
24.3.3 UART Flag Register (HW_UARTDBG_FR)

The FR register is the flag register.
Address: HW_UARTDBG_FR – 8007_4000h base + 18h offset = 8007_4018h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R UNAVAILABLE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RESERVED RI TXFE RXFF TXFF RXFE BUSY DCD DSR CTS
Reset 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0
HW_UARTDBG_FR field descriptions

Field Description

Reserved Reserved, do not modify, read as zero.
8 Ring Indicator. This bit is the complement of the UART ring indicator (nUARTRI) modem status input. That
RI is, the bit is 1 when the modem status input is 0.
7 Transmit FIFO Empty. The meaning of this bit depends on the state of the FEN bit in the LCR_H register.
TXFE If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the
TXFE bit is set when the transmit FIFO is empty.
6 Receive FIFO Full.

RXFF
5 Transmit FIFO Full.
TXFF

HW_UARTDBG_FR field descriptions (continued)

Field Description
4 Receive FIFO Empty.
RXFE
3 UART Busy.
BUSY
2 Data Carrier Detect.
DCD
1 Data Set Ready.
DSR
0 Clear To Send.
CTS
24.3.4 UART IrDA Low-Power Counter Register (HW_UARTDBG_ILPR)

The ILPR register is the IrDA Low-Power Counter Register. This is an 8-bit read/write
register which stores a low-power counter divisor value used to divde down the UARTCLK
to generate the IrLPBaud16 signal.
Address: HW_UARTDBG_ILPR – 8007_4000h base + 20h offset = 8007_4020h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R UNAVAILABLE
ILPDVSR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_UARTDBG_ILPR field descriptions

Field Description
7–0 IrDA Low Power Divisor [7:0]. 8-bit low-power divisor value.
ILPDVSR
24.3.5 UART Integer Baud Rate Divisor Register (HW_UARTDBG_IBRD)

The IBRD register is the integer part of the baud rate divisor value.

Address: HW_UARTDBG_IBRD – 8007_4000h base + 24h offset = 8007_4024h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R UNAVAILABLE
BAUD_DIVINT
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_UARTDBG_IBRD field descriptions

Field Description
15–0 Baud Rate Integer [15:0]. The integer baud rate divisor.
BAUD_DIVINT
24.3.6 UART Fractional Baud Rate Divisor Register

(HW_UARTDBG_FBRD)
The FBRD register is the fractional part of the baud rate divisor value.
Address: HW_UARTDBG_FBRD – 8007_4000h base + 28h offset = 8007_4028h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R UNAVAILABLE[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R UNAVAILABLE[15:8] RESERVED
BAUD_DIVFRAC
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_UARTDBG_FBRD field descriptions

Field Description

Reserved Not documented.
5–0 Baud Rate Fraction [5:0]. The fractional baud rate divisor.
BAUD_DIVFRAC

24.3.7 UART Line Control Register, HIGH Byte (HW_UARTDBG_H)

The LCR_H is the Line Control Register.
Address: HW_UARTDBG_H – 8007_4000h base + 2Ch offset = 8007_402Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WLEN
STP2
PEN
BRK
SPS
FEN
EPS
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_UARTDBG_H field descriptions

Field Description

7 Stick Parity Select. When bits 1, 2, and 7 of the LCR_H register are set, the parity bit is transmitted and
SPS checked as a 0. When bits 1 and 7 are set, and bit 2 is 0, the parity bit is transmitted and checked as a 1.
When this bit is cleared stick parity is disabled.
6–5 Word length [1:0]. The select bits indicate the number of data bits transmitted or received in a frame as
WLEN follows: 11 = 8 bits, 10 = 7 bits, 01 = 6 bits, 00 = 5 bits.
4 Enable FIFOs. If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO mode). When
FEN cleared to 0, the FIFOs are disabled (character mode); that is, the FIFOs become 1-byte-deep holding
registers.
3 Two Stop Bits Select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive
STP2 logic does not check for two stop bits being received.
2 Even Parity Select. If this bit is set to 1, even parity generation and checking is performed during transmission
EPS and reception, which checks for an even number of 1s in data and parity bits. When cleared to 0, then odd
parity is performed which checks for an odd number of 1s. This bit has no effect when parity is disabled by
Parity Enable (PEN, bit 1) being cleared to 0.
1 Parity Enable. If this bit is set to 1, parity checking and generation is enabled, else parity is disabled and no
PEN parity bit added to the data frame.
0 Send Break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing
BRK transmission of the current character. For the proper execution of the break command, the software must
set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.
24.3.8 UART Control Register (HW_UARTDBG_CR)

The CR is the Control Register.

Address: HW_UARTDBG_CR – 8007_4000h base + 30h offset = 8007_4030h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R UNAVAILABLE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RESERVED
UARTEN
CTSEN
RTSEN
SIREN
SIRLP
OUT2
OUT1
RTS DTR RXE TXE LBE

W
Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
HW_UARTDBG_CR field descriptions

Field Description
15 CTS Hardware Flow Control Enable.

CTSEN
14 RTS Hardware Flow Control Enable.
RTSEN
13 This bit is the complement of the UART Out2 (nUARTOut2) modem status output. Not Implemented.
OUT2
12 This bit is the complement of the UART Out1 (nUARTOut1) modem status output. Not Implemented.
OUT1
11 Request To Send.
RTS
10 Data Transmit Ready. Not Implemented.
DTR
9 Receive Enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for
RXE the UART signals. When the UART is disabled in the middle of reception, it completes the current character
before stopping.
8 Transmit Enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs
TXE for the UART signals. When the UART is disabled in the middle of transmission, it completes the current
character before stopping.
7 Loop Back Enable. This feature reduces the amount of external coupling required during system test. If this
LBE bit is set to 1, the UARTTXD path is fed through to the UARTRXD path. When this bit is set, the modem
outputs are also fed through to the modem inputs.

2 IrDA SIR low-power mode. Not Supported.

SIRLP

HW_UARTDBG_CR field descriptions (continued)

Field Description
1 SIR Enable. Not Supported.
SIREN
0 UART Enable. If this bit is set to 1, the UART is enabled. Data transmission and reception occurs for the
UARTEN UART signals. When the UART is disabled in the middle of transmission or reception, it completes the current
character before stopping.
24.3.9 UART Interrupt FIFO Level Select Register (HW_UARTDBG_IFLS)

The IFLS register is the Interrupt FIFO Level Select Register. You can use the IFLS register
to define the FIFO level at which the UARTTXINTR and UARTRXINTR are triggered.
The interrupts are generated based on a transition through a level rather than being based
on the level. That is, the design is such that the interrupts are generated when the fill level
progresses through the trigger level. The bits are reset so that the trigger level is when the
FIFOs are at the half-way mark.
Address: HW_UARTDBG_IFLS – 8007_4000h base + 34h offset = 8007_4034h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXIFLSEL TXIFLSEL
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
set
HW_UARTDBG_IFLS field descriptions

Field Description

5–3 Receive Interrupt FIFO Level Select. The trigger points for the receive interrupt are as follows:
RXIFLSEL
0x0 ONE_EIGHT — Trigger when FIFO becomes at least one-eight full.
0x1 ONE_QUARTER — Trigger when FIFO becomes at least one-quarter full.
0x2 ONE_HALF — Trigger when FIFO becomes at least one-half full.
0x3 THREE_QUARTERS — Trigger when FIFO becomes at least three-quarters full.
0x4 SEVEN_EIGHTHS — Trigger when FIFO becomes at least seven-eights full.
0x5 INVALID5 — Reserved.
2–0 Transmit Interrupt FIFO Level Select. The trigger points for the transmit interrupt are as follows:
TXIFLSEL
0x0 ONE_EIGHT — Trigger when FIFO becomes equal or less than one-eight full.
0x1 ONE_QUARTER — Trigger when FIFO becomes equal or less than one-quarter full.

HW_UARTDBG_IFLS field descriptions (continued)

Field Description
0x2 ONE_HALF — Trigger when FIFO becomes equal or less than one-half full.
0x3 THREE_QUARTERS — Trigger when FIFO becomes equal or less than three-quarters full.
0x4 SEVEN_EIGHTHS — Trigger when FIFO becomes equal or less than seven-eights full.
24.3.10 UART Interrupt Mask Set/Clear Register (HW_UARTDBG_IMSC)

The IMSC register is the Interrupt Mask Set/Clear Register. On a read, this register gives
the current value of the mask on the relevant interrupt. On a write of 1 to the particular bit,
it sets the corresponding mask of that interrupt. A write of 0 clears the corresponding mask.
Special Note: Here Mask means Enable.Mask=1 means that bit interrupt is enabled
Address: HW_UARTDBG_IMSC – 8007_4000h base + 38h offset = 8007_4038h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R UNAVAILABLE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RESERVED
DCDMIM
DSRMIM
CTSMIM
RIMIM
OEIM BEIM PEIM FEIM RTIM TXIM RXIM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_UARTDBG_IMSC field descriptions

Field Description

10 Overrun Error Interrupt Mask. On a read, the current mask for the OEIM interrupt is returned. On a write of
OEIM 1, the mask of the OEIM interrupt is set. A write of 0 clears the mask.
9 Break Error Interrupt Mask.

BEIM
8 Parity Error Interrupt Mask.
PEIM

HW_UARTDBG_IMSC field descriptions (continued)

Field Description
7 Framing Error Interrupt Mask.
FEIM
6 Receive Timeout Interrupt Mask.
RTIM
5 Transmit Interrupt Mask.
TXIM
4 Receive Interrupt Mask.
RXIM
3 nUARTDSR Modem Interrupt Mask.
DSRMIM
2 nUARTDCD Modem Interrupt Mask.
DCDMIM
1 nUARTCTS Modem Interrupt Mask.
CTSMIM
0 nUARTRI Modem Interrupt Mask.
RIMIM
24.3.11 UART Raw Interrupt Status Register (HW_UARTDBG_RIS)

The RIS register is the Raw Interrupt Status Register. It is a read-only register. On a read
this register gives the current raw status value of the corresponding interrupt. A write has
no effect. All the bits, except for the modem status interrupt bits (bits 3 to 0), are cleared
to 0 when reset. The modem status interrupt bits are undefined after reset.
Address: HW_UARTDBG_RIS – 8007_4000h base + 3Ch offset = 8007_403Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R UNAVAILABLE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSRRMIS
CTSRMIS
DCDRMIS
RIRMIS
OERIS
RXRIS
BERIS
PERIS
RTRIS
FERIS
TXRIS
R RESERVED
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_UARTDBG_RIS field descriptions

Field Description

Reserved Reserved, read as zero, do not modify.
10 Overrun Error Interrupt Status.

OERIS
9 Break Error Interrupt Status.
BERIS
8 Parity Error Interrupt Status.
PERIS
7 Framing Error Interrupt Status.
FERIS
6 Receive Timeout Interrupt Status.
RTRIS
5 Transmit Interrupt Status.
TXRIS
4 Receive Interrupt Status.
RXRIS
3 nUARTDSR Modem Interrupt Status.
DSRRMIS
2 nUARTDCD Modem Interrupt Status.
DCDRMIS
1 nUARTCTS Modem Interrupt Status.
CTSRMIS
0 nUARTRI Modem Interrupt Status.
RIRMIS

24.3.12 UART Masked Interrupt Status Register (HW_UARTDBG_MIS)

The MIS register is the Masked Interrupt Status Register. It is a read-only register. On a
read this register gives the current masked status value of the corresponding interrupt. A
write has no effect. All the bits except for the modem status interrupt bits (bits 3 to 0) are
cleared to 0 when reset. The modem status interrupt bits are undefined after reset.
Address: HW_UARTDBG_MIS – 8007_4000h base + 40h offset = 8007_4040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R UNAVAILABLE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCDMMIS
DSRMMIS
RIMMIS
CTSMMIS
OEMIS
RXMIS
BEMIS
PEMIS
RTMIS
FEMIS
TXMIS
R RESERVED
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_UARTDBG_MIS field descriptions

Field Description

10 Overrun Error Masked Interrupt Status.

OEMIS
9 Break Error Masked Interrupt Status.
BEMIS
8 Parity Error Masked Interrupt Status.
PEMIS
7 Framing Error Masked Interrupt Status.
FEMIS
6 Receive Timeout Masked Interrupt Status.
RTMIS

HW_UARTDBG_MIS field descriptions (continued)

Field Description
5 Transmit Masked Interrupt Status.
TXMIS
4 Receive Masked Interrupt Status.
RXMIS
3 nUARTDSR Modem Masked Interrupt Status.
DSRMMIS
2 nUARTDCD Modem Masked Interrupt Status.
DCDMMIS
1 nUARTCTS Modem Masked Interrupt Status.
CTSMMIS
0 nUARTRI Modem Masked Interrupt Status.
RIMMIS
24.3.13 UART Interrupt Clear Register (HW_UARTDBG_ICR)

The ICR register is the Interrupt Clear Register and is write-only. On a write of 1, the
corresponding interrupt is cleared. A write of 0 has no effect.
Address: HW_UARTDBG_ICR – 8007_4000h base + 44h offset = 8007_4044h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R UNAVAILABLE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RESERVED
W OEIC BEIC PEIC FEIC RTIC TXIC RXIC DSRMICDCDMICCTSMIC RIMIC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_UARTDBG_ICR field descriptions

Field Description

HW_UARTDBG_ICR field descriptions (continued)

Field Description
10 Overrun Error Interrupt Clear.

OEIC
9 Break Error Interrupt Clear.
BEIC
8 Parity Error Interrupt Clear.
PEIC
7 Framing Error Interrupt Clear.
FEIC
6 Receive Timeout Interrupt Clear.
RTIC
5 Transmit Interrupt Clear.
TXIC
4 Receive Interrupt Clear.
RXIC
3 nUARTDSR Modem Interrupt Clear.
DSRMIC
2 nUARTDCD Modem Interrupt Clear.
DCDMIC
1 nUARTCTS Modem Interrupt Clear.
CTSMIC
0 nUARTRI Modem Interrupt Clear.
RIMIC
24.3.14 UART DMA Control Register (HW_UARTDBG_DMACR)

This register is reserved in this system.
Address: HW_UARTDBG_DMACR – 8007_4000h base + 48h offset = 8007_4048h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R UNAVAILABLE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAONERR
RESERVED
RXDMAE
R
TXDMAE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_UARTDBG_DMACR field descriptions

Field Description

Reserved Reserved.
2 Reserved.
DMAONERR
1 Reserved.
TXDMAE
0 Reserved.
RXDMAE

Chapter 25
Controller Area Network (FlexCAN)
Interface
Protocol
25.1 FlexCAN Introduction

The FlexCAN module is a communication controller implementing the CAN protocol
according to the CAN 2.0B protocol specification. A general block diagram is shown in
Figure 25-1, which describes the main sub-blocks implemented in the FlexCAN module,
including two embedded memories, one for storing Message Buffers (MB) and another one
for storing Rx Individual Mask Registers. The functions of the sub-modules are described
in subsequent sections.
Message CAN
MB63
Buffer
Management
MB62
RXIMR63
RXIMR62 CAN Tx
Message CAN Rx
ID Mask Buffer
Storage Storage
256- 1056-
byte RAM byte RAM
RXIMR1
RXIMR0
MB1
MB0 Bus Interface Unit
Clocks, Address & Data buses,

APB Bus Interface Interrupt and Test Signals
Figure 25-1. FlexCAN Block Diagram

Overview
25.2 Overview
The CAN protocol was primarily, but not only, designed to be used as a vehicle serial data
bus, meeting the specific requirements of this field: real-time processing, reliable operation
in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. The
FlexCAN module is a full implementation of the CAN protocol specification, Version 2.0
B, which supports both standard and extended message frames. The Message Buffers are
stored in an embedded RAM dedicated to the FlexCAN module.
The CAN Protocol Interface (CPI) sub-module manages the serial communication on the
CAN bus, requesting RAM access for receiving and transmitting message frames, validating
received messages and performing error handling. The Message Buffer Management (MBM)
sub-module handles Message Buffer selection for reception and transmission, taking care
of arbitration and ID matching algorithms. The Bus Interface Unit (BIU) sub-module controls
the access to and from the internal interface bus, in order to establish connection to the CPU
and other blocks. Clocks, address and data buses, interrupt outputs and test signals are
accessed through the Bus Interface Unit, which is compliant to APB Bus Specification.
25.2.1 Features
The FlexCAN module includes the following distinctive Features:
• Full Implementation of the CAN protocol specification, Version 2.0B
• Standard data and remote frames
• Extended data and remote frames
• Zero to eight bytes data length
• Programmable bit rate up to 1 Mb/sec
• Content-related addressing
• 64 Message Buffers of zero to eight bytes data length

• Each MB configurable as Rx or Tx, all supporting standard and extended messages
• Individual Rx Mask Registers per Message Buffer
• Includes either 1056 bytes (64 MBs) of RAM used for MB storage
• Includes either 256 bytes (64 MBs) of RAM used for individual Rx Mask Registers
• Full featured Rx FIFO with storage capacity for six frames and internal pointer handling

Chapter 25 Controller Area Network (FlexCAN)
• Powerful Rx FIFO ID filtering, capable of matching incoming IDs against either 8

extended, 16 standard or 32 partial (8 bits) IDs, with individual masking capability
• Selectable backward compatibility with previous FlexCAN version
• CAN Protocol Interface with clock only from crystal oscillator
• Unused MB and Rx Mask Register space can be used as general purpose RAM space
• Listen only mode capability
• Programmable loop-back mode supporting self-test operation
• Programmable transmission priority scheme: lowest ID, lowest buffer number or highest
priority
• Time Stamp based on 16-bit free-running timer
• Global network time, synchronized by a specific message
• Maskable interrupts
• Independent of the transmission medium (an external transceiver is assumed)
• Short latency time due to an arbitration scheme for high-priority messages
• Low power modes, with programmable wake up on bus activity
• Configurable Glitch filter width to filter the noise on CAN bus when waking up
25.2.2 Modes of Operation

The FlexCAN module has four functional modes: Normal Mode, Freeze Mode, Listen-Only
Mode and Loop-Back Mode. There are also two low power modes: Disable Mode, Stop
Mode.
• Normal Mode :
In Normal Mode, the module operates receiving and/or transmitting message frames,
errors are handled normally and all the CAN Protocol functions are enabled.
• Freeze Mode:
It is enabled when the FRZ bit in the MCR Register is asserted. If enabled, Freeze Mode
is entered when the HALT bit in MCR is set or when Debug Mode is requested. In this
mode, no transmission or reception of frames is done and synchronicity to the CAN
bus is lost. See Freeze Mode for more information.

Message Buffer Structure
• Listen-Only Mode:
The module enters this mode when the LOM bit in the Control Register is asserted. In
this mode, transmission is disabled, all error counters are frozen and the module operates
in a CAN Error Passive mode. Only messages acknowledged by another CAN station
will be received. If FlexCAN detects a message that has not been acknowledged, it will
flag a BIT0 error (without changing the REC), as if it was trying to acknowledge the
message.
• Loop-Back Mode:
The module enters this mode when the LPB bit in the Control Register is asserted. In
this mode, FlexCAN performs an internal loop back that can be used for self test
operation. The bit stream output of the transmitter is internally fed back to the receiver
input. The Rx CAN input pin is ignored and the Tx CAN output goes to the recessive
state (logic '1'). FlexCAN behaves as it normally does when transmitting and treats its
own transmitted message as a message received from a remote node. In this mode,
FlexCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field
to ensure proper reception of its own message. Both transmit and receive interrupts are
generated.
• Module Disable Mode:
This low power mode is entered when the MDIS bit in the MCR Register is asserted.
When disabled, the module shuts down the clocks to the CAN Protocol Interface and
Message Buffer Management sub-modules. Exit from this mode is done by negating
the MDIS bit in the MCR Register. See Module Disable Mode for more information.
• Stop Mode:
This low power mode is entered when Stop Mode is requested at ARM chip level.When
in Stop Mode, the module puts itself in an inactive state and then informs the ARM
that the clocks can be shut down globally. Exit from this mode happens when the Stop
Mode request is removed or when activity is detected on the CAN bus and the Self
Wake Up mechanism is enabled. See Stop Mode for more information.
25.3 Message Buffer Structure

The Message Buffer structure used by the FlexCAN module is represented in Table 25-1.
Both Extended and Standard Frames (29-bit Identifier and 11-bit Identifier, respectively)
used in the CAN specification (Version 2.0 Part B) are represented.

Table 25-1. Message Buffer Structure

31 28 27 24 22 21 20 19 16 15 8 7 0
$0 CODE SRR IDE RTR LENGTH TIME STAMP
$4 PRIO ID (Standard/Extended) ID (Extended)
$8 Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3
$C Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7
= Unimplemented or Reserved
CODE—Message Buffer Code

This 4-bit field can be accessed (read or write) by the CPU and by the Flexcan module itself,
as part of the message buffer matching and arbitration process. The encoding is shown in
Table 25-2 and Table 25-3. See Overview for additional information.
Table 25-2. Message Buffer Code for Rx buffers
Rx Code BE-
Rx Code AFTER
FORE Description Comment
Rx New Frame
Rx New Frame
0000 INACTIVE: MB is not active. — MB does not participate in the matching process.
MB participates in the matching process. When a

0100 EMPTY: MB is active and empty. 0010 frame is received successfully, the code is auto-
matically updated to FULL.
The act of reading the C/S word followed by unlock-

ing the MB does not make the code return to
0010 EMPTY. It remains FULL. If a new frame is written
to the MB after the C/S word was read and the MB
was unlocked, the code still remains FULL.
0010 FULL: MB is full.
If the MB is FULL and a new frame is overwritten
to this MB before the CPU had time to read it, the
0110 code is automatically updated to OVERRUN. Refer
to Matching Process for details about overrun be-
havior.
If the code indicates OVERRUN but the CPU reads

the C/S word and then unlocks the MB, when a
0010
new frame is written to the MB the code returns to
FULL.
OVERRUN: a frame was overwritten
0110
into a full buffer. If the code already indicates OVERRUN, and yet
another new frame must be written, the MB will be
0110 overwritten again, and the code will remain
OVERRUN. Refer to Matching Process for details
about overrun behavior.

Rx Code BE-
Rx Code AFTER
FORE Description Comment
Rx New Frame
Rx New Frame
An EMPTY buffer was written with a new frame

0010
BUSY: Flexcan is updating the con- (XY was 01).
1
0XY1 tents of the MB. The CPU must not
access the MB. A FULL/OVERRUN buffer was overwritten (XY
0110
was 11).
1. For Tx MBs (see Table 25-3), the BUSY bit should be ignored upon read, except when the AEN bit is set in the MCR register.
Table 25-3. Message Buffer Code for Tx buffers

Code after successful
RTR Initial Tx code Description
transmission
X 1000 — INACTIVE: MB does not participate in the arbitration process.
ABORT: MB was configured as Tx and CPU aborted the transmission.

X 1001 — This code is only valid when AEN bit in MCR is asserted. MB does
not participate in the arbitration process.
Transmit data frame unconditionally once. After transmission, the MB

0 1100 1000
automatically returns to the INACTIVE state.
Transmit remote frame unconditionally once. After transmission, the

1 1100 0100
MB automatically becomes an Rx MB with the same ID.
Transmit a data frame whenever a remote request frame with the

same ID is received. This MB participates simultaneously in both the
matching and arbitration processes. The matching process compares
the ID of the incoming remote request frame with the ID of the MB. If
0 1010 1010 a match occurs this MB is allowed to participate in the current arbitra-
tion process and the Code field is automatically updated to '1110' to
allow the MB to participate in future arbitration runs. When the frame
is eventually transmitted successfully, the Code automatically returns
to '1010' to restart the process again.
This is an intermediate code that is automatically written to the MB

by the MBM as a result of match to a remote request frame. The data
0 1110 1010 frame will be transmitted unconditionally once and then the code will
automatically return to '1010'. The CPU can also write this code with
the same effect.
SRR—Substitute Remote Request

Fixed recessive bit, used only in extended format. It must be set to '1' by the user for
transmission (Tx Buffers) and will be stored with the value received on the CAN bus for
Rx receiving buffers. It can be received as either recessive or dominant. If FlexCAN receives
this bit as dominant, then it is interpreted as arbitration loss.
1 = Recessive value is compulsory for transmission in Extended Format frames
0 = Dominant is not a valid value for transmission in Extended Format frames
IDE—ID Extended Bit

This bit identifies whether the frame format is standard or extended.
1 = Frame format is extended
0 = Frame format is standard
RTR—Remote Transmission Request
This bit is used for requesting transmissions of a data frame. If FlexCAN transmits this bit
as '1' (recessive) and receives it as '0' (dominant), it is interpreted as arbitration loss. If this
bit is transmitted as '0' (dominant), then if it is received as '1' (recessive), the FlexCAN
module treats it as bit error. If the value received matches the value transmitted, it is
considered as a successful bit transmission.
1 = Indicates the current MB has a Remote Frame to be transmitted
0 = Indicates the current MB has a Data Frame to be transmitted
LENGTH—Length of Data in Bytes
This 4-bit field is the length (in bytes) of the Rx or Tx data, which is located in offset $8
through $F of the MB space (see Table 25-1). In reception, this field is written by the
FlexCAN module, copied from the DLC (Data Length Code) field of the received frame.
In transmission, this field is written by the CPU and corresponds to the DLC field value of
the frame to be transmitted. When RTR=1, the Frame to be transmitted is a Remote Frame
and does not include the data field, regardless of the Length field.
TIME STAMP—Free-Running Counter Time Stamp
This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the
time when the beginning of the Identifier field appears on the CAN bus.
PRIO—Local priority
This 3-bit field is only used when LPRIO_EN bit is set in MCR and it only makes sense
for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define
the transmission priority. See Arbitration Process.
ID—Frame Identifier
In Standard Frame format, only the eleven most significant bits (28 to 18) are used for frame
identification in both receive and transmit cases. The 18 least significant bits are ignored.
In Extended Frame format, all bits are used for frame identification in both receive and
transmit cases.
DATA—Data Field

Up to eight bytes can be used for a data frame. For Rx frames, the data is stored as it is
received from the CAN bus. For Tx frames, the CPU prepares the data field to be transmitted
within the frame.
25.3.1 Rx FIFO Structure

When the FEN bit is set in the MCR, the memory area from $80 to $FF (which is normally
occupied by MBs 0 to 7) is used by the reception FIFO engine. Table 25-4 shows the Rx
FIFO data structure. The region $0-$C contains a MB structure which is the port through
which the CPU reads data from the FIFO (the oldest frame received and not read yet). The
region $10-$DF is reserved for internal use of the FIFO engine. The region $E0-$FF contains
an 8-entry ID table that specifies filtering criteria for accepting frames into the FIFO. Table
25-5 shows the three different formats that the elements of the ID table can assume,
depending on the IDAM field of the MCR. Note that all elements of the table must have
the same format. See Rx FIFO for more information.
Table 25-4. Rx FIFO Structure
31 28 27 24 22 21 20 19 16 15 8 7 0
$0 SRR IDE RTR LENGTH TIME STAMP
$4 ID (Standard/Extended) ID (Extended)
$8 Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3
$C Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7
$10
to Reserved
$DF
$E0 ID Table 0
$E4 ID Table 1
$E8 ID Table 2
$EC ID Table 3
$F0 ID Table 4
$F4 ID Table 5
$F8 ID Table 6
$FC ID Table 7

Table 25-5. ID Table 0 - 7

Format 31 28 27 24 22 21 20 19 16 15 8 7 0
RXIDA
A REM EXT
(Standard = 29-19, Extended = 29-1)
RXIDB_0 RXIDB_1
B REM EXT REM EXT
(Standard = 29-19, Extended = 29-16) (Standard = 13-3, Extended = 13-0)
RXIDC_0 RXIDC_1 RXIDC_2 RXIDC_3

C
(Std/Ext = 31-24) (Std/Ext = 23-16) (Std/Ext = 15-8) (Std/Ext = 7-0)
REM — Remote Frame

This bit specifies if Remote Frames are accepted into the FIFO if they match the target ID.
1 = Remote Frames can be accepted and data frames are rejected
0 = Remote Frames are rejected and data frames can be accepted
EXT — Extended Frame
Specifies whether extended or standard frames are accepted into the FIFO if they match the
target ID.
1 = Extended frames can be accepted and standard frames are rejected
0 = Extended frames are rejected and standard frames can be accepted
RXIDA — Rx Frame Identifier (Format A)
Specifies an ID to be used as acceptance criteria for the FIFO. In the standard frame format,
only the eleven most significant bits are used for frame identification. In the extended frame
format, all bits are used.
RXIDB_0, RXIDB_1 — Rx Frame Identifier (Format B)
Specifies an ID to be used as acceptance criteria for the FIFO. In the standard frame format,
the eleven most significant bits (a full standard ID) are used for frame identification. In the
extended frame format, all 14 bits of the field are compared to the 14 most significant bits
of the received ID.
RXIDC_0, RXIDC_1, RXIDC_2, RXIDC_3 — Rx Frame Identifier (Format C)

Functional Description
Specifies an ID to be used as acceptance criteria for the FIFO. In both standard and extended
frame formats, all eight bits of the field are compared to the eight most significant bits of
the received ID.
25.4 Functional Description

25.4.1 Overview
The FlexCAN module is a CAN protocol engine with a very flexible mailbox system for
transmitting and receiving CAN frames. The mailbox system is composed by a set of 64
Message Buffers (MB) that store configuration and control data, time stamp, message ID
and data (see Message Buffer Structure). The memory corresponding to the first 8 MBs can
be configured to support a FIFO reception scheme with a powerful ID filtering mechanism,
capable of checking incoming frames against a table of IDs (up to 8 extended IDs or 16
standard IDs or 32 8-bit ID slices), each one with its own individual mask register.
Simultaneous reception through FIFO and mailbox is supported. For mailbox reception, a
matching algorithm makes it possible to store received frames only into MBs that have the
same ID programmed on its ID field. A masking scheme makes it possible to match the ID
programmed on the MB with a range of IDs on received CAN frames. For transmission, an
arbitration algorithm decides the prioritization of MBs to be transmitted based on the message
ID (optionally augmented by three local priority bits) or the MB ordering.
Before proceeding with the functional description, an important concept must be explained.
A Message Buffer is said to be active at a given time if it can participate in the matching
and arbitration algorithms that are happening at that time. An Rx MB with a 0000 code is
inactive (refer to Table 25-2). Similarly, a Tx MB with a 1000 or 1001 code is also inactive
(refer to Table 25-3). An MB not programmed with 0000, 1000 or 1001 is temporarily
deactivated (does not participate in the current arbitration or matching run) when the ARM
writes to the C/S field of that MB (see Message Buffer Deactivation).
The FlexCAN also provide a glitch filter which can filter the noises on CAN bus when the
FlexCAN is in the STOP mode. The glitch filter width is configurable by the register
HW_CAN_GFWR.
25.4.2 Transmit Process

In order to transmit a CAN frame, the ARM must prepare a Message Buffer for transmission
by executing the following procedure:

• If the MB is active (transmission pending), write an ABORT code ('1001') to the Code
field of the Control and Status word to request an abortion of the transmission, then
read back the Code field and the IFLAG register to check if the transmission was aborted
(see Transmission Abort Mechanism). If backwards compatibility is desired (AEN in
MCR negated), just write '1000' to the Code field to inactivate the MB but then the
pending frame may be transmitted without notification (see Message Buffer
Deactivation).
• Write the ID word.
• Write the data bytes.
• Write the Length, Control and Code fields of the Control and Status word to activate
the MB.
Once the MB is activated in the fourth step, it will participate in the arbitration process and
eventually be transmitted according to its priority. At the end of the successful transmission,
the value of the Free Running Timer is written into the Time Stamp field, the Code field in
the Control and Status word is updated, a status flag is set in the Interrupt Flag Register and
an interrupt is generated if allowed by the corresponding Interrupt Mask Register bit. The
new Code field after transmission depends on the code that was used to activate the MB in
step four (see Table 25-2 and Table 25-3 in Section Message Buffer Structure). When the
Abort feature is enabled (AEN in MCR is asserted), after the Interrupt Flag is asserted for
a MB configured as transmit buffer, the MB is blocked, therefore the ARM is not able to
update it until the Interrupt Flag be negated by ARM. It means that the ARM must clear
the corresponding IFLAG before starting to prepare this MB for a new transmission or
reception.
25.4.3 Arbitration Process

The arbitration process is an algorithm executed by the MBM that scans the whole MB
memory looking for the highest priority message to be transmitted. All MBs programmed
as transmit buffers will be scanned to find the lowest ID1 or the lowest MB number or the
highest priority, depending on the LBUF and LPRIO_EN bits on the Control Register. The
arbitration process is triggered in the following events:
• During the CRC field of the CAN frame
• During the error delimiter field of the CAN frame
1. Actually, if LBUF is negated, the arbitration considers not only the ID, but also the RTR and IDE bits placed inside the ID at
the same positions they are transmitted in the CAN frame.

• During Intermission, if the winner MB defined in a previous arbitration was deactivated,

or if there was no MB to transmit, but the ARM wrote to the C/S word of any MB after
the previous arbitration finished
• When MBM is in Idle or Bus Off state and the ARM writes to the C/S word of any MB
• Upon leaving Freeze Mode
When LBUF is asserted, the LPRIO_EN bit has no effect and the lowest number buffer is
transmitted first. When LBUF and LPRIO_EN are both negated, the MB with the lowest
ID is transmitted first. But, if LBUF is negated and LPRIO_EN is asserted, the PRIO bits
augment the ID used during the arbitration process. With this extended ID concept, arbitration
is performed based on the full 32-bit ID and the PRIO bits define which MB should be
transmitted first, therefore MBs with PRIO = 000 have higher priority. If two or more MBs
have the same priority, the regular ID will determine the priority of transmission. If two or
more MBs have the same priority (3 extra bits) and the same regular ID, the lowest MB
will be transmitted first.
Once the highest priority MB is selected, it is transferred to a temporary storage space called
Serial Message Buffer (SMB), which has the same structure as a normal MB but is not user
accessible. This operation is called move-out and after it is done, write access to the
corresponding MB is blocked (if the AEN bit in MCR is asserted). The write access is
released in the following events:
• After the MB is transmitted
• FlexCAN enters in HALT or BUS OFF
• FlexCAN loses the bus arbitration or there is an error during the transmission
At the first opportunity window on the CAN bus, the message on the SMB is transmitted
according to the CAN protocol rules. FlexCAN transmits up to eight data bytes, even if the
DLC (Data Length Code) value is bigger.
25.4.4 Receive Process

To be able to receive CAN frames into the mailbox MBs, the ARM must prepare one or
more Message Buffers for reception by executing the following steps:
• If the MB has a pending transmission, write an ABORT code ('1001') to the Code field
of the Control and Status word to request an abortion of the transmission, then read
back the Code field and the IFLAG register to check if the transmission was aborted
(see Transmission Abort Mechanism). If backwards compatibility is desired (AEN in

MCR negated), just write '1000' to the Code field to inactivate the MB, but then the
pending frame may be transmitted without notification (see Message Buffer
Deactivation). If the MB already programmed as a receiver, just write '0000' to the
Code field of the Control and Status word to keep the MB inactive.
• Write the ID word
• Write '0100' to the Code field of the Control and Status word to activate the MB
Once the MB is activated in the third step, it will be able to receive frames that match the
programmed ID. At the end of a successful reception, the MB is updated by the MBM as
follows:
• The value of the Free Running Timer is written into the Time Stamp field
• The received ID, Data (8 bytes at most) and Length fields are stored
• The Code field in the Control and Status word is updated (see Table 25-2 and Table
25-3 in Section Message Buffer Structure)
• A status flag is set in the Interrupt Flag Register and an interrupt is generated if allowed
by the corresponding Interrupt Mask Register bit
Upon receiving the MB interrupt, the ARM should service the received frame using the
following procedure:
• Read the Control and Status word (mandatory – activates an internal lock for this buffer)
• Read the ID field (optional – needed only if a mask was used)
• Read the Data field
• Read the Free Running Timer (optional – releases the internal lock)
Upon reading the Control and Status word, if the BUSY bit is set in the Code field, then
the ARM should defer the access to the MB until this bit is negated. Reading the Free
Running Timer is not mandatory. If not executed the MB remains locked, unless the ARM
reads the C/S word of another MB. Note that only a single MB is locked at a time. The only
mandatory ARM read operation is the one on the Control and Status word to assure data
coherency (see Data Coherence).
The ARM should synchronize to frame reception by the status flag bit for the specific MB
in one of the IFLAG Registers and not by the Code field of that MB. Polling the Code field
does not work because once a frame was received and the ARM services the MB (by reading
the C/S word followed by unlocking the MB), the Code field will not return to EMPTY. It

will remain FULL, as explained in Table 25-2. If the ARM tries to workaround this behavior
by writing to the C/S word to force an EMPTY code after reading the MB, the MB is actually
deactivated from any currently ongoing matching process. As a result, a newly received
frame matching the ID of that MB may be lost. In summary: never do polling by reading
directly the C/S word of the MBs. Instead, read the IFLAG registers.
Note that the received ID field is always stored in the matching MB, therefore the contents
of the ID field in an MB may change if the match was due to masking. Note also that
FlexCAN does receive frames transmitted by itself if there exists an Rx matching MB,
provided the SRX_DIS bit in the MCR is not asserted. If SRX_DIS is asserted, FlexCAN
will not store frames transmitted by itself in any MB, even if it contains a matching MB,
and no interrupt flag or interrupt signal will be generated due to the frame reception.
To be able to receive CAN frames through the FIFO, the ARM must enable and configure
the FIFO during Freeze Mode (see Rx FIFO). Upon receiving the frames available interrupt
from FIFO, the ARM should service the received frame using the following procedure:
• Read the Control and Status word (optional – needed only if a mask was used for IDE
and RTR bits)
• Read the ID field (optional – needed only if a mask was used)
• Read the Data field
• Clear the frames available interrupt (mandatory – release the buffer and allow the ARM
to read the next FIFO entry)
25.4.5 Matching Process

The matching process is an algorithm executed by the MBM that scans the MB memory
looking for Rx MBs programmed with the same ID as the one received from the CAN bus.
If the FIFO is enabled, the 8-entry ID table from FIFO is scanned first and then, if a match
is not found within the FIFO table, the other MBs are scanned. In the event that the FIFO
is full, the matching algorithm will always look for a matching MB outside the FIFO region.
When the frame is received, it is temporarily stored in a hidden auxiliary MB called Serial
Message Buffer (SMB). The matching process takes place during the CRC field of the
received frame. If a matching ID is found in the FIFO table or in one of the regular MBs,
the contents of the SMB will be transferred to the FIFO or to the matched MB during the
sixth bit of the End-Of-Frame field of the CAN protocol. This operation is called move-in.
If any protocol error (CRC, ACK, and so on) is detected, than the move-in operation does
not happen.

For the regular mailbox MBs, an MB is said to be free to receive a new frame if the following
conditions are satisfied:
• The MB is not locked (see Message Buffer Lock Mechanism)
• The Code field is either EMPTY or it is FULL or OVERRUN but the ARM has already
serviced the MB (read the C/S word and then unlocked the MB)
If the first MB with a matching ID is not free to receive the new frame, then the matching
algorithm keeps looking for another free MB until it finds one. If it can not find one that is
free, then it will overwrite the last matching MB (unless it is locked) and set the Code field
to OVERRUN (see Table 25-2 and Table 25-3). If the last matching MB is locked, then the
new message remains in the SMB, waiting for the MB to be unlocked (see Message Buffer
Lock Mechanism).
Suppose, for example, the FIFO is disabled and there are two MBs with the same ID, and
FlexCAN starts receiving messages with that ID. Let us say that these MBs are the second
and the fifth in the array. When the first message arrives, the matching algorithm will find
the first match in MB number 2. The code of this MB is EMPTY, so the message is stored
there. When the second message arrives, the matching algorithm will find MB number 2
again, but it is not free to receive, so it will keep looking and find MB number 5 and store
the message there. If yet another message with the same ID arrives, the matching algorithm
finds out that there are no matching MBs that are free to receive, so it decides to overwrite
the last matched MB, which is number 5. In doing so, it sets the Code field of the MB to
indicate OVERRUN.
The ability to match the same ID in more than one MB can be exploited to implement a
reception queue (in addition to the full featured FIFO) to allow more time for the ARM to
service the MBs. By programming more than one MB with the same ID, received messages
will be queued into the MBs. The ARM can examine the Time Stamp field of the MBs to
determine the order in which the messages are arrived.
The matching algorithm described above can be changed to be the same one used in previous
versions of the FlexCAN module. When the BCC bit in MCR is negated, the matching
algorithm stops at the first MB with a matching ID that it founds, whether this MB is free
or not. As a result, the message queueing feature does not work if the BCC bit is negated.
Matching to a range of IDs is possible by using ID Acceptance Masks. FlexCAN supports
individual masking per MB. During the matching algorithm, if a mask bit is asserted, then
the corresponding ID bit is compared. If the mask bit is negated, the corresponding ID bit
is "don't care". The Individual Mask Registers are implemented in RAM, so they are not
initialized out of reset. Also, they can only be programmed if the BCC bit is asserted and
while the module is in Freeze Mode.

FlexCAN also supports an alternate masking scheme with only three mask registers
(RGXMASK, RX14MASK and RX15MASK) for backwards compatibility. This alternate
masking scheme is enabled when the BCC bit in the MCR Register is negated.
25.4.6 Data Coherence

In order to maintain data coherency and FlexCAN proper operation, the ARM must obey
the rules described in Transmit Process and Receive Process. Any form of ARM accessing
a MB structure within FlexCAN other than those specified may cause FlexCAN to behave
in an unpredictable way.
25.4.6.1 Transmission Abort Mechanism

The abort mechanism provides a safe way to request the abortion of a pending transmission.
A feedback mechanism is provided to inform the ARM if the transmission was aborted or
if the frame could not be aborted and was transmitted instead. In order to maintain backwards
compatibility, the abort mechanism must be explicitly enabled by asserting the AEN bit in
the MCR.
In order to abort a transmission, the ARM must write a specific abort code (1001) to the
Code field of the Control and Status word. When the abort mechanism is enabled, the active
MBs configured as transmission must be aborted first and then they may be updated. If the
abort code is written to a MB that is currently being transmitted, or to an MB that was
already loaded into the SMB for transmission, the write operation is blocked and the MB
is not deactivated, but the abort request is captured and kept pending until one of the
following conditions is satisfied:
• The module loses the bus arbitration
• There is an error during the transmission
• The module is put into Freeze Mode
If none of conditions above are reached, the MB is transmitted correctly, the interrupt flag
is set in the IFLAG register and an interrupt to the ARM is generated (if enabled). The abort
request is automatically cleared when the interrupt flag is set. In the other hand, if one of
the above conditions is reached, the frame is not transmitted, therefore the abort code is
written into the Code field, the interrupt flag is set in the IFLAG and an interrupt is
(optionally) generated to the ARM.

If the ARM writes the abort code before the transmission begins internally, then the write
operation is not blocked, therefore the MB is updated and no interrupt flag is set. In this
way the ARM just needs to read the abort code to make sure the active MB was deactivated.
Although the AEN bit is asserted and the ARM wrote the abort code, in this case the MB
is deactivated and not aborted, because the transmission did not start yet. One MB is only
aborted when the abort request is captured and kept pending until one of the previous
conditions are satisfied.
The abort procedure can be summarized as follows:
• ARM writes 1001 into the code field of the C/S word
• ARM reads the CODE field and compares it to the value that was written
• If the CODE field that was read is different from the value that was written, the ARM
must read the corresponding IFLAG to check if the frame was transmitted or it is being
currently transmitted. If the corresponding IFLAG is set, the frame was transmitted. If
the corresponding IFLAG is reset, the ARM must wait for it to be set, and then the
ARM must read the CODE field to check if the MB was aborted (CODE=1001) or it
was transmitted (CODE=1000).
25.4.7 Message Buffer Deactivation

Deactivation is a mechanism provided to maintain data coherence when the ARM writes
to the Control and Status word of active MBs out of Freeze Mode. Any ARM write access
to the Control and Status word of a MB causes that MB to be excluded from the transmit
or receive processes during the current matching or arbitration round. The deactivation is
temporary, affecting only for the current match/arbitration round.
The purpose of deactivation is data coherency. The match/arbitration process scans the MBs
to decide which MB to transmit or receive. If the ARM updates the MB in the middle of a
match or arbitration process, the data of that MB may no longer be coherent, therefore
deactivation of that MB is done.
Even with the coherence mechanism described above, writing to the Control and Status
word of active MBs when not in Freeze Mode may produce undesirable results. Examples
are:
• Matching and arbitration are one-pass processes. If MBs are deactivated after they are
scanned, no re-evaluation is done to determine a new match/winner. If a Rx MB with
a matching ID is deactivated during the matching process after it was scanned, then
this MB is marked as invalid to receive the frame, and FlexCAN will keep looking for
another matching MB within the ones it has not scanned yet. If it can not find one, then

the message will be lost. Suppose, for example, that two MBs have a matching ID to
a received frame, and the user deactivated the first matching MB after FlexCAN has
scanned the second. The received frame is lost even if the second matching MB was
free to receive.
• If a Tx MB containing the lowest ID is deactivated after FlexCAN has scanned it, then
FlexCAN will look for another winner within the MBs that it has not scanned yet.
Therefore, it may transmit a MB with ID that may not be the lowest at the time because
a lower ID might be present in one of the MBs that it had already scanned before the
deactivation.
• There is a point in time until which the deactivation of a Tx MB causes it not to be
transmitted (end of move-out). After this point, it is transmitted but no interrupt is issued
and the Code field is not updated. In order to avoid this situation, the abort procedures
described in Transmission Abort Mechanism should be used.
25.4.8 Message Buffer Lock Mechanism

Besides MB deactivation, FlexCAN has another data coherence mechanism for the receive
process. When the ARM reads the Control and Status word of an "active not empty" Rx
MB, FlexCAN assumes that the ARM wants to read the whole MB in an atomic operation,
and therefore it sets an internal lock flag for that MB. The lock is released when the ARM
reads the Free Running Timer (global unlock operation), or when it reads the Control and
Status word of another MB. The MB locking is done to prevent a new frame to be written
into the MB while the ARM is reading it.
Note
The locking mechanism only applies to Rx MBs which have a code
different than INACTIVE ('0000') or EMPTY2('0100'). Also, Tx
MBs can not be locked.
Suppose, for example, that the FIFO is disabled and the second and the fifth MBs of the
array are programmed with the same ID, and FlexCAN has already received and stored
messages into these two MBs. Suppose now that the ARM decides to read MB number 5
and at the same time another message with the same ID is arriving. When the ARM reads
the Control and Status word of MB number 5, this MB is locked. The new message arrives
and the matching algorithm finds out that there are no MBs that are free to receive, so it
decides to override MB number 5. However, this MB is locked, so the new message can
not be written there. It will remain in the SMB waiting for the MB to be unlocked, and only
2. In previous FlexCAN versions, reading the C/S word locked the MB even if it was EMPTY. This behavior will be honoured
when the BCC bit is negated.

then will be written to the MB. If the MB is not unlocked in time and yet another new
message with the same ID arrives, then the new message overwrites the one on the SMB
and there will be no indication of lost messages either in the Code field of the MB or in the
Error and Status Register.
While the message is being moved-in from the SMB to the MB, the BUSY bit on the Code
field is asserted. If the ARM reads the Control and Status word and finds out that the BUSY
bit is set, it should defer accessing the MB until the BUSY bit is negated.
Note
If the BUSY bit is asserted or if the MB is empty, then reading the
Control and Status word does not lock the MB.
Deactivation takes precedence over locking. If the ARM deactivates a locked Rx MB, then
its lock status is negated and the MB is marked as invalid for the current matching round.
Any pending message on the SMB will not be transferred anymore to the MB.
25.4.9 Rx FIFO
The receive-only FIFO is enabled by asserting the FEN bit in the MCR. The reset value of
this bit is zero to maintain software backwards compatibility with previous versions of the
module that did not have the FIFO feature. When the FIFO is enabled, the memory region
normally occupied by the first 8 MBs ($80-$FF) is now reserved for use of the FIFO engine
(see Rx FIFO Structure). Management of read and write pointers is done internally by the
FIFO engine. The ARM can read the received frames sequentially, in the order they were
received, by repeatedly accessing a Message Buffer structure at the beginning of the memory.
The FIFO can store up to 6 frames pending service by the ARM. An interrupt is sent to the
ARM when new frames are available in the FIFO. Upon receiving the interrupt, the ARM
must read the frame (accessing an MB in the $80 address) and then clear the interrupt. The
act of clearing the interrupt triggers the FIFO engine to replace the MB in $80 with the next
frame in the queue, and then issue another interrupt to the ARM. If the FIFO is full and
more frames continue to be received, an OVERFLOW interrupt is issued to the ARM and
subsequent frames are not accepted until the ARM creates space in the FIFO by reading
one or more frames. A warning interrupt is also generated when 4frames are accumulated
in the FIFO.
A powerful filtering scheme is provided to accept only frames intended for the target
application, thus reducing the interrupt servicing work load. The filtering criteria is specified
by programming a table of 8 32-bit registers that can be configured to one of the following
formats (see also Rx FIFO Structure):
• Format A: 8 extended or standard IDs (including IDE and RTR)
• Format B: 16 standard IDs or 16 extended 14-bit ID slices (including IDE and RTR)
• Format C: 32 standard or extended 8-bit ID slices
Note
A chosen format is applied to all 8 registers of the filter table. It
is not possible to mix formats within the table.
The eight elements of the filter table are individually affected by the first eight Individual
Mask Registers (RXIMR0 - RXIMR7), allowing very powerful filtering criteria to be
defined. The rest of the RXIMR, starting from RXIM8, continue to affect the regular MBs,
starting from MB8. If the BCC bit is negated (or if the RXIMR are not available for the
particular MCU), then the FIFO filter table is affected by the legacy mask registers as
follows: element 6 is affected by RX14MASK, element 7 is affected by RX15MASK and
the other elements (0 to 5) are affected by RXGMASK.
25.4.10.1 Remote Frames

Remote frame is a special kind of frame. The user can program a MB to be a Request Remote
Frame by writing the MB as Transmit with the RTR bit set to '1'. After the Remote Request
frame is transmitted successfully, the MB becomes a Receive Message Buffer, with the
same ID as before.
When a Remote Request frame is received by FlexCAN, its ID is compared to the IDs of
the transmit message buffers with the Code field '1010'. If there is a matching ID, then this
MB frame will be transmitted. Note that if the matching MB has the RTR bit set, then
FlexCAN will transmit a Remote Frame as a response.
A received Remote Request Frame is not stored in a receive buffer. It is only used to trigger
a transmission of a frame in response. The mask registers are not used in remote frame
matching, and all ID bits (except RTR) of the incoming received frame should match.
In the case that a Remote Request Frame was received and matched an MB, this message
buffer immediately enters the internal arbitration process, but is considered as normal Tx
MB, with no higher priority. The data length of this frame is independent of the DLC field
in the remote frame that initiated its transmission.
If the Rx FIFO is enabled (bit FEN set in MCR), FlexCAN will not generate an automatic
response for Remote Request Frames that match the FIFO filtering criteria. If the remote
frame matches one of the target IDs, it will be stored in the FIFO and presented to the ARM.
Note that for filtering formats A and B, it is possible to select whether remote frames are
accepted or not. For format C, remote frames are always accepted (if they match the ID).

25.4.10.2 Overload Frames

FlexCAN does transmit overload frames due to detection of the following conditions on
CAN bus:
• Detection of a dominant bit in the first/second bit of Intermission
• Detection of a dominant bit at the seventh bit (last) of End of Frame field (Rx frames)
• Detection of a dominant bit at the eighth bit (last) of Error Frame Delimiter or Overload
Frame Delimiter
25.4.10.3 Time Stamp

The value of the Free Running Timer is sampled at the beginning of the Identifier field on
the CAN bus, and is stored at the end of move-in in the TIME STAMP field, providing
network behavior with respect to time.
The Free Running Timer can be reset upon a specific frame reception, enabling network
time synchronization.
25.4.10.4 Protocol Timing

The FlexCAN only supports the crystal oscillator clock as the CPI clock.
The crystal oscillator clock should be selected whenever a tight tolerance (up to 0.1%) is
required in the CAN bus timing. The crystal oscillator clock has better jitter performance
than PLL generated clocks.
The FlexCAN module supports a variety of means to setup bit timing parameters that are
required by the CAN protocol. The Control Register has various fields used to control bit
timing parameters: PRESDIV, PROPSEG, PSEG1, PSEG2 and RJW.
The PRESDIV field controls a prescaler that generates the Serial Clock (Sclock), whose
period defines the 'time quantum' used to compose the CAN waveform. A time quantum is
the atomic unit of time handled by the CAN engine.
f CANCLK
f Tq = (PrescalerValue)
A bit time is subdivided into three segments3 (reference Figure 25-2 and Table 25-6):
3. For further explanation of the underlying concepts please refer to ISO/DIS 11519–1, Section 10.3. Reference also the Bosch
CAN 2.0A/B protocol specification dated September 1991 for bit timing.

• SYNC_SEG: This segment has a fixed length of one time quantum. Signal edges are
expected to happen within this section
• Time Segment 1: This segment includes the Propagation Segment and the Phase Segment
1 of the CAN standard. It can be programmed by setting the PROPSEG and the PSEG1
fields of the CTRL Register so that their sum (plus 2) is in the range of 4 to 16 time
quanta
• Time Segment 2: This segment represents the Phase Segment 2 of the CAN standard.
It can be programmed by setting the PSEG2 field of the CTRL Register (plus 1) to be
2 to 8 time quanta long
f Tq
BitRate = (number of Time Quanta)
NRZ Signal
SYNC_SEG Time Segment 1 Time Segment 2

(PROP_SEG + PSEG1 + 2) (PSEG2 + 1)
1 4 ... 16 2 ... 8
8 ... 25 Time Quanta

= 1 Bit Time
Transmit Point Sample Point

(single or triple sampling)
Figure 25-2. Segments within the Bit Time
Table 25-6. Time Segment Syntax

Syntax Description
SYNC_SEG System expects transitions to occur on the bus during this period.
Transmit Point A node in transmit mode transfers a new value to the CAN bus at this point.
Sample Point A node samples the bus at this point. If the three samples per bit option is selected, then this point
marks the position of the third sample.
Table 25-7 gives an overview of the CAN compliant segment settings and the related
parameter values.
Table 25-7. CAN Standard Compliant Bit Time Segment Settings
Time Segment 1 Time Segment 2 Re-synchronization Jump Width
5 .. 10 2 1 .. 2

Time Segment 1 Time Segment 2 Re-synchronization Jump Width
4 .. 11 3 1 .. 3
5 .. 12 4 1 .. 4
6 .. 13 5 1 .. 4
7 .. 14 6 1 .. 4
8 .. 15 7 1 .. 4
9 .. 16 8 1 .. 4
Note
It is the user's responsibility to ensure the bit time settings are in
compliance with the CAN standard. For bit time calculations, use
an IPT (Information Processing Time) of 2, which is the value
implemented in the FlexCAN module.
25.4.10.5 Arbitration and Matching Timing

During normal transmission or reception of frames, the arbitration, matching, move-in and
move-out processes are executed during certain time windows inside the CAN frame, as
shown in Figure 25-3.
Start Move
(bit 6)
CRC (15) EOF (7) Interm
Move
Matching/Arbitration Window (24 bits) Window
Figure 25-3. Arbitration, Match and Move Time Windows
When doing matching and arbitration, FlexCAN needs to scan the whole Message Buffer
memory during the available time slot. In order to have sufficient time to do that, the
following requirements must be observed:
• A valid CAN bit timing must be programmed, as indicated in Table 25-7
• The peripheral clock frequency can not be smaller than the oscillator clock frequency,
that is the PLL can not be programmed to divide down the oscillator clock
• There must be a minimum ratio between the peripheral clock frequency and the CAN
bit rate, as specified in Table 25-8

Table 25-8. Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate
Number of Message Buffers Minimum Ratio
16 8
32 8
64 16
A direct consequence of the first requirement is that the minimum number of time quanta
per CAN bit must be 8, so the oscillator clock frequency should be at least eight times the
CAN bit rate. The minimum frequency ratio specified in Table 25-8 can be achieved by
choosing a high enough peripheral clock frequency when compared to the oscillator clock
frequency, or by adjusting one or more of the bit timing parameters (PRESDIV, PROPSEG,
PSEG1, PSEG2). As an example, taking the case of 64 MBs, if the oscillator and peripheral
clock frequencies are equal and the CAN bit timing is programmed to have 8 time quanta
per bit, then the prescaler factor (PRESDIV + 1) should be at least 2. For prescaler factor
equal to one and CAN bit timing with 8 time quanta per bit, the ratio between peripheral
and oscillator clock frequencies should be at least 2.
25.4.11.1 Freeze Mode

This mode is entered by asserting the HALT bit in the MCR Register or when the i.MX28
is put into Debug Mode. In both cases, it is also necessary that the FRZ bit is asserted in
the MCR Register and the module is not in any of the low power modes (Disable, Stop).
When Freeze Mode is requested during transmission or reception, FlexCAN does the
following:
• Waits to be in either Intermission, Passive Error, Bus Off or Idle state
• Waits for all internal activities like arbitration, matching, move-in and move-out to
finish
• Ignores the Rx input pin and drives the Tx pin as recessive
• Stops the prescaler, therefore halting all CAN protocol activities
• Grants write access to the Error Counters Register, which is read-only in other modes
• Sets the NOT_RDY and FRZ_ACK bits in MCR
After requesting Freeze Mode, the user must wait for the FRZ_ACK bit to be asserted in
MCR before executing any other action, otherwise FlexCAN may operate in an unpredictable
way. In Freeze mode, all memory mapped registers are accessible.

Exiting Freeze Mode is done in one of the following ways:

• ARM negates the FRZ bit in the MCR Register
• The MCU is removed from Debug Mode (negating ipg_debug) and/or the HALT bit
is negated
Once out of Freeze Mode, FlexCAN tries to re-synchronize to the CAN bus by waiting for
11 consecutive recessive bits.
25.4.11.2 Module Disable Mode

This low power mode is entered when the MDIS bit in the MCR Register is asserted. If the
module is disabled during Freeze Mode, it shuts down the clocks to the CPI and MBM
sub-modules, sets the LPM_ACK bit and negates the FRZ_ACK bit. If the module is disabled
during transmission or reception, FlexCAN does the following:
• Waits to be in either Idle or Bus Off state, or otherwise waits for the third bit of
Intermission and then checks it to be recessive
finish
• Ignores its Rx input pin and drives its Tx pin as recessive
• Shuts down the clocks to the CPI and MBM sub-modules
• Sets the NOT_RDY and LPM_ACK bits in MCR
The Bus Interface Unit continues to operate, enabling the ARM to access memory mapped
registers, except the Free Running Timer, the Error Counter Register and the Message
Buffers, which cannot be accessed when the module is in Disable Mode. Exiting from this
mode is done by negating the MDIS bit, which will resume the clocks and negate the
LPM_ACK bit.
25.4.11.3 Stop Mode

This is a system low power mode in which all i.MX28 clocks are stopped for maximum
power savings. If FlexCAN receives the global Stop Mode request (through ipg_stop) during
Freeze Mode, it sets the LPM_ACK bit, negates the FRZ_ACK bit and then sends a Stop
Acknowledge signal to the ARM, in order to shut down the clocks globally. If Stop Mode
is requested during transmission or reception, FlexCAN does the following:

• Waits to be in either Idle or Bus Off state, or otherwise waits for the third bit of
Intermission and checks it to be recessive
finish
• Ignores its Rx input pin and drives its Tx pin as recessive
• Sets the NOT_RDY and LPM_ACK bits in MCR
• Sends a Stop Acknowledge signal to the ARM, so that it can shut down the clocks
globally
Exiting Stop Mode is done in one of the following ways:

• ARM resuming the clocks and removing the Stop Mode request
• ARM resuming the clocks and Stop Mode request as a result of the Self Wake
mechanism
In the Self Wake mechanism, if the SLF_WAK bit in MCR Register was set at the time
FlexCAN entered Stop Mode, then upon detection of a recessive to dominant transition on
the CAN bus, FlexCAN sets the WAK_INT bit in the ESR Register and, if enabled by the
WAK_MSK bit in MCR, generates a Wake Up interrupt to the ARM. Upon receiving the
interrupt, the ARM should resume the clocks and remove the Stop Mode request. FlexCAN
will then wait for 11 consecutive recessive bits to synchronize to the CAN bus. As a
consequence, it will not receive the frame that woke it up. Table 25-9 details the effect of
SLF_WAK and WAK_MSK upon wake-up from Stop Mode. Note that wake-up from Stop
Mode only works when both bits are asserted.
Table 25-9. Wake-up from Stop Mode
i.MX28
SLF_WAK WAK_MSK Wake-up Interrupt Generated
Clocks Enabled
0 0 No No
0 1 No No
1 0 No No
1 1 Yes Yes

The sensitivity to CAN bus activity can be modified by applying a low-pass filter function
to the Rx CAN input line while in Stop Mode. This feature can be used to protect FlexCAN
from waking up due to short glitches on the CAN bus lines. Such glitches can result from
electromagnetic interference within noisy environments.
25.4.11.4 Interrupts
The module can generate up to 70 interrupt sources (64 interrupts due to message buffers
and 6 interrupts due to ORed interrupts from MBs, Bus Off, Error, Tx Warning, Rx Warning
and Wake Up).
Each one of the message buffers can be an interrupt source, if its corresponding IMASK
bit is set. There is no distinction between Tx and Rx interrupts for a particular buffer, under
the assumption that the buffer is initialized for either transmission or reception. Each of the
buffers has assigned a flag bit in the IFLAG Registers. The bit is set when the corresponding
buffer completes a successful transmission/reception and is cleared when the ARM writes
it to 1 (unless another interrupt is generated at the same time).
If the Rx FIFO is enabled (bit FEN on MCR set), the interrupts corresponding to MBs 0 to
7 have a different behavior. Bit 7 of the IFLAG1 becomes the FIFO Overflow flag; bit 6
becomes the FIFO Warning flag, bit 5 becomes the Frames Available in FIFO flag and bits
4-0 are unused.
A combined interrupt for all MBs is also generated by an OR of all the interrupt sources
from MBs. This interrupt gets generated when any of the MBs generates an interrupt. In
this case the ARM must read the IFLAG Registers to determine which MB caused the
interrupt.
The other 5 interrupt sources (Bus Off, Error, Tx Warning, Rx Warning and Wake Up)
generate interrupts like the MB ones, and can be read from the Error and Status Register.
The Bus Off, Error, Tx Warning and Rx Warning interrupt mask bits are located in the
Control Register, and the Wake-Up interrupt mask bit is located in the MCR.
25.5 Initialization/Application Information

This section provide instructions for initializing the FlexCAN module.
25.5.1 FlexCAN Initialization Sequence

The FlexCAN module may be reset in three ways:

Initialization/Application Information
• i.MX28 level hard reset using ipg_hard_async_reset_b, which resets all memory mapped
registers asynchronously
• i.MX28 level soft reset, which resets some of the memory mapped registers
synchronously
• SOFT_RST bit in MCR, which has the same effect as the i.MX28 level soft reset
Soft reset is synchronous and has to follow an internal request/acknowledge procedure

across clock domains. Therefore, it may take some time to fully propagate its effects. The
SOFT_RST bit remains asserted while soft reset is pending, so software can poll this bit to
know when the reset has completed. Also, soft reset can not be applied while clocks are
shut down in any of the low power modes. The low power mode should be exited and the
clocks resumed before applying soft reset.
The clock source (CLK_SRC bit) should be selected while the module is in Disable Mode.
After the clock source is selected and the module is enabled (MDIS bit negated), FlexCAN
automatically goes to Freeze Mode. In Freeze Mode, FlexCAN is un-synchronized to the
CAN bus, the HALT and FRZ bits in MCR Register are set, the internal state machines are
disabled and the FRZ_ACK and NOT_RDY bits in the MCR Register are set. The Tx pin
is in recessive state and FlexCAN does not initiate any transmission or reception of CAN
frames. Note that the Message Buffers and the Rx Individual Mask Registers are not affected
by reset, so they are not automatically initialized.
For any configuration change/initialization it is required that FlexCAN is put into Freeze
Mode (see Freeze Mode). The following is a generic initialization sequence applicable to
the FlexCAN module:
• Initialize the Module Configuration Register
• Enable the individual filtering per MB and reception queue features by setting the
BCC bit
• Enable the warning interrupts by setting the WRN_EN bit
• If required, disable frame self reception by setting the SRX_DIS bit
• Enable the FIFO by setting the FEN bit
• Enable the abort mechanism by setting the AEN bit
• Enable the local priority feature by setting the LPRIO_EN bit
• Initialize the Control Register

• Determine the bit timing parameters: PROPSEG, PSEG1, PSEG2, RJW

• Determine the bit rate by programming the PRESDIV field

• Determine the internal arbitration mode (LBUF bit)
• Initialize the Message Buffers

• The Control and Status word of all Message Buffers must be initialized
• If FIFO was enabled, the 8-entry ID table must be initialized
• Other entries in each Message Buffer should be initialized as required
• Initialize the Rx Individual Mask Registers

• Set required interrupt mask bits in the IMASK Registers (for all MB interrupts), in
CTRL Register (for Bus Off and Error interrupts) and in MCR Register for Wake-Up
interrupt
• Negate the HALT bit in MCR
Starting with the last event, FlexCAN attempts to synchronize to the CAN bus.

CAN Hardware Register Format Summary
There are Two CAN in chip. CAN0 base address is 0x80032000 and CAN1 base address
is 0x80034000
HW_CAN memory map
Absolute
Width Section/
(in bits) page
(hex)
8003_2000 Module Configuration Register (HW_CAN_MCR) 32 R/W 5890_000Fh 25.6.1/1578
8003_2004 Control Register (HW_CAN_CTRL) 32 R/W 0000_0000h 25.6.2/1580
8003_2008 Free Running Timer (HW_CAN_TIMER) 32 R/W 0000_0000h 25.6.3/1582
8003_2010 Rx Global Mask (HW_CAN_RXGMASK) 32 R/W FFFF_FFFFh 25.6.4/1583
8003_2014 Rx 14 Mask (HW_CAN_RX14MASK) 32 R/W FFFF_FFFFh 25.6.5/1583
8003_2018 Rx 15 Mask (HW_CAN_RX15MASK) 32 R/W FFFF_FFFFh 25.6.6/1584
8003_201C Error Counter Register (HW_CAN_ECR) 32 R/W 0000_0000h 25.6.7/1584
8003_2020 Error and Status Register (HW_CAN_ESR) 32 R/W 0000_0000h 25.6.8/1586
8003_2024 Interrupt Masks 2 Register (HW_CAN_IMASK2) 32 R/W 0000_0000h 25.6.9/1587
8003_2028 Interrupt Masks 1 Register (HW_CAN_IMASK1) 32 R/W 0000_0000h 25.6.10/1588

HW_CAN memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
8003_202C Interrupt Flags 2 Register (HW_CAN_IFLAG2) 32 R/W 0000_0000h 25.6.11/1588
8003_2030 Interrupt Flags 1 Register (HW_CAN_IFLAG1) 32 R/W 0000_0000h 25.6.12/1589
8003_2034 Glitch Filter Width Register (HW_CAN_GFWR) 32 R/W 0000_007Fh 25.6.13/1590
8003_2080 CAN Messager Buffer Registers (HW_CAN_MBn) 32 R/W 0000_0000h 25.6.14/1590
8003_2880 Rx Individual Mask Registers (HW_CAN_RXIMRn) 32 R/W 0000_0000h 25.6.15/1591
25.6.1 Module Configuration Register (HW_CAN_MCR)

This register defines global system configurations, such as the module operation mode (e.g.,
low power)and maximum message buffer configuration.Most of the fields in this register
can be accessed at any time, except the MAXMB field, which should only be changed while
the module is in Freeze Mode. The default value of this register is 0x5890000f.
The MCR defines global system configurations such as the module operation mode (for
example, low-power mode) and maximum message buffer configuration. The MAXMB
field must only be changed while the module is in freeze mode: all other fields in this register
can be accessed at any time.
Address: HW_CAN_MCR – 8003_2000h base + 0h offset = 8003_2000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NOT_ FRZ_ LPM_

SOFT_RST
WAK_MSK
WAK_SRC
WRN_EN
RSVD3
RDY ACK ACK
HALT
SLF_ SRX_
MDIS FRZ FEN SUPV BCC
WAK DIS
W
Reset 0 1 0 1 1 0 0 0 1 0 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPRIO_EN
R RSVD2 RSVD1 RSVD0

AEN IDAM MAXMB
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
HW_CAN_MCR field descriptions

Field Description
31 This bit controls whether CAN is enabled or not.When disabled, CAN shuts down the clocks to the CAN
MDIS Protocol Interface and Message Buffer Management sub-modules. This is the only bit in MCR not affected
by soft reset.
1 Disable the FlexCAN module

HW_CAN_MCR field descriptions (continued)

Field Description
0 Enable the FlexCAN module
30 The FRZ bit specifies the CAN behavior when the HALT bit in the MCR Register is set or when Debug Mode
FRZ is requested at MCU level (through assertion of the ipg_debug signal on the IP Interface). When FRZ is
asserted, CAN is enabled to enter Freeze Mode. Negation of this bit field causes CAN to exit from Freeze
Mode.
29 This bit controls whether the FIFO feature is enabled or not. When FEN is set, MBs 0 to 7 cannot be used
FEN for normal reception and transmission because the corresponding memory region ($80-$FF) is used by the
FIFO engine.
28 Assertion of this bit puts the CAN module into Freeze Mode. The ARM should clear it after initializing the
HALT Message Buffers and Control Register. No reception or transmission is performed by CAN before this bit is
cleared. While in Freeze Mode, the ARM has write access to the Error Counter Register, that is otherwise
read-only. Freeze Mode can not be entered while CAN is in any of the low power modes.
27 This read-only bit indicates that CAN is either in DisableMode, StopMode or Freeze Mode. It is negated
NOT_RDY once CAN has exited these modes.
26 This bit enables the Wake Up Interrupt generation.

WAK_MSK
25 When this bit is asserted, CAN resets its internal state machines and some of the memory mapped registers.
SOFT_RST The following registers are reset: MCR (except the MDIS bit), TIMER, TCR, ECR, ESR, IMASK1, IMASK2,
IFLAG1, IFLAG2. Configuration registers that control the interface to the CAN bus are not affected by soft
reset.
24 This read-only bit indicates that CAN is in Freeze Mode and its prescaler is stopped.
FRZ_ACK
23 This bit configures some of the CAN registers to be either in Supervisor or Unrestricted memory space.
SUPV
22 This bit enables the Self Wake Up feature when CAN is in Stop Mode. If this bit had been asserted by the
SLF_WAK time CAN entered StopMode, then CAN will look for a recessive to dominant transition on the bus during
these modes.
21 When asserted, this bit enables the generation of the TWRN_INT and RWRN_INT flags in the Error and
WRN_EN Status Register. If WRN_EN is negated, the TWRN_INT and RWRN_INT flags will always be zero,
independent of the values of the error counters, and no warning interrupt will ever be generated.
20 This read-only bit indicates that CAN is either in Disable Mode or Stop Mode.
LPM_ACK
19 This bit defines whether the integrated low-pass filter is applied to protect the Rx CAN input from spurious
WAK_SRC wake up.
18 This bit field is reserved.

RSVD3
17 This bit defines whether CAN is allowed to receive frames transmitted by itself.
SRX_DIS
16 This bit is provided to support Backwards Compatibility with previous CAN versions.
BCC

HW_CAN_MCR field descriptions (continued)

Field Description
15–14 Reserved.
RSVD2
13 This bit is provided for backwards compatibility reasons. It controls whether the local priority feature is
LPRIO_EN enabled or not.
12 This bit is supplied for backwards compatibility reasons.

AEN
11–10 Reserved.
RSVD1
9–8 This 2-bit field identifies the format of the elements of the Rx FIFO filter table
IDAM
7–6 Reserved.
RSVD0
5–0 This 6-bit field defines the maximum number of message buffers that will take part in the matching and
MAXMB arbitration processes.
25.6.2 Control Register (HW_CAN_CTRL)

This register is defined for specific CAN control features related to the CAN bus. The default
value of this register is 0x00000000.
This register is defined for specific FlexCAN control features related to the CAN bus, such
as bit rate, programmable sampling point within an Rx bit, loopback mode, listen-only
mode, bus-off recovery behavior and interrupt enabling (bus-off, error, warning). It also
determines the division factor for the clock prescaler. Most of the fields in this register can
only be changed while the module is in disable mode or in freeze mode. Exceptions are the
BOFF_MSK, ERR_MSK, TWRN_MSK, RWRN_MSK and BOFF_REC bits, that can be
accessed at any time.
Address: HW_CAN_CTRL – 8003_2000h base + 4h offset = 8003_2004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESDIV RJW PSEG1 PSEG2

W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RWRN_MSK
TWRN_MSK
BOFF_MSK
BOFF_REC
R RSVD
TSYN
ERR_ CLK_
LPB SMP LBUF LOM PROP_SEG
MSK SRC
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_CAN_CTRL field descriptions

Field Description
31–24 This 8-bit field defines the ratio between the CPI clock frequency and the serial clock (SCLK) frequency.
PRESDIV
23–22 This 2-bit field defines the maximum number of time quanta that a bit time can be changed by one RJW
RJW re-synchronization.
21–19 This 3-bit field defines the length of phase buffer segment 1 in the bit time.
PSEG1
18–16 This 3-bit field defines the length of phase buffer segment 2 in the bit time.
PSEG2
15 This bit provides a mask for the bus-off interrupt.
BOFF_MSK
14 This bit provides a mask for the error interrupt.
ERR_MSK
13 This bit selects the clock source to the CAN Protocol Interface (CPI) to be either the peripheral clock (driven
CLK_SRC by the PLL) or the crystal oscillator clock.
In i.MX28, the clock source is just from the crystal oscillator clock. Setting this bit has no effects.
12 This bit configures CAN to operate in Loop-Back Mode.

LPB
11 This bit provides a mask for the TxWarning Interrupt associated with the TWRN_INT flag in the Error and
TWRN_MSK Status Register.
10 This bit provides amask for the RxWarning Interrupt associated with the RWRN_INT flag in the Error and
RWRN_MSK Status Register.
9–8 Reserved.
RSVD
7 This bit defines the sampling mode of CAN bits at the Rx input.
SMP
6 This bit defines how CAN recovers from the bus-off state.
BOFF_REC
5 This bit enables a mechanism that resets the free-running timer each time a message is received in Message
TSYN Buffer 0.
4 This bit defines the ordering mechanism for Message Buffer transmission.
LBUF
3 This bit configures CAN to operate in Listen Only Mode.
LOM

HW_CAN_CTRL field descriptions (continued)

Field Description
2–0 This 3-bit field defines the length of the propagation segment in the bit time.
PROP_SEG
25.6.3 Free Running Timer (HW_CAN_TIMER)

This register represents a 16-bit free-running counter that can be read and written by the
ARM. The timer starts at 0x0000 upon reset, counts linearly to 0xFFFF, then wraps back
to 0x0000. The default value of this register is 0x00000000.
This register represents a 16-bit free-running counter that can be read and written by the
ARM. The timer starts at 0x0000 upon reset, counts linearly to 0xFFFF, then wraps back
to 0x0000. The timer is clocked by the FlexCAN bit-clock (which defines the baud rate on
the CAN bus). During a message transmission/reception, it increments each time a bit is
received or transmitted. When there is no message on the bus, it counts using the
previously-programmed baud rate. During freeze mode, the timer is not incremented. The
timer value is captured at the beginning of the identifier field of any frame on the CAN bus.
This captured value is written into the time stamp entry in a message buffer after a successful
reception or transmission of a message. Writing to the timer is an indirect operation. The
data is first written to an auxiliary register and then an internal request/acknowledge
procedure across clock domains is executed. All this is transparent to the user, except for
the fact that the data takes some time to actually be written to the register. If desired, software
can poll the register to discover when the data was actually written.
Address: HW_CAN_TIMER – 8003_2000h base + 8h offset = 8003_2008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD
TIMER
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_CAN_TIMER field descriptions

Field Description
31–16 Reserved .
RSVD
15–0 each time a message is received in Message Buffer
TIMER

25.6.4 Rx Global Mask (HW_CAN_RXGMASK)

The default value of this register is 0xffffffff.
This register is provided for legacy support and for low cost MCUs that do not have the
individual masking per message buffer feature. For MCUs supporting individual masks per
message buffer, setting the BCC bit in the MCR causes the RXGMASK register to have no
effect on the module operation. For MCUs not supporting individual masks per message
buffer, this register is always effective. RXGMASK is used as acceptance mask for all Rx
message buffers, excluding message buffers 14C15, which have individual mask registers.
When the FEN bit in the MCR is set (FIFO enabled), the RXGMASK also applies to all
elements of the ID filter table, except elements 6-7, which have individual masks. Setting
the BCC bit in MCR causes the RXGMASK register to have no effect on the modules
operation. The contents of this register must be programmed while the module is in freeze
mode, and must not be modified when the module is transmitting or receiving frames.
Address: HW_CAN_RXGMASK – 8003_2000h base + 10h offset = 8003_2010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MI
W
Re- 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
set
HW_CAN_RXGMASK field descriptions

Field Description
31–0 This register is provided for legacy support and for low cost MCUs that do not have the individual masking
MI per message buffer feature.
25.6.5 Rx 14 Mask (HW_CAN_RX14MASK)

RX14MASK is used as acceptance mask for the identifier in message buffer 14. When the
FEN bit in the MCR is set (FIFO enabled), the RXG14MASK also applies to element 6 of
the ID filter table. Setting the BCC bit in the MCR causes the RX14MASK register to have
no effect on the module operation. This register has the same structure as RXGMASK. It
must be programmed while the module is in freeze mode, and must not be modified when
the module is transmitting or receiving frames.

Address: HW_CAN_RX14MASK – 8003_2000h base + 14h offset = 8003_2014h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MI
W
Re- 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
set
HW_CAN_RX14MASK field descriptions

Field Description
25.6.6 Rx 15 Mask (HW_CAN_RX15MASK)

When the BCC bit is cleared, RX15MASK is used as acceptance mask for the identifier in
message buffer 15. When the FEN bit in the MCR is set (FIFO enabled), the RXG14MASK
also applies to element 7 of the ID filter table. Setting the BCC bit in the MCR causes the
RX15MASK register to have no effect on the module operation. This register has the same
structure as the RXGMASK. It must be programmed while the module is in freeze mode,
and must not be modified when the module is transmitting or receiving frames.
Address: HW_CAN_RX15MASK – 8003_2000h base + 18h offset = 8003_2018h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MI
W
Re- 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
set
HW_CAN_RX15MASK field descriptions

Field Description
25.6.7 Error Counter Register (HW_CAN_ECR)

This register has two 8-bit fields which reflect the value of the transmit error counter
(tx_err_counter field) and receive error counter (rx_err_counter field).

This register has two 8-bit fields which reflect the value of the transmit error counter
(tx_err_counter field) and receive error counter (rx_err_counter field). The rules for
increasing and decreasing these counters are described in the CAN protocol and are
completely implemented in the FlexCAN module. Both counters are read only except in
freeze mode, where they can be written by the ARM. Writing to the error counter register
while in freeze mode is an indirect operation. The data is first written to an auxiliary register,
and then an internal request/acknowledge procedure across clock domains is executed. All
this is transparent to the user, except for the fact that the data takes some time to actually
be written to the register. If desired, software can poll the register to discover when the data
was actually written. FlexCAN responds to any bus state as described in the protocol, for
example, by transmitting an error active or error passive flag, delaying its transmission start
time (error passive), and avoiding any influence on the bus when in the bus-off state. The
following are the basic rules for FlexCAN bus state transitions: If the value of tx_err_counter
or rx_err_counter increases to exceed 127, the FLT_CONF field in the error and status
register is updated to reflect error passive state. If the FlexCAN state is error passive, and
either tx_err_counter or rx_err_counter decrements to a value less than or equal to 127 while
the other already satisfies this condition, the FLT_CONF field in the error and status register
is updated to reflect error active state. If the value of tx_err_counter increases to be greater
than 255, the FLT_CONF field in the error and status register is updated to reflect the bus-off
state, and an interrupt is issued. The value of tx_err_counter is then reset to zero. If FlexCAN
is in the bus-off state, then tx_err_counter is cascaded together with another internal counter
to count the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
tx_err_counter is reset to zero and counts in a manner where the internal counter counts 11
such bits and then wraps around while incrementing the tx_err_counter. when tx_err_counter
reaches the value of 128, the FLT_CONF field in the error and status register is updated to
be error active and both error counters are reset to zero. at any instance of dominant bit
following a stream of less than 11 consecutive recessive bits, the internal counter resets
itself to zero without affecting the tx_err_counter value. If during system start-up, only one
node is operating, then its tx_err_counter increases in each message it is trying to transmit,
as a result of acknowledge errors (indicated by the ACK_ERR bit in the error and status
register). After the transition to error passive state, the tx_err_counter does not increment
anymore by acknowledge errors. Therefore the device never goes to the bus-off state. If the
rx_err_counter increases to a value greater than 127, it is not incremented further, even if
more errors are detected while being a receiver. At the next successful message reception,
the counter is set to a value between 119 and 127 to resume to error active state.

Address: HW_CAN_ECR – 8003_2000h base + 1Ch offset = 8003_201Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD
RX_ERR_COUNTER TX_ERR_COUNTER
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_CAN_ECR field descriptions

Field Description
31–16 Reserved .
RSVD
15–8 Receive error counter
RX_ERR_
COUNTER
7–0 Transmit error counter
TX_ERR_
COUNTER
25.6.8 Error and Status Register (HW_CAN_ESR)

This register reflects various error conditions, some general status of the device and it is
the source of four interrupts to the ARM.
This register reflects various error conditions, some general status of the device and it is
the source of four interrupts to the ARM. The reported error conditions are those that
occurred since the last time the ARM read this register. The ARM read action clears bits.
Bits are status bits. Most bits in this register are read-only, except TWRN_INT, RWRN_INT,
BOFF_INT, WAK_INT and ERR_INT, which are interrupt flags that can be cleared by
writing 1 to them (writing 0 has no effect).
Address: HW_CAN_ESR – 8003_2000h base + 20h offset = 8003_2020h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD1
TWRN_ RWRN_
INT INT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIT1_ BIT0_ ACK_ CRC_ FRM_ STF_ TX_ RX_

BOFF_INT
IDLE TXRX FLT_CONF

WAK_INT
R RSVD0
ERR ERR ERR ERR ERR ERR WRN WRN
ERR_
INT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

HW_CAN_ESR field descriptions

Field Description
31–18 Reserved .
RSVD1
17 If theWRN_EN bit in MCR is asserted, the TWRN_INT bit is set when the TX_WRN flag transition from 0 to
TWRN_INT 1, meaning that the Tx error counter reached
16 If theWRN_EN bit in MCR is asserted, the RWRN_INT bit is set when the RX_WRN flag transition from 0
RWRN_INT to 1, meaning that the Rx error counters reached
15 This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message.
BIT1_ERR
14 This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message.
BIT0_ERR
13 This bit indicates that an Acknowledge Error has been detected by the transmitter node
ACK_ERR
12 This bit indicates that a CRC Error has been detected by the receiver node
CRC_ERR
11 This bit indicates that a Form Error has been detected by the receiver node
FRM_ERR
10 This bit indicates that a Stuffing Error has been detected.
STF_ERR
9 This bit indicates when repetitive errors are occurring during message transmission.
TX_WRN
8 This bit indicates when repetitive errors are occurring during message reception.
RX_WRN
7 This bit indicates when CAN bus is in IDLE state.
IDLE
6 This bit indicates if CAN is transmitting or receiving a message when the CAN bus is not in IDLE state.
TXRX
5–4 This 2-bit field indicates the Confinement State of the CAN module
FLT_CONF
3 Reserved.
RSVD0
2 This bit is set when CAN enters Bus Off state
BOFF_INT
1 This bit indicates that at least one of the Error Bits (bits 15-10) is set.
ERR_INT
0 When CAN is Stop Mode and a recessive to dominant transition is detected on the CAN bus and if the
WAK_INT WAK_MSK bit in the MCR Register is set, an interrupt is generated to the ARM.
25.6.9 Interrupt Masks 2 Register (HW_CAN_IMASK2)

The default value of this register is 0x00000000.

This register allows any number of a range of 32 message buffer interrupts to be enabled
or disabled. It contains one interrupt mask bit per buffer, enabling the ARM to determine
which buffer generates an interrupt after a successful transmission or reception (that is,
when the corresponding IFLAG2 bit is set).
Address: HW_CAN_IMASK2 – 8003_2000h base + 24h offset = 8003_2024h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BUFM
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_CAN_IMASK2 field descriptions

Field Description
31–0 Each bit enables or disables the respective FlexCAN message buffer interrupt (message buffers 32~63).
BUFM
25.6.10 Interrupt Masks 1 Register (HW_CAN_IMASK1)

This register enables or disables any number of a range of 32 message buffer interrupts. It
contains one interrupt mask bit per buffer, enabling the ARM to determine which buffer
generates an interrupt after a successful transmission or reception (that is, when the
corresponding IFLAG1 bit is set)
Address: HW_CAN_IMASK1 – 8003_2000h base + 28h offset = 8003_2028h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BUFM
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_CAN_IMASK1 field descriptions

Field Description
31–0 This register allows any number of a range of 32 message buffer interrupts to be enabled or disabled.
BUFM
25.6.11 Interrupt Flags 2 Register (HW_CAN_IFLAG2)


This register defines the flags for 32 message buffer interrupts. It contains one interrupt
flag bit per buffer. Each successful transmission or reception sets the corresponding IFLAG2
bit. If the corresponding IMASK2 bit is set, an interrupt is generated. The interrupt flag
must be cleared by writing a 1; writing 0 has no effect. When the AEN bit in the MCR is
set (abort enabled), while the IFLAG2 bit is set for a message buffer configured as Tx,
ARM write access to the corresponding message buffer is blocked.
Address: HW_CAN_IFLAG2 – 8003_2000h base + 2Ch offset = 8003_202Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BUFI
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_CAN_IFLAG2 field descriptions

Field Description
31–0 This register defines the flags for 32Message Buffer interrupts.
BUFI
25.6.12 Interrupt Flags 1 Register (HW_CAN_IFLAG1)

This register defines the flags for 32 message buffer interrupts and FIFO interrupts. It
contains one interrupt flag bit per buffer. Each successful transmission or reception sets the
corresponding IFLAG1 bit. If the corresponding IMASK1 bit is set, an interrupt is generated.
The interrupt flag must be cleared by writing a 1 to it. Writing 0 has no effect. Setting the
abort enabled (AEN) bit in the MCR while the IFLAG1 bit is set for a message buffer
configured as Tx blocks the ARMs write access to the corresponding message buffer. Setting
the FIFO enable (FEN) bit in the MCR changes the function of the 8 least significant interrupt
flags (BUF7ICBUF0I) to support the FIFOs operation. BUF7I, BUF6I, and BUF5I indicate
operating conditions of the FIFO; BUF4ICBUF0I are not used.
Address: HW_CAN_IFLAG1 – 8003_2000h base + 30h offset = 8003_2030h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BUFI
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

HW_CAN_IFLAG1 field descriptions

Field Description
31–0 This register defines the flags for 32 Message Buffer interrupts.
BUFI
25.6.13 Glitch Filter Width Register (HW_CAN_GFWR)

The default value of this register is 0x0000007f.
The Glitch Filter just takes effects when the FlexCAN enters the STOP mode.
Address: HW_CAN_GFWR – 8003_2000h base + 34h offset = 8003_2034h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD0
GFWR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
set
HW_CAN_GFWR field descriptions

Field Description
31–8 Reserved
RSVD0
7–0 The Glitch Filter Width Register defines the glitch width which will be filtered.
GFWR
25.6.14 CAN Messager Buffer Registers (HW_CAN_MBn)

The default value of this register is 0x00000000. There are 64 MB registers ( MB0~MB63)
n denotes the number from 0 to 63.
See the Messager Buffer structure in previous section.
Address: HW_CAN_MBn – 8003_2000h base + 80h offset = 8003_2080h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MBn
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

HW_CAN_MBn field descriptions

Field Description
31–0 These registers are used as acceptance storage for messages.
MBn
25.6.15 Rx Individual Mask Registers (HW_CAN_RXIMRn)

The default value of this register is 0x00000000. There are 64 Rx Individual Mask registers
( RXIMR0¨RXIMR63) n denotes the number from 0 to 63.
These registers are used as acceptance masks for ID filtering in Rx message buffers and the
FIFO. If the FIFO is not enabled, one mask register is provided for each available message
buffer, providing ID masking capability on a per message buffer basis. When the FIFO is
enabled (FEN bit in the MCR is set), the first 8 mask registers apply to the 8 elements of
the FIFO filter table (on a one-to-one correspondence), while the rest of the registers apply
to the regular message buffers, starting from message buffer 8. The individual Rx mask
registers are implemented in RAM, so they are not affected by reset and must be explicitly
initialized prior to any reception. Furthermore, they can only be accessed by the ARM while
the module is in freeze mode. Outside of freeze mode, write accesses are blocked and read
accesses return all zeros. Furthermore, if the BCC bit in the MCR is cleared, any read or
write operation to these registers results in an access error.
Address: HW_CAN_RXIMRn – 8003_2000h base + 880h offset = 8003_2880h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MI
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_CAN_RXIMRn field descriptions

Field Description
31–0 These registers are used as acceptance masks for ID filtering in Rx message buffers and the FIFO.
MI


Chapter 26
Ethernet Controller (ENET)
26.1 Overview
The ethernet controller (ENET) consists of two MACs (media access controllers), each with
it's own dedicated uDMA (unified DMA) module. The MAC module is third party IP from
"More Than IP" (MTIP). The MACs interface to 10 Mbps and 100 Mbps Ethernet/IEEE
802.3™ networks. For Ethernet, an external PHY or SerDes device is required to complete
the interface to the media. Each MAC supports multiple standard media-independent
interfaces. An integrated 3-Port Switch allows the macs to filter and forward traffic at
wire-speed to each other or the core, or operate as two independent ports.
The ENET assembly provides two master ports on the AHB Bus. IP provides interface for
connecting various FIFOs for data storage (for MAC and Switch).
The ENET MAC is backward compatible with the Freescale FEC controller (Such as the
FEC used in i.MX25).
26.1.1 Block Diagram

SOC Pad
MAC0 uDMA0
APB Mux
APB AHB
Bus Switch Bus
MAC1 uDMA1
Figure 26-1.SOC Pad Overview Block Diagram

ENET
26.1.2 Features
• MAC supports full 802.3 specification with preamble/SFD generation, frame padding
generation, CRC generation and checking

Unified DMA Block Guide
• Dynamically configurable to support 10/100 Mbps

• Supports full duplex and configurable half duplex operations
• Supports AMD magic packet detection with interrupt for node remote power
management
• Supports interface to Fast Ethernet Phy devices through Medium independent interface
(MII) working at 25 MHz and Reduced Medium independent interface (RMII) working
at 50 MHz
• Provides 64 bit FIFO interface (transmit and receive)
• When operating in Full Duplex mode, implements automated Pause Frame (802.3 x
31A) generation and termination providing flow control without user application
intervention
• Implements standard flow control mechanism in full duplex operation mode
• In half duplex mode, provides full collision support, including jamming, backoff and
automatic retransmission
• Support for VLAN tagged frames as per IEEE 802.1Q
• Programmable MAC address
• Multicast and unicast address filtering on receive based on 64 entries hash table thus
reducing higher layer processing load
• Programmable frame maximum length providing support for any standard or proprietary
frame length
• Statistic indicators for frame traffic as well as errors (alignment, CRC error and so on)
and pause frames providing for IEEE 802.3 basic and mandatory management
information database (MIB) package and Remote network monitoring (RFC 2819)
• Multiple internal loopback options
• MDIO master interface for PHY device configuration
• Support for all IEEE 1588 frames
• Reference clock can be chosen independently of network speed
• Software programmable precise time stamping of Ingress frames and Egress frames
• Hardware and software controllable timer synchronization
26.2 Unified DMA Block Guide

This section includes an introduction, descriptions of signals, a description of the control
interface, and a functional description.
26.2.1 Introduction
This section includes an overview, description of features, and a description of the modes
of operation.

Chapter 26 Ethernet Controller (ENET)
26.2.1.1 Overview
The Unified DMA (uDMA) block is connected with the ENET-MAC and through the
3PSWITCH. This is NOT a general purpose DMA but is highly specific to support Ethernet
traffic.
Fundamentally, there are two basic modes of operation. The uDMA supports a legacy mode
which enables data to be transferred in a format significantly consistent with the legacy
FEC device that exists on several parts through the Legacy Buffer Descriptor (LBD).
Additionally the uDMA supports an Enhanced Buffer Descriptor (EBD) which in turn
provides the ability to make use of several new features including (but not limited to)
IEEE-1588 support, Gigabit Ethernet, transmit error checking and various off loading
features.
The uDMA blocks are highlighted in Figure 26-2.
SOC Pad
1
2 3
MAC0 uDMA0
APB Mux
APB AHB
Bus Switch Bus
MAC1 2 uDMA1 3
Figure 26-2.SOC Pad uDMA SoC Connection

Typical
In reference to the figure:

1 - The interface between the MAC-NET and the SoC Pad Logic. All pin multiplexing takes
place outside the ENET-MAC, including RMII and MII.
2 - The ENET-MAC communicates with the Unified DMA through two FIFO interfaces.
One of the FIFO interfaces is for RX the other is for TX. These interfaces also contain a
set of sideband signals.
3 - The Unified DMA communicates with the SoC Platform through this interface.
26.2.1.2 Features
The primary features of the uDMA are listed below:
• Only Surport big-endian.
• Separate TX and RX interfaces to allow for minimum space or maximum data
throughput.
• Supports Legacy Buffer Descriptor programming models and functionality.

• Enables an Enhanced Buffer Descriptor programming model to support new Ethernet
functionality.
26.2.1.3 Modes of Operation

The primary modes of operation of the uDMA are described in this section:
• Legacy mode
• Enhanced mode
26.2.1.3.1 Legacy Mode

While in legacy mode, the uDMA reads and generates Legacy Buffer Descriptors (LBD).
Additionally, great effort is made to ensure that support signals such as interrupts behave
consistently with the legacy programming model used with the FEC. This is the default
mode of operation.
26.2.1.3.2 Enhanced Mode
While in enhanced mode, the uDMA reads and generates Enhanced Buffer Descriptors
(EBD). The descriptors are based on the LBD but allow for the support of additional features
such as IEEE-1588 support, additional interrupts and error checking among other features.
While in this mode, there is no hard requirement that the programming model is consistent
with the legacy programming model; however where reasonable the same look and feel is
accomplished.
26.2.2 Functional Description

This section provides the detailed functional description of the uDMA. The uDMA is a data
mover between the FIFO interface and the bus master and vice-versa. Additionally, the
uDMA is responsible for formatting the data being transferred into and out of buffer
descriptors. Further, the uDMA is responsible for the generation of various control signals
(that is, interrupts) that may occur during the process. The uDMA is the key link for enabling
the legacy programming format of the FEC module to work with the ENET-MAC.
This section provides the technical details for the uDMA. Additional details required for
legacy mode compatibility is provided in the FEC specification (FEC_BlockGuide.pdf).
There are two FIFO interfaces, one for transmit and one for receive. Please refer to the
documentation in the reference section for the detailed specification for these FIFO interfaces.

26.2.2.1 Legacy Buffer Descriptor Models

Table 26-1 and Table 26-2 show the legacy buffer descriptor (LBD) models.
26.2.2.1.1 Legacy FEC Receive Buffer Descriptor
This section discusses the legacy FEC receive buffer descriptors.
Table 26-1. Legacy FEC Receive Buffer Descriptor
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Offset + 0 E RO1 W RO2 L — — M BC MC LG NO — CR OV TR
Offset + 2 Data length
Offset + 4 RX Data Buffer Pointer - A[31:16]
Offset + 6 RX Data buffer Pointer - A[15:0]
The following sections reference Table 26-1.

26.2.2.1.1.1 Bit-15 E
Empty. Written by the uDMA (=0) and user (=1). The functionality and
operation of this bit does not change from the FEC. The uDMA clears this bit to indicate
that the buffer descriptor is complete and ready for the driver to process.
26.2.2.1.1.2 Bit-14 RO1
Receive software ownership. This field is reserved for use by software. This
read/write bit will not be modified by hardware, nor will its value affect hardware.
26.2.2.1.1.3 Bit-13 W
Wrap. Written by user. The functionality and operation of this bit does not
change from the FEC. It indicates the next buffer descriptor the uDMA is supposed to use.
If 0 the next buffer descriptor is found in the consecutive location, and if 1 the next buffer
descriptor is found at the location defined in ERDSR.
26.2.2.1.1.4 Bit-12 RO2
Receive software ownership.This field is reserved for use by software. This
26.2.2.1.1.5 Bit-11 L
Last in frame. Written by the uDMA. Setting this bit to '1' indicates that the
buffer descriptor is the last buffer descriptor in the frame.
26.2.2.1.1.6 Bit-10 and Bit 9 —
These bits are reserved and must not be modified.

26.2.2.1.1.7 Bit-8 M
Miss. Written by the uDMA. This bit is set by the uDMA for frames accepted
in promiscuous mode, but flagged as a miss by the internal address recognition. Therefore,
while in promiscuous mode, the user can use the M-bit to quickly determine whether the
frame was destined to this station. This bit is only valid if the L-bit is set and the PROM
bit is set inside the ENET-MAC. If 0,the frame was received because of an address
recognition hit. If 1, the frame was received because of promiscuous mode. This field is
only valid if the BD is the last in the frame, that is, L-bit is set.
26.2.2.1.1.8 Bit-7 BC
Set if the DA is broadcast (FF-FF-FF-FF-FF-FF).
26.2.2.1.1.9 Bit-6 MC
Set if the DA is multicast and not BC.
26.2.2.1.1.10 Bit-5 LG
Rx frame length violation, written by the uDMA. A frame length greater
than MAX_FL was recognized. This bit is valid only if the L-bit is set. The receive data is
not altered in any way unless the length exceeds TRUNC_FL bytes.
26.2.2.1.1.11 Bit-4 NO
Receive non-octet aligned frame, written by the uDMA. A frame that
contained a number of bits not divisible by 8 was received, and the CRC check that occurred
at the preceding byte boundary generated an error or Phy error occurred. This bit is valid
only if the L-bit is set. If this bit is set the CR bit will not be set.
26.2.2.1.1.12 Bit-3 —
Reserved.
26.2.2.1.1.13 Bit-2 CR
Rx CRC or Rx Frame error, written by the uDMA. This frame contains a
Frame with Phy error or CRC error and is an integral number of octets in length. This bit
is valid only if the L-bit is set.
26.2.2.1.1.14 Bit-1 OV
Overrun, written by the uDMA. A receive FIFO overrun occurred during
frame reception. If this bit is set, the other status bits, M, LG, NO, SH, CR, and CL lose
their normal meaning and will be zero. This bit is valid only if the L-bit is set.
26.2.2.1.1.15 Bit-0 TR
Will be set if the receive frame is truncated (frame length > TRUNC_FL).
If the TR bit is set, the frame should be discarded and the other error bits should be ignored
as they may be incorrect.

26.2.2.1.1.16 Data Length

Data length. Written by the uDMA. Data length is the number of octets
written by the uDMA into this BD's data section. If L equals 0, the value written will be
equal to EMRBR. If L equals 1, complete length of the frame including the CRC. It is
written by the uDMA once as the BD is closed.
26.2.2.1.1.17 RX Data Buffer Pointer - A[31:16]
RX data buffer pointer, bits [31:16].
26.2.2.1.1.18 RX Data Buffer Pointer - A[15:0]
RX data buffer pointer, bits [15:0]. The receive buffer pointer, which always
points to the first location of the associated data buffer, must always be evenly divisible by
16.
26.2.2.1.20 Legacy FEC Transmit Buffer Descriptor
This section discusses the legacy FEC transmit buffer descriptors.
Table 26-2. Legacy FEC Transmit Buffer Descriptor
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Offset + 0 R TO1 W TO2 L TC ABC — — — — — — — — —
Offset + 4 TX Data Buffer Pointer A[31:16]
Offset + 6 TX Data buffer Pointer A[15:0]

26.2.2.1.20.1 Bit-15 R
Ready. Written by the uDMA (=0) and the user (=1). It is set by the user
to indicate the buffer descriptor is ready for transmission. The uDMA clears this bit at the
start of data transmission.
26.2.2.1.20.2 Bit-14 TO1
Transmit software ownership. This field is reserved for software use. This
read/write bit will not be modified by hardware, nor will its value affect the hardware.
26.2.2.1.20.3 Bit-13 W
Wrap. Written by user. The functionality and operation of this bit does not
change from the FEC.
• 0 The next buffer descriptor is found in the consecutive location.
• 1 The next buffer descriptor is found at the location defined in ETDSR.

26.2.2.1.20.4 Bit-12 TO2

Transmit software ownership. This field is reserved for software use. This
26.2.2.1.20.5 Bit-11 L
Last in frame. Written by the user. The functionality and operation of this
bit does not change from the FEC.
• 0 The buffer descriptor is not the last in the transmit frame.
• 1 The buffer descriptor is the last in the transmit frame.
26.2.2.1.20.6 Bit-10 TC
Tx CRC. This bit is written by the user. If '0' this indicates that the frame is sent as-is and
it is up to the software to provide a valid frame with CRC field. If '1' the MAC will calculate
and append the CRC field to the frame.
26.2.2.1.20.7 Bit-9 ABC
Append bad CRC. This bit is not supported in the uDMA legacy or enhanced
modes and is ignored.
26.2.2.1.20.8 Bit 8-0 —
These values are reserved and should not be modified.
Datalength. Written by the user. The functionality and operation of this
field does not change from the FEC.
26.2.2.1.20.10 TX Data Buffer Pointer A[31:16]
TX data buffer pointer. A[31:0] contains the address of the associated data
buffer and must always be evenly divisible by 4. The functionality and operation of this
field does not change from the FEC.
26.2.2.1.20.11 TX Data Buffer Pointer A[15:0]
TX data buffer pointer. The functionality and operation of this field does
not change from the FEC.
26.2.2.31 Enhanced Buffer Descriptor Models

In order to support various new functionality now available in the ENET-MAC the uDMA
also supports an enhanced buffer descriptor model (EBD). Table 26-3 and Table 26-4 shows
what is being referred to as the EBD models. To promote the maximum reuse of driver
software where possible the LBD fields were reused.
26.2.2.31.1 Enhanced uDMA Receive Buffer Descriptor
This section discusses the enhanced uDMA receive buffer descriptors.

Table 26-3. Enhanced uDMA Receive Buffer Descriptor

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Offset + 0 E RO1 W RO2 L — — M BC MC LG NO — CR OV TR
Offset + 4 RX Data Buffer Pointer A[31:16]
Offset + 6 RX Data buffer Pointer A[15:0]
Offset + 8 ME — — — — PE CE UC INT — — — — — — —
Offset + A — — — — — — — — — — ICE PCR — VLAN IPV6 FRAG
Offset + C Header Length — — — Protocol Type
Offset + E Payload Checksum
Offset + 10 BDU — — — — — — — — — — — — — — —
Offset + 12 — — — — — — — — — — — — — — — —
Offset + 14 1588 Timestamp[31:16]
Offset + 16 1588 Timestamp[15:0
Offset + 18 — — — — — — — — — — — — — — — —
Offset + 1A — — — — — — — — — — — — — — — —
Offset + 1C — — — — — — — — — — — — — — — —
Offset + 1E — — — — — — — — — — — — — — — —
26.2.2.31.1.1 Offset + 0 Bit 15:0

This set of bits behaves exactly as in legacy mode with the exception of bit
15 E. See Legacy FEC Receive Buffer Descriptor. The Last Buffer Descriptor is already
updated when bit E=0 and bit BDU=1.
This field behaves exactly the same as in legacy mode. See Legacy FEC
Receive Buffer Descriptor .
26.2.2.31.1.3 RX Data Buffer Pointer A[31:16]
Receive Buffer Descriptor.
26.2.2.31.1.4 RX Data Buffer Pointer A[15:0]
Receive Buffer Descriptor.

26.2.2.31.1.5 Offset + 8 Bit 15 ME

MAC error. This bit is written by the uDMA. This bit means that the frame stored in the
system memory was received with an error. This bit is only valid when the L-bit is set.
26.2.2.31.1.6 Offset + 8 Bit 14 —
This bit is not used (reserved) since the uDMA aborts the operation when
a DMA detects an error during the data transfer.
26.2.2.31.1.7 Offset + 8 Bit 10 PE
PHY Error. This bit is written by the uDMA. Set to 1 when the frame was received with an
Error character on the PHY interface. The frame is invalid. This bit is valid only when the
L-bit is set.
26.2.2.31.1.8 Offset + 8 – Bit 9 CE
Collision. This bit is written by the uDMA. Set to 1 when the frame was received with a
collision detected during reception. The frame is invalid and sent to the user application.
This bit is valid only when the L-bit is set.
26.2.2.31.1.9 Offset + 8 – Bit 8 UC
Unicast. This bit is written by the uDMA. This bit means that the frame is unicast. This bit
is valid regardless of if the L-bit is set.
26.2.2.31.1.10 Offset + 8 – Bit 7 INT
Generate RXB/RXF interrupt. This bit is set by the user. This bit indicates
that the uDMA is to generate an interrupt on the dma_int_rxb / dma_int_rxf event.
26.2.2.31.1.11 Offset + A – Bit 5 ICE
IP header checksum error. This is an accelerator option. This bit is written by the uDMA.
Set to 1 when either not an IP frame is received, or the IP header checksum was invalid.
This bit is only valid if the L-bit is set.
26.2.2.31.1.12 Offset + A – Bit 4 PCR
Protocol checksum error. This is an accelerator option. This bit is written by the uDMA.
Set to 1 when the checksum of the protocol is invalid, or an unknown protocol is found and
checksumming could not be performed. This bit is only valid if the L-bit is set.
26.2.2.31.1.13 Offset + A – Bit 3 —
Type removed. This is an accelerator option. This bit is written by the uDMA. If set, this
bit indicates that the frame's type feld has been removed: The frames payload starts
immediately after the MAC source address within the frame, or after the VLAN tag if
present. This bit is only valid if the L-bit is set. The date for this bit comes from the MTIP
sideband signal ff_rx_ip_stat[7].

26.2.2.31.1.14 Offset + A – Bit 2 VLAN

VLAN. This is an accelerator option. This bit is written by the uDMA. This bit means that
the frame has a VLAN tag. This bit is valid only if the L-bit is set.
26.2.2.31.1.15 Offset + A – Bit 1 IPV6
IPV6 Frame. This bit is written by the uDMA. This bit indicates that the frame has a IPv6
frame type. If this bit is not set, it means that an IPv4 or other protocol frame was received.
This bit is valid only if the L-bit is set.
26.2.2.31.1.16 Offset + A – Bit 0 FRAG
Pv4 Fragment.This is an accelerator option.This bit is written by the uDMA.This bit indicates
that the frame is an IPv4 fragment frame. This bit is only valid when the L-bit is set.
26.2.2.31.1.17 Offset + C – Bit [15:11] Header Length
Header length. This is an accelerator option. This field is written by the
uDMA. This field is the sum of 32 bit words found within the IP and its following protocol
headers. If an IP datagram with an unknown protocol is found, the value is the length of
the IP header. If no IP frame or an erroneous IP header is found, the value is 0. The following
values are minimum values if no header options exist in the respective headers:
• ICMP/IP: 6 (5 IP header, 1 ICMP header)
• UDP/IP: 7 (5 IP header, 2 UDP header)
• TCP/IP: 10 (5 IP header, 5 TCP header)
This field is only valid if the L-bit is set.
26.2.2.31.1.18 Offset + C – Bit [7:0] Protocol Type
Protocol type. This is an accelerator option. The 8-Bit protocol field found
within the IP header of the frame. Only valid if "ICE" bit is 0. This bit is only valid if the
L-bit is set.
26.2.2.31.1.19 Offset + E – Bit [15:0] Payload Checksum
Internet payload checksum. This is an accelerator option. The one's complement sum of the
payload section of the IP frame. The sum is calculated over all data following the IP header
until the end of the IP payload. This field is valid only when the L-bit is set.
26.2.2.31.1.20 Offset + 0x10 – Bit 15 BDU
Last Buffer Descriptor Update Done. This bit indicates that all the last
BD data has been updated by uDMA. This bit is written by the user (=0) and uDMA (=1).
26.2.2.31.1.21 1588 Timestamp [31:0]
It is only valid if the L-bit is set.

26.2.2.31.23 Enhanced uDMA Transmit Buffer Descriptor

This section discusses the enhanced uDMA transmit buffer descriptors.
Table 26-4. Enhanced uDMA Transmit Buffer Descriptor
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Offset + 0 R TO1 W TO2 L TC - - - - - - - - - -
Offset + 4 TX Data Buffer Pointer - A[31:16]
Offset + 6 TX Data buffer Pointer - A[15:0]
Offset + 8 - INT TS PINS IINS - - - - - - - - - - -
Offset + A TXE - UE EE FE LCE OE TSE - - - - - - - -
Offset + C - - - - - - - - - - - - - - - -
Offset + E - - - - - - - - - - - - - - - -
Offset + 10 BDU - - - - - - - - - - - - - - -
Offset + 12 - - - - - - - - - - - - - - - -
Offset + 14 1588 Timestamp [31:16]
Offset + 16 1588 Timestamp [15:0]
Offset + 18 - - - - - - - - - - - - - - - -
Offset + 1A - - - - - - - - - - - - - - - -
Offset + 1C - - - - - - - - - - - - - - - -
Offset + 1E - - - - - - - - - - - - - - - -

26.2.2.31.23.1 Offset + 0 - Bit 15:0
This functionality does not change from the legacy programming model
with the exception of bit 9 "ABC" which has been explicitly removed and bit 15 "R". See
Legacy FEC Transmit Buffer Descriptor.
26.2.2.31.23.2 Offset + 2 - Data Length
This functionality does not change from the legacy programming model.
See Legacy FEC Transmit Buffer Descriptor .

26.2.2.31.23.3 Offset + 4 and Offset + 6 - TX Data Buffer Pointer

This functionality does not change from the legacy programming model.
See Legacy FEC Transmit Buffer Descriptor.
26.2.2.31.23.4 Offset + 8 Bit 15 "-"
Error Indication. This bit is written by the user. This bit is used by the
application software to indicate that the frame stored in the system memory contains an
error. This bit is valid regardless of if the L-bit is set and must be the same for all EBD for
a given frame. The uDMA does not update this value.
26.2.2.31.23.5 Offset + 8 Bit 14 "INT"
Generate interrupt. This bit is written by the user. This indicates that the
uDMA is to generate a dma_int_txb / dma_int_txf interrupt in relation to this frame / buffer
descriptor. This bit is valid regardless of if the L-bit is set and must be the same for all EBD
for a given frame. The uDMA does not update this value.
26.2.2.31.23.6 Offset + 8 Bit 13 "TS"
Timestamp. This bit is written by the user. This indicates that the uDMA is to generate a
timestamp frame. This bit is valid regardless of if the L-bit is set and must be the same for
all EBD for the given frame. The uDMA does not update this value.
26.2.2.31.23.7 Offset + 8 Bit 12 "PINS"
Insert protocol specifc checksum. This bit is written by the user. If '1' the MAC's IP
accelerator calculates the protocol checksum and overwrites the corresponding checksum
feld with the calculated value. The checksum feld must be set to 0 by the application
generating the frame. The uDMA does not update this value. This bit is valid regardless of
if the L-bit is set and must be the same for all EBD for a given frame.
26.2.2.31.23.8 Offset + 8 Bit 11 "IINS"
Insert IP header checksum. This bit is written by the user. If '1' the MAC's IP accelerator
calculates the IP header checksum and overwrites the corresponding header feld with the
calculated value. The checksum feld must be set to 0 by the application generating the
frame. The uDMA does not update this value. This bit is valid regardless of if the L-bit is
set and must be the same for all EBD for a given frame.
26.2.2.31.23.9 Offset + A Bit 15 "TXE"
Transmit error occurred. This bit is written by the uDMA. This bit indicates
that there was a transmit error reported with the frame. Effectively this bit is the "or" of all
other error bits including UE, EE, FE, LCE, OE, and TSE. This bit is only valid when the
L-bit is set.

26.2.2.31.23.10 Offset + A Bit 14 "-"

This bit is not used (reserved) since the uDMA will abort the operation
when a DMA detects an error during the data transfer.
26.2.2.31.23.11 Offset + A Bit 13 "UE"
Underflow error. This bit is written by the uDMA. This bit indicates that the MAC reported
an underfow error on transmit.
26.2.2.31.23.12 Offset + A Bit 12 "EE"
Excess Collision error. This bit is written by the uDMA. This bit indicates that the MAC
reported an excess collision error on transmit. This bit is only valid when the L-bit is set.
26.2.2.31.23.13 Offset + A Bit 11 "FE"
Frame with error. This bit is written by the uDMA. This bit indicates that the MAC reported
that the uDMA reported an error when providing the packet. This bit is only valid when the
L-bit is set.
26.2.2.31.23.14 Offset + A Bit 10 "LCE"
Late collision error. This bit is written by the uDMA. This bit indicates that the MAC
reported that there was a Late Collision on transmit. This bit is only valid when the L-bit
is set.
26.2.2.31.23.15 Offset + A Bit 9 "OE"
Overfow error. This bit is written by the uDMA. This bit indicates that the MAC reported
that there was a FIFO overfow condition on transmit. This bit is only valid when the L-bit
is set.
26.2.2.31.23.16 Offset + A Bit 8 "TSE"
Timestamp error. This bit is written by the uDMA. This bit indicates that the MAC reported
a different frame type then a timestamp frame. This bit is only valid when the L-bit is set.
26.2.2.31.23.17 Offset + 0x10 - Bit 15 "BDU"
Last Buffer Descriptor Update Done. This bit indicates that all the last
BD data has been updated by uDMA. This bit is written by the user (=0) and uDMA (=1).
26.2.2.31.23.18 1588 Timestamp [31:0]
This value is written by the uDMA when switch is in Bypass mode. It is only valid if the
L-bit is set.

26.3 Ethernet ENET-MAC Core

This section describes the ENET-MAC core, including the block diagram and formats.
26.3.1 Introduction
Ethernet is available in different speeds (10/100 Mbps) and provides connectivity to meet
a wide range of needs and from desktop to switches.
10GbEth
1GbEth Access switch
Backone
switch
1GbEth 1GbEth
Work group Work group

Switch Switch
100MbEth 100MbEth 100MbEth

10MbEth
Desktop (Wiring Closet)
Figure 26-3. Enterprise LAN Topology Example
The ENET-MAC Core implements, in conjunction with a dual-speed 10/100 MAC, Layer
3 network acceleration functions, which are designed to accelerate the processing of various
common networking protocols such as IP, TCP, UDP and ICMP providing wire speed
services to Client applications.
The Core implements a dual speed 10/100 Mbps Ethernet MAC compliant with the
IEEE802.3-2002 standard. The MAC layer provides compatibility with Half or Full Duplex
10/100 Mbps Ethernet and Fast Ethernet LANs.
The MAC operation is fully programmable and can be used in NIC (Network Interface
Card), bridging or switching applications. The Core implements the Remote Network
Monitoring (RMON) counters according to IETF RFC 2819. All registers are accessible
through a 32-Bit APB interface.
The Core also implements a Hardware acceleration block to optimize the performance of
network controllers providing IP and TCP, UDP, ICMP protocol services. The acceleration
block performs, in hardware, critical functions, which are typically implemented with large
software overhead.
The Core implements programmable embedded FIFOs that can provide, on the Receive
path, buffering for loss-less flow control.

10 100Mbps Ethernet ENET-MAC Core Features
Advanced Power Management features are available with Magic Packet detection and
programmable power down modes.
For industrial automation application, the IEEE 1588 standard is becoming the main
technology for precise time synchronization on Ethernet networks providing accurate clock
synchronization for distributed control nodes to overcome one of the drawbacks of Ethernet.
The programmable 10/100 Ethernet MAC with IEEE 1588 support integrates a standard
IEEE 802.3 Ethernet MAC with a time stamping module to support Ethernet applications
requiring precise timing references for incoming and outgoing frames to implement a
distributed time synchronization protocol such as the IEEE 1588.
26.3.2 10 100Mbps Ethernet ENET-MAC Core Features
26.3.2.1 Ethernet MAC Features

• Implements the full 802.3 specification with preamble / SFD generation, frame padding
generation, CRC generation and checking
• Dynamically configurable to support 10 Mbps and 100 Mbps operation
• Supports full duplex and configurable half duplex operation
• Supports AMD Magic Packet detection with interrupt for node remote power
management
• Seamless interface to commercial Fast Ethernet PHY device through a 4-Bit Media
Independent Interface (MII) operating at 25MHz
• Simple 64-Bit FIFO interface to user application
• CRC-32 checking at full speed with optional forwarding of the FCS field to client
• CRC-32 generation and append on transmit or forwarding of user application provided
FCS selectable on a per-frame basis
• When operating in Full Duplex mode, implements automated Pause Frame (802.3
x31A) generation and termination providing flow control without user application
intervention
• When operating in full duplex mode, pause quanta used to form Pause frames,
dynamically programmable
• Pause frame generation additionally controllable by user application offering flexible
traffic flow control

• Optional forwarding of received pause frames to the user application when operating
in Full Duplex mode
• Implements standard flow-control mechanism in full-duplex operation mode
• In half-duplex mode, provides full collision support, including jamming, backoff, and
automatic retransmission
• Support for VLAN tagged frames according to IEEE 802.1Q
• Programmable MAC address: Insertion on transmit; discards frames with mismatching
destination address on receive (except broadcast and pause frames)
• Programmable group of four supplemental MAC addresses that can be used to filter
Unicast traffic
• Programmable Promiscuous mode support to omit MAC destination address checking
on receive
• Multicast and Unicast address filtering on receive based on 64 entries hash table reducing
higher layer processing load
• Programmable frame maximum length providing support for any standard or proprietary
frame length
• Statistics indicators for frame traffic as well as errors (alignment, CRC, length) and
pause frames providing for IEEE 802.3 basic and mandatory Management Information
Database (MIB) package and Remote Network Monitoring (RFC 2819)
• Simple handshake user application FIFO interface with fully programmable depth and
threshold levels ensuring data rates of 1Gbps
• 64-Bit Client FIFO interface
• Separate status word available for each received frame on the user interface providing
information such as frame length, frame type, VLAN tag and error information
• Multiple internal loopback options
• MDIO Master interface for PHY device configuration and management with two
programmable MDIO base addresses
26.3.2.2 IP Protocol Performance Optimization Features

• Operates on TCP/IP and UDP/IP and ICMP/IP protocol data or IP header only
• Enables wire-speed processing

10 100Mbps Ethernet ENET-MAC Core Features
• IPv4 and IPv6 support

• Transparent passing of frames of other types and protocols
• Support for VLAN tagged frames according to IEEE 802.1q with transparent forwarding
of VLAN tag and control field
• Automatic IP-header and payload (protocol specific) checksum calculation and
verification on receive
• Automatic IP-header and payload (protocol specific) checksum generation and automatic
insertion on transmit configurable on a per-frame basis
• Support for IP and TCP, UDP, ICMP data for checksum generation and checking
• Full header options support for IPv4 and TCP protocol headers
• IPv6 support limited to datagrams with base header only. Datagrams with extension
headers are passed transparently unmodifed/unchecked
• Statistics information for received IP and protocol errors
• Configurable automatic discard of erroneous frames
• Configurable automatic Host-to-Network (RX) and Network-to-Host (TX) byte order
conversion for IP and TCP/UDP/ICMP headers within the frame
• Configurable padding remove for short IP datagrams on receive
• Configurable Ethernet Payload alignment to allow for 32-bit word aligned header and
payload processing
• Programmable Store & Forward operation with clock and rate decoupling FIFOs
26.3.2.3 IEEE 1588 Functions

• Support for all IEEE 1588 Frames
• Reference Clock can be chosen independently of the Network speed
• Software Programmable Precise Time-Stamping of Ingress Frames and Egress Frames
• Timer monitoring capabilities for System calibration and timing accuracy management
• Precise time stamping of external events with programmable interrupt generation
• Programmable event and interrupt generation for external system control
• Hardware and Software controllable timer synchronization

26.3.3 ENET-MAC Core Block Diagram
TOE MAC
Receve Interface Receve Interface Transmit Interface Transmit Interface

MII/SERDES
Functions
Receive Application
RX Control
Interface
TCP-IP
Receive
GMII/SERDES
Performance
FIFO Optimization
Pause Frame
CRC Check
Terminate
MII/SERDES
Transmit Application
Interface
TCP-IP TX Control
Transmit Performance
FIFO
GMII/SERDES
Optimization
Pause Frame
CRC Gen Generate
PHY Management
Interface
Configuration MDIO
Satistics Master
Register Interface
Figure 26-4. ENET-MAC Core Overview
26.3.4 Ethernet MAC Frame Formats
26.3.4.1 Overview
The IEEE 802.3 Standard defines the Ethernet frame format as follows: An Ethernet frame
has a minimum length of 64 bytes and a maximum length of 1518 bytes or more if jumbo
frames are supported, excluding the preamble and the start frame delimiter bytes. An Ethernet
frame consists of the following fields:
• Seven bytes preamble
• Start frame delimiter (SFD)
• Two address fields
• Length or type field
• Data field
• Frame check sequence (CRC value)
• An EXTENSION field is defined only for gigabit Ethernet half-duplex implementations
and is not supported by the MAC core

Ethernet MAC Frame Formats
7 octets PREAMBLE
1 octet SFD
6 octets DESTINATION ADDRESS
6 octets SOURCE ADDRESS
2 octets LENGTH/TYPE Payload length
Frame length
0..1500/9000 octets PAYLOAD DATA
0..46 octets PAD
4 octets FRAME CHECK SEQUENCE
EXTENSION (half dup only)
Figure 26-5. MAC Frame Format Overview
Optionally MAC frames can be VLAN-tagged with an additional 4-byte field (VLAN Tag
and VLAN Info) inserted between the MAC source address and the Type/Length Field.
VLAN tagging is defined by the IEEE P802.1q specification. VLAN tagged frames have
a maximum length of 1522 bytes, excluding the preamble and the SFD bytes.
7 octets PREAMBLE
1 octet SFD
6 octets DESTINATION ADDRESS
6 octets SOURCE ADDRESS
2 octets VLAN Tag (0x8100) lengthtype field
2 octets VLAN info
Frame length
2 octets LENGTH/TYPE Payload length
0..1500/9000 octets PAYLOAD DATA
0..42 octets PAD
4 octets FRAME CHECK SEQUENCE
EXTENSION (half dup only)
Figure 26-6. VLAN Tagged MAC Frame Format Overview
Table 26-5. MAC Frame Definition

Term Description
Frame length The length, in octets, defines the length of the complete Frame without preamble and SFD. A frame
has a valid length if it contains at least 64 octets and does not exceed the programmed maximum
length (typical 1518).
Payload Length The length / type field indicates the length of the frame's payload section. The most significant byte
is sent/received first.
If the Length/type field is set to a value lower than 46, the payload is padded so that the minimum
frame length requirement (64 Bytes) is met. For VLAN tagged frames, a value less than 42 indicates
a padded frame.
If the Length/type field is set to a value larger than the programmed frame maximum length (e.g. 1518)
it is interpreted as a type field.
Destination and Source 48-bit MAC addresses. The least significant byte is sent/received first and the two first bits (two least
Address significant bits) of the MAC address are used to distinguish MAC frames.
Note
Although the IEEE specification defines a maximum frame length,
the MAC core provides the flexibility to program any value for
the frame maximum length.

26.3.4.2 Pause Frames

A Pause Frame is generated by the receiving device to indicate a congestion to the emitting
device which should stop sending data.
Pause Frames are indicated by the Length/Type set to 0x8808. The two first bytes of a Pause
Frame following the type, defines a 16-Bit opcode field set to 0x0001 always. A 16-Bit
Pause Quanta is defined in the Frame payload Bytes 2 (Byte P1) and 3 (Byte P2) as defined
in Table 26-6. The pause quanta byte P1 is the most significant.
Table 26-6. Pause Frame Format (values in hex)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
55 55 55 55 55 55 55 D5 01 80 C2 00 00 01
Preamble SFD Multicast Destination Address
15 16 17 18 19 20 21 22 23 24 25 26 27-68
00 00 00 00 00 00 88 08 00 01 hi lo 00
Source Address Type Opcode P1 P2 pad (42)
69 70 71 72
26 6B AE 0A
CRC-32
There is no Payload Length field found within a Pause Frame and a Pause Frame is always
padded with 42 bytes (0x00).
If a pause frame with a pause value greater zero (XOFF Condition) is received, the MAC
stops transmitting data as soon the current Frame transfer is completed. The MAC stops
transmitting data for the value defined in pause quanta. One pause quanta fraction refers to
512 bit times.
If a pause frame with a pause value of zero (XON Condition) is received, the transmitter is
allowed to send data immediately (See chapter 10 for details).
26.3.4.3 Magic Packets

A Magic Packet can be a Unicast, Multicast or Broadcast packet, which carries a defined
sequence in the payload section. Magic Packet are received and inspected only under specific
conditions as described in Magic Packet Detection

IP and Higher Layers Frame Format
The defined sequence used to decode a Magic Packet is formed with a synchronization
stream (Six consecutive 0xFF bytes) followed by a sequence of six consecutive Unicast
MAC addresses (The Unicast Address of the Node to be awakened).
The sequence can be located anywhere in the Magic Packet payload and the Magic Packet
is formed with standard Ethernet header optional padding and CRC.
26.3.5 IP and Higher Layers Frame Format
26.3.5.1 Definitions
The following chapters use the term datagram to describe the protocol specific data unit,
which is found within the payload section of its container entity.
For example, an IP datagram specifies the payload section of an Ethernet frame. A TCP
datagram specifies the payload section within an IP datagram.
26.3.5.2 Ethernet Types

IP datagrams are carried in the payload section of an Ethernet frame. The Ethernet frame
type/length field is used to discriminate several datagram types. The following table lists
the types of interest:
Table 26-7. Ethernet Type Value Examples
Type Description
0x8100 VLAN tagged frame. The actual type is found 4 octets later in the frame
0x0800 IP
0x0806 ARP
0x86dd IPv6
26.3.5.3 IPv4 Datagram Format

The following Figure 6 shows the IP Version 4 (IPv4) header, which is located at the
beginning of an IP datagram. It is organized in 32-bit words. The most significant bit is bit
31 in the following figure. The first byte sent/received is the leftmost byte of the first word
(that is, Version/IHL field).
The IP Header can contain further options, which are always padded if necessary, to
guarantee the payload following the header is aligned to a 32-bit boundary.

The IP header is followed by the payload immediately, which can contain further protocol
headers like for example, TCP or UDP as indicated by the protocol field value. The complete
IP datagram is transported in the payload section of an Ethernet frame.
3 2 2 1 1 1
1 7 3 9 5 1 7 3 0
Vers IHL TOS length
fragment ID flags fragment offset
TTL protocol header checksum
source address
destination address
options
Figure 26-7. IPv4 Header Format
Table 26-8. IPv4 Header Fields

Field Name Description
Vers 4-bit IP version information. It is 4 for IPv4 frames
4-bit internet header length information. Determines number of 32-bit words found within the IP
IHL header. The default value, if no options are present is 5
TOS Type of Service / DiffServ field
length Total length of the datagram in bytes. It includes all octets of header and payload
fragment ID, flags, frag-

ment offset Fields used for IP fragmentation
TTL Time-to-live. If zero, datagram must be discarded
protocol Protocol Identifier of protocol that follows in the datagram
header checksum Checksum over all IP header fields
source address Source IP address
destination address Destination IP address
26.3.5.4 IPv6 Datagram Format

Figure 26-8 shows the IP Version 6 (IPv6) header, which is located at the beginning of an
IP datagram. It is organized in 32-bit words and has a fixed length of 10 words (40 byte).
The next header field identifies the type of the header to follow the IPv6 header. It is defined
identical to the protocol identifier within IPv4 with new definitions for identifying so-called

IP and Higher Layers Frame Format
extension headers, which can be inserted between the IPv6 header and the protocol header,
shifting the protocol header accordingly. The accelerator currently only supports IPv6
without extension headers (that is, next header identifies TCP or UDP or ICMP protocol).
The most significant bit is bit 31 in the following figure. The first byte sent/received is the
leftmost byte of the first word (that is, Version/Traffic class fields).
3 2 2 1 1 1
1 7 3 9 5 1 7 3 0
Vers TrafficClass folowlable
payload length next header hop limit
source address
destination address
start of next header / payload
Figure 26-8. IPv6 Header Format
Table 26-9. IPv6 Header Fields

Vers 4-bit IP version information. It is 6 for all IPv6 frames
Traffic Class 8-bit field defining the traffic class
flow label 20-bit flow label identifying frames of the same flow
payload length 16-Bit Length of the datagram payload (!) in bytes. It includes all octets following the IPv6 header.
Identifies the header that follows the IPv6 header. This can be the protocol header or any IPv6 defined
next header extension header.
Hop counter, decremented by 1 by each station that forwards the frame. If hop limit is 0 the frame
hop limit must be discarded.
source address 128-bit IPv6 source address
destination address 128-bit IPv6 destination address
26.3.5.5 ICMP Datagram Format

Following the IP Header, an Internet Control Message Protocol (ICMP) datagram is found
when the protocol identifier has a decimal value of 1. The ICMP datagram has 4 octets
header followed by the additional message data.

3 2 2 1 1 1
1 7 3 9 5 1 7 3 0
type code checksum
icmp message data
Figure 26-9. ICMP Header Format
Table 26-10. IP Header Fields

type 8-bit type information
code 8-bit code that is related to the message type
checksum 16-bit one's complement checksum over the complete ICMP datagram
26.3.5.6 UDP Datagram Format

Following the IP Header, a user datagram protocol header is found when the protocol
identifier has a decimal value of 17.
Following the UDP header is the payload of the datagram. The header byte order follows
the conventions given for the IP header above.
3 2 2 1 1 1
1 7 3 9 5 1 7 3 0
source port destination port
length checksum
Figure 26-10. UDP Header Format
Table 26-11. UDP Header Fields

source port Source application port
destination port Destination application port
Length of user data which follows immediately the header including the UDP header. That is, the
length minimum value is 8.
checksum Checksum over the complete datagram and some IP header information
26.3.5.7 TCP Datagram Format

Following the IP Header, a TCP header is found when the protocol identifier has a decimal
value of 6.

IEEE 1588 Message Formats
The TCP payload follows immediately the TCP header.

3 2 2 1 1 1
1 7 3 9 5 1 7 3 0
source port destination port
sequence number
acknowledgment number
offs reserved flags window
checksum urgent pointer
options
Figure 26-11. TCP Header Format
Table 26-12. TCP Header Fields

source port Source application port
destination port Destination application port
sequence number Transmit sequence number
ack. number Receive sequence number
offs Data offset. Number of 32-bit words within the TCP header. If no options, a value of 5.
flags URG, ACK, PSH, RST, SYN, FIN flags
window TCP receive window size information
checksum Checksum over the complete datagram (TCP Header and data) and IP header information
options Additional 32-bit words for protocol options
26.3.6 IEEE 1588 Message Formats
26.3.6.1 Transport Encapsulation

The Precision-Time-Protocol (PTP) datagrams are encapsulated in Ethernet frames using
the UDP/IP transport mechanism, or, optionally, with the newer 1588v2 directly in Ethernet
frames (Layer 2). Typically multicast addresses are used to allow efficient distribution of
the synchronization messages.

26.3.6.1.1 UDP/IP
The 1588 messages (v1 and v2) can be transported using UDP/IP multicast messages. The
following IP multicast groups are defined for PTP. The table also shows their respective
MAC layer multicast address mapping according to RFC 1112 (last 3 octets of IP follow
the fixed value of 01-00-5e).
Table 26-13. UDP/IP Multicast Domains
Name IP Address MAC Address mapping
DefaultPTPdomain 224.0.1.129 01-00-5e-00-01-81
AlternatePTPdomain1 224.0.1.130 01-00-5e-00-01-82
Table 26-14. UDP Portnumbers

Message Type UDP Port Note
event 319 Used for SYNC and DELAY_REQUEST messages
general 320 All other messages (for example, follow-up, delay-response)
26.3.6.1.2 Native Ethernet (PTPv2)

In addition to the usage of UDP/IP frames, IEEE 1588v2 defines a native Ethernet frame
format that uses ethertype=0x88f7. The payload of the Ethernet frame immediately contains
the PTP datagram, starting with the PTPv2 header.
Beside others, version 2 adds a peer delay mechanism to allow delay measurements between
individual point-to-point links along a path over multiple nodes. The following multicast
domains are additionally defined in PTPv2.
Table 26-15. PTPv2 Multicast Domains
Name MAC Address
Normal messages 01-1b-19-00-00-00
peer delay messages 01-80-c2-00-00-0e
26.3.6.2 PTP Header

All PTP frames contain a common header, which is used to determine the protocol version
as well as the type of message, which defines the further content of the message.

IEEE 1588 Message Formats
All multi-octet fields are transmitted in big-endian order meaning, the most significant byte
is transmitted/received first.
The version field's (versionPTP) last four bits are at the same position (that is, 2nd byte)
for both PTPv1 and PTPv2 headers, allowing a correct identification by inspecting the first
two bytes of the message.
26.3.6.2.1 PTPv1 Header
Table 26-16. Common PTPv1 message header
Bits Octets Offset
7 6 5 4 3 2 1 0
versionPTP = 0x0001 2 0
versionNetwork 2 2
subdomain 16 4
messageType 1 20
sourceCommunicationTechnology 1 21
sourceUuid 6 22
sourcePortId 2 28
sequenceId 2 30
control 1 32
0x00 1 33
flags 2 34
reserved 4 36
The type of message is encoded in the fields messageType and control as follows:
Table 26-17. PTPv1 Message Type Identification
messageType control Message Name Message
0x01 0 SYNC event message
0x01 1 DELAY_REQ event message
0x02 2 FOLLOW_UP general message
0x02 3 DELAY_RESP general message
0x02 4 MANAGEMENT general message

messageType control Message Name Message
other other reserved
The field sequenceId is used to non-ambiguously identify a message.

26.3.6.2.2 PTPv2 Header
Table 26-18. Common PTPv2 message Header
Bits Octets Offset
7 6 5 4 3 2 1 0
transportSpecific messageId 1 0
reserved versionPTP = 0x2 1 1
messageLength 2 2
domainNumber 1 4
reserved 1 5
flags 2 6
correctionField 8 8
reserved 4 16
sourcePortIdentity 10 20
sequenceId 2 30
control 1 32
logMeanMessageInterval 1 33
The type of message is encoded in the field messageId which is as follows:

Table 26-19. PTPv2 Message Type Identification
messageId Message Name Message
0x0 SYNC event message
0x1 DELAY_REQ event message
0x2 PATH_DELAY_REQ event message
0x3 PATH_DELAY_RESP event message
0x4 - 0x7 reserved
0x8 FOLLOW_UP general message

MAC Receive
messageId Message Name Message
0x9 DELAY_RESP general message
0xa PATH_DELAY_FOLLOW_UP general message
0xb ANNOUNCE general message
0xc SIGNALING general message
0xd MANAGEMENT general message
The PTPv2 flags field contains further details on the type of message, especially if one-step
or two-step implementations are used. The flags field consists of two octets with the
following meanings for the bits. Reserved bits are set to 0 (false).
Table 26-20. PTPv2 Message Flags Field Definitions
Octet Offset bit Name Description
6 (first) 0 ALTERNATE_MASTER See IEEE 1588 Clause 17.4
1 TWO_STEP True (1) for two-step clock

False (0) for one-step clock
2 UNICAST True (1) if transport layer address uses a unicast destination

address, false (0) if multicast is used.
3 reserved
4 reserved
5 profile specific
6 profile specific
7 reserved
26.3.7 MAC Receive
26.3.7.1 Overview
The MAC receive engine performs the following tasks:
• Check Frame Framing
• Remove Frame preamble and Frame SFD field
• Frame Discarding based on Frame Destination address field

• Terminate Pause Frames

• Check Frame Length
• Remove payload padding if it exists
• Calculate and verify CRC-32
• Write received Frames in the Core receive FIFO
In the MAC is programmed to operate in half duplex mode, the MAC performed the
following additional action:
• Check if the frame is received with a collision
discard Detect Preamble
discard Collision
Half Duplex only
Compare Destination Address

discard with locol/multicast/broadcast
discriminate length/type
discard
information
receive payload
remove padding
verify CRC
verify frame length
write data FIFO

and frame status
Figure 26-12. MAC Receive Flow
26.3.7.2 Collision Detection in Half Duplex Mode

If the packet is received with a collision detected during the reception of the first 64 bytes,
the packet is discarded (if frame size was less than ~14 octets) or transmitted to the user
application with an error and status bit ff_rx_err_stat(24) set to '1'.

MAC Receive
26.3.7.3 Preamble Processing

The IEEE 802.3 Standard allows a maximum size of 56 bits (7 bytes) for the preamble,
while the MAC Core allows any arbitrary preamble length. The MAC Core checks for the
start frame delimiter (SFD) byte. If the next byte of the preamble, which is different from
0x55, is not 0xD5, the frame will be discarded.
Although the IEEE specification specifies that Frames should be separated at least by 96
bit (Inter Packet Gap or IPG), the MAC Core is designed to accept frames only separated
by 64 MII (10/100Mbps operation) bits.
The MAC Core removes all the preamble bytes and the SFD byte.
26.3.7.4.1 Overview
The destination address bit 0 is used to differentiate Multicast and Unicast Addresses:
• If bit 0 is set '0' the MAC address is an individual (Unicast) address.
• If bit 0 is set '1' the MAC address defines a group address (Multicast Address).
• If all 48 bits of the MAC address are set to '1' it indicates a Broadcast address.
26.3.7.4.2 Unicast Address Check

If a Unicast address is received, the destination MAC address is compared to the Node
MAC address programmed by the host in the registers PADDR1/PADDR2. In addition, it
is compared to the supplemental MAC addresses programmed in the registers
SMAC_0_0/SMAC_0_1, SMAC_1_0/SMAC_1_1, SMAC_2_0/SMAC_2_1 and
SMAC_3_0/SMAC_3_1. If the destination address matches any of the programmed MAC
addresses, the frame is accepted.
If only one MAC address is required, all the supplemental MAC addresses should be
programmed with the Node MAC address.
If promiscuous mode is enabled (configuration register RCR(PROM) set to '1' ) no address
checking is performed and all Unicast frames are accepted.
26.3.7.4.3 Multicast and Unicast Address Resolution
The hash table algorithm used in the group and individual hash filtering operates as follows.
The 48-bit destination address is mapped into one of 64 bits, represented by 64 bits stored
in GAUR, GALR (group address hash match), or IAUR, IALR (individual address hash
match). This mapping is performed by passing the 48-bit address through the on-chip 32
bit CRC generator and selecting the six most significant bits of the CRC-encoded result to

generate a number between 0 and 63. The msb of the CRC result selects GAUR (msb equals
1) or GALR (msb equals 0). The least significant five bits of the hash result select the bit
within the selected register. If the CRC generator selects a bit set in the hash table, the frame
is accepted; otherwise, it is rejected.
For example, if eight group addresses are stored in the hash table and random group addresses
are received, the hash table prevents roughly 56/64 (or 87.5%) of the group address frames
from reaching memory. Those that do reach memory must be further filtered by the processor
to determine if they truly contain one of the eight desired addresses.
The effectiveness of the hash table declines as the number of addresses increases.
The user must initialize the hash table registers. Use this CRC32 polynomial to compute
the hash:
• FCS(X) = X 32 +X 26 +X 23 +X 22 +X 16 +X 12 +X 11 +X 10 +X 8 +X 7 +X 5 +X
4 +X 2 +X 1 +1
If promiscuous mode is enabled (Configuration register bit PROM set to '1'), all Unicast
and all Multicast frames are accepted regardless of GAUR / GALR and IAUR / IALR
settings.
26.3.7.4.4 Broadcast Address Reject
All Broadcast Frames are accepted if the register bit BC_REJ is set to '0' or if the register
bit PROM is set to '1'. If PROM is set to '0' when BC_REJ set to '1', all Broadcast Frames
are rejected.
Table 26-21. Broadcast Address Reject Programming
PROM BC_REJ Broadcast Frames
0 0 Accepted
0 1 Rejected
1 0 Accepted
1 1 Accepted
26.3.7.4.5 Miss-Bit Implementation

For higher layer filtering purposes, the receive FIFO interface provides a status bit
(ff_rx_err_stat[26]) indicating an address miss when the MAC operates in promiscuous
mode and accepted a frame that would otherwise be rejected.

MAC Receive
If neither a hash match (group or individual) nor an exact match (group or individual) occur,
and if promiscuous mode is enabled (RCR[PROM] equals 1), the frame is accepted and the
MISS bit is set; otherwise, the frame is rejected.
This means the status bit is set in any of the following conditions during promiscuous mode:
• BC_REJ=1. A broadcast frame is received in promiscuous mode while broadcast reject
is set.
• A unicast is received that does not match with any of the following:
• PADDR1/ 2 (Node address, PALR/PAUR)
• SMAC_0/1/2/3 (supplemental unicast addresses)
• IADDR1/2 hash table entries (hash table for unicast, IALR/IAUR)
• A multicast is received that does not match the GADDR1/2 hash table entries
(GALR/IAUR)
26.3.7.5.1 Payload Length Check

If the Length / Type has a value lower than 0x600 and if the register bit NO_LGTH_CHECK
is configured to perform the check, the MAC checks the payload length and reports any
error in the frame status word (Bit 1 of Core signal ff_rx_err_stat(0) and interrupt bit PLR).
If the Length / Type field has a value greater or equal 0x600, the MAC interprets the field
as a type and no payload length check is performed.
The length check is performed on VLAN and stacked VLAN frames.
If a padded frame is received, no length check can be performed due to the extended frame
payload (that is, padded frames never can have a payload length error).
26.3.7.5.2 Frame Length Check
When the receive frame length exceeds MAX_FL bytes, the BABR interrupt bit is generated.
The LG register bit and ff_rx_err_stat(1) are set to '1'.
The frame is not truncated unless the frame length exceeds the value programmed in
TRUNC_FL. If the frame is truncated, ff_rx_err_stat(2) is set to '1'. In addition, a truncated
frame will always have the CRC error indication set (ff_rx_err_stat(3)).

26.3.7.6 VLAN Frames Processing

VLAN frames have a Length / Type field set to 0x8100 immediately followed by a 16-Bit
VLAN Control Information field. VLAN tagged frames are received as normal frames
(VLAN Tag not interpreted by the MAC function) and are completely (Including the VLAN
tag) pushed to the user application. If the length/type field of the VLAN tagged frame,
which is found four octets later in the frame is less than 42, padding will be removed. In
addition, the frame status word (Core signal ff_rx_err_stat(7)) indicates that the current
frame is VLAN tagged.
26.3.7.7 Pause Frame Termination

Pause frames are terminated within the receive engine and not transferred to the receive
FIFO. The Quanta is extracted and sent to the MAC Transmit path through a small internal
Clock Rate decoupling asynchronous FIFO.
The Quanta is written only if a correct CRC and a correct frame length are detected by the
control state machine. If not, the Quanta is discarded and the MAC Transmit path is not
paused.
Good Pause Frames are ignored if the register bit FCE is set to '0' and are forwarded to the
Client interface when register bit PAUSE_FWD is set to '1'.
26.3.7.8 CRC Check

The CRC-32 field is checked and is forwarded to the Core FIFO interface if the Core
configuration registers CRC_FWD and PAD_EN are set to '0' and '1' respectively. When
the Core register CRC_FWD is set to '1' (Regardless of PAD_EN register value), the CRC-32
field is checked and terminated (Not transmitted to the Core FIFO).
The CRC polynomial, as specified in the 802.3 Standard, is as follows:
4 +X 2 +X 1 +1
The 32 bits of the CRC value are placed in the FCS field so that the X31 term is the
right-most bit of the first octet. The CRC bits are thus received in the following order: X31,
X30,..., X1, X0.
If a CRC error is detected, the frame is marked invalid and ff_rx_err_stat(3) is set °Æ1°Ø.

MAC Transmit
26.3.7.9 Frame Padding Remove

When a frame is received with a Payload length field set to lower than 46 (42 for VLAN
tagged and 38 for frames with stacked VLANs) the '0' padding can be optionally removed
before the Frame is written into the data FIFO as configured by the configuration bit
PAD_EN.
Note
If a frame is received with excess padding (that is, length field as
mentioned above, but frame has more than 64 octets) and padding
removal is enabled, the padding is removed as normal and no
error is caused if the frame is otherwise correct (for example, good
CRC and less maximum length and no other error).
26.3.8 MAC Transmit
26.3.8.1 Overview
Frame transmission starts when the Transmit FIFO holds enough data. Once a transfer has
started, the MAC transmit function performs the following tasks:
• Generate Preamble and SFD field before Frame transmission.
• Generate XOFF pause frames if the Receive FIFO reports a congestion or if register
TFC_PAUSE signal is asserted with PAUSE_DUR set to a non zero value.
• Generate XON pause frames if the Receive FIFO congestion condition is cleared or if
register TFC_PAUSE signal is asserted with PAUSE_DUR set to 0.
• Suspend Ethernet Frame transfer (XOFF) if a non zero Pause Quanta is received from
the MAC receive path.
• Add padding to the frame if required.
• Calculate and append CRC-32 to the transmitted frame.
• Send Frame with correct Inter Packet Gap (IPG) (Deferring).
When the MAC is configured to operate in Half Duplex mode, the following additional
tasks are performed:
• Collision detection
• Frame retransmit after back-off timer has expired

Send Preamble
Send Destination Address
send local MAC address

(overwrite FIFO data)
send payload
send padding
(if necessary)
send CRC
Figure 26-13. Frame Transmit Overview
26.3.8.2 Frame Payload Padding

The IEEE specification defines a minimum frame length of 64 bytes. If the frame sent to
the MAC from the user application has a size smaller than 60 bytes, the MAC automatically
adds padding bytes (0x00) so that frames transmitted to the Ethernet link do not violate the
Ethernet minimum frame length specification. Transmit padding is always performed and
cannot be disabled.
If the MAC is not allowed to append a CRC (ff_tx_crc_fwd=1) the user application is
responsible for providing frames with a minimum length of 64 octets.
26.3.8.3 MAC Address Insertion

On each frame received from the Core transmit FIFO interface, the source MAC address
is optionally replaced by the address programmed on the configuration registers PADDR1
and PADDR2 (Core Configuration register TX_ADDR_INS set to '1') or is transparently
forwarded to the Ethernet line (Core Configuration register TX_ADDR_INS set to '0').
26.3.8.4 CRC-32 generation

The CRC-32 field is optionally generated and appended at the end of a Frame if the Frame
is transmitted to the Core with the Frame status bit ff_tx_crc_fwd set to '0' when ff_tx_eop
is asserted.
The CRC polynomial, as specified in the 802.3 Standard, is as follows:

MAC Transmit
4 +X 2 +X 1 +1
The 32 bits of the CRC value are placed in the FCS field so that the X31 term is the
right-most bit of the first octet. The CRC bits are thus transmitted in the following order:
X31, X30,..., X1, X0.
26.3.8.5 Inter Packet Gap

In full duplex mode, after frame transmission and before transmission of a new frame, an
Inter Packet Gap (IPG), programmed with register TX_IPG_LENGTH, is maintained. The
minimum IPG can be programmed to any value between 8 and 27 byte-times (64 and 216
bit-times).
In half duplex mode, the core constantly monitors the line. Actual transmission of the data
onto the network occurs only if it has been idle for a 96-bit time period and any backoff
time requirements have been satisfied. In accordance with the standard, the Core begins to
measure the IPG from mii_crs / gmii_crs de-assertion.
26.3.8.6 Collision Detection and Handling - Half Duplex Operation Only

A collision occurs on a half-duplex network when concurrent transmissions from two or
more nodes take place. During transmission, the Core monitors the line condition and detects
a collision when the PHY device asserts the MII mii_col signal.
When the Core detects a collision while transmitting, it stops the transmission of data and
transmits a 32-bit jam pattern. If the collision is detected during the preamble or the SFD
transmission, the jam pattern is transmitted after completing the SFD, which results in a
minimum 96-bit fragment. The jam pattern is a fixed pattern that is not compared to the
actual frame CRC and has a very low probability (0.532) of having a jam pattern identical
to the CRC.
If a collision occurs before the transmission of 64 bytes (Including preamble and SFD), the
MAC Core waits for the backoff period and retransmits the packet data (Stored in a 64-Bytes
re-transmit buffer) already sent on the line. The backoff period is generated from a pseudo
random process (Truncated binary exponential backoff).
If a collision occurs after the transmission of 64 bytes (Including preamble and SFD), the
MAC discards the remaining of the Frame, optionally sets the interrupt bit LC and sets the
transmit status bit tx_ts_stat(1).

Core Tx Engine
LFSR
PHY Control
Back off Period col
Core FIFO
rden
MAC Transmit
Control
Retransmit
Buffer Control
Waddr
raddr
64x5 Retransmit
Buffer
Frame
Discard
Transmit FIFO
PHY Interface
Interface
MAC Transmit Datapath
Figure 26-14. Packet Re-Transmit Overview
The backoff time is represented by an integer multiple of slot times (1 slot is equal to a
512-bit time period). The number of delay slot times, before the nth retransmission attempt,
is chosen as a uniformly distributed random integer in the range:
• 0 < r < 2^k
• k = min(n, N) where n is the number of retransmissions and N = 10
For example, after the first collision, the backoff period (in slot time) is 0 or 1, if a collision
occurs on the 1st retransmission, the backoff period (in slot time) is 0, 1, 2 or 3 and so on.
The maximum backoff time (in 512-Bit time slots) is limited by N set to 10 as specified in
the IEEE 802.3 Standard.
If a collision occurs after 16 consecutive retransmissions, the Core reports an excessive
collision condition (Interrupt bit RL and transmit status bit tx_ts_stat(2)) and discards the
current packet from the FIFO.
In networks violating the standard requirements, a collision may occur after the transmission
of first 64 bytes. In this case, the Core stops the current packet transmission and discards
the rest of the packet from the transmit FIFO. The Core resumes transmission with the next
packet available in the Core transmit FIFO.
26.3.9 Full Duplex Flow Control Operation
26.3.9.1 Overview
Three conditions are handled by the Core's Flow Control engine:

Full Duplex Flow Control Operation
• Remote Device Congestion: The Remote device connected to the same Ethernet segment
as the Core reports a Congestion requesting the Core to stop sending Data.
• Core FIFO Congestion: When the Core's receive FIFO reaches a user programmable
threshold (rx section empty), the Core sends a Pause Frame back to the Remote device
requesting data transfer to be stopped.
• Local Device Congestion: Any device connected to the Core can request (Typically
through the Host Processor) the remote device to stop transmitting data.
26.3.9.2 Remote Device Congestion

When the MAC Transmit control gets a valid Pause Quanta from the receive path and if
the bit FCE is set to '1', the MAC Transmit logic completes the transfer of the current Frame,
stops sending data for the amount of time specified by the Pause Quanta in 512 bit time
increments and asserts the bit RFC_PAUSE.
Frame transfer resumes when the time specified by the Quanta has expired and if no new
Quanta value has been received or if a new Pause Frame with a Quanta value set to 0x0000
is received. The MAC also resets the bit RFC_PAUSE to '0'.
If the register bit FCE is set to '0', Pause Frames received by the MAC are ignored.
Optionally and independently of the FCE register bit setting, Pause Frame are forwarded
to the Client interface if the register bit PAUSE_FWD is set to '1'.
26.3.9.3 Local Device / FIFO Congestion

Pause Frames are generated by the MAC transmit engine, when the local receive FIFO is
not able to receive more than a pre-defined number of words (FIFO programmable threshold)
or when a Pause Frame generation is requested by the Local Host Processor:
• To generate a Pause Frame, the Host Processor asserts the register TFC_PAUSE. A
single pause frame is generated when the current Frame transfer is completed and the
register bit TFC_PAUSE is automatically cleared. Optionally, an interrupt () is generated.
• A XOFF Pause Frame is generated when the Receive FIFO asserts its section empty
flag (internal). A XOFF Pause Frame is generated automatically, when the current
Frame transfer is completed.
• A XON Pause Frame is generated when the Receive FIFO de-asserts its section empty
flag (internal). A XON Pause Frame is generated automatically, when the current Frame
transfer is completed.

When a XOFF Pause Frame is generated, the Pause Quanta (Payload Byte P1 and P2) is
filled with the value programmed in the Core register PAUSE_DUR.
The Source Address is set to the MAC address programmed in the Core configuration
registers PADDR1 and PADDR2 and the destination address is set to the fixed Multicast
address 01-80-C2-00-00-01 (0x010000c28001).
When a XON Pause Frame is generated, the Pause Quanta (Payload Byte P1 and P2) is
filled with 0x0000 (Zero Quanta). The Source Address is set to the MAC address
programmed in the Core configuration registers PADDR1 and PADDR2 and the destination
address is set to the fixed Multicast address 01-80-C2-00-00-01 (0x010000c28001).
Pause Frames generated are compliant to the IEEE 802.3 annex 31A&B.
From Ethernet Line
Programmable
Thereshold
Pause
TFC_PAUSE Frame PAUSE_DUR
Generation
To Ethernet Line
Figure 26-15. Pause Frame Generation Overview
Note
Although the flow control mechanism should prevent any FIFO
overflow on the MAC Core receive path, the Core receive FIFO
is protected. When an overflow is detected on the receive FIFO,
the current frame is truncated with an error indication set in the
frame status word. The frame should subsequently be discarded
by the user application.

Magic Packet Detection
26.3.10 Magic Packet Detection
26.3.10.1 Overview
Magic Packet detection is used to wake up a node that is put in the power down mode by
the node management agent. Magic Packet detection is supported only if the MAC is
configured in sleep mode.
26.3.10.2 Sleep Mode

To put the MAC in sleep mode, the configuration ECR(SLEEP) should be set to °Æ1°Ø.
At the same time, ECR(MAGIC_ENA) should be set to 1, to enable magic packet detection.
In addition, when the external input pin ipg_stop is asserted, sleep mode is entered also,
without affecting the ECR register bits.
When the Core is in sleep mode:
• The MAC transmit logic is disabled.
• The Core FIFO receive / transmit functions are disabled.
The MAC receive logic is kept in normal mode but it ignores all traffic from the line except
Magic Packets, which are detected so that a remote agent can wake up the node.
26.3.10.3 Magic Packet Detection

The Core is designed to detect Magic Packets (see 5.3 page 30) with the destination address
set to:
• Any Multicast address.
• The Broadcast address.
• The Unicast address programmed in the Core registers PADDR1 / PADDR2.
• If enabled, to any of the Unicast addresses programmed in the Core supplemental MAC
address registers SMAC_0.. to SMAC_3.. .
When a Magic Packets is detected, the interrupt bit EIR(WAKEUP) is asserted and none
of the statistic registers is incremented.
In addition, the external pin magic_det is asserted and held asserted until the magic packet
detection is disabled or the sleep mode is cancelled.
26.3.10.4 Wakeup
When a Magic Packet was detected, indicated by an asserted EIR(WAKEUP), the
configuration bit ECR(SLEEP) should be cleared to resume normal operation of the MAC.
Clearing the SLEEP bit will automatically mask the MAGIC_ENA bit, disabling magic
packet detection.
This will also deassert the external pin magic_det.
26.3.11 IP Accelerator Functions
26.3.11.1 Checksum Calculation

The IP and ICMP, TCP, UDP checksums are calculated with one's complement arithmetic
summing up 16-bit values.
For ICMP, the checksum is calculated over the complete ICMP datagram (that is, without
IP header).
For TCP and UDP, the checksums contain the header and data sections and in addition the
values from the IP header, which can be seen as a pseudo header that is not actually present
as such in the datastream.
3 2 2 1 1 1
1 7 3 9 5 1 7 3 0
source address
destination address
zero protocol TCP/UDP length
Figure 26-16. IPv4 Pseudo Header for Checksum calculation

3 2 2 1 1 1
1 7 3 9 5 1 7 3 0
source address
destination address
TCP/UDP length
zero next header
Figure 26-17. IPv6 Pseudo Header for Checksum Calculation

IP Accelerator Functions
The TCP/UDP length value is the length of the TCP or UDP datagram, which is equal to
the payload of an IP datagram. It is derived by subtracting the IP header length from the
complete IP datagram length that is given in the IP header (IPv4) or directly taken from the
IP header (IPv6). The protocol field is the corresponding value from the IP header and 'zero'
is filled with zeroes.
For IPv6, the complete 128 bit addresses are considered. The next header value identifies
the upper layer protocol (TCP or UDP) and may differ from the IPv6 header's actual next
header value. if the extension headers are inserted before the protocol header.
The checksum calculation uses 16-bit words in network byte order: The first byte
sent/received is the most significant byte and the second byte sent/received is the least
significant byte of the 16-bit value to add to the checksum. If the frame ends on an odd
number of bytes, a zero byte is appended for checksum calculation only (not actually
transmitted).
26.3.11.2 Additional Padding Processing

Any Ethernet frame according to IEEE 802.3 must have a minimum length of 64 octets.
The MAC usually removes padding on receive, when a frame with length information is
received. As IP frames have a type value instead of the length, the MAC will not remove
padding for short IP frames, as it is not aware of the frame contents.
The IP Accelerator function can be configured to remove the Ethernet padding bytes that
might follow the IP datagram.
On transmit, the MAC automatically ensures to add padding as necessary to fill any frame
to a length of 64.
26.3.11.3 32-bit Ethernet Payload Alignment

The data FIFOs allow inserting two additional arbitrary bytes in front of a frame. This
extends the 14-byte Ethernet header to a 16-byte header, which leads to the alignment of
the Ethernet payload, following the Ethernet header, on a 32-bit boundary.
This function can be enabled for transmit and receive independently with the corresponding
SHIFT16 bits in the ipaccTxConf register and ipaccRxConf register respectively.
When enabled, the valid frame data is arranged as shown in the table below.
Table 26-22. 64-Bit Interface Data Structure with SHIFT16 option enabled
63 56 55 48 47 40 39 32 31 24 23 16 15 8 70
Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 Any value Any value

Byte 13 Byte 12 Byte 11 Byte 10 Byte 9 Byte 8 Byte 7 Byte 6
...
Receive Processing
When the SHIFT16 bit in ipaccRxConf register is enabled, each frame is received with two
additional bytes in front of the frame. The user application has to ignore these first two
bytes and has to find the first byte of the frame in bits 23:16 of the first word from the RX
FIFO.
Note that the SHIFT16 bit must be set during initialization and kept asserted during the
complete operation as it influences the FIFO write behavior.
Transmit Processing
When the SHIFT16 bit in ipaccTxConf register is enabled, the first two bytes of the first
word written (that is, bits 15:0) will be discarded immediately by the FIFO write logic.
The SHIFT16 bit can be enabled/disabled for each frame individually if required, but can
be changed only in-between frames.
26.3.11.4 Received Frame Discard

As the Receive FIFO must be operated in store and forward mode (Register
RX_SECTION_FULL must be set 0), received Frames can be discarded based on the
following errors:
1. The MAC function receives the frame with an error:
• The Frame has an invalid payload length.
• Frame length is greater than MAX_FL.
• Frame received with a CRC-32 error.
• Frame truncated due to receive FIFO overflow.
• Frame is corrupted as PHY signaled an error (mii_rx_err asserted during reception).
2. An IP frame is detected and the IP header checksum is wrong

3. An IP frame with a valid IP header and a valid IP header checksum is detected, the
protocol is known but the protocol specific checksum is wrong

IP Accelerator Functions
If one of the errors occurs and the IP Accelerator function is configured to discard frames
(Register ipaccRxConf), the frame is automatically discarded. Statistics are maintained
normally and are not affected by this discard function.
26.3.11.5 IPv4 Fragments

When an IP (IPv4) fragment frame is received, only the IP header is inspected and its
checksum is verified. The 32-bit alignment operates on fragments as on normal IP frames,
as specified above.
The IP fragment frame payload is not inspected for any protocol headers, as such a protocol
header would only exist in the very first fragment. To assist in the protocol specific checksum
verification, the one's-complement sum is calculated on the IP payload (that is, all bytes
following the IP header) and provided with the frame status word.
Note
The application software can take advantage of the payload
checksum delivered with the frame's status word to calculate the
protocol specific checksum of the datagram after all the fragments
have been received and reassembled.
For example, if a TCP payload is delivered by multiple IP
fragments, the application software can calculate the pseudo
header checksum value from the first fragment and add the payload
checksums delivered with the status for all fragments to verify
the TCP datagram checksum.
26.3.11.6.1 Receive Processing
An Ethernet frame of type 0x86dd identifies an IP Version 6 frame (IPv6) Frame. If an IPv6
frame is received, the first IP header is inspected (first 10 words) which is available in every
IPv6 frame.
If the receive SHIFT16 function is enabled, the IP header is aligned on a 32-bit boundary
allowing more efficient processing (see 12.3 page 54).
For TCP and UDP datagrams, the pseudo-header checksum calculation is performed and
verified.
To assist in protocol specific checksum verification, the one's-complement sum is always
calculated on the IP payload (that is, all bytes following the IP header) and provided with
the frame status word. For example, if extension headers were present, their sum(s) can be
subtracted in software from the checksum to isolate the TCP/UDP datagram checksum if
required.
26.3.11.6.2 Transmit Processing

For IPv6 transmission, the SHIFT16 function is supported to process 32-bit aligned
datagrams.
IPv6 has no IP header checksum therefore, the IP checksum insertion configuration is
ignored.
The protocol checksum will be inserted only if the next header of the IP header is a known
protocol (that is, TCP, UDP or ICMP). If a known protocol is detected, the checksum over
all bytes following the IP header is calculated and inserted in the correct position.
The pseudo-header checksum calculation is performed for TCP and UDP datagrams
accordingly.
26.3.12 Resets and Stop Controls
26.3.12.1 Hardware Reset

Setting the ECR(RESET) bit, resets the Ethernet controller and initializes all registers and
logic. This bit is self-clare.
26.3.12.2 Soft Reset

When ECR(ETHER_EN) is cleared, during operation, the following happens:
• DMA, buffer descriptor and FIFO control logic are reset, including the buffer descriptor
and FIFO pointers.
• Transmission is terminated by asserting mii_tx_err to the PHY.
• The current FIFO write is terminated and all further data from the application is ignored.
All subsequent writes are ignored until re-enabled.
• The current FIFO read is terminated.
26.3.12.3 Graceful Stop

The following conditions lead to a graceful stop of the MAC transmit or receive datapaths.
A graceful stop means that any currently ongoing transactions are completed normally and
no further frames after that will be accepted. The MAC can resume from a graceful stop
without the need for a reset (for example, ECR(ETHER_EN) bit deassertion is not required).

Resets and Stop Controls
26.3.12.4 Graceful Transmit Stop (GTS)

When gracefully stopped, the MAC is no longer reading frame data from the transmit FIFO
and has completed any ongoing transmission. In any of the following conditions, the transmit
datapath will stop after an ongoing frame transmission has been completed normally.
• Register bit TCR(GTS) is set by software.
• Register bit TCR(TFC_PAUSE) is set by software requesting a pause frame transmission.
The status (and register bit) is cleared after the pause frame has been sent.
• A pause frame was received stopping the transmitter. The stopped situation is terminated
when the pause timer expired or a pause frame with zero quanta is received.
• MAC is placed in Sleep mode by set SLEEP or SLEEP bit (see Sleep Mode).
When the transmitter has reached its stopped state, the following events occur:
• The GRA interrupt is asserted (once, when transitioned into stopped).
26.3.12.5 Graceful Receive Stop (GRS)

When gracefully stopped, the MAC is no longer writing frames into the receive FIFO. If
any of the following conditions occur, the receive datapath will stop after any ongoing frame
reception has been completed normally.
• MAC is placed in sleep mode (by set SLEEP or SLEEP ). The MAC will continue to
receive frames and hunt for magic packets if enabled (see Sleep Mode). However, no
frames will be written into the receive FIFO and therefore will not be forwarded to the
application.
When the receive datapath is stopped, the following events will occur:
• The RCR(GRS) bit is set as long as the RX is in the stopped state.
• The GRA interrupt is asserted when the transmitter is also stopped (both TX and RX
are stopped).
• Any ongoing receive transaction to the application (RX FIFO read) will continue
normally until the frame is completed (eop). After this, the following happens:
• When sleep mode is active, all further frames will be discarded, flushing the rx
FIFO.

Note
The assertion of GRS will not wait for an ongoing transaction on
the application side of the FIFO (FIFO read). If necessary, the
signal can be ANDed with the ff_rx_dval (considering proper
clock domains).
26.3.12.6 Graceful Stop Interrupt (GRA)

The graceful stopped interrupt (GRA) is asserted for the following conditions:
• If sleep mode is active, the interrupt asserts only after both TX and RX datapaths are
stopped.
•
• The MAC transmit datapath is stopped for any other condition (GTS, TFC_PAUSE,
pause received).
The GRA interrupt is triggered only once when the stopped state is entered. If the interrupt
is cleared while the stop condition persists, no further interrupt will be triggered.
26.3.13 IEEE 1588 Functions
26.3.13.1 Overview
To allow for IEEE 1588 or similar time synchronization protocol implementations, the
MAC is combined with a time-stamping module to support precise time stamping of
incoming and outgoing frames. 1588 Support is enabled when the register bit ENA_1588
is set to '1'.
MAC with 1588
Frame Data 10/100 MAC

(mac) PHY
Adjustable 1PPS
Control/ Timing Events
Status Timer Module
gen
(tsm)
Control/
Status
Data Control
User Application
Figure 26-18. IEEE 1588 Functions Overview

IEEE 1588 Functions
26.3.13.2.1 Overview
The Adjustable Timer Module (TSM) implements the Free Running Counter (FRC), the
timer, which is used to generate the timestamps. The FRC operates with the clock
CLK_ENET_TIME, which can be set to any value depending on the system requirements.
However, it is recommended to choose a period, which is an integer value (for example, 5
ns, 6 ns, 8 ns, but not 7.5 ns) to implement a precise timer.
The current value of the FRC is available on the Core toplevel pins frc().
Through dedicated correction logic (see below), the timer can be adjusted allowing
synchronization to a remote master and provide a synchronized timing reference to the local
system. The timer can be configured to cause an interrupt after a fixed period of time to
allow synchronization of software timers or perform other synchronized system functions.
The timer is usually used to implement a period of 1 second, hence, its value would range
from 0 to (1*109)-1. The period event can trigger an interrupt and software then can maintain
the seconds and hours time values and so on as necessary.
26.3.13.2.2 Adjustable Timer Implementation
The adjustable timer consists of a programmable counter/accumulator and a correction
counter. The periods of both counters and its increment rate are freely configurable allowing
very fine tuning of the timer.
frc_in(31:0)
Adjustable Timer frc(31:0)
Counter
current time to intemal
modules
ATIME_EVT_PERICD mod (MAC,capture/
compare)
Correction Inc by normal correction
Counter FRC_SLAVE
ATIME_CORR ATIME_INC(14:8) ATIME_INC(6:0)

correction Increment normal Increment
Figure 26-19. Adjustable Timer Implementation Detail
The counter is producing the current time. Each clock cycle (CLK_ENET_TIME), a constant
value is added to the current time as programmed in the ATIME_INC(4:0) register. The
value depends on the chosen clock frequency of CLK_ENET_TIME. For example, if the
CLK_ENET_TIME operates at 125 MHz, the increment would be set to 8 representing 8
ns.
The period, configured in register ATIME_EVT_PERIOD, defines the modulo when the
counter has to wrap around. In a typical implementation, the period is set to 1*109, so the
counter wraps every 1 second and hence, all timestamps represent the absolute nanoseconds

within the 1 second period. When the period is reached, the counter wraps to start again
respecting the period modulo. This means it will not necessarily start from 0 but instead the
counter will be loaded with the value (current + inc - (1*109)) assuming the period was set
to 1*109.
The correction counter operates fully independently and increments by 1 with each clock
cycle (CLK_ENET_TIME). When it reaches the value configured in ATIME_CORR, it
restarts and instructs the timer once to increment by the correction value, instead of the
normal value. The normal and correction increments are configured in register ATIME_INC.
To speed up the timer, the correction increment would be larger than the normal increment
value. To slow down the timer, the correction increment would be smaller than the normal
increment value. Note that the correction counter only defines the distance of the corrective
actions, not the amount. This allows very fine corrections (and hence low jitter) happening
in the range of 1ns independently from the chosen clock frequency.
By enabling the slave mode (ATIME_CTRL(FRC_SLAVE)), the timer is ignored and the
current time is the externally provided time from pins frc_in(). This is useful if multiple
modules within the system need to operate from a single timer (see below).
When slave mode is enabled, it is still required to set the ATIME_INC(6:0) increment value
to the value of the master as it is used for internal comparisons.
26.3.13.3 Timer Synchronization for Multi-Port Implementations

An additional timer input is available on the Core toplevel pins frc_in() to allow to use an
externally provided timer value for all time stamping functions. This is necessary if multiple
instances (ports) of the MAC should be synchronized to a single reference timer in the
system. In i.MX28, ENET-MAC0 is used as master, so the timer input (frc_in) of
ENET_MAC0 is unused and wired to all 0. The FRC value of ENET_MAC0 is wired to
frc_in of ENET_MAC1 (acting as slave). To operate the MAC in Slave mode, the timer
module configuration ATIME_CTRL(FRC_SLAVE) is used to disable the internal adjustable
timer and use only the externally provided time value.
Timing Master Timing Slave
MAC with 1588
MAC with 1588 10/100 MAC
10/100 MAC (mac1 as slave)
(mac0 as master)
frc frc_in
frc_in Timing
Adjustable Events
Timing Events
Timer Module gen.
gen.
(tsm)
Figure 26-20. 1588 Multiple MAC implementation

IEEE 1588 Functions
26.3.13.4 Transmit Timestamping

On transmit, only 1588 event frames need to be time-stamped. The Client application (for
example, the MAC driver) should detect 1588 event frames and set 'TS' bit in Enhanced
uDMA Transmit Buffer Descriptor.
For every transmitted frame, the MAC returns the captured timestamp in '1588 Timestamp'
and the transmit status TSE in Enhanced uDMA Transmit Buffer Descriptor. The transmit
status bit indicates that the application had the TS bit asserted for the frame.
If TS is set to '1', the MAC additionally memorizes the timestamp for the frame in the
register TS_TIMESTAMP. The interrupt bit EIR(TS_AVAIL) is set to indicate that a new
timestamp is available.
Software would implement a handshaking procedure by setting the TS bit when it transmits
the frame it needs a timestamp for and then waits on the EIR(TS_AVAIL) interrupt bit to
know when the timestamp is available. It then can read the timestamp from the
TS_TIMESTAMP register. This is done for all event frames, other frames will not use the
TS indicator and hence will not interfere with the timestamp capture.
26.3.13.5 Receive Timestamping

When a frame is received, the MAC latches the value of the timer when the frame SFD
field is detected and provides the captured timestamp '1588 Timestamp' in Enhanced uDMA
Receive Buffer Descriptor. This is done for all received frames.
The DMA controller has to ensure that it transfers the timestamp provided for the frame
into the corresponding field within the receive descriptor for software access.
26.3.13.6 Time Synchronization

To synchronize the local clock of a node to a remote master, the adjustable timer module
is available. It implements a free running 32-bit counter, which has an additional correction
counter connected to it. The correction counter is used to increase or decrease the rate of
the free running counter, enabling very fine granular changes of the timer for synchronization,
yet adding only very low jitter when performing corrections.
The application (software) implements, in a slave scenario, the required control algorithm
setting the correction to compensate for local oscillator drifts and locking the timer to the
remote master clock on the network.

The timer and all timestamp related information should be configured to show the true
nanoseconds value of a second (that is, the timer is configured to have a period of 1 second).
Hence, the values range from 0 to (1*109)-1. In this application, the seconds counter is
implemented in software using an interrupt function that is executed whenever the
nanoseconds counter wraps at 1*109.
Note
Implementing the seconds counter in software is not a strict
requirement.
26.3.13.7 Capture/Compare Block

The Capture / Compare block can provide precise hardware timing for four input events
and four output events.
The capture registers (CAPT_REG..) latch the time value when the corresponding external
event occurs (evt_in()). If the corresponding interrupt bit is enabled in the CCB_INT register,
an interrupt can be generated.
The compare registers (COMP_REG_..) are loaded with the time at which the corresponding
event should occur. The timer reached the value, the corresponding output pin (evt_out())
is asserted. If the corresponding interrupt bit is enabled in the EIMR register, an interrupt
can be generated.
26.3.14 FIFO Thresholds
26.3.14.1 Overview
The Core FIFO thresholds are all fully programmable to provide the possibility to
dynamically change the FIFO operation. For example, store and forward transfer can be
enabled by a simple change in the FIFO threshold registers. The thresholds are defined in
64-bit words.
26.3.14.2 Receive FIFO

Four programmable thresholds are available which are programmed with the registers
RX_ALMOST_EMPTY, RX_ALMOST_FULL, RX_SECTION_EMPTY and
RX_SECTION_FULL which can be set to any value to control operation as follows table.

FIFO Thresholds
Table 26-23. Receive FIFO Thresholds Definition

Register Description
RX_ALMOST_EMPTY When the FIFO level reaches the value programmed in the register RX_ALMOST_EMPTY, and the
end-of-frame has not been received for the frame yet, the Core receive read control stops FIFO read
(and subsequently stops transferring data to the MAC client application).
It continues to deliver the frame, if again more data than the threshold or the end-of-frame is available
in the FIFO.
A minimum value of 6 should be set.
RX_ALMOST_FULL When the FIFO level comes close to the maximum, so that there is no more space for at least
RX_ALMOST_FULL number of words, the MAC control logic stops writing data in the FIFO and
truncates the received frame to avoid FIFO overflow.
The corresponding error status will be set when the frame is delivered to the application.
RX_SECTION_EMPTY When the FIFO level reaches the value programmed in the register RX_SECTION_EMPTY, an indic-
ation is provided to the MAC transmit logic, which generates a XOFF Pause frame to indicate FIFO
congestion to the remote Ethernet client.
When the FIFO level goes below the value programmed in the register RX_SECTION_EMPTY, an
indication is provided to the MAC transmit logic, which generates a XON Pause frame to indicate the
FIFO congestion is cleared to the remote Ethernet client.
A value of 0 disables any pause frame generation.
RX_SECTION_FULL When the FIFO level reaches the value programmed in the register RX_SECTION_FULL, the MAC
will indicate uDMA that data is available in the Receive FIFO (cut-through operation) by asserted a
internal signal. MAC will deassert the siganl again after asserted, if the fifo empties below the threshold
set with RX_ALMOST_EMPTY, and if the end-of-frame is not yet stored in the fifo (Hysteresis).
If a Frame has a size smaller than the threshold (i.e. an end-of-frame is available for the frame), the
status is also asserted.
To enable store and forward on the receive path, set the register RX_SECTION_FULL to 0. In this
case, The signal is asserted only when a complete frame is stored in the receive FIFO.
When programming a value>0 (cut-through operation) it should be greater than RX_ALMOST_EMPTY.
FIFO Read Control
MAC Receive
(FIFO White Proctection
(FIFO Read Control)
Almost Full
Almost Empty
(Core FIFO Status)
Section Full
Section Empty
(Pause Frame Generation)
Figure 26-21. Receive FIFO Overview

26.3.14.3 Transmit FIFO

Four programmable thresholds are available which are programmed with registers
TX_ALMOST_EMPTY, TX_ALMOST_FULL, TX_SECTION_EMPTY and TFWR /
STR_FWD.
Table 26-24. Transmit FIFO Thresholds Definition
Register Description
TX_ALMOST_EMPTY When the FIFO level reaches the value programmed in the register TX_ALMOST_EMPTY, and no
end-of-frame is available for the frame, the MAC transmit logic, to avoid FIFO underflow, stops reading
the FIFO and transmits the Ethernet frame with a MII error indication.
TX_ALMOST_FULL When the FIFO level comes close to the maximum, so that there is no more space for at least
TX_ALMOST_FULL number of words, the pin ff_tx_rdy is deasserted.
If the application does not react on this signal, the FIFO write control logic, to avoid FIFO overflow,
truncates the current frame and sets the error status. As a result the frame will be transmitted with an
MII error indication.
A minimum value of 4 should be set. Larger values allow more latency for the application to react on
ff_tx_rdy deassertion, before the frame is being truncated.
A typical setting is 8, which offers 3-4 clock cycles of latency to the application to react on ff_tx_rdy
deassertion.
TX_SECTION_EMPTY When the FIFO level reaches the value programmed in the register TX_SECTION_EMPTY, the Core
status ff_tx_septy is deasserted to indicate that the Transmit FIFO is getting full.
This gives the application an indication to slow down or stop its write transaction to avoid a buffer
overflow.
This is a pure indication function to the application. It has no effect within the MAC.
When a value of 0 is set, the signal is never deasserted.
TFWR / STR_FWD When the FIFO level reaches the value coded in the register TFWR and when the register bit STR_FWD
is set to '0', the MAC transmit control logic starts frame transmission even before the end-of-frame is
available in the FIFO (cut-through operation).
If a complete frame has a size smaller than the threshold programmed with TFWR, the MAC also
transmits the Frame to the line.
To enable store and forward on the Transmit path, set the register bit STR_FWD to '1'. In this case,
the MAC starts to transmit data only when a complete frame is stored in the Transmit FIFO.

Loopback Options
FIFO Write Control
MAC Transmit
(FIFO White Control)
(MAC Read Control)

Almost Empty
Almost Full
(Core FIFO Status)
(MAC Transmit Start)

Section Empty
Section Full
Figure 26-22. Transmit FIFO Overview
26.3.15 Loopback Options
26.3.15.1 Overview
The Core implements external and internal loopback options with are controlled by the
RCR register bits LOOP.
Table 26-25. Loopback Options
Register Bit Description
LOOP Internal MII Loopback

The MAC transmit is returned to the MAC receive. No data is transmitted to the external interfaces.
RMII_LOOP External RMII Near End Loopback. Not surpport now.
RMII_ECHO External RMII Far End Loopback. Not surpport now.

MAC Interface
Line Interface
LOOP ena_loop
RMII_ECHO ena_rmii_loop
RMII_LOOP ena_rmii_echo
Figure 26-23. Loopback Options
26.3.16 FIFO Protection
26.3.16.1 Transmit FIFO Underflow

When the Transmit FIFO, during a frame transfer, reaches the almost empty threshold with
no End of Frame indication stored in the FIFO, the MAC logic stops reading data from the
FIFO, sets the MII error signal (mii_tx_err) to '1' to indicate that the fragment already
transferred is not valid and deasserts the MII transmit enable signal (mii_tx_en) to terminate
the frame transfer .
When after an underflow, the application completes the frame transfer , the MAC transmit
logic discards any new data available in the FIFO until the end of packet is reached and sets
bit UE of Enhanced uDMA Transmit Buffer Descriptor.
The MAC starts to transfer data on the MII interface when the application sends a new
frame with a start of frame indication .
26.3.16.2 Transmit FIFO Overflow

On the transmit path, when the FIFO reaches the programmable almost full threshold, if
the application keeps sending new data, the transmit FIFO will overflow, corrupting
previously stored contents. ENET-MAC will set bit OE of Enhanced uDMA Transmit Buffer
Descriptor for the next frame transmitted to indicate this overflow occurrence.

PHY Management Interface
Note that overflow is a fatal error and must be addressed by resetting the core or deasserting
the ECR(ETHER_EN) bit to clear the FIFOs and prepare for normal operation again.
26.3.16.3 Receive FIFO Overflow

If, during a frame reception the client application is not able to receive data , the MAC
receive control, when the FIFO reaches the programmable almost full threshold truncates
the incoming frame (To avoid a overflow). The frame is subsequently received on the FIFO
interface with an error indication (ME of Enhanced uDMA Receive Buffer Descriptor )
with the truncation error status bit (TR of Legacy FEC Receive Buffer Descriptor) set to
'1'.
GMII /MII Receive
rx_clk
gmii/mii_rx_en
gmii/mii_rx_data
gmii/mii_rx_err
Receive FIFO
ff_rx_clk
ff_rx_rdy
ff_rx_dsav
ff_rx_dval
ff_rx_sop
ff_rx_eop
ff_rx_data
ff_rx_err
ff_rx_err_stat
2 3
1
Figure 26-24. Receive FIFO Overflow Protection
26.3.17 PHY Management Interface
26.3.17.1 Overview
The MDIO interface is a two-wire Management Interface. The MDIO management interface
implements a standardized method to access the PHY device management registers. This
is a Master MDIO interface, which can be connected to up to 32 PHY devices.
26.3.17.2 MDIO Frame Format

The MDIO Master controller communicates with the Slave (PHY device) using Frames,
which are defined in Table 26-26. A complete frame has a length of 64 bits (Optional 32
bit preamble, 14 bit command, 2 bit bus direction change, 16 bit data). Each bit is transferred
with the rising edge of the MDIO clock (MDC signal). The PHY Management interface
supports the standard MDIO specification (IEEE803.2 Clause 22).
Table 26-26. MDIO Frame Formats (Read / Write)
Type Command

PRE ST OP Addr1 Addr2 TA Data Idle

MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB
Read 1...1 01 10 xxxxx xxxxx Z0 xxxxxxxxxxxxxxxx Z
Write 1...1 01 01 xxxxx xxxxx 10 xxxxxxxxxxxxxxxx Z
Table 26-27. MDIO Frame Fields Description

Name Description
PRE Preamble: 32 Bits of logical '1' sent prior to every transaction when the register bit DIS_PRE is set to
'0. If DIS_PRE is set to '1', the preamble is not generated.
ST Start indication, programmed with the register bits ST:

Standard MDIO (Clause 22): '01'
OP The opcode, programmed with the register bits OP, defines whether a read or write operation is per-
formed:
If '10' a read operation is performed.
If '01' a write operation is performed.
Addr1 The PHY device address, programmed with the register bits PA. Up to 32 devices can be addressed.
Addr2 Register Address, programmed with the register bits RA. Each PHY can implement up to 32 registers.
TA Turnaround time, programmed with register bits TA. Two bit-times are reserved for read operations
to switch the data bus from write to read for read operations. The PHY device will present its register
contents in the data phase and drives the bus from the second bit of the turnaround phase.
Data 16 bits of data written, set to register bits DATA, to the PHY or read from the PHY on register bits
DATA.
Idle Between frames, the MDIO data signal is tri-stated.
26.3.17.3 MDIO Clock Generation

The MDC clock is generated from the register interface clock pclk divided by the value
programmed in the Core register MII_SPEED.
26.3.17.4 MDIO Operation

To perform a MDIO access, the MDIO Command register (Register MMFR) should be set
according to the description provided in MAC_MMFR. To check when the programmed
access is completed, the EIR status register should be read and the register bit MII checked.

MII Interface
Start
Load MMFR
Register
Read EIR
No
MII='1'
Yes
Figure 26-25. MDIO Access Overview
26.3.17.5 MDIO Buffer Connection
mdio_in
MDIO
mdio_out
mdio_oeN
Figure 26-26. MDIO Buffer Connection
26.3.18 MII Interface
26.3.18.1 Transmit
On Transmit, all data transfers are synchronous to tx_clk rising edge. The MII data enable
signal mii_tx_en is asserted to indicate the start of a new frame and remains asserted until
the last byte of the frame is present on mii_tx_d(3:0) bus. Between frames, mii_tx_en
remains de-asserted.

CRC-32
Preamble SFD
tx_dk
mii_tx_d(3:0) 5
mii_tx_en
mii_tx_err
Figure 26-27. MII Transmit Operation
If a frame is received on the FIFO interface with an error (for example, Signal ff_rx_err
asserted) the frame is subsequently transmitted with the MII mii_tx_err error signal for one
clock cycle at any time during the packet transfer.
CRC-32
Preamble SFD
tx_clk
mii_tx_d(3:0) 5
mii_tx_en
mii_tx_err
Figure 26-28. MII Transmit Operation - Errored Frame
26.3.18.2 Transmit with Collision - Half Duplex

When a collision is detected during a frame transmission (MII signal mii_col asserted), the
MAC stops the current transmission, sends a 32-Bit jam pattern and re-transmits the current
frame (See section Collision Detection in Half Duplex Mode for detail).
Jam
tx_clk
mii_tx_d(3:0) 5
mii_tx_en
mii_tx_err
mii_crs
mii_col
Figure 26-29. MII Transmit Operation - Transmission with Collision
26.3.18.3 Receive
On Receive, all signals are sampled on the rx_clk rising edge. The MII data enable signal
mii_rx_dv is asserted by the PHY to indicate the start of a new frame and remains asserted
until the last byte of the frame is present on mii_rx_d(3:0) bus. Between frames, mii_rx_dv
remains de-asserted.

MII Interface
CRC-32
Preamble SFD
rx_clk
mii_rx_d(3:0) 5
mii_rx_dv
mii_rx_err
Figure 26-30. MII Receive Operation
If the PHY detects an error on the frame received from the line, the PHY asserts the MII
error signal, mii_rx_err, for at least one clock cycle at any time during the packet transfer.
CRC-32
Preamble SFD
rx_clk
mii_rx_d(3:0) 5
mii_rx_dv
mii_rx_err
Figure 26-31. MII Receive Operation - Errored Frame
26.3.19 MII Interface Timing Characteristics
rx_clk
tx_clk
1/F max
rx_clk
mii_rx_d(3:0)
mii_rx_dv
mii_rx_err
thold
tsu

tx_clk
mii_tx_d(3:0)
mii_tx_en
mii_tx_err
too
Table 26-28. MII Timing Characteristics

Symbol Description Value
Min Max
Fmax MII Maximum Frequency 2.5 MHz 25 MHz
tsu MII Inputs Setup Time 2 ns -
thold MII Inputs Hold Time 0 ns -
tco MII Outputs Clock to Out - 5 ns

Each ENET-MAC with its corresponding management counters implements a register space
of 512 32-bit registers. All reads and writes must be 32 bits wide. Reserved bits should be
written with 0 and ignored on read to allow future extension. Unused registers read back 0
and a write has no effect.
ENET-MAC0 base address is 0x800F0000; ENET-MAC1 base address is 0x800F4000.
HW_ENET memory map
Absolute
Width Section/
(in bits) page
(hex)
800F_0004 ENET MAC Interrupt Event Register (HW_ENET_MAC_EIR) 32 R/W 0000_0000h 26.4.1/1661
800F_0008 ENET MAC Interrupt Mask Register (HW_ENET_MAC_EIMR) 32 R/W 0000_0000h 26.4.2/1663
800F_0010 ENET MAC Receive Descriptor Active Register 32 R/W 0000_0000h 26.4.3/1663
(HW_ENET_MAC_RDAR)
800F_0014 ENET MAC Transmit Descriptor Active Register 32 R/W 0000_0000h 26.4.4/1664
(HW_ENET_MAC_TDAR)
800F_0024 ENET MAC Control Register (HW_ENET_MAC_ECR) 32 R/W F000_0000h 26.4.5/1665
800F_0040 ENET MAC MII Management Frame Register 32 R/W 0000_0000h 26.4.6/1666
(HW_ENET_MAC_MMFR)
800F_0044 ENET MAC MII Speed Control Register 32 R/W 0000_0000h 26.4.7/1667
(HW_ENET_MAC_MSCR)

HW_ENET memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
800F_0064 ENET MAC MIB Control/Status Register 32 R/W C000_0000h 26.4.8/1668
(HW_ENET_MAC_MIBC)
800F_0084 ENET MAC Receive Control Register (HW_ENET_MAC_RCR) 32 R/W 05EE_0001h 26.4.9/1669
800F_00C4 ENET MAC Transmit Control Register 32 R/W 0000_0000h 26.4.10/1671
(HW_ENET_MAC_TCR)
800F_00E4 ENET MAC Physical Address Lower Register 32 R/W 0000_0000h 26.4.11/1672
(HW_ENET_MAC_PALR)
800F_00E8 ENET MAC Physical Address Upper Register 32 R/W 0000_8808h 26.4.12/1673
(HW_ENET_MAC_PAUR)
800F_00EC ENET MAC Opcode/Pause Duration Register 32 R/W 0001_0000h 26.4.13/1673
(HW_ENET_MAC_OPD)
800F_0118 ENET MAC Descriptor Individual Upper Address Register 32 R/W 0000_0000h 26.4.14/1674
(HW_ENET_MAC_IAUR)
800F_011C ENET MAC Descriptor Individual Lower Address Register 32 R/W 0000_0000h 26.4.15/1674
(HW_ENET_MAC_IALR)
800F_0120 ENET MAC Descriptor Group Upper Address Register 32 R/W 0000_0000h 26.4.16/1675
(HW_ENET_MAC_GAUR)
800F_0124 ENET MAC Descriptor Group Lower Address Register 32 R/W 0000_0000h 26.4.17/1675
(HW_ENET_MAC_GALR)
800F_0144 ENET MAC Transmit FIFO Watermark and Store and Forward 32 R/W 0000_0000h 26.4.18/1676
Control Register (HW_ENET_MAC_TFW_SFCR)
800F_014C ENET MAC FIFO Receive Bound Register 32 R/W 0000_0600h 26.4.19/1677
(HW_ENET_MAC_FRBR)
800F_0150 ENET MAC FIFO Receive FIFO Start Register 32 R/W 0000_0500h 26.4.20/1677
(HW_ENET_MAC_FRSR)
800F_0180 ENET MAC Pointer to Receive Descriptor Ring Register 32 R/W 0000_0000h 26.4.21/1678
(HW_ENET_MAC_ERDSR)
800F_0184 ENET MAC Pointer to Transmit Descriptor Ring Register 32 R/W 0000_0000h 26.4.22/1679
(HW_ENET_MAC_ETDSR)
800F_0188 ENET MAC Maximum Receive Buffer Size Register 32 R/W 0000_0000h 26.4.23/1680
(HW_ENET_MAC_EMRBR)
800F_0190 ENET MAC Receive FIFO Section Full Threshold Register 32 R/W 0000_0000h 26.4.24/1681
(HW_ENET_MAC_RX_SECTION_FULL)
800F_0194 ENET MAC Receive FIFO Section Empty Threshold Register 32 R/W 0000_0000h 26.4.25/1681
(HW_ENET_MAC_RX_SECTION_EMPTY)
800F_0198 ENET MAC Receive FIFO Almost Empty Threshold Register 32 R/W 0000_0004h 26.4.26/1682
(HW_ENET_MAC_RX_ALMOST_EMPTY)
800F_019C ENET MAC Receive FIFO Almost Full Thresholdt Register 32 R/W 0000_0004h 26.4.27/1682
(HW_ENET_MAC_RX_ALMOST_FULL)
800F_01A0 ENET MAC Transmit FIFO Section Empty Threshold Register 32 R/W 0000_0000h 26.4.28/1683
(HW_ENET_MAC_TX_SECTION_EMPTY)


Absolute
Width Section/
(in bits) page
(hex)
800F_01A4 ENET MAC Transmit FIFO Almost Empty Threshold Register 32 R/W 0000_0004h 26.4.29/1683
(HW_ENET_MAC_TX_ALMOST_EMPTY)
800F_01A8 ENET MAC Transmit FIFO Almost Full Threshold Register 32 R/W 0000_0008h 26.4.30/1684
(HW_ENET_MAC_TX_ALMOST_FULL)
800F_01AC ENET MAC Transmit Inter-Packet Gap Register 32 R/W 0000_000Ch 26.4.31/1684
(HW_ENET_MAC_TX_IPG_LENGTH)
800F_01B0 ENET MAC Frame Truncation Length Register 32 R/W 0000_07FFh 26.4.32/1685
(HW_ENET_MAC_TRUNC_FL)
800F_01C0 ENET MAC Accelerator Transmit Function Configuration 32 R/W 0000_0000h 26.4.33/1685
Register (HW_ENET_MAC_IPACCTXCONF)
800F_01C4 ENET MAC Accelerator Receive Function Configuration 32 R/W 0000_0000h 26.4.34/1686
Register (HW_ENET_MAC_IPACCRXCONF)
800F_0200 ENET MAC RMON Tx packet drop 32 R 0000_0000h 26.4.35/1687
(HW_ENET_MAC_RMON_T_DROP)
800F_0204 ENET MAC RMON Tx packet count 32 R 0000_0000h 26.4.36/1688
(HW_ENET_MAC_RMON_T_PACKETS)
800F_0208 ENET MAC RMON Tx Broadcast Packets 32 R 0000_0000h 26.4.37/1688
(HW_ENET_MAC_RMON_T_BC_PKT)
800F_020C ENET MAC RMON Tx Multicast Packets 32 R 0000_0000h 26.4.38/1689
(HW_ENET_MAC_RMON_T_MC_PKT)
800F_0210 ENET MAC RMON Tx Packets w CRC/Align error 32 R 0000_0000h 26.4.39/1689
(HW_ENET_MAC_RMON_T_CRC_ALIGN)
800F_0214 ENET MAC RMON Tx Packets < 64 bytes, good CRC 32 R 0000_0000h 26.4.40/1690
(HW_ENET_MAC_RMON_T_UNDERSIZE)
800F_0218 ENET MAC RMON Tx Packets > MAX_FL bytes, good CRC 32 R 0000_0000h 26.4.41/1690
(HW_ENET_MAC_RMON_T_OVERSIZE)
800F_021C ENET MAC RMON Tx Packets < 64 bytes, bad CRC 32 R 0000_0000h 26.4.42/1691
(HW_ENET_MAC_RMON_T_FRAG)
800F_0220 ENET MAC RMON Tx Packets > MAX_FL bytes, bad CRC 32 R 0000_0000h 26.4.43/1691
(HW_ENET_MAC_RMON_T_JAB)
800F_0224 ENET MAC RMON Tx collision count 32 R 0000_0000h 26.4.44/1692
(HW_ENET_MAC_RMON_T_COL)
800F_0228 ENET MAC RMON Tx 64 byte packets 32 R 0000_0000h 26.4.45/1692
(HW_ENET_MAC_RMON_T_P64)
800F_022C ENET MAC RMON Tx 65 to 127 byte packets 32 R 0000_0000h 26.4.46/1693
(HW_ENET_MAC_RMON_T_P65TO127N)
800F_0230 ENET MAC RMON Tx 128 to 255 byte packets 32 R 0000_0000h 26.4.47/1693
(HW_ENET_MAC_RMON_T_P128TO255N)
(HW_ENET_MAC_RMON_T_P256TO511)


Absolute
Width Section/
(in bits) page
(hex)
800F_023C ENET MAC RMON Tx 1024 to 2047 byte packets 32 R 0000_0000h 26.4.50/1695
800F_0240 ENET MAC RMON Tx packets w > 2048 bytes 32 R 0000_0000h 26.4.51/1695
(HW_ENET_MAC_RMON_T_P_GTE2048)
800F_0244 ENET MAC RMON Tx Octets 32 R 0000_0000h 26.4.52/1696
(HW_ENET_MAC_RMON_T_OCTETS)
800F_0248 ENET MAC Frames Transmitted count drop 32 R 0000_0000h 26.4.53/1696
(HW_ENET_MAC_IEEE_T_DROP)
800F_024C ENET MAC Frames Transmitted OK 32 R 0000_0000h 26.4.54/1697
(HW_ENET_MAC_IEEE_T_FRAME_OK)
800F_0250 ENET MAC Frames Transmitted with Single Collision 32 R 0000_0000h 26.4.55/1697
(HW_ENET_MAC_IEEE_T_1COL)
800F_0254 ENET MAC Frames Transmitted with Multiple Collisions 32 R 0000_0000h 26.4.56/1698
(HW_ENET_MAC_IEEE_T_MCOL)
800F_0258 ENET MAC Frames Transmitted after Deferral Delay 32 R 0000_0000h 26.4.57/1698
(HW_ENET_MAC_IEEE_T_DEF)
800F_025C ENET MAC Frames Transmitted with Late Collision 32 R 0000_0000h 26.4.58/1699
(HW_ENET_MAC_IEEE_T_LCOL)
800F_0260 ENET MAC Frames Transmitted with Excessive Collisions 32 R 0000_0000h 26.4.59/1699
(HW_ENET_MAC_IEEE_T_EXCOL)
800F_0264 ENET MAC Frames Transmitted with Tx FIFO Underrun 32 R 0000_0000h 26.4.60/1700
(HW_ENET_MAC_IEEE_T_MACERR)
800F_0268 ENET MAC Frames Transmitted with Carrier Sense Error 32 R 0000_0000h 26.4.61/1700
(HW_ENET_MAC_IEEE_T_CSERR)
800F_026C ENET MAC Frames Transmitted with SQE Error 32 R 0000_0000h 26.4.62/1700
(HW_ENET_MAC_IEEE_T_SQE)
800F_0270 ENET MAC Frames Transmitted flow control 32 R 0000_0000h 26.4.63/1701
(HW_ENET_MAC_IEEE_T_FDXFC)
800F_0274 ENET MAC Frames Transmitted error 32 R 0000_0000h 26.4.64/1701
(HW_ENET_MAC_IEEE_T_OCTETS_OK)
800F_0284 ENET MAC RMON Rx packet count 32 R 0000_0000h 26.4.65/1702
(HW_ENET_MAC_RMON_R_PACKETS)
800F_0288 ENET MAC RMON Rx Broadcast Packets 32 R 0000_0000h 26.4.66/1702
(HW_ENET_MAC_RMON_R_BC_PKT)
800F_028C ENET MAC RMON Rx Multicast Packets 32 R 0000_0000h 26.4.67/1703
(HW_ENET_MAC_RMON_R_MC_PKT)
800F_0290 ENET MAC RMON Rx Packets w CRC/Align error 32 R 0000_0000h 26.4.68/1703
(HW_ENET_MAC_RMON_R_CRC_ALIGN)
800F_0294 ENET MAC RMON Rx Packets < 64 bytes, good CRC 32 R 0000_0000h 26.4.69/1704
(HW_ENET_MAC_RMON_R_UNDERSIZE)
800F_0298 ENET MAC RMON Rx Packets > MAX_FL, good CRC 32 R 0000_0000h 26.4.70/1704
(HW_ENET_MAC_RMON_R_OVERSIZE)


Absolute
Width Section/
(in bits) page
(hex)
800F_029C ENET MAC RMON Rx Packets < 64 bytes, bad CRC 32 R 0000_0000h 26.4.71/1705
(HW_ENET_MAC_RMON_R_FRAG)
800F_02A0 ENET MAC RMON Rx Packets > MAX_FL bytes, bad CRC 32 R 0000_0000h 26.4.72/1705
(HW_ENET_MAC_RMON_R_JAB)
800F_02A8 ENET MAC RMON Rx 64 byte packets 32 R 0000_0000h 26.4.73/1706
(HW_ENET_MAC_RMON_R_P64)
800F_02AC ENET MAC RMON Rx 65 to 127 byte packets 32 R 0000_0000h 26.4.74/1706
(HW_ENET_MAC_RMON_R_P65TO127)
800F_02B0 ENET MAC RMON Rx 128 to 255 byte packets 32 R 0000_0000h 26.4.75/1707
800F_02BC ENET MAC RMON Rx 1024 to 2047 byte packets 32 R 0000_0000h 26.4.78/1708
800F_02C0 ENET MAC RMON Rx packets w > 2048 bytes 32 R 0000_0000h 26.4.79/1709
(HW_ENET_MAC_RMON_R_P_GTE2048)
800F_02C4 ENET MAC RMON Rx Octets 32 R 0000_0000h 26.4.80/1709
(HW_ENET_MAC_RMON_R_OCTETS)
800F_02C8 ENET MAC Frames Received count drop 32 R 0000_0000h 26.4.81/1709
(HW_ENET_MAC_IEEE_R_DROP)
800F_02CC ENET MAC Frames Received OK 32 R 0000_0000h 26.4.82/1710
(HW_ENET_MAC_IEEE_R_FRAME_OK)
800F_02D0 ENET MAC Frames Received with CRC Error 32 R 0000_0000h 26.4.83/1710
(HW_ENET_MAC_IEEE_R_CRC)
800F_02D4 ENET MAC Frames Received with Alignment Error 32 R 0000_0000h 26.4.84/1711
(HW_ENET_MAC_IEEE_R_ALIGN)
800F_02D8 ENET MAC Frames Received overflow 32 R 0000_0000h 26.4.85/1711
(HW_ENET_MAC_IEEE_R_MACERR)
800F_02DC ENET MAC Frames Received flow control 32 R 0000_0000h 26.4.86/1712
(HW_ENET_MAC_IEEE_R_FDXFC)
800F_02E0 ENET MAC Frames Received error 32 R 0000_0000h 26.4.87/1712
(HW_ENET_MAC_IEEE_R_OCTETS_OK)
800F_0400 ENET MAC IEEE1588 Timer Control Register 32 R/W 0000_0000h 26.4.88/1713
(HW_ENET_MAC_ATIME_CTRL)
800F_0404 ENET MAC IEEE1588 Timer value Register 32 R/W 0000_0000h 26.4.89/1715
(HW_ENET_MAC_ATIME)
800F_0408 ENET MAC IEEE1588 Offsetvalue for one-shot event 32 R/W 0000_0000h 26.4.90/1715
generation Register (HW_ENET_MAC_ATIME_EVT_OFFSET)
800F_040C ENET MAC IEEE1588 Timer Period Register 32 R/W 3B9A_CA00h 26.4.91/1716
(HW_ENET_MAC_ATIME_EVT_PERIOD)


Absolute
Width Section/
(in bits) page
(hex)
800F_0410 ENET MAC IEEE1588 Correction counter wrap around value 32 R/W 0000_0000h 26.4.92/1716
Register (HW_ENET_MAC_ATIME_CORR)
800F_0414 ENET MAC IEEE1588 Clock period of the timestamping clock 32 R/W 0000_0000h 26.4.93/1717
(ts_clk) in nanoseconds and correction increment Register
(HW_ENET_MAC_ATIME_INC)
800F_0418 ENET MAC IEEE1588 Timestamp of the last Frame Register 32 R 0000_0000h 26.4.94/1718
(HW_ENET_MAC_TS_TIMESTAMP)
800F_0500 ENET MAC Supplemental MAC Address 0 32 R/W 0000_0000h 26.4.95/1719
(HW_ENET_MAC_SMAC_0_0)
800F_050C ENET MAC Supplemental MAC Address 1 32 R/W 0000_0000h 26.4.98/1720
800F_051C ENET MAC Supplemental MAC Address 3 32 R/W 0000_0000h 26.4.102/1722
800F_0600 ENET MAC Compare register 0 32 R/W 0000_0000h 26.4.103/1722
(HW_ENET_MAC_COMP_REG_0)
800F_060C ENET MAC Compare register 3 32 R/W 0000_0000h 26.4.106/1724
800F_0640 ENET MAC Capture register 0 32 R 0000_0000h 26.4.107/1724
(HW_ENET_MAC_CAPT_REG_0)
800F_064C ENET MAC Capture register 3 32 R 0000_0000h 26.4.110/1726
800F_0680 ENET MAC IEEE1588 Interrupt register. 32 R/W 0000_0000h 26.4.111/1726
(HW_ENET_MAC_CCB_INT)


Absolute
Width Section/
(in bits) page
(hex)
800F_0684 ENET MAC IEEE1588 Interrupt enable mask register 32 R/W 0000_0000h 26.4.112/1727
(HW_ENET_MAC_CCB_INT_MASK)
26.4.1 ENET MAC Interrupt Event Register (HW_ENET_MAC_EIR)

When an event occurs that sets a bit in HW_ENET_MAC_EIR, an interrupt occurs if the
corresponding bit in the interrupt mask register (HW_ENET_MAC_EIMR) is also set.
Writing a 1 to an HW_ENET_MAC_EIR bit clears it; writing 0 has no effect. This register
is cleared upon hardware reset.
Address: HW_ENET_MAC_EIR – 800F_0000h base + 4h offset = 800F_0004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSRVD0
TS_AVAIL
WAKEUP
EBERR
BABR BABT GRA TXF TXB RXF RXB MII LC RL UN PLR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD1
TS_TIMER
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_ENET_MAC_EIR field descriptions

Field Description
31 Reserved bits. Write as 0.
RSRVD0
30 Babbling receive error. This bit indicates a frame was received with length in excess of MAX_FL bytes.
BABR
29 Babbling transmit error. This bit indicates the transmitted frame length exceeds MAX_FL bytes. This condition
BABT usually caused by a frame that is too long placed into the transmit data buffer(s). Truncation does not occur.

HW_ENET_MAC_EIR field descriptions (continued)

Field Description
28 Graceful stop complete.This interrupt is asserted after the transmitter is put into a pause state after completion
GRA of the frame currently being transmitted. See Graceful Transmit Stop (GTS) for conditions that lead to graceful
stop.
Note: The GRA interrupt is asserted only when the TX transitions into the stopped state. If this bit is cleared
(by writing 1) and the TX is still stopped, the bit will not become set again.
27 Transmit frame interrupt. This bit indicates a frame has been transmitted and the last corresponding buffer
TXF descriptor has been updated (Signal dma_txf_int asserted).
26 Transmit buffer interrupt. This bit indicates a transmit buffer descriptor has been updated (Signal dma_txb_int
TXB asserted).
25 Receive frame interrupt. This bit indicates a frame has been received and the last corresponding buffer
RXF descriptor has been updated (Signal dma_rxf_int asserted).
24 Receive buffer interrupt. This bit indicates a receive buffer descriptor not the last in the frame has been
RXB updated (Signal dma_rxb_int asserted).
23 MII interrupt. This bit indicates the MII has completed the data transfer requested.
MII
22 Ethernet bus error. This bit indicates a system bus error occurs when a DMA transaction is underway (Signal
EBERR dma_eberr_int asserted). When the EBERR bit is set, ETHER_EN is cleared, halting frame processing by
the MAC. When this occurs, software needs to insure proper actions (possibly resetting the system) to
resume normal operation.
21 Late collision. This bit indicates a collision occurs beyond the collision window (slot time) in half duplex mode.
LC The frame truncates with a bad CRC and the remainder of the frame is discarded.
20 Collision retry limit. This bit indicates a collision occurs on each of 16 successive attempts to transmit the
RL frame. The frame is discarded without being transmitted and transmission of the next frame commences.
This error can only occur in half duplex mode.
19 Transmit FIFO underrun. This bit indicates the transmit FIFO became empty before the complete frame was
UN transmitted. A bad CRC is appended to the frame fragment and the remainder of the frame is discarded.
18 Payload receive error. This bit indicates a frame was received with a payload length error.
PLR
17 Node Wake Up Request Indication. Read only status bit to indicate that a Magic Packet has been detected.
WAKEUP Will act only if ECR(MAGIC_ENA) is 1.
16 Transmit Timestamp Available. Indicates that the timestamp of the last transmitted Timing Frame is available
TS_AVAIL in the register TS_TIMESTAMP.
15 The adjustable timer reached the period or offset events.

TS_TIMER
14–0 Reserved bits. Write as 0.
RSRVD1

26.4.2 ENET MAC Interrupt Mask Register (HW_ENET_MAC_EIMR)

Address: HW_ENET_MAC_EIMR – 800F_0000h base + 8h offset = 800F_0008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
EIMR (bit define is same with EIR register)
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_ENET_MAC_EIMR field descriptions

Field Description
31–0 Each bit corresponds to an interrupt source defined by the EIR register.
EIMR (bit define is same with EIR register) The corresponding EIMR bit determines whether an interrupt condition
can generate an interrupt. At every processor clock, the EIR samples the
signal generated by the interrupting source. The corresponding EIR bit
reflects the state of the interrupt signal even if the corresponding EIMR
bit is not set.
• 0 The corresponding interrupt source is masked.
• 1 The corresponding interrupt source is not masked (i.e. interrupt
is enabled).
26.4.3 ENET MAC Receive Descriptor Active Register

(HW_ENET_MAC_RDAR)
The Receive Descriptor Active Register (RDAR) is a command register, written by the
user, indicating the receive descriptor ring is updated (empty receive buffers have been
produced by the driver with the empty bit set)
Whenever the register is written, the RDAR bit is set. This is independent of the data actually
written by the user. When set, the uDMA polls the receive descriptor ring and processes
receive frames (provided ether_en is also set). Once the uDMA polls a receive descriptor
whose empty bit is not set, the uDMA clears the RDAR bit and ceases receive descriptor
ring polling until the user sets the bit again, signifying that additional descriptors are placed
into the receive descriptor ring. The RDAR registers are cleared at reset and when ether_en
transitions from asserted to de-asserted or when the ecr_reset is set.

Address: HW_ENET_MAC_RDAR – 800F_0000h base + 10h offset = 800F_0010h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD0 RSRVD1
RDAR
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_ENET_MAC_RDAR field descriptions

Field Description
RSRVD0
24 Set to 1 when this register is written, regardless of the value written. Cleared by the uDMA when no additional
RDAR empty descriptors remain in the receive ring. Also cleared when ether_en transitions from asserted to
de-asserted.

RSRVD1
26.4.4 ENET MAC Transmit Descriptor Active Register

(HW_ENET_MAC_TDAR)
The Transmit Descriptor Active Register (TDAR) is a command register which the user
writes to indicate the transmit descriptor ring has been updated (transmit buffers have been
produced by the driver with the ready bit set in the buffer descriptor)
When the register is written, the TDAR bit is set. This value is independent of the data
actually written by the user. When set, the uDMA polls the transmit descriptor ring and
processes transmit frames (provided ether_en is also set). Once the uDMA polls a transmit
descriptor that has a ready bit not set, the uDMA clears the TDAR bit and ceases transmit
descriptor ring polling until the user sets the bit again to signify additional descriptors have
been placed into the transmit descriptor ring. The TDAR register is cleared at reset, when
ether_en transitions from asserted to de-asserted, or when the ecr_reset is set.
Address: HW_ENET_MAC_TDAR – 800F_0000h base + 14h offset = 800F_0014h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD0 RSRVD1
TDAR
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set

HW_ENET_MAC_TDAR field descriptions

Field Description
RSRVD0
24 Set to 1 when this register is written, regardless of the value written. Cleared by the uDMA when no additional
TDAR ready descriptors remain in the transmit ring. Also cleared when ether_en transitions from asserted to
de-asserted.

RSRVD1
26.4.5 ENET MAC Control Register (HW_ENET_MAC_ECR)

To clear any of the event bits within the Interrupt Event Register (EIR), the register must
be written with a '1' in the corresponding bit position.
Address: HW_ENET_MAC_ECR – 800F_0000h base + 24h offset = 800F_0024h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD0[31:16]
Reset 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD0
RSRVD0[15:7]
MAGIC_ENA
R
ETHER_EN
ENA_1588
DBG_EN
RESET
SLEEP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_ENET_MAC_ECR field descriptions

Field Description
RSRVD0
6 Enables the debug input pin mac_freeze. When set, the input has an effect. When cleared (0, reset value)
DBG_EN the input pin has no effect.

RSRVD0

HW_ENET_MAC_ECR field descriptions (continued)

Field Description
4 IEEE1588 Enable. Should be set to '1' to enable the Frame Time Stamping functions. Also drives the DMA
ENA_1588 control bit ena_1588.
3 Put controller in Sleep Mode. When asserted (Set to 1) the controller is configured in sleep mode. When set
SLEEP to 0 (Reset value) the controller is in normal operating mode.
2 Enable Magic Packet Detection. When set to 1, the controller detects Magic Packets and will assert the EIR
MAGIC_ENA (WAKEUP) bit when a frame is detected.
When set to 0 (Reset value) the Magic Detection logic is disabled.
Note: MAGIC_ENA is relevant only if the SLEEP bit is 1. If set to 1, changing the SLEEP bit will enable or
disable both sleep mode and magic packet detection.
1 When this bit is set, MAC is enabled, and reception and transmission are possible. When this bit is cleared,
ETHER_EN reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted
frame. The buffer descriptor(s) for an aborted transmit frame are not updated after clearing this bit. When
ETHER_EN is cleared, the DMA, buffer descriptor, and FIFO control logic are reset, including the buffer
descriptor and FIFO pointers. Hardware alters the ETHER_EN bit under the following conditions:
RESET is set by software, in which case ETHER_EN is cleared
An error condition causes the EBERR bit to set, in which case ETHER_EN is cleared
0 The behavior of ENET-MAC when set this bit is depend on Switch mode.
RESET
If disable switch, assert this bit will reset MAC and UDMA. If enable switch, assert this bit will only reset
MAC. UDMA will be reset by software reset of switch.
26.4.6 ENET MAC MII Management Frame Register

(HW_ENET_MAC_MMFR)
MDIO Management Register
Performing a write to the MMFR register triggers a management frame transaction to the
PHY device unless the MSCR is programmed to 0. If the MSCR register is written to a
non-zero value in the case of writing to MMFR when MSCR equals 0, an MII frame is
generated with the data previously written to the MMFR. This allows MMFR and MSCR
to be programmed in either order if MSCR is currently zero. If the MMFR register is written
while frame generation is in progress, the frame contents are altered. Software must use the
EIR(MII) interrupt indication to avoid writing to the MMFR register while frame generation
is in progress.

Address: HW_ENET_MAC_MMFR – 800F_0000h base + 40h offset = 800F_0040h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ST OP PA RA TA DATA
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_ENET_MAC_MMFR field descriptions

Field Description
31–30 Start of frame delimiter. These bits must be programmed to 0b01 for a valid MII management frame.
ST
29–28 Operation code:
OP
00 Write frame operation, but not MII compliant.
01 Write frame operation for a valid MII management frame.
10 Read frame operation for a valid MII management frame.
11 Read frame operation, but not MII compliant.
27–23 PHY address. This field specifies one of up to 32 attached PHY devices.
PA
22–18 Register address. This field specifies one of up to 32 registers within the specified PHY device.
RA
17–16 Turn around. This field must be programmed to '10' to generate a valid MII management frame.
TA
15–0 Management frame data. This is the field for data to be written to or read from the PHY register.
DATA
26.4.7 ENET MAC MII Speed Control Register (HW_ENET_MAC_MSCR)

Address: HW_ENET_MAC_MSCR – 800F_0000h base + 44h offset = 800F_0044h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD0[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD1
R RSRVD0[15:11]
DIS_
HOLDTIME MII_SPEED
PRE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_ENET_MAC_MSCR field descriptions

Field Description
RSRVD0
10–8 The IEEE802.3 Clause 22 defines a minimum of 10ns for the holdtime on the MDIO output. Depending on
HOLDTIME the host bus frequency the setting may need to be increased. The following
Bit 10:8: MDIO hold time setting: 000 : 1 pclk cycle (default) 001 : 2 pclk cycles 010 : 3 pclk cycles 011 : 4
pclk cycles 100 : 5 pclk cycles 101 : 6 pclk cycles 110 : 7 pclk cycles 111 : 8 pclk cycles
7 Asserting this bit causes preamble (32 1s) not to be prepended to the MII management frame. The MII
DIS_PRE standard allows the preamble to be dropped if the attached PHY device(s) does not require it.
6–1 MII_SPEED controls the frequency of the MII management interface clock (Signal mdc) relative to the internal
MII_SPEED bus clock (pclk). A value of 0 in this field turns off the mdc and leaves it in low voltage state. Any non-zero
value results in the mdc frequency of 1/(MII_SPEED × 2) of the internal bus frequency (Clock pclk).

RSRVD1
26.4.8 ENET MAC MIB Control/Status Register (HW_ENET_MAC_MIBC)

Address: HW_ENET_MAC_MIBC – 800F_0000h base + 64h offset = 800F_0064h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIB_CLEAR
R RSRVD0[28:16]
MIB_ MIB_
DIS IDLE
W
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSRVD0[15:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

HW_ENET_MAC_MIBC field descriptions

Field Description
31 A read/write control bit. If set, the MIB logic halts and does not update any MIB counters.
MIB_DIS
30 A read-only status bit. If set the MIB block is not currently updating any MIB counters.
MIB_IDLE
29 A read/write control bit. If set all statistics counters are reset to 0.
MIB_CLEAR
RSRVD0
26.4.9 ENET MAC Receive Control Register (HW_ENET_MAC_RCR)

Address: HW_ENET_MAC_RCR – 800F_0000h base + 84h offset = 800F_0084h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NO_LGTH_CHECK
GRS MAX_FL
Reset 0 0 0 0 0 1 0 1 1 1 1 0 1 1 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD0
RSRVD0
RSRVD0
RSRVD0
CNTL_FRM_ENA
PAUSE_FWD
R
RMII_MODE
MII_MODE
RMII_10T
PROM
LOOP
CRC_ PAD_ BC_
FCE DRT
FWD EN REJ
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
HW_ENET_MAC_RCR field descriptions

Field Description
31 Graceful receive stopped. Read-only status indicating that the MAC receive datapath is stopped
GRS
30 Payload Length Check Disable. When set to 1, the controller checks the frame's payload length with the
NO_LGTH_ Frame Length/Type field. When set to 0 (Reset value) the payload length check is disabled
CHECK
29–16 Maximum frame length. Resets to decimal 1518. Length is measured starting at DA and includes the CRC
MAX_FL at the end of the frame. Transmit frames longer than MAX_FL causes the BABT interrupt to occur. Receive
frames longer than MAX_FL causes the BABR interrupt to occur and sets the LG bit in the end of frame
receive buffer descriptor. Set to 1518 (Decimal) after reset.

HW_ENET_MAC_RCR field descriptions (continued)

Field Description
15 MAC Control Frame Enable. When set to 1, MAC Control frames with any Opcode other than 0x01 (Pause
CNTL_FRM_ENA Frame) are silently discarded. When set to 0 (Reset value), MAC Control frames with any Opcode other
than 0x01 are accepted and forwarded to the Client interface.
14 Terminate / Forward Received CRC. If cleared (Reset value 0) the CRC field of received frames is transmitted
CRC_FWD to the user application. If set to 1 the CRC field is stripped from the frame.
Note: If padding function is enabled (Bit PAD_EN set to 1), CRC_FWD is ignored and the CRC field is
checked and always terminated and removed.
13 Terminate / Forward Pause Frames. If enabled (Set to 1) pause frames are forwarded to the user application.
PAUSE_FWD In normal mode (Set to reset value 0) pause frames are terminated and discarded in the MAC.
12 Enable / Disable Frame Padding Remove on receive. If enabled (Set to 1) padding is removed from received
PAD_EN frames. If disabled (set to reset value 0) no padding is removed on receive by the MAC.

RSRVD0
RSRVD0
9 RMII 10-Base T. Enables 10Mbps mode of the RMII. When set to 1, the controller signal set_10 is set to 1,
RMII_10T when set to 0 set_10 is set to 0.
8 RMII Mode Enable. Indicates, when ECR(ETH_SPEED) is set to 0, if the MAC is in RMII or MII.
RMII_MODE
0 MAC configured for MII mode.
1 MAC configured for RMII operation.
When set to 1, the controller signal ena_rmii is set to 1, when set to 0, ena_rmii is set to 0.

RSRVD0
RSRVD0
5 Flow control enable. If asserted, the receiver detects PAUSE frames. Upon PAUSE frame detection, the
FCE transmitter will stop transmitting data frames for a given duration.
4 Broadcast frame reject. If asserted, frames with DA (destination address) equals 0xFFFFFFFFFFFF are
BC_REJ rejected unless the PROM bit is set. If both BC_REJ and PROM equals 1, frames with broadcast DA are
accepted and the M (MISS) is set in the receive buffer descriptor.
3 Promiscuous mode. All frames are accepted regardless of address matching.

PROM
2 Media independent interface mode. Should always be set to 1, setting MII_MODE to 0 has no effect.
MII_MODE
1 Disable receive on transmit.
DRT
0 Receive path operates independently of transmit (use for full duplex or to monitor transmit activity in half
duplex mode).
1 Disable reception of frames while transmitting (normally used for half duplex mode).

HW_ENET_MAC_RCR field descriptions (continued)

Field Description
0 Internal loopback. If set, transmitted frames are looped back internal to the device and transmit MII output
LOOP signals are not asserted. When asserted the controller signal ena_loop is set to 1.
26.4.10 ENET MAC Transmit Control Register (HW_ENET_MAC_TCR)

Address: HW_ENET_MAC_TCR – 800F_0000h base + C4h offset = 800F_00C4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSRVD0[31:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD0
TX_ADDR_INS
RSRVD0[15:10]
RFC_PAUSE
R
TFC_PAUSE
TX_
FEDN
CRC_ TX_ADDR_SEL GTS
FWD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_ENET_MAC_TCR field descriptions

Field Description
RSRVD0
9 Forward frame from application with CRC. When set (1) the transmitter will not append any CRC to transmitted
TX_CRC_FWD frames as it is expecting a frame with crc from the application.
When cleared (0, default) the toplevel input pin ff_tx_crc_fwd controls if the frame has a crc from the
application (1) or not (0) (i.e. the register bit is OR'ed with ff_tx_crc_fwd input).
8 Set MAC address on transmit. If enabled (Set to 1) the MAC overwrites the source MAC address with the
TX_ADDR_INS programmed MAC address according to TX_ADDR_SEL. If disabled (Set to reset value 0), the source MAC
address is not modified by the MAC.
7–5 Source MAC address select on transmit. If register TX_ADDR_INS is set to 1 the MAC address that is used
TX_ADDR_SEL to overwrite the source MAC address:
000: Node MAC Address programmed on PADDR1/2 registers is used as the source address.
100: Supplemental MAC Address 0 programmed on SMAC_0_0 and SMAC_0_1 registers is used as the
source address.

HW_ENET_MAC_TCR field descriptions (continued)

Field Description
source address.
source address.
other (any value other than above): Supplemental MAC Address 3 programmed on SMAC_3_0 and
SMAC_3_1 registers is used as the source address.
4 Receive frame control pause. This read-only status bit is asserted when a full duplex flow control pause
RFC_PAUSE frame is received and the transmitter pauses for the duration defined in this pause frame.This bit automatically
clears when the pause duration is complete.
3 Transmit frame control pause. Transmits a PAUSE frame when asserted. When this bit is set, the MAC
TFC_PAUSE stops transmission of data frames after the current transmission is complete. At this time, GRA interrupt in
the EIR register is asserted. With transmission of data frames stopped, MAC transmits a MAC Control
PAUSE frame. Next, the MAC clears the TFC_PAUSE bit and resumes transmitting data frames. If the
transmitter pauses due to user assertion of GTS or reception of a PAUSE frame, the MAC may continue
transmitting a MAC Control PAUSE frame.
2 Full duplex enable. If set, frames transmit independent of carrier sense and collision inputs. This bit should
FEDN only be modified when ETHER_EN is cleared.

RSRVD0
0 Graceful transmit stop. When this bit is set, MAC stops transmission after any frame currently transmitted
GTS is complete and GRA interrupt in the EIR register is asserted. If frame transmission is not currently underway,
the GRA interrupt will be asserted immediately. Once transmission has completed, a restart can accomplish
by clearing the GTS bit. The next frame in the transmit FIFO is then transmitted. If an early collision occurs
during transmission when GTS equals 1, transmission stops after the collision. The frame is transmitted
again once GTS is cleared. There may be old frames in the transmit FIFO that transmit when GTS is
reasserted. To avoid this, clear the ECR register bit ETHER_EN following the GRA interrupt.
26.4.11 ENET MAC Physical Address Lower Register

(HW_ENET_MAC_PALR)
Address: HW_ENET_MAC_PALR – 800F_0000h base + E4h offset = 800F_00E4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PADDR1
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
set
HW_ENET_MAC_PALR field descriptions

Field Description
31–0 Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the 6-byte individual address are used
PADDR1 for exact match and the source address field in PAUSE frames.

26.4.12 ENET MAC Physical Address Upper Register

(HW_ENET_MAC_PAUR)
Address: HW_ENET_MAC_PAUR – 800F_0000h base + E8h offset = 800F_00E8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PADDR2 TYPE
W
Re- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0
set
HW_ENET_MAC_PAUR field descriptions

Field Description
31–16 Bytes 4 (bits 31

MCIMX28RM

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

MCIMX28RM

Uploaded by

Copyright:

Available Formats

i.

MX28 Applications Processor

Document Number: MCIMX28RM

1.2 Hardware Features..........................................................................................................................................................87

1.3 i.MX28 Product Features................................................................................................................................................92

1.3.1 ARM9 CPU Subsystem...............................................................................................................................94

1.3.2 System Buses...............................................................................................................................................94

1.3.2.1 AXI Bus Segments....................................................................................................................95

1.3.2.2 AHB Buses................................................................................................................................96

1.3.2.3 APB Buses................................................................................................................................97

1.3.3 On-Chip RAM and ROM............................................................................................................................97

1.3.4 On-Chip One-Time-Programmable (OCOTP) ROM..................................................................................98

1.3.5 External Memory Controller (EMI)............................................................................................................99

1.3.6 Interrupt Collector.....................................................................................................................................100

1.3.7 Default First-Level Page Table..................................................................................................................100

1.3.8 DMA Controller........................................................................................................................................100

1.3.9 Clock Generation Subsystem....................................................................................................................101

1.3.10 Power Management Unit...........................................................................................................................102

1.3.11 Ethernet Interfaces.....................................................................................................................................103

1.3.12 CAN Interfaces..........................................................................................................................................103

1.3.13 USB Interfaces...........................................................................................................................................103

1.3.14 General-Purpose Media Interface (GPMI)................................................................................................104

1.3.15 Hardware Acceleration for ECC for Robust External Storage..................................................................104

1.3.15.1 Bose Ray-Choudhury Hocquenghem ECC Engine................................................................105

1.3.16 Data Co-Processor (DCP)—Memory Copy, Crypto.................................................................................105

1.3.17 I2C Interface..............................................................................................................................................106

1.3.18 General-Purpose Input/Output (GPIO)......................................................................................................106

i.MX28 Applications Processor Reference Manual, Rev. 1, 2010

1.3.19 Display and Capture Processing................................................................................................................106

1.3.19.1 Display Controllers / LCD Interfaces (LCDIF)......................................................................107

1.3.19.2 Pixel Processing Pipeline (PXP).............................................................................................108

1.3.20 SPDIF Transmitter.....................................................................................................................................109

1.3.21 Dual Serial Audio Interfaces......................................................................................................................109

1.3.22 Rotary Decoder..........................................................................................................................................109

1.3.24 Low-Resolution ADC, Touch-Screen Interface and Temperature Sensor.................................................110

1.3.25 High Speed ADC (HSADC) Controller....................................................................................................111

1.3.26 Pulse Width Modulator (PWM) Controller...............................................................................................111

2.2 ARM 926 Processor Core.............................................................................................................................................113

2.3 JTAG Debugger............................................................................................................................................................116

2.4 Embedded Trace Macrocell (ETM) Interface...............................................................................................................116

3.2.1 Top-Level Symbol and Functional Overview............................................................................................120

3.2.2 Memory Map.............................................................................................................................................120

i.MX28 Applications Processor Reference Manual, Rev. 1, 2010

5.2.1 Nesting of Multi-Level IRQ Interrupts......................................................................................................132

5.2.2 FIQ Generation..........................................................................................................................................134

5.2.3 Interrupt Sources.......................................................................................................................................134

5.2.4 CPU Wait-for-Interrupt Mode...................................................................................................................139

5.3 Behavior During Reset..................................................................................................................................................141

5.4 Programmable Registers...............................................................................................................................................141

5.4.1 Interrupt Collector Interrupt Vector Address Register (HW_ICOLLVECTOR).......................................148

5.4.2 Interrupt Collector Level Acknowledge Register (HW_ICOLLLEVELACK).........................................149

5.4.3 Interrupt Collector Control Register (HW_ICOLLCTRL).......................................................................150

5.4.4 Interrupt Collector Interrupt Vector Base Address Register (HW_ICOLLVBASE).................................152

5.4.5 Interrupt Collector Status Register (HW_ICOLLSTAT)...........................................................................153

5.4.6 Interrupt Collector Raw Interrupt Input Register 0 (HW_ICOLLRAW0)................................................154

5.4.7 Interrupt Collector Raw Interrupt Input Register 1 (HW_ICOLLRAW1)................................................154

5.4.8 Interrupt Collector Raw Interrupt Input Register 2 (HW_ICOLLRAW2)................................................155

5.4.9 Interrupt Collector Raw Interrupt Input Register 3 (HW_ICOLLRAW3)................................................156

5.4.10 Interrupt Collector Interrupt Register 0 (HW_ICOLLINTERRUPT0).....................................................157

5.4.11 Interrupt Collector Interrupt Register 1 (HW_ICOLLINTERRUPT1).....................................................158

5.4.12 Interrupt Collector Interrupt Register 2 (HW_ICOLLINTERRUPT2).....................................................159

5.4.13 Interrupt Collector Interrupt Register 3 (HW_ICOLLINTERRUPT3).....................................................160

5.4.14 Interrupt Collector Interrupt Register 4 (HW_ICOLLINTERRUPT4).....................................................162

5.4.15 Interrupt Collector Interrupt Register 5 (HW_ICOLLINTERRUPT5).....................................................163