Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

Use the SDK to cure the FLASH code

------ Based on ZYNQ MINI development board

Writers: Teacher Yang, Teacher Wu

Date of writing final draft: 2022.10.12

1
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

Table of contents

1. Document Implementation Function Introduction................................... ................................................... ..................................3

2. ZYNQ project establishment............ ................................................... ................................................... .............. 3 3.

Preparatory work before curing - calling of ZYNQ processor.................. ................................................... ...................................3

4. Create a new FSBL SDK project and FPGA solidification............ ................................................... ................................

18 5. Possible problems and solutions.......... ................................................... ................................................ 28

2
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

1. Document Implementation Function Introduction

This document realizes that the bit stream generated by the design is solidified into the FLASH of the FPGA startup configuration. After curing, the bit file can be automatically configured after power-on

, will not be lost when power off. This document is aimed at projects with only FPGA code. If it involves ARM software code downloading, the following tutorials will

There are special chapters for supplementary study. For SD card booting, the method is similar. The following tutorials will explain in detail separately. For how to create a new project, please refer to

Document "Development Software Installation and Introduction/Introduction to VIVADO and Tutorial for New ZYNQ Project under the Software".

2. ZYNQ project establishment

Start page (or file->Project->New) Create a new project (CreateNewProject)

Wizard start page Click Next->

ProjectName (project name) Project name: fpga_03_fpga_flash_dowload

Project path: (choose by yourself, try not to have a Chinese path)

Check CreateProjectSubdirectory, click Next->

AddSource (add design source file) Click Next->

AddExsixtingIP (add existing IP) Click Next->

AddConstraints (add existing constraint files) Click Next->

DefaultPart (default configuration, chip selection) Family->Zynq-7000

Package->clg400

Speed->7010 selection-1,7020

selection-2 7010 version selection target device:

xc7z010clg400-1 7020 version selection target device: xc7z020clg400-2

Click Next->

NewProjectSummary (new project overview) Confirm project information, type selection, etc., click Finish to complete

3. Preparatory work before curing - ZYNQ processor call

We know that there is an ARM processor inside the zynq chip. When the power is turned on, ARM runs a piece of startup code

to assist in configuring the FPGA, and if there is software code, it can run the software code at the same time after the configuration is

completed. Therefore, we need to use the ARM processor module in the ZYNQ chip. On the ZYNQ chip, there is a processor module

called ZYNQ7 Prosessing System module. This module is the processor core of ZYNQ. Like the modules of DSP, gate circuit, and

adder, this hardware can be directly called through IP. Through this hardware call, we can use this processor conveniently, and then

use the XILINX software development environment (SDK) to create a new processor software boot code to complete the FPGA

configuration of ZYNQ. The boot code can be realized by creating a new project template. No need to write code yourself. Finally,

package and burn the executable file and BIT file after the boot code is compiled to FLASH to complete the functions we need.

First, we create a new bd file in the newly completed fpga_03_fpga_flash_dowload project. We click Create Block Design under

IP INTEGRATOR in the project management bar to create a bd file. The Bd file can be used to chart and schematic diagram the FPGA

3
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

Development is more intuitive and convenient.

The default bd file name remains unchanged. Click OK:

After the creation, we can see our newly created bd file in the sources.

By default, the Diagram window will appear after creating a new one. If it doesn't appear, double-click the bd file to open it. We click

on the + sign in the opened Diagram:

4
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

After clicking +, in the pop-up IP core option, we enter ZYNQ in Serach to see what we need to use

ZYNQ System-on-Chip:

Then we double-click it to add it to the bd file.

5
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

Then we double-click the ZYNQ module to open the IP configuration. As you can see from the configuration interface, this IP is very

complicated, and there are many things that need to be set. Here we do not explain the configuration function in detail. We only need to configure

it as a minimum processor system, and set the FLASH pin storage of the chip, and turn off other unnecessary ones. We will explain the

configuration and use of this ZYNQ IP core in more detail later .

6
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

First of all, in the general of PS-PL configuration, pull down to find enable clock resets, expand it, and set the first

Check it out, and check off the M AXI GP0 interface of the GP Master AXI Interface under AXI Non Secure

Enablement:

7
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

Then, in peripheral I/O Pins, select Quad SPI Flash and check the first item:

MIO Configuration, expand Memory interfaces->Quad SPI Flash->Signle SS 4-bit IO, set

8
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

Change speed to fast:

Then, Clock Configuration check off FCLK_CLK0 under PL Fabric Clocks:

Finally, we configure the DDR3 memory controller, the model we choose MT41J256M16 HA-125, the bit width is 16 bits,

Be sure to check that the bit width is 16! If it is 32 and cannot run, our physical DDR3 is 16 bits:

9
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

Finally, we click OK to exit the IP configuration. We can see that the ZYNQ interface in Diagram is much less, only DDR and FIXED_IO are left. Then,

we click on the blue font Run Block Automation on the top of the Diagram file basket on the way:

The dialog box that pops up clicks OK by default:

10
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

Finally, the IP in the generated module diagram becomes the state of leading out DDR and FIXED_IO.

11
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

We click the maximize in the middle of the upper right corner of the Diagram to maximize the icon window (there is a mark in the upper right corner of the above picture

Note), and then click the symbol with a tick in the small box of the symbol tool above the chart document to check the chart:

Finally, the check result dialog box pops up, indicating that the design is correct, and we click OK to close:

Then, we find the file management bar. Click Sources at the top left of the Diagram icon:

12
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

Then right-click Generate Output Products on the bd file to generate output related files. The output file includes

A hardware description language generated by Zynq's IP.

The Generate IP Output File dialog box pops up. By default, click generate and wait for the generation to complete:

13
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

Let's go back to the file manager again, right click on the bd file, click Create HDL Wrapper, and generate the top-level interface

The HDL file of the mouth, this file is our top-level module HDL file.

After clicking, the pop-up dialog box defaults, click OK:

14
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

Since the ZYNQ processor call is to directly call the module, we also need the HDL top-level file automatically generated in the project

Instantiate our FPGA code. We add breath_led.v in the fpga_02_breath_led routine to the project. We add our breath_led.v file by right-

clicking Add Sources on Design Sources in the Sources column. When adding, you can choose to copy to the project:

Finally click Finish to complete the addition. We can see that the source file of the file navigation bar is as shown in the figure:

Let's instantiate the modules in breath_led.v to design_1_wrapper. First, the top-level signal interface adds three signals of

breath_led, clk, rstn, led, and then adds the type declaration of the signal. Finally, add an instantiation of the breath_led module at the

end of the module:

15
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

After the completion of the module physics and chemistry, it needs to be synthesized first! Remember to synthesize first, remember to synthesize first! ! Otherwise, no new pin binding can be found

Added interface signal! ! Please be careful! ! Say important things three times! !

After the first pass of synthesis, the pins need to be bound. Binding pins is in the Open elaborate design under RTL ANALYSIS in the

project management bar. After entering, switch the view to I/O planning. For detailed operations of binding pin constraints, please refer to the led

running water light tutorial developed by 01_fpga. The pins are also consistent, and the level standards are all LVCMOS3.3. We only need to restrict

the external interface of the breath_led.v signal that is instantiated, and we don't care about the other signals and the interface of zynq.

16
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

Save the pin assignment file:

Synthesis, place and route, generate bit files, and wait for completion. Click Cancel when finished:

17
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

After completion, we export the hardware description file.

In the dialog box that pops up, check Include bit files.

4. New FSBL SDK project and FPGA curing

In the previous section we derived a hardware description. This derived hardware description describes the relevant configuration of a processor

document. Then, we started to use the exported hardware for the next step. Let's go back to the main interface of the software, click File->Launch SDK on the top

toolbar to start VIVADO's SDK development software. After startup, the SDK will automatically import the customized

18
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

The processor hardware description engineering code. We don't care about it and wait for the SDK to start and import to complete.

After clicking Start SDK, the pop-up dialog box clicks OK by default:

The SDK startup interface pops up:

19
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

After startup, we can see a code project describing the hardware. We don't need to make any changes to this project. The

hardware description file is in the left directory, system.hdf.

We create a new startup boot project in the SDK: File->New->Application on the toolbar at the top of the SDK

Projectÿ

In the pop-up interface, we fill in the project name as fsbl, and then leave the rest unchanged by default, and click NEXT:

20
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

Next, we select the Zynq FSBL project template, and finally click Finish to complete.

Finally, we can see that there are three projects in the project directory on the left side of the SDK, which are the hardware description project and the fsbl startup guide

Code project, and fsbl board support package project.

21
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

At this point, we are ready to make the FPGA startup configuration file and solidify it to FLASH.

We click XILINX->Create Boot Image in the toolbar above the SDK, and we start to make the ZYNQ boot image

Dynamic BIN file (the prepared BIN file contains the BIT file that our FPGA needs to solidify)

Then, on the pop-up interface, we configure the Output BIF file path to output the path of the generated bif file as shown in the figure. We

click Browse, and save it to the debug path of the project by default:

22
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

After saving the path, the Output path is also under this path by default. Output path is the output

FPGA startup configuration BIN file path.

Next, we add the files. First, we add the executable file generated by the fsbl startup boot code, that is, the arm executable file

automatically generated by the newly created FSBL project of our SDK.

23
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

Click browse in the pop-up dialog box to select and note that the Partition type defaults to bootloader:

24
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

Select the fsbl.elf file and click to open:

Then back to the situation we have added the fsbl file path. Click OK:

Then add our bit file in the same way. The path is in this project:

fpga_flash_dowload_project\fpga_flash_dowload_project.runs\impl_1

25
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

Confirm that the file type is datafile. Then click OK.

In general, to make a bootable BIN file, add the fsbl.elf file (bootloader) first, and then add the bit file (datafile). If there is a software arm code app

application, then add an app.elf (datafile). This project only has FLASH solidification developed by FPGA, and there is no application program, so only these

two files are needed. You can see that there are two files in the list and click Create Image:

At this point, the BIN file for starting the FPGA for curing is ready. We set up the DIP switches next. development board

There are three BOOT modes that can be set, corresponding to the following:

26
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

There is a BOOT setting table on the back of the development board, which provides two references of SD and QSPI. In fact, there are NAND memory

settings, but our board does not have NAND, so we will not write it out, and the JTAG mode is not commonly used. For more detailed dial settings, please refer to

the PS part of the schematic diagram.

We start to solidify. Set the DIP switches to 00, that is, JTAG mode. Attention, set in power-off state!

After setting the BOOT dial switch system, connect the computer and power on. Plug the USB cable of the DEBUG interface to the computer on the development board,

and wait for about ten seconds, because it takes a while to recognize the download cable connected to the computer. Back to the SDK, we click on the toolbar, click

XILINX->Program Flash programming.

The Image file is the BIN file we just generated, and the FSBL is the FSBL.elf we just selected. Then wait for the FLASH operation to complete.

27
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

Note, after the programming is completed, be sure to power off and reset the BOOT DIP switch, which is the following mode:

Then we power cycle the development board. You can also press the reset button if operating with power on. Sometimes JTAG is connected to computer VIVADO

software or SDK software, which may cause startup failure. Everyone unplug the data cable of the DEBUG port, switch to the other two USB ports for power supply, and then

it can be reset and started normally.

In addition, the sdk programming is very slow, and it is not easy to use. You can refer to "ZYNQ Several Debugging Skills Extended Tutorial" to learn

Learn to use VIVADO for programming.

5. Possible problems and solutions

1. Burning cannot succeed. Solution: Check the DIP switch, set all to 00, that is, ON state; then turn off the power and turn on the switch again to

connect to the computer. Still can’t be programmed, check the configuration of ZYNQ’s PS, the key part is the QSPI pin configuration, as well as the model and

bit width of DDR3, which must be consistent with the tutorial.

2. Unable to run after programming: Please check whether it is set to QSPI after programming and then power off and restart.

3. The programming progress bar stops moving. In this case, if no programming error message is output, it is normal. because

28
Machine Translated by Google

Little Panda Academy ZYNQ Teaching Documents

The FLASH erase may take several minutes. Nothing to do with downloader speed. please wait patiently.

4. Programming can also be started using TF. Set the SD0 interface of the ZYNQ processor, make a BIN file, and finally

Copy directly to the memory card formatted as FAT32, set the BOOT dial to 11 (TF card boot mode). A 16G high-quality card is recommended.

Do not use low-quality or counterfeit cards, otherwise it will fail to start.

29