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Test Vector
Test Vector
mr 0 0 0 1 1 1 1
mw 0 0 0 0 0 0 0
busy 0 0 0 1 1 0 1
req 0 0 0 1 1 1 1
store
I/O signal Expected Values . .2 .3 .4 .5 .6
I #clk 1 2 3 4 5 6 7
I reset 0 1 0 0 0 0 0
I step_en 0 0 1 0 0 0 0
I opcode 0 0 0 0 0 0 0
I ACK_N 1 1 1 1 1 0 1
O IN_INIT 1 1 1 0 0 0 0
O as_n 0 0 0 0 1 1 0
O wr_n 0 0 0 0 0 0 0
O MAC_state 0 0 0 0 1 1 2
O ir_ce 0 0 0 0 0 0 1
O gpr_we 0 0 0 0 0 0 0
O select_pc 0 0 0 1 1 1 1
O load 0 0 0 0 0 0 0
O decode 0 0 0 0 0 0 0
O dlx_state 0 0 0 1 1 1 1
mr 0 0 0 1 1 1 1
mw 0 0 0 0 0 0 0
busy 0 0 0 1 1 0 1
req 0 0 0 1 1 1 1
hold
I/O signal Expected Values . .2 .3 .4 .5 .6
I #clk 1 2 3 4 5 6 7
I reset 0 1 0 0 0 0 0
I step_en 0 0 1 0 0 0 0
I opcode 0 0 0 0 0 0 0
I ACK_N 1 1 1 1 1 0 1
O IN_INIT 1 1 1 0 0 0 0
O as_n 0 0 0 0 1 1 0
O wr_n 0 0 0 0 0 0 0
O MAC_state 0 0 0 0 1 1 2
O ir_ce 0 0 0 0 0 0 1
O gpr_we 0 0 0 0 0 0 0
O select_pc 0 0 0 1 1 1 1
O load 0 0 0 0 0 0 0
O decode 0 0 0 0 0 0 0
O dlx_state 0 0 0 1 1 1 1
mr 0 0 0 1 1 1 1
mw 0 0 0 0 0 0 0
busy 0 0 0 1 1 0 1
req 0 0 0 1 1 1 1
.7 .8 .9 .10 .11 .12 .13
8 9 10 11 12 13 14
0 0 0 0 0 0 0
0 0 0 0 0 0 0
100011 100011 100011 100011 100011 100011 100011
1 1 1 0 1 1 1
0 0 0 0 0 0 1
0 0 1 1 0 0 0
0 0 0 0 0 0 0
0 0 1 1 2 0 0
0 0 0 0 0 0 0
0 0 0 0 0 1 0
0 0 0 0 0 0 0
0 0 0 0 1 0 0
1 0 0 0 0 0 0
2 5 5 5 5 6 0
0 1 1 1 1 0 0
0 0 0 0 0 0 0
0 1 1 0 1 0 0
0 1 1 1 1 0 0
0 0 0 0 0 0
0 1 1 1 1 0
0 1 1 0 1 0
0 1 1 1 1 0
.7 .8 .9 .10
8 9 10 11
0 0 0 1
0 0 0 0
0 0 0 0
1 1 1 1
0 1 1 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
1 0 0 0
2 3 3 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0