EE8351

DIGITAL LOGIC CIRCUITS

S.S.Harish
Department of EEE
UNIT III SYNCHRONOUS SEQUENTIAL CIRCUITS
Objective
To design various synchronous circuits

• Sequential logic
• SR, JK, D and T flip flops
• level triggering and edge triggering
• counters - asynchronous and synchronous type - Modulo counters
• Shift registers
• Design of synchronous sequential circuits
• Moore and Melay models- Counters
• state diagram
• state reduction
• state assignment
 SEQUENTIAL Logic
• Sequential- order
• Memory required

• State- condition of element

• Output depends on input and present state
• Next state depends on input and present state
• Input, present state , next state, output
• Synchronous- at discrete time instants- or same clock to all
• Asynchronous – order in which input changes
 SEQUENTIAL Logic
• Binary Storage (Memory) element- flip-flops
• One flip-flop to Store one bit
• ‘N’ flip-flops to store ‘N’ bits
Latch Flip-flop
Signal level Transition of clock pulse
Level sensitive Edge sensitive
• Types of flip-flop 2 latches controlled by clock
• Set-Reset (SR) flip flop
• J-K Flip-flop
• Delay (D) flip-flop
• Toggle (T) flip-flop
 SR Latch

S R Q Q’ Comment
0 0 Hold
0 1 0 1 Reset
1 0 1 0 Set
1 1 0 0 Forbidden

SR latch using cross coupled NOR

 SR Latch
State Table State transition diagram
S R Present Next
Truth Table state state
0 0 0 0
S R Q Q’ Comment
1 1 1 1
0 0 Hold
0 1 0 0
0 1 0 1 Reset
0 1 1 0
1 0 1 0 Set
1 0 0 1
1 1 0 0 Forbidden
1 0 1 1
1 1 0 X
1 1 1 x

Qn+1=S+R’Qn
SR latch using cross coupled NOR
 SR Latch
Only on condition SR latch to work
SR with Enable

Truth Table

S R Q Q’ Comment
0 0 1 1 Not used
0 1 0 1 Reset
1 0 1 0 Set
1 1 Hold

SR latch using cross coupled NANDS’R’ Latch

 D Latch

State transition diagram

State Table
Truth Table
D Present Next
state state
D Q Q’
0 0 0
0 0 1
0 1 0
1 1 0
1 0 1
1
1 1 1
 SR flip-flop
• Clock as Enable to SR latch
 SR flip-flop

• Master -slave
D flip-flop
 JK flip-flop
• SR flip – 1 invalid condition
• To overcome feedback used- JK flip-flop
JK flip-flop
T flip-flop
 Flip flop Conversion
SR flip flop to JK flipflop

Q JK Q JK
00 01 11 10 00 01 11 10
0 1 1
S=J.Qn’ 0 x x
R=K.Qn
1 x x
1 1 1
 Flip flop Conversion
JK flip-flop to SR flip-flop

Q SR Q SR
00 01 11 10 00 01 11 10

1 0 x x
0 J=S.R’ K=R.Qn’
1 1 1
1 x x
 Flip flop Conversion
JK flip flop to T flipflop

J=K=T
 Flip flop Conversion
D flip flop to T flipflop

D=QnT’+Qn’T
 Flip flop Conversion
SR flip flop to T flipflop

S=TQn’
R=TQn
 Flip flop Conversion
JK flip flop to D flipflop

J=D
K=D’
 Flip flop Conversion
T flip flop to JK flipflop

Q JK T=JQn’+KQn
00 01 11 10

0 1 1

1 1 1
 Counters
• Sequential circuit to count
• Flip-flops in cascade
• Counter based on clock, number of stages, sequential states
• Application of clock: Synchronous counter, Asynchronous counter
• Number of stages: 2 bit, 3 bit, …..
• Sequential states: Up counter, Down counter
 Counters
Synchronous-UP- 3 bit Using T flip flop
Present state Next state Excitation table
Cn B n A n Cn+1 Bn+1 An+1 TC TB TA
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1 TA=1
1 0 1 1 1 0 0 1 1 TB=A
1 1 0 1 1 1 0 0 1
TC=A.B
1 1 1 0 0 0 1 1 1
K-map for TC
K-map for TA K-map for TB
C BA
C BA C BA 00 01 11 10
00 01 11 10 00 01 11 10
0 0 0 1 0
0 1 1 1 1 0 0 1 1 0
1 0 0 1 0
1 1 1 1 1 1 0 1 1 0
 Counters
Synchronous-UP- 3 bit
C B A

1 TA=1
TB=A
C B A TC=A.B

Clk

3 Bit synchronous UP counter using T Flip-flop

 Counters
Synchronous-UP- 3 bit Using D flip flop
Present state Next state Excitation table
Cn B n A n Cn+1 Bn+1 An+1 DC DB DA DA=A’
0 0 0 0 0 1 0 0 1 DB=A.B’+A’.B=A (+)B
0 0 1 0 1 0 0 1 0 DC=A.B.C’+B’.C+A’.C
0 1 0 0 1 1 0 1 1 =A.B.C’+C.(A’+B’)
0 1 1 1 0 0 1 0 0 =(A.B).C’+C.(A.B)’
1 0 0 1 0 1 1 0 1 = (A.B) exor C
1 0 1 1 1 0 1 1 0
1 1 0 1 1 1 1 1 1
1 1 1 0 0 0 0 0 0
K-map for DC
K-map for DA K-map for DB
C BA
C BA C BA 00 01 11 10
00 01 11 10 00 01 11 10
0 0 0 1 0
0 1 0 0 1 0 0 1 0 1
1 1 1 0 1
1 1 0 0 1 1 0 1 0 1
 Counters
Synchronous-UP- 3 bit
C B A
Ex-OR Ex-OR

D
D D

C B A

Clk

3 Bit synchronous UP counter using D Flip-flop

 Counters
Synchronous-UP- 3 bit
• Modulo-n counters
• At n resets and starts from 0
• 3 bit modulo -8 counter or mod-8 counter
 Counters
Synchronous-UP- 3 bit Using T flip flop
Mod-5
Present state Next state Excitation table
Cn B n A n Cn+1 Bn+1 An+1 TC TB TA
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1 TA=C’
0 1 1 1 0 0 1 1 1 TB=A
1 0 0 0 0 0 1 0 0 TC=A.B
K-map for TC
K-map for TA K-map for TB
C BA
C BA C BA 00 01 11 10
00 01 11 10 00 01 11 10
0 0 0 1 0
0 1 1 1 1 0 0 1 1 0
1 0 x x x
1 0 x x x 1 0 x x x
 Counters
Synchronous-UP- 3 bit
C B A

C B A

Clk

Mod-5 synchronous counter using T Flip-flop

 Counters
Synchronous-UP- 4 bit Mod-10 Using T flip flop
Present state Next state Excitation table
Dn Cn Bn An Dn+1 Cn+1 Bn+1 An+1 TD TC TB TA
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 1 0 0 0 1 1
0 0 1 0 0 0 1 1 0 0 0 1
0 0 1 1 0 1 0 0 0 1 1 1
0 1 0 0 0 1 0 1 0 0 0 1
0 1 0 1 0 1 1 0 0 0 1 1
0 1 1 0 0 1 1 1 0 0 0 1
0 1 1 1 1 0 0 0 1 1 1 1
1 0 0 0 1 0 0 1 0 0 0 1
1 0 0 1 0 0 0 0 1 0 0 1
 Counters
Synchronous-DOWN- 3 bit
Excitation table
Using T flip flop
Present state Next state
Cn B n A n Cn+1 Bn+1 An+1 TC TB TA
0 0 0 1 1 1 1 1 1
1 1 1 1 1 0 0 0 1
1 1 0 1 0 1 0 1 1
1 0 1 1 0 0 0 0 1
1 0 0 0 1 1 1 1 1 TA=1
0 1 1 0 1 0 0 0 1 TB=A’
0 1 0 0 0 1 0 1 1 TC=A’.B’
0 0 1 0 0 0 0 0 1
K-map for TC
K-map for TA K-map for TB
C BA
C BA C BA 00 01 11 10
00 01 11 10 00 01 11 10
0 1 0 0 0
0 1 1 1 1 0 1 0 0 1
1 1 0 0 0
1 1 1 1 1 1 1 0 0 1
 Counters
Synchronous-DOWN- 3 bit

C B A

1 TA=1
TB=A’
C B A TC=A’.B’

Clk

3 Bit synchronous UP counter using T Flip-flop

 Counters
Synchronous-UP/DOWN- 3 bit
 Counters
Asynchronous or ripple counter

• 2 bit mod-4 counter

• Down counter: Q’ to clock

 Counters
Asynchronous decade counter
• Counter not as 2^n also possible using logic gates
• Count  0-9 10 so mod-10 counter or decade counter
 Shift register
• shift binary information to neighbouring memory
• Cascade flip-flops output of one flip flop connected as input to next
• Same clock to all
• Left shift- information from right to left
• Right shift- information from left to right
• Bidirectional- left or right can be select
• Serial- one after other
• Parallel- At a time
• Serial-in Serial out (SISO) shift register
• Serial-in Parallel out (SIPO) shift register
• Parallel-in Serial out (PISO) Shift register
• Parallel in parallel out (PIPO) shift register
 Shift register
SIPO
 Shift register
SISO
 Shift register
PIPO
 Shift register
PISO
 Shift register
Universal
• Serial and parallel in can be selected
 Shift register

Ring counter

• Modulo-n counter
• 4 flip-flops- 4 states- mod-4
 Shift register
Twisted Ring counter
Or Johnson counter

• Repeated sequence or pattern

 Sequential circuit model/ Analysis
Mealy Model
• Output depends on present state and input

• Input must be synchronized to avoid momentary transitions during

clock
 Sequential circuit model/ Analysis
• Moore model
• Output depends only on present state

• Input transitions don’t care

 Sequential circuit model/ Analysis
Truth table
Serial Adder Circuit diagram X Y Ci Ci+1 Sum X Y Ci Ci+1 Sum
• 2 bits- at a time input Xi Si
0 0 0 0 0 0 0 0 0 0
0 0 1 0 1
• Carry from memory Yi Full
Adder Ci 0 1 0 0 1
0 1 0 0 1

Ci+1 1 0 0 0 1
• One output 0 1 1 1 0 1 1 0 1 0
• Carry- 2 states- S0, S1 Flip-flop
1 0 0 0 1 0 0 1 0 1
1 0 1 1 0 0 1 1 1 0
1 1 0 1 0 1 0 1 1 0
State table 1 1 1 1 1 1 1 1 1 1
Next state Output(Sum) State diagram
00 01
Input 00 01 10 11 00 01 10 11 0 11
0 Mealy Model
(XY) 01 0
10
S0 S0 S0 S0 S1 0 1 1 0 1 S0 S1 0
10 11
S1 S0 S1 S1 S1 1 0 0 1
1 00 1
1
 Sequential circuit model/ Analysis
State diagram
• Serial Adder Moore Model
Truth table State table 00 01
X Y Ci Sum Ci+1 Ci Sum Ci+1 10
0 0 0 0 0 00 01 10 11 S0 11 S2
0 1
1 1 0 0 1 0 0 S0 S0 S1 S1 S2 0 0

0 1 0 1 0 0 1 S1 S0 S1 S1 S2 01 01
00 11 11
1 0 0 1 0 1 0 S2 S1 S2 S2 S3 10 00 10
0 1 1 0 1 1 1 S3 S1 S2 S2 S3 S1 S3
0 1
1 0 1 0 1 1 00 1

0 0 1 1 0 01

1 1 1 1 1 10 11
 State reduction

• Complex models- more states

• Some states – same effect
• Same next state and output
• Can be eliminated to reduce state and thereby flipflop required
• Equivalent states
State reduction
 State Assignment
• Giving representations for design of circuit.
• Unique coded binary values for the state
• Binary assignment-
• 2^n>m; m states, n – no of bits
• E.g:- 5 states000, 001,010,011,100
• One hot assignment
• variables= states
• 1 flip flop for 1 state
• Only one 1 in assignment “one hot”
• E.g:- 5 states 10000, 01000, 00100, 00010, 00001
 Sequential circuit
Application of sequential circuits
• Sequence detector
• Parallel to serial communication
 Course outcome
• Sequential logic- ordered working
• Latches- hold a bit
• Level triggered and Edge triggered
• Flip-flop- SR, D, JK, T; conversion
• Counters • Analysis model-
• Synchronous
• Asynchronous
• Mealy model
• Modulo • Moore model
• Shift register • State reduction
• SISO • State assignment
• SIPO
• PISO
• PIPO
• Ring counter, Johnson counter