ment ‘Registers & Counters) Design a 4 bit Parallel In Paralle! Out Shift register with two conteol inputs and below given functionality Consider a 4-bit adder with an accumulator, as in below figure, Suppose the Y register (with asynchronous clear input) contains a number from a previous calculation, We do not want Yo) + tt — co a he he © G G i & I i i d (On the below timing diagram, give values for ‘add” and ‘clr”so that we will have Y= 3 « X held in the accumulator. ca fe add!3. Determine the functional behaviour ofthe circuit in the diagram below. Assume that input “ck is driven by a square wave signal 4. ‘The circuit in the figure below is a counter. What is the sequence that this circuit counts iar om 5. Consider the following circuit Initially, all the flip-flop’s outputs X, Y, Z are in the O state, before applying the clock pulses. Sketch the waveforms for W, X, ¥ & Z for eight elk cycles, -——————— ea | a + + > tte s s 6 Design a logic circuit that has 2 inputs, Clock and Start, and 2 ourputs, f and g. when a palse is received on ‘star’ signal, the circuit produces pulse on the outputs as shown in the ‘timing diagram. Design this circuit using only a 3 bit resettable positive edge triggered synchronous counter and basic gates. eS LS Ln ef TLE oo ses7. Convert a MOD 8 counter made with T flipflops with Synchronous Reset input as a MOD 5 counter by using some additional gates and without modifying the existing electrical ‘connections. 8. Design a 3 bit up/down counter using negative edge triggered T-FF, 9. Explain, how can, the counters be used to construct a digital clock using 7 segment displays. 10, Change an n-bit counter (a normal one, which counts in order) to one which counts down rather than up, just by rewiring it, adding no additional circuitry of any kind (no additional gates). 1, An LM flip-flop works as follows: If LM=00 , the next state ofthe fFis 1 If LM=01 , the next state of the fis the same as the present state, If LM= 10 , the next state of the {Tis the complement of the present state. If LM= 11, the next state of the fT 0. Using this LM flipflop, design a counter with the following counting sequence (000,100,101,111,011,001,000, the circuit logic 1, the 12, Design a4-bit right shift register with one mode signal. If mode signal is logi should work like Serial In Parallel Out Shift Register. And if mode signal circuit should work like Parallel In Parallel Out Shift Register. 13, Using 7418164, design a circuit to display “MAVEN” in serial manner in a display board ‘constructed using $ LED's as shown below. The pin diagram and the internal circuitry of | TALS164 is also shown below. v, 2 & Mm mo ea |} 74L8164 waves toatotatatatatad14, Use some combinational blocks and the same 74LS164 deseribed in the previous question, to mimic the behavior of a 5-bit ring counter whose functionality is described with following waveforms. 15. Given a 100 MHz clock signal, derive a circuit using D FFs to generate $0 MHz and 25 MHz clock signals. 16, What will be the count of a6 bit binary counter, whose inital state is 0, after 250 cycles? 17. A 7 bit ring counters initial state output is 0100010. After how many clock cycles, will it return to inital state? 18. Design a counter with T flipflops whose count sequence is 0,2.4,5,3.1,0.., 19. Show how 3bit binary counters, 5 bit Johnson counters and D flip-flops can be used to derive a signal with a frequency of IMHz from an input clock with a frequency of 320MHz, 20, Design a 3bit counter like circuit controlled by the input w. if w=1, then the counter adds 2 to its contents, wrapping around if the count reaches 8 or 9. Thus if present state is 6 or 7 then next state becomes 0 or | respectively. If w = 0, then the counter subtracts 1 from ite contents, acting like a normal down counter. 21, Design a counter using D flip-flops and with the following specifications : & The counting sequence is 0,1,2,...6.7.01,.. & There is an input signal w ; if w = 0, the present count remains the same and if w = 1, the count increments by 1. 22, Design a counter which counts in the following given sequence. Use D flip-flops and AND gates. (000,110,111,100,101,001,000,,