10, Assignment - 6 (Finite State Machines) Design a PSM over (0,1, 2,3 } that will output the largest input digit read so far. eg. input: 001032 will produce output: 001133 ‘Design an FSM that has 1 input and 1 output. The o/p becomes 1 and remains 1 when at Feast two 0'S and two 1’s have occurred as p's. Derive a single input and single output Moore-type FSM that produces an output of | if in the input sequence it detects either 110 oF 101 patterns. Overlapping sequence should be detected, Derive a minimal state table for an FSM that acts as a 3 bit parity generator. For every 3 bits observed on the input ‘w’ during 3 consecutive eyeles, the FSM generates the parity 1-1 if'and only ifthe no. of 1s is odd. {A sequential circuit has 2 inputs w 1 and w2 and an output zits funetion isto compare the input sequences on the 2 inputs. If wl=w2 during any 4 consecutive clock eyes, the circuit produces 2 ~ 1; otherwise 2 ~ 0. Eg. w! : 0110111000110, w2 : 1110101000111, 0000100001110. Derive a suitable eiteuit Design @ FSM over {0, 1} that will output 1 if the first bit and the current bt of the input string are equal, 0 otherwise. e.g. input: 010011 will produce output: 101100 Design a FSM over {0, 1,b} that will output a copy ofthe input string except thatthe first bit will have been moved to the end ofthe string. (“b” represents a blank” here). eg. « input: 1010011 will produce output: 0100111 Design a coin operated vending machine that dispenses candy under the following conditions: The machine accepts Rs.5 and Rs.10 “4 It takes Rs.15 for a candy tobe released from the machine 4 IF Rs.20 is deposited, the machine will not return the change, but it will credit the ‘buyer with Rs.5 and wait for 1 min, forthe buyer to make a 2nd purchase. Draw the state diagram for a FSM, the output toggles whenever it detects *110° LSB first (overlapping). Consider initial value of output as 0. Describe a finite state machine using state diagram that will detect three consecutive coin tosses (of one coin) that results in heads, Design a FSM with input as a bit stream, and op which goes I whenever the number received so far is divisible by 3.A sequential circuit has two inputs and two outputs. The inputs (X1X2) represents a 2 bit binary number, N. Ifthe present value of N is greater than the previous value, then Z1 =1 If the present value of N is less than the previous value, then Z2 ~1. Otherwise Z1, 22 are 0. Draw FSM for the same, - Design FSM for a system which gives output high when bit-1 is in majority in three bit number (overlapping is allowed). Assume input is coming serially. J. How to design a dvide-by- counter with equal duty cycle? Design a sequence generator which generates 1011 continuously. Use'T flip-flops for this design,