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  • IE Lab 13

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    Muzzamil Shah
    8 views4 pages
    This document describes a lab experiment on combinational logic. It outlines 4 tasks: 1) designing a 2x1 multiplexer in Verilog, 2) designing an 8x1 multiplexer in Verilog, 3) designing a 1x8 demultiplexer in Verilog, and 4) designing an 8-bit ROM using Xilinx ISE. For each task, the student provides the code and results.

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    This document describes a lab experiment on combinational logic. It outlines 4 tasks: 1) designing a 2x1 multiplexer in Verilog, 2) designing an 8x1 multiplexer in Verilog, 3) designing a 1x8 demultiplexer in Verilog, and 4) designing an 8-bit ROM using Xilinx ISE. For each task, the student provides the code and results.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as docx, pdf, or txt
    8 views4 pages

    IE Lab 13

    Uploaded by

    Muzzamil Shah
    This document describes a lab experiment on combinational logic. It outlines 4 tasks: 1) designing a 2x1 multiplexer in Verilog, 2) designing an 8x1 multiplexer in Verilog, 3) designing a 1x8 demultiplexer in Verilog, and 4) designing an 8-bit ROM using Xilinx ISE. For each task, the student provides the code and results.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as docx, pdf, or txt
    of 4

    Name:muzzamil shah

    Sec:B Roll no:2020-EE-076

    Lab No. 13
    COMBINATIONAL LOGIC
    OBJECTIVE:
    Combinational Logic Schematic Example and Simulation by using Xilinx ISE simulator.

    Task No.1 : To design 2x1 MUX in verilog by using Xilinx ISE.

    Code:

    Result:

    ELECTRONIC ENGINEERING DEPARTMENT 1


    Name:muzzamil shah
    Sec:B Roll no:2020-EE-076

    Task No.2 : To design 8x1 MUX in verilog by using Xilinx ISE.

    Code:

    Result:

    ELECTRONIC ENGINEERING DEPARTMENT 2


    Name:muzzamil shah
    Sec:B Roll no:2020-EE-076

    Task No.3: To design 1x8 DEMUX in verilog by using Xilinx ISE.

    Code:

    Result:

    ELECTRONIC ENGINEERING DEPARTMENT 3


    Name:muzzamil shah
    Sec:B Roll no:2020-EE-076

    Task No.4 : To design 8 bit ROM (4x2) by using Xilinx ISE.

    Code:

    Result:

    ELECTRONIC ENGINEERING DEPARTMENT 4

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