SUBJECT NAME: INTEGRATED ELECTRONICS NAME: muzzamil shah

ROLL NO: 2020-EE-076

SECTION: B

LAB NO. 4

“Switch Level Modeling”

Objective: Respond the behavior of following circuits by switch level modeling and
simulating them.

TASK: 01 :

Y= ab+c

CIRCUIT DIAGRAM:

TRUTH TABLE:

a b
0 0
0 0
0 1
1 1
c Out
0 1
1 0
0 1
1 0

1
DEPARTMENT OF ELECTRONIC ENGINEERING
SIR SYED UNIVERSITY OF ENGINEERING AND TECHNOLOGY
SUBJECT NAME: INTEGRATED ELECTRONICS NAME: muzzamil shah
ROLL NO: 2020-EE-076
SECTION: B

CODING:
//design module
module gate(y,a,b,c);
input a,b,c;
output y;
wire x,z;
supply1 vdd;
supply0 gnd;
pmos p1(x,vdd,a);
pmos p2(x,vdd,b);
pmos p3(y,x,c);
nmos n1(y,z,a);
nmos n2(z,gnd,b);
nmos n3(y,gnd,c);
endmodule
//stimulus design
module muzzamil;
reg a,b,c;
wire y;
gate g1(y,a,b,c);
initial
begin a=1'b0; b=1'b0; c=1'b0; #20
a=1'b0; b=1'b0; c=1'b1;
#20 a=1'b0; b=1'b1; c=1'b0;
#20 a=1'b0; b=1'b1; c=1'b1;
#20 a=1'b1; b=1'b0; c=1'b0;
#20 a=1'b1; b=1'b0; c=1'b1;
#20 a=1'b1; b=1'b1; c=1'b0;

2
DEPARTMENT OF ELECTRONIC ENGINEERING
SIR SYED UNIVERSITY OF ENGINEERING AND TECHNOLOGY
SUBJECT NAME: INTEGRATED ELECTRONICS NAME: muzzamil shah
ROLL NO: 2020-EE-076
SECTION: B

#20 a=1'b1; b=1'b1; c=1'b1;

#20
$finish;
end
endmodule

RESULT:

TASK: 02

Y= (a+b)c

CIRCUIT DIAGRAM:

3
DEPARTMENT OF ELECTRONIC ENGINEERING
SIR SYED UNIVERSITY OF ENGINEERING AND TECHNOLOGY
SUBJECT NAME: INTEGRATED ELECTRONICS NAME: muzzamil shah
ROLL NO: 2020-EE-076
SECTION: B

TRUTH TABLE:

a b c out
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
CODING:

//design module

module gate(out,a,b,c);

input a,b,c;

output out;

wire x,y;

supply1 vdd;

supply0 gnd;

pmos p1(x,vdd,a);

pmos p2(out,x,b);

pmos p3(out,vdd,c);

nmos n1(out,y,a);

nmos n2(out,y,b);

nmos n3(y,gnd,c);

endmodule

//stimulus design

module muzzamil;
4
DEPARTMENT OF ELECTRONIC ENGINEERING
SIR SYED UNIVERSITY OF ENGINEERING AND TECHNOLOGY
SUBJECT NAME: INTEGRATED ELECTRONICS NAME: muzzamil shah
ROLL NO: 2020-EE-076
SECTION: B

reg a,b,c;

wire out;

gate g1(out,a,b,c);

initial

begin

a=1'b0; b=1'b0; c=1'b0;

#20

a=1'b0; b=1'b0; c=1'b1;

#20

a=1'b0; b=1'b1; c=1'b0;

#20

a=1'b0; b=1'b1; c=1'b1;

#20

a=1'b1; b=1'b0; c=1'b0;

#20

a=1'b1; b=1'b0; c=1'b1;

#20

a=1'b1; b=1'b1; c=1'b0;

#20

a=1'b1; b=1'b1; c=1'b1;

#20

$finish;

end

endmodule

5
DEPARTMENT OF ELECTRONIC ENGINEERING
SIR SYED UNIVERSITY OF ENGINEERING AND TECHNOLOGY
SUBJECT NAME: INTEGRATED ELECTRONICS NAME: muzzamil shah
ROLL NO: 2020-EE-076
SECTION: B

RESULT:

TASK: 03

Y= ab+cd

CIRCUIT DIAGRAM:

6
DEPARTMENT OF ELECTRONIC ENGINEERING
SIR SYED UNIVERSITY OF ENGINEERING AND TECHNOLOGY
SUBJECT NAME: INTEGRATED ELECTRONICS NAME: muzzamil shah
ROLL NO: 2020-EE-076
SECTION: B

TRUTH TABLE:

a b c d y
0 0 0 0 1
0 0 1 1 0
0 1 0 1 1
0 1 1 0 1
1 0 0 1 1
1 0 1 0 1
1 1 0 0 0
1 1 1 1 0

CODING:
//design module
module gate(out,a,b,c,d);
input a,b,c,d;
output out;
wire x,w,z;
supply1 vdd;
supply0 gnd;
pmos p1(x,vdd,a);
pmos p2(x,vdd,b);
pmos p3(out,x,c);
pmos p4(out,x,d);
nmos n1(out,z,a);
nmos n2(z,gnd,b);
nmos n3(out,w,c);
nmos n4(w,gnd,d);
endmodule
//stimulus module
module muzzamil;
7
DEPARTMENT OF ELECTRONIC ENGINEERING
SIR SYED UNIVERSITY OF ENGINEERING AND TECHNOLOGY
SUBJECT NAME: INTEGRATED ELECTRONICS NAME: muzzamil shah
ROLL NO: 2020-EE-076
SECTION: B

reg a,b,c,d;
wire out;
gate g1(out,a,b,c,d);
initial
begin
a=1'b0; b=1'b0; c=1'b0; d=1'b0;
#20
a=1'b0; b=1'b0; c=1'b0; d=1'b1;
#20
a=1'b0; b=1'b0; c=1'b1; d=1'b0;
#20
a=1'b0; b=1'b0; c=1'b1; d=1'b1;
#20
a=1'b0; b=1'b1; c=1'b0; d=1'b0;
#20
a=1'b0; b=1'b1; c=1'b0; d=1'b1;
#20
a=1'b0; b=1'b1; c=1'b1; d=1'b0;
#20
a=1'b0; b=1'b1; c=1'b1; d=1'b1;
#20
a=1'b1; b=1'b0; c=1'b0; d=1'b0;
#20
a=1'b1; b=1'b0; c=1'b0; d=1'b1;
#20
a=1'b1; b=1'b0; c=1'b1; d=1'b0;
#20
a=1'b1; b=1'b0; c=1'b1; d=1'b1;

8
DEPARTMENT OF ELECTRONIC ENGINEERING
SIR SYED UNIVERSITY OF ENGINEERING AND TECHNOLOGY
SUBJECT NAME: INTEGRATED ELECTRONICS NAME: muzzamil shah
ROLL NO: 2020-EE-076
SECTION: B

#20
a=1'b1; b=1'b1; c=1'b0; d=1'b0;
#20
a=1'b1; b=1'b1; c=1'b0; d=1'b1;
#20
a=1'b1; b=1'b1; c=1'b1; d=1'b0;
#20
a=1'b1; b=1'b1; c=1'b1; d=1'b1;
#20
$finish;
end
endmodule

RESULT:

TASK: 04
Y= a̅b+ab̅

CIRCUIT DIAGRAM:

9
DEPARTMENT OF ELECTRONIC ENGINEERING
SIR SYED UNIVERSITY OF ENGINEERING AND TECHNOLOGY
SUBJECT NAME: INTEGRATED ELECTRONICS NAME: muzzamil shah
ROLL NO: 2020-EE-076
SECTION: B

TRUTH TABLE:

a b y
0 0 0
0 1 1
1 0 1
1 1 0

CODING:
//design module
module xor1(y, a, b);
input a,b;
output y;
wire w,x,y,z,r;
supply1 vdd;
supply0 gnd;
not n1(abar,a);
not n2(bbar,b);
pmos p1(w, vdd, abar);
pmos p2(y, w, b);
pmos p3(x,vdd,a);
pmos p4(y,x,bbar);
nmos n1(z,gnd,b);
nmos n2(y,z,a);
nmos n3(r,gnd,bbar);
nmos n4(y,r,abar);
endmodule
//stumulus module
module muzzamil;
reg a, b;

10
DEPARTMENT OF ELECTRONIC ENGINEERING
SIR SYED UNIVERSITY OF ENGINEERING AND TECHNOLOGY
SUBJECT NAME: INTEGRATED ELECTRONICS NAME: muzzamil shah
ROLL NO: 2020-EE-076
SECTION: B

wire y;
xor1 w1(y, a, b);
initial
begin
a=1'b0; b=1'b0;
#20
a=1'b1; b=1'b0;
#20
a=1'b0; b=1'b1;
#20
a=1'b1; b=1'b1;
#20
$finish;
end
endmodule

RESULT:

11
DEPARTMENT OF ELECTRONIC ENGINEERING
SIR SYED UNIVERSITY OF ENGINEERING AND TECHNOLOGY
SUBJECT NAME: INTEGRATED ELECTRONICS NAME: muzzamil shah
ROLL NO: 2020-EE-076
SECTION: B

TASK: 05

1-bit Full adder

CIRCUIT DIAGRAM:

TRUTH TABLE:

a b Cin Cout out

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

CODING:

// design module

module xorgate(out,a,b);

input a,b;

output out;

wire w,x,y,z;

supply1 vdd;

supply0 gnd;

12
DEPARTMENT OF ELECTRONIC ENGINEERING
SIR SYED UNIVERSITY OF ENGINEERING AND TECHNOLOGY
SUBJECT NAME: INTEGRATED ELECTRONICS NAME: muzzamil shah
ROLL NO: 2020-EE-076
SECTION: B

not ng1(abar,a);

not ng2(bbar,b);

pmos p1(x,vdd,abar);

pmos p2(out,x,b);

pmos p3(y,vdd,a);

pmos p4(out,y,bbar);

nmos n1(out,w,a);

nmos n2(w,gnd,b);

nmos n3(out,z,abar);

nmos n4(z,gnd,bbar);

endmodule

//And gate Module

module andgate(out,a,b);

input a,b;

output out;

wire x,y;

supply1 vdd;

supply0 gnd;

pmos p1(y,vdd,a);

pmos p2(y,vdd,b);

pmos p3(out,vdd,y);

nmos n1(y,x,a);

nmos n2(x,gnd,b);

nmos n3(out,gnd,y);

13
DEPARTMENT OF ELECTRONIC ENGINEERING
SIR SYED UNIVERSITY OF ENGINEERING AND TECHNOLOGY
SUBJECT NAME: INTEGRATED ELECTRONICS NAME: muzzamil shah
ROLL NO: 2020-EE-076
SECTION: B

endmodule

//Or gate Module

module orgate(out,a,b);

input a,b;

output out;

wire x,y;

supply1 vdd;

supply0 gnd;

pmos p1(x,vdd,a);

pmos p2(y,x,b);

pmos p3(out,vdd,y);

nmos n1(y,gnd,a);

nmos n2(y,gnd,b);

nmos n3(out,gnd,y);

endmodule

//design Main module

module circuit(out,cout,a,b,cin);

input a,b,cin;

output out,cout;

wire x,y,z;

supply1 vdd;

supply0 gnd;

xorgate x1(x,a,b);

xorgate x2(out,x,cin);

14
DEPARTMENT OF ELECTRONIC ENGINEERING
SIR SYED UNIVERSITY OF ENGINEERING AND TECHNOLOGY
SUBJECT NAME: INTEGRATED ELECTRONICS NAME: muzzamil shah
ROLL NO: 2020-EE-076
SECTION: B

andgate a1(y,a,b);

andgate a2(z,x,cin);

orgate o1(cout,y,z);

endmodule

//stimulus module

module muzzamil;

reg a,b,cin;

wire out,cout;

circuit xgate(out,cout,a,b,cin);

initial

begin

a=1'b0; b=1'b0; cin=1'b0; //d=1'b1;

#30

a=1'b0; b=1'b0; cin=1'b1; //d=1'b0;

#30

a=1'b0; b=1'b1; cin=1'b0; //d=1'b1;

#30

a=1'b0; b=1'b1; cin=1'b1; //d=1'b0;

#30

a=1'b1; b=1'b0; cin=1'b0; //d=1'b1;

#30

a=1'b1; b=1'b0; cin=1'b1; //d=1'b0;

#30

a=1'b1; b=1'b1; cin=1'b0; //d=1'b1;

15
DEPARTMENT OF ELECTRONIC ENGINEERING
SIR SYED UNIVERSITY OF ENGINEERING AND TECHNOLOGY
SUBJECT NAME: INTEGRATED ELECTRONICS NAME: muzzamil shah
ROLL NO: 2020-EE-076
SECTION: B

#30

a=1'b1; b=1'b1; cin=1'b1; //d=1'b0;

#30

$finish;

end

endmodule

RESULT:

16
DEPARTMENT OF ELECTRONIC ENGINEERING
SIR SYED UNIVERSITY OF ENGINEERING AND TECHNOLOGY