EPE1301 Computing Systems

 Registers & Memory

 Address Mapping & Decoding

Dr Kwee Hiong Lee

kweehiong.lee@singaporetech.edu.sg
Registers & Memory
 Register

 A register is a parallel set of N flip-flops, with all

clock lines connected together.
 Typically, N is equal to the machine word length.
In a 32-bit CPU, you are likely to find 32-bit registers.
 Registers are used as high-speed memory.
 Random Access Memory (RAM)

 Small amounts of memory:

• A flip-flop can store one bit of information.
• A register can store a single word, typically 32 bits.
 Random access memory, or RAM, allows us to store
larger amounts of data.
We need this to put together a working computer,
which typically needs gigabytes of memory.
 RAM (2)

 RAM provides large quantities of temporary storage

(lost when the power is switched off).
• It should be able to store a value.
• You should be able to read a value that was saved.
• You should be able to change a stored value.
 An address specifies the memory value we are
interested in. Each value can be a multiple-bit word.
 A RAM should therefore be able to:
- Store many words, one per address
- Read the word that was saved at an address
- Change the word that’s saved at an address
 RAM (3)

 You can think of computer memory as

being one big array of data.
• The address serves as an array index.
• Each address refers to one word of data.
 You can read or modify the data at any
given memory address, just like you
can read or modify the contents of an
array at any given index.
 What does the hardware look like?
 Memory organisation

 Large memories (millions of bits) simply contain large

numbers of flip-flops. They need to be organised
specially to keep the pin count acceptable.
 A typical setup is shown on the
next slide. Abbreviations used:
A = Address
I = Input data
D = Data output
W = word select line
CS = chip select
RD = read/write
OE = output enable
Memory organisation
 Memory organisation (2)
This is a 4 × 3 memory (4 locations each 3 bits wide). Every
column acts as a unit.
A1
A0

Input Bit 0

Input Bit 1
Output Bit 0

Output Bit 1

Input Bit 2
Output Bit 2
 Memory organisation (2)

Read from mem : A1=1,A0=0,CS=1,RD=1,OE=1

A1
A0

Output Bit 0

Output Bit 1

Output Bit 2
 Memory organisation (2)

Write to mem : A1=0,A0=1,CS=1,RD=0,OE=0

A1
A0

Input Bit 0

Input Bit 1

Input Bit 2
 Memory organisation (3)

 Explanation of the diagram:

• CS must be set, otherwise nothing can happen. If
CS is set, this “tells” the device it has work to do.
• The address decoder sets one of the word select
lines, depending upon the incoming address.
• This causes the AND gates on the column of flip-
flops to be enabled.
• The values of that column appears on the outputs,
if OE and RD (meaning READ operation) are set.
• If RD is clear (meaning WRITE operation), the CK
lines on the enabled column are set and the
incoming data is written into the flip-flops.
 Memory organisation (4)

 Only 8 pins are required, even though there are

12 flip-flops with 3 pins each.
 This setup can easily be extended - just add more
rows and/or columns (and expand the decoder as
required).
 Note that in commercial designs, the same set of pins
is used for both input and output (and are usually
called D for Data). This is not shown in the diagram
for the sake of clarity, but it clearly means a major
reduction in pins.
 Register file

 Modern processors have a number of registers (32, 64

or even more) grouped together in a register file.
There are simply too many to cope with individually.
Individual registers are identified by an address.
 Here is a block symbol for a n
k
2 x n register file. Inside, it Data in
is organised the same way as R/W
k
RAM (with an address decoder address

and output buffers). Register File

 There are 2k registers, so register

addresses are k bits long. Each Data out

register holds an n-bit word, so the n

data inputs and outputs are n bits wide.

 Memory expansion

 Consider using 2K X 8 chips to build a 16-bit memory

As each chip provides 8 bits, 2 chips are required for 16-bits.

There are 11 A pins (A0-A10) and 8 D pins (D0-D7 or D8-D15) per
chip. Total memory size using TWO 2K x 8 chips is 4K bytes.
All the chips act simultaneously, on the same internal address.
Address Mapping & Decoding
 Address decoder

 I/O chips must have at least the following:

• RW line, to allow the CPU to tell the device what to
do.
• CS line, which indicates whether it is to do
something or not (i.e. selected or not selected)
• Registers for storing data to be transmitted to/from
the bus.
 Address decoder (2)

 Two related questions:

• How can the CPU access a register on an I/O chip?
• How does the I/O chip "know" that the CPU is trying
to access it?

 The most elegant solution is memory mapping. All

I/O devices "appear" in memory space, so that each
register in the device has “its own” address. When the
CPU reads or writes to the address, a read or write
operation takes place.
 Address decoder (3)

 Example: a 16-bit machine with 0000

EPROM
• 2K X 8 EPROM 07FF

• 2K X 8 RAM
• UART (needs 8 bytes, for mode,
status, transmit and receive registers)
8000
 The address space is 64K (0..FFFF) of RAM
which 4K+8 is needed. Possible choice 87FF
(of many):
• EPROM at address 0
• RAM at 32K = 8000 hex
• UART at FF00 (e.g. FF00 status, FF00 UART
FF02 mode, FF04 Tx, FF06 Rx) FF07
 Address decoder (4)

 Each device has an address decoder to check

whether it is being accessed. When the decoder
recognises the address, it sets the CS (Chip Select)
input of the device to 1, so it will start to work.

Address bus

Address Address Address

decoder 1 decoder 2 decoder 3

CS CS CS

EPROM RAM UART

 Address decoder (5)

 For example, the EPROM (size 2K = 211, so has 11

address lines) is accessed by addresses of the form
00000xxxxxxxxxxx.
 In other words, all addresses in the range 0 to 2K-1
have the five high order bits set to zero:
0000000000000000 0
0000000000000001 1
…………
0000011111111110 2K-2
0000011111111111 2K-1
 The decoder is a 5-input NOR gate:
 Address decoder (6)

 However, since the EPROM is the only chip in the

lower half of the address space, it is the only device
with bit A15 set to 0.
So, in this case, we can invert A15, and then connect
to CS (but then you cannot add another device in the
lower half of the address space).
 The RAM is accessed by addresses of the form
10000xxxxxxxxxxx. The decoder looks like:
 Address decoder (7)

 Example: a 16-bit machine with 0000

EPROM
• 2K X 8 EPROM 07FF
0800
RAM
• 2K X 8 RAM 0FFF
• UART (needs 8 bytes, for mode,
status, transmit and receive registers)
 The address space is 64K (0..FFFF) of
which 4K+8 is needed. Possible choice
(of many):
• EPROM at addresses 0x0000-0x07FF
• RAM at addresses 0x0800-0x0FFF
• UART at FF00 (e.g. FF00 status, FF00 UART
FF02 mode, FF04 Tx, FF06 Rx) FF07
 Address Mapping & Decoding

The RAM has 32k CY62256

address locations.
Microprocessor How many addr. SRAM
bits on it?
32k x 8
32,768 = 215,so 15
address bits. DAT ADR OE WE

DAT ADR R/W DS DTACK

15

A0 - 14
20
8
 0
Suppose we have 4 of the 32k x 8 memories, and need 32k x 8
to design the memory map and decoding. CE SRAM
0000 0000 0000 0000 0000 - 0000 0111 1111 1111 1111 RAM 0 DAT ADR OE
OEWE
WE
00000 - 07FFF RAM 0 1
08000 - 0FFFF RAM 1 2-4 X0 32k x 8
10000 - 17FFF RAM 2 DEC CE SRAM
A15 X1 DAT ADR OE
OEWE
WE
18000 – 1FFFF RAM 3
A0 2
A16
DAT ADR R/W DS DTACK A1 X2
32k x 8
CE SRAM
X3
2-to-4 decoder: E DAT ADR OE WE
A1 A0 X3 X2 X1 X0 3
0 0 1 1 1 0
0 1 1 1 0 1 32k x 8
1 0 1 0 1 1 CE SRAM
1 1 0 1 1 1 A0 - 1
DAT ADR OE WE

20 A15-16 A0-14