Download as docx, pdf, or txt
Download as docx, pdf, or txt
You are on page 1of 3

Did you know?

a D (data) latch, or transparent latch, is a modification of the gated SR latch because it


prevents problems when both inputs are logic 1.

Here is another information, When the enable input of the D latch is high, the Q output always reflects
the logic level present at the D input. Another is when the input to the D latch falls to logic 0, the latch is
disabled or "closed" and the Q output holds its last value regardless of the D input.

The enable input to the gated S-R latch provides a way to latch the Q and non-Q outputs regardless of
the state of S or R, so remove one of these inputs to create an "illegal" input. You can create a
multivibrator latch circuit without having to state.

Such a circuit is called a D Latch and its internal logic looks like this:

Note that the R input has been replaced with the complement (inverted) of the old S input, and the S
input has been renamed to D. Similar to gated S-R latches, when the enable input is 0, the D latch does
not respond to signal inputs and remains latched in its last state. However, when the enable input is 1,
the Q output follows the D input. There is no "invalid" or "illegal" state for this latch because the R input
in the S-R circuit has been removed. Q and non-Q are always opposites.

If the above diagram is confusing, the following diagram simplifies the concept.
Like both the S-R and gated S-R latches, the D latch circuit may be found as its own
prepackaged circuit, complete with a standard symbol:

The D latch is nothing more than a gated S-R latch with an inverter added to make R the
complement (inverse) of S.
Let’s explore the ladder logic equivalent of a D latch, modified from the basic ladder diagram of
an S-R latch:
One application for D latches is in 1-bit memory circuits. To "write" (store) a 0 or 1 bit in this
latch circuit, set the enable input high (1) and set the bit to store D to whatever. When the
enable input goes low (0), the latch ignores the state of the D input, happily latches the stored
bit value, outputs the stored value on Q, and its inverse on any non-Q output. output.

You might also like