NITTE-574 110, KARNATAKA, INDIA

(ISO 9001:2015 Certified, Accredited with ‘A’ Grade by NAAC)

DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING

(Accredited by NBA)

DIGITAL SYSTEM DESIGN

21EE303
 Digital System Design 21EE303

DIGITAL SYSTEM DESIGN

Course Code 21EE303 Course Type IPCC

Teaching Hours/Week (L:T:P: S) 3:0:2 Credits 04
Total Teaching Hours 40+0+25 CIE + SEE Marks 50+50

Course Outcomes: At the end of the course student will be able to

1. Recall basic gates, Boolean algebra and apply K-map technique to simplify Boolean expressions.
2. Design combinational logic circuits for the given requirements.
3. Identify and describe working of latches and Flip Flops.
4. Design of sequential logic circuits for the given specifications.
5. Design clocked synchronous sequential networks and comprehend the operation of digital
integrated circuits

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 Digital System Design 21EE303

LIST OF EXPERIMENTS

1. a) Introduction to Basic gates, Universal gates

b) Realization of Combinational logic circuits
2. Realizations of adders and subtractors using basic and universal gates.
3. Realization of one- and two-bit comparator using logic gates.
4. Realization of multiplexer and demultiplexer using logic gates and IC chips.
5. Realization of Flipflops using basic gates and IC chips
6. Realization of ripple counters using flip flops
7. Realization of synchronous counters using flip flops
8. Shift registers

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 Digital System Design 21EE303

Experiment 1a: Introduction to Basic gates, Universal gates

Aim: To study and verify the truth table of Logic Gates

Components:
1. IC7408
2. IC7404
3. IC7432
4. IC7486
5. IC7400
6. IC7411
7. IC Trainer kit
8. Patch
Chords

Truth table verification of Logic Gates:

1) AND Gate (2 inputs):

Logic Symbol Pin Diagram Truth Table

A B Y
0 0 0
A 0 1 0
Y
B 1 0 0
1 1 1

IC 7408

AND Gate (3 inputs): Pin Diagram

Truth Table
A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
IC74LS11 1 1 0 0
1 1 1 1

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 Digital System Design 21EE303

2) OR Gate (2 inputs):
Logic Symbol Pin Diagram Truth Table

A B Y
0 0 0
A 0 1 1
Y
B 1 0 1
1 1 1

IC 7432

3) NOT Gate (1 input):

Logic Symbol Pin Diagram Truth Table

A Y
0 1
A Y
1 0

IC 7404

4) EX-OR Gate (2 inputs):

Logic Symbol Pin Diagram Truth Table

A B Y
0 0 0
A 0 1 1
Y
B 1 0 1
1 1 0

IC 7486
5) NAND Gate (2 inputs):
Logic Symbol Pin Diagram Truth Table

A B Y
A 0 0 1
Y
B 0 1 1
1 0 1
1 1 0

IC 7400

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 Digital System Design 21EE303

6) NOR Gate (2 inputs):

Logic Symbol Pin Diagram Truth Table

A B Y
A 0 0 1
Y
B 0 1 0
1 0 0
1 1 0
IC 7402

Viva Questions:

1. List the different types of logic gates.

2. List the basic gates.
3. Differentiate between basic gate and universal gates.

Result/Inference:

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 Digital System Design 21EE303

Experiment 1b: Realization of Combinational logic circuits

Aim: To simplify and realize given Boolean functions using Basic gates/Universal gates.
Components:
1. IC7408
2. IC7432
3. IC7400
4. IC7402
7. IC Trainer
kit
8. Patch
Chords

(I) Design of combinational logic circuits using Logic gates:

Simplification:
𝒀 = 𝑨𝑩 + 𝑨 𝑩 + 𝑪 + 𝑩 𝑩 + 𝑪
= 𝑨𝑩 + 𝑨𝑩 + 𝑨𝑪 + 𝑩𝑩 + 𝑩𝑪 ∵ 𝑨 + 𝑨 = 𝑨; 𝑨. 𝑨 = 𝑨
= 𝑨𝑩 + 𝑨𝑪 + 𝑩(𝟏 + 𝑪) ∵ 𝟏 + 𝑪 = 𝟏
= 𝑩 𝟏 + 𝑨 + 𝑨𝑪
𝒀 = 𝑩 + 𝑨𝑪

➢ Realization:

(i) Using primary gates

Truth table
7408
A A B C Y
0 0 0 0
C 7432
0 0 1 0
Y = B+AC 0 1 0 1
B 0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

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 Digital System Design 21EE303

(ii)Using NAND gates only (SOP form)

Y = 𝑩 + 𝑨𝑪
= ̿̿̿̿̿̿̿̿̿̿
𝑩 + 𝑨𝑪
̅̅̅̅̅̅̅̅̅̅̅̅
Y = 𝑩 ̅ ̅̅̅̅̅̅
𝑨𝑪 ( using De Morgon’s Theorem)

7400
B
7400
Y = B+AC

A
C
7400

(iii) Using NOR gates only (POS form)

Y = 𝑩 + 𝑨𝑪
= 𝑩 + 𝑨 𝑩 + 𝑪 (using Distributive property)
̅ = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝒀 𝑩+𝑨 𝑩+𝑪
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝒀 = 𝑨 + 𝑩 + ̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅ 𝑩+𝑪

7402
A
7402
B Y = B+AC

C
7402

Viva Questions:

1. State and prove De Morgan’s theorems.

2. Define the basic laws of Boolean algebra.
3. Explain the necessity of truth table.

Result/Inference:

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 Digital System Design 21EE303

Experiment 2: Realizations of adders and subtractors using basic and universal

gates.

Aim: To realize Half/Full adder and Half/Full Subtractor using Logic Gates.

Components:

1. IC7408
2. IC7432
3. IC7404
4. IC7486
5. IC Trainer kit
6. Patch
Chords

1. Half Adder:

Block Diagram: Truth Table:

Inputs Outputs
A B S C
Outputs

A S,Sum 0 0 0 0
Inputs

Half Adder
0 1 1 0
B C,Carry
1 0 1 0
1 1 0 1

Simplified Boolean Expressions:

̅ 𝑩 + 𝑨𝑩
𝑺=𝑨 ̅ = 𝑨⊕𝑩

𝑪 = 𝑨𝑩

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 Digital System Design 21EE303
Circuit Diagram:

A B

7486
S

7408
C

2.Full Adder:

Block Diagram: Truth Table:

Inputs Outputs
A A B Ci S Co
S,Sum Outputs
0 0 0 0 0
Inputs

B Full Adder
Co,Carry 0 0 1 1 0
Ci
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Simplified Boolean Expressions:

𝑺 = 𝑨 ⊕ 𝑩 ⊕ 𝑪𝒊

𝑪𝒐 = 𝑨𝑩 + 𝑪𝒊 𝑨 + 𝑩

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 Digital System Design 21EE303

Circuit Diagram:

A B Ci

7486

7486
S

7408
7432
Co

7432
7408

3.Half Subtractor:

Block Diagram: Truth Table:

Inputs Outputs
A B D Bo
Outputs

A D,Difference 0 0 0 0
Inputs

Half Subtractor
B Bo,Borrow 0 1 1 1
1 0 1 0
1 1 0 0

Simplified Boolean Expressions:

̅ 𝑩 + 𝑨𝑩
𝑫=𝑨 ̅ = 𝑨⊕𝑩

̅𝑩
𝑩𝒐 = 𝑨

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 Digital System Design 21EE303

Circuit Diagram:
A B

7486
D

7404
7408
Bo

4.Full Subtractor:

Block Diagram: Truth Table:

Inputs Outputs
A Outputs A B Bi D Bo
D,Difference
Inputs

Full Subtractor
0 0 0 0 0
B
Bo,Borrow 0 0 1 1 1
Bi
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Simplified Boolean Expressions:

𝑺 = 𝑨 ⊕ 𝑩 ⊕ 𝑩𝒊

̅ 𝑩 + 𝑩𝒊 𝑨
𝑩𝒐 = 𝑨 ̅ +𝑩

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 Digital System Design 21EE303

Circuit Diagram:

A B Bi

7404
7486
7486
D

7432

7408

7432
7408
Bo

Viva Questions:

1. Write the expression for half adder and explain its working?
2. With an expression explain the working of full adder?
3. Differentiate between half subtractor and full Subtractor?

Result/Inference:

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 Digital System Design 21EE303

Experiment 3: Realization of one- bit and two-bit comparator using logic gates.

Aim: Realization of one/ two-bit comparator (using logic gates) and to study magnitude
comparator (using IC7485)

Components:

1. IC7404
2. IC7408
3. IC7486
4. IC7432
5. IC7411
6. IC Trainer
kit
7. Patch
Chords

(I) One bit Comparator:

Block diagram: Truth Table:

Input Output
A A<B A B A<B A=B A>B
Inputs

Outputs

A=B
0 0 0 1 0
One Bit Comparator
B 0 1 1 0 0
A>B
1 0 0 0 1
1 1 0 1 0

Simplified Boolean Expressions:

𝑨<𝐵= 𝑨 ̅𝑩
̅ + 𝑨𝑩 = ̅̅̅̅̅̅̅̅̅
𝑨 = 𝑩 = 𝑨̅ 𝑩 𝑨⊕𝑩
𝑨 > 𝐵 = 𝐴𝑩 ̅

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 Digital System Design 21EE303
Circuit Diagram:

A B

7404 7404

7408
A>B

7408
A<B

7486 7404
A=B

(II) Two bit Comparator:

Block diagram: Truth Table:

Input A Input B Output

A1 A0 B1 B0 A<B A=B A>B
0 0 0 0 0 1 0
A1 A<B 0 1 1 0 0
Outputs

1 0 1 0 0
Inputs

A0
Two Bit Comparator A=B 1 1 1 0 0
B1
A>B
0 1 0 0 0 0 1
B0
0 1 0 1 0
1 0 1 0 0
1 1 1 0 0
1 0 0 0 0 0 1
0 1 0 0 1
1 0 0 1 0
1 1 1 0 0
1 1 0 0 0 0 1
0 1 0 0 1
1 0 0 0 1
1 1 0 1 0

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 Digital System Design 21EE303
Circuit Diagram:

A1 A0 B1 B0

7404 7404 7404 7404

7432

7411

7432
7408
A<B

7486 7404

7408
A=B
7486
7404

7432

7411

7432
7408
A>B

Simplified Boolean Expressions:

̅̅̅̅𝑩𝟏 + 𝑨𝟎
𝑨 < 𝐵 = 𝑨𝟏 ̅̅̅̅𝑩𝟎 𝑩𝟏 + 𝑨𝟏
̅̅̅̅

̅̅̅̅̅̅̅̅̅̅̅̅
𝑨 = 𝑩 = (𝑨𝟎 ̅̅̅̅̅̅̅̅̅̅̅̅
⊕ 𝑩𝟎) (𝑨𝟏 ⊕ 𝑩𝟏)

̅̅̅̅𝑨𝟏 + 𝑩𝟎
𝑨 > 𝐵 = 𝑩𝟏 ̅̅̅̅𝑨𝟎 𝑨𝟏 + 𝑩𝟏
̅̅̅̅

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 Digital System Design 21EE303

(III) Magnitude Comparator- IC 7485 (4 Bit Comparator):

Block Diagram: Pin Diagram:

Truth Table:

COMPARING INPUTS OUTPUTS

A3, B3 A2, B2 A1, B1 A0, B0 A<B A=B A>B
A3 > B3 X X X 0 0 1
A3 < B3 X X X 1 0 0
A3 = B3 A2 > B2 X X 0 0 1
A3 = B3 A2 < B2 X X 1 0 0
A3 = B3 A2 = B2 A1 > B1 X 0 0 1
A3 = B3 A2 = B2 A1 < B1 X 1 0 0
A3 = B3 A2 = B2 A1 = B1 A0 > B0 0 0 1
A3 = B3 A2 = B2 A1 = B1 A0 < B0 1 0 0
A3 = B3 A2 = B2 A1 = B1 A0 = B0 0 1 0

Viva Questions:

1. Define comparator
2. Explain the working of the comparator
3. What are the applications of comparator?

Result/Inference:

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 Digital System Design 21EE303

Experiment 4: Realization of multiplexer and demultiplexer using logic gates and

IC chips.

Aim: i) To verify the truth table of Multiplexer using IC74153 and to verify the Demultiplexer
using IC74139.

ii) To study the Arithmetic Circuits (Half/Full adder and Half/Full Subtractors)

Components:

1. IC74153
2. IC74139
3. IC7404
4. IC7486
5. IC7411
6. IC7420
7 IC7432
8. IC Trainer kit
9. Patch
Chords

A) Multiplexer:

I) 4:1 Multiplexer using Logic Gates:

Block diagram: Truth Table:

D0 Input Output
(Inputs)

D1 4:1
MUX Y 𝑺𝟏 𝑺𝟎 𝒀
D2 (Output)
D3 0 0 𝐷0
0 1 𝐷1
1 0 𝐷2
S1 S0 1 1 𝐷3
Selection
Inputs

Boolean Expression:

̅̅̅̅ 𝑺𝟎
𝒀 = 𝑺𝟏 ̅̅̅̅𝑫𝟎 + 𝑺𝟏
̅̅̅̅ 𝑺𝟎𝑫𝟏 + 𝑺𝟏 𝑺𝟎
̅̅̅̅𝑫𝟐 + 𝑺𝟏 𝑺𝟎𝑫𝟑

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 Digital System Design 21EE303
II) Half / Full Adder using IC74153:

Pin Diagram of IC74153: (Active High Output)

Function Table:

Select Inputs Enable Inputs Output

B A ̅̅̅̅
𝟏𝑮/𝟐𝑮̅̅̅̅ C0 C1 C2 C3 1Y/2Y
* * 1 * * * * 0
0 0 0 0 * * * 0
0 0 0 1 * * * 1
0 1 0 * 0 * * 0
0 1 0 * 1 * * 1
1 0 0 * * 0 * 0
1 0 0 * * 1 * 1
1 1 0 * * * 0 0
1 1 0 * * * 1 1

i) Half Adder:

Circuit Diagram: Truth Table:

Inputs Outputs
B A Sum Carry
1G 2G
0 0 0 0
0 1C0 0 1 1 0
1 1C1
1 1C2 1 0 1 0
74LS153

0 1C3 1Y Sum 1 1 0 1

0 2C0 2Y Carry
0 2C1
0 2C2
1 2C3

B A

B A

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 Digital System Design 21EE303

ii) Full Adder:

Circuit Diagram: Truth Table:

Cin

Inputs Outputs
1G 2G B A Cin Sum Carry
7404
1C0
0 0 0 0 0
1C1 0 0 1 1 𝑪𝒊𝒏 0 0
1C2
̅̅̅̅̅
74LS153
1C3 1Y Sum 0 1 0 1 𝑪𝒊𝒏 0 𝑪𝒊𝒏
0 1 1 0 1
0 2C0 2Y Carry
1 0 0 1 ̅̅̅̅̅
𝑪𝒊𝒏 0 𝑪𝒊𝒏
2C1
2C2 1 0 1 0 1
1 2C3
1 1 0 0 𝑪𝒊𝒏 1 1
B A 1 1 1 1 1

B A

Reduced Truth table

Inputs Outputs
B A Sum Carry
0 0 𝑪𝒊𝒏 0
0 1 ̅̅̅̅̅
𝑪𝒊𝒏 𝑪𝒊𝒏
1 0 ̅̅̅̅̅
𝑪𝒊𝒏 𝑪𝒊𝒏
1 1 𝑪𝒊𝒏 1

B) Demultiplexer:

I) 1:4 Demultiplexer using Logic Gates:

Block diagram:
Y0
(Outputs)

(Input) Din Y1
1:4
DE-MUX
Y2
(Enable) E
Y3

S1 S0
Selection
Inputs

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 Digital System Design 21EE303

Truth Table:

Enable Select Inputs Input Output

𝑬 𝑺𝟏 𝑺𝟎 𝑫𝒊𝒏 𝒀𝟎 𝒀𝟏 𝒀𝟐 𝒀𝟑
0 * * 0 0 0 0 0
1 0 0 0 0 0 0 0
1 0 0 1 1 0 0 0
1 0 1 0 0 0 0 0
1 0 1 1 0 1 0 0
1 1 0 0 0 0 0 0
1 1 0 1 0 0 1 0
1 1 1 0 0 0 0 0
1 1 1 1 0 0 0 1

Boolean Expressions:
1. 𝒀𝟎 = ̅̅̅̅
𝑺𝟏 ̅̅̅̅
𝑺𝟎𝑫𝒊𝒏𝑬
2. 𝒀𝟏 = ̅̅̅̅
𝑺𝟏 𝑺𝟎𝑫𝒊𝒏𝑬
3. 𝒀𝟐 = 𝑺𝟏 ̅̅̅̅
𝑺𝟎𝑫𝒊𝒏𝑬
4. 𝒀𝟑 = 𝑺𝟏𝑺𝟎𝑫𝒊𝒏𝑬

1. Half/Full Subtractor using IC74139:

Pin Diagram of IC74139: ( Active low Outputs)

Function Table:

Inputs Enable Outputs

B A ̅̅̅̅ ̅̅̅̅ ̅̅̅̅
𝟏𝑮/𝟐𝑮 𝒀𝟎 ̅̅̅̅
𝒀𝟏 ̅̅̅̅
𝒀𝟐 ̅̅̅̅
𝒀𝟑
* * 1 1 1 1 1
0 0 0 0 1 1 1
0 1 0 1 0 1 1
1 0 0 1 1 0 1
1 1 0 1 1 1 0
Half Subtractor

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 Digital System Design 21EE303

A 1A 1Y0
1B 1Y1 D
B 1Y2
~1G 1Y3 7400

74139 Bout
7404

TruthTable
Inputs Outputs
B A D Bout
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Full Subtractor

Truth Table
Inputs Outputs
B A Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

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 Digital System Design 21EE303

Viva Questions:

2. What are the applications of multiplexer and de-multiplexer?

3. How do you realize a given function using multiplexer?
4. What is the difference between multiplexer & demultiplexer?
5. In 2n to 1 multiplexer how many selection lines are there?
6. Compare multiplexer and demultiplexer

Result/Inference:

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 Digital System Design 21EE303

Experiment 5: Realization of Flipflops using basic gates and IC chips

Aim: Truth Table verification of Flip Flops: i) D Flip Flop

ii)T Flip Flop

iii)JK Master Slave Flip Flop

Components:

1. IC7404
2. IC7400
3. IC7411
4. IC7402
5. IC7474
6. IC7476
7. IC7410
8. IC
Trainer
kit
9. Patch
Chords

Circuit Diagram:

D-Flip Flop

D-flip flop using IC7474:

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 Digital System Design 21EE303

Truth Table:

D flipflop using gates D flipflop using IC 7474

D Qn Qn+1 State Input Output

0 X 0 Reset PRE’ CLR’ CLK D Q
1 X 1 Set L H X X H
X X Qn NC H L X X L
X 0 Qn NC H H ↑ H H
H H ↑ L L

Circuit Diagram:

T-flipflop using gates

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 Digital System Design 21EE303

T-flip flop using IC7476:

Truth Table:

T-flipflop using gates

Qn T Qn+1
0 0 Qn
0 1 Qn’
1 0 Qn
1 1 Qn’

T Flipflop using IC 7474

Input Output
SET’ RST’ CLK T Qn+1
0 1 X X 1
1 0 X X 0
1 1 ↑ 1 1
1 1 ↑ 0 1

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 Digital System Design 21EE303

JK-Flip Flop
Circuit Diagram:

JK-flip flop using IC7476

Truth Table:
JK-flipflop using gates
Qn J K Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0

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 Digital System Design 21EE303

JK-flipflop using IC7476

PRE’ CLR’ CLK J K Q Q’
L H X X X H L
H L X X X L H
L L X X X H H
H H ↑ L L Q0 Q0’
H H ↑ H L H L
H H ↑ L H L H
H H ↑ H H TOGGLE

Circuit Diagram: Master Slave JK- flip flop

Master Slave JK- flip flop

CLK J K Q
↑ 0 0 Qn
↑ 1 0 1
↑ 0 1 0
↑ 1 1 Qn ’

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 Digital System Design 21EE303

Viva Questions:

1. What is the difference between Flip-Flop & latch?

2. What is the advantage of edge triggering over level triggering?
3. List the applications of latches and flip flops?
4. Write the characteristic equation of SR and JK flipflop
5. Write the excitation table for D, T FF

Result/Inference:

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 Digital System Design 21EE303

Experiment 6: Realization of ripple counters using flip flops

Aim: To design i) mod-8 binary ripple counter using IC 7476

ii)mod-5 counter, decade counter using IC7490

Components:

1. IC7476
2. IC7490
3. IC Trainer
kit
4. Patch
Chords

Logic Diagram: Binary ripple mod-8 counter

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 Digital System Design 21EE303

Truth table:

Asynchronous mod-8 counter

CLK CLR’ PRE’ MSB B LSB

C A
0 L H 0 0 0
1 H L 1 1 1
2 H H 0 0 0
3 H H 0 0 1
4 H H 0 1 0
5 H H 0 1 1
6 H H 1 0 0
7 H H 1 0 1
8 H H 1 1 0
9 H H 1 1 1

Design of counters using IC7490

a) MOD 5 counter

Truth table

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 Digital System Design 21EE303

b) Decade counter

Truth table
CLK Qd Qc Qb Qa
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

Viva Questions:
1. What do you mean by a ripple counter?
2. What is a decade counter?
3. List the types of counters
Result/Inference:

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 Digital System Design 21EE303

Experiment 7: Realization of synchronous counters using flip flop

Aim: To design i) Synchronous mod-16 counter using IC 7476
ii)mod-n counter using IC 74192 and IC74193

Components:

1. IC7476
2. IC74192
3. IC74193
4. IC Trainer kit

5. Patch Chords

Circuit Diagram: Synchronous mod-16 counter

Truth table
Qd Qc Qb Qa
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0

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 Digital System Design 21EE303

1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

Design of counters using IC74192

1. BCD up counter using IC74192

Truth table

CLK Qd Qc Qb Qa
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

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 Digital System Design 21EE303

2. BCD down counter using IC74192

Truth table
CLK Qd Qc Qb Qa
0 1 0 0 1
1 1 0 0 0
2 0 1 1 1
3 0 1 1 0
4 0 1 0 1
5 0 1 0 0
6 0 0 1 1
7 0 0 1 0
8 0 0 0 1
9 0 0 0 0

3. Binary up counter using IC74193

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 Digital System Design 21EE303

Truth table

CLK Qd Qc Qb Qa
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

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 Digital System Design 21EE303

4. Binary down counter using IC74193

Truth table

CLK Qd Qc Qb Qa
0 1 1 1 1
1 1 1 1 0
2 1 1 0 1
3 1 1 0 0
4 1 0 1 1
5 1 0 1 0
6 1 0 0 1
7 1 0 0 0
8 0 1 1 1
9 0 1 1 0
10 0 1 0 1
11 0 1 0 0
12 0 0 1 1
13 0 0 1 0
14 0 0 0 1
15 0 0 0 0

Viva Questions:

1.What are synchronous counters,

2.What are the advantages of synchronous counters?

Result/Inference:

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 Digital System Design 21EE303

Experiment.8: Shift Registers

Aim: To realize and study of Shift Register operation:

1) Circular Shift Right 2) Shift Left 3) SISO

4) SIPO 5) PISO 6) PIPO

Components:

1. IC7495
2. IC Trainer
kit
3. Patch
Chords

Procedure:

1. Verify all the components and patch chords.

2. Insert the appropriate IC into the IC base.
3. Connect VCC and GND of IC to respective pins of IC Trainer Kit.
4. Clear all the flip flop outputs of IC 7495 by loading A=B=C=D=0 with Mode = 1 and
clock at Clk2.
5. Make connections as shown in the logical diagram.

Circular Shift Right Operation:

6. Set SER= 1. Apply one clock pulse at clk1. This data appears at QA.
7. Now remove SER=1 and connect it to QD o/p. This QA o/p is shifted right and
circulated by applying the clock pulses.
8. The outputs are available at QA, QB, QC and QD. The QA o/p appears at QD at the end
of 4th clock pulse.
9. Each time record the output after the application of clock pulse.
(Note: 4 bit data can be applied to SER i/p)

Shift Left Operation:

10. Apply the first bit at ‘D’ i/p and apply one clock pulse at clk2. This data appears at
Q D.
11. Now the second bit is available at ‘D’ i/p and one clock pulse is applied. The bit
appears at QD to QC and the new bit appears at QD.
12. Step 11 is repeated until all the 4 bits are entered one by one.
13. At the end of the 4th clock pulse all the 4 bits are available at QA, QB, QC and QD.
14. Each time record the output after the application of clock pulse.

Serial In Serial Out (SISO)(Shift Right) Operation:

15. Apply 4-bit data at ‘SER’ input one by one, starting from LSB. Apply one clock pulse
for each bit at Clk1.
16. At the end of 4th clock pulse the LSB bit appears at QD.
17. Observe only QD output. Apply the clock pulses till all the 4 bits come out from QD.
18. Each time record the output after the application of clock pulse.

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 Digital System Design 21EE303
Serial In Parallel Out (SIPO) Operation:
19. Apply 4-bit data at ‘SER’ input one by one, starting from LSB. Apply one clock pulse
for each bit at Clk1.
20. At the end of 4th clock pulse all the 4 bits appear at QA, QB, QC and QD.
21. Each time record the output after the application of clock pulse.

Parallel In Serial Out (PISO) Operation:

22. Load the required 4-bit data at A, B, C and D.
23. Apply one clock pulse. The data appear at A, B, C and D will appear at QA, QB, QC
and QD respectively.
24. Now made Mode=0, apply the clock pulse one at a time and observe the data coming
out serially at QD.
25. Each time record the output after the application of clock pulse.

Parallel in parallel out (PIPO) operation:

26. Load the required 4-bit data at A, B, C and D.
27. Apply one clock pulse at Clk2.
28. The data appear at A, B, C and D will appear at QA, QB, QC and QD respectively.
29. Each time record the output after the application of clock pulse.

Shift Register Operation using IC 7495:

Serial loading Clk1 Mode 0

Shift right Clk1 Mode 0
Shift left Clk2 Mode 1
Parallel loading Clk2 Mode 1

Pin Diagram of IC7495:

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 Digital System Design 21EE303

1. Circular Shift Right Operation:

Logic Diagram: Function Table:

Clk1 QA QB QC QD
↓ 1 0 0 0
↓ 0 1 0 0
↓ 0 0 1 0
↓ 0 0 0 1
↓ 1 0 0 0
↓ 0 1 0 0
↓ 0 0 1 0
↓ 0 0 0 1
↓ 1 0 0 0

2. Shift Left Operation:

Logic Diagram:

Function Table:
Data: 1101

Clk2 Mode Input (D) QA QB QC QD

↓ 1 1 0 0 0 1
↓ 1 0 0 0 1 0
↓ 1 1 0 1 0 1
↓ 1 1 1 0 1 1
↓ 1 X 0 1 1 x
↓ 1 x 1 1 x x
↓ 1 x 1 x x x

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 Digital System Design 21EE303

3. Serial In Serial Out Operation:

Logic Diagram:

Function Table:
Data: 1011
Clk1 Mode SER QA QB QC QD
↓ 0 1 1 0 0 0
↓ 0 1 1 1 0 0
↓ 0 0 0 1 1 0
↓ 0 1 1 0 1 1
↓ 0 x x 1 0 1
↓ 0 x x x 1 0
↓ 0 x x x x 1

4. Serial In Parallel Out Operation:

Logic Diagram:

Function Table:
Data: 1011
Clk1 Mode SER QA QB QC QD
↓ 0 1 1 0 0 0
↓ 0 1 1 1 0 0
↓ 0 0 0 1 1 0
↓ 0 1 1 0 1 1

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 Digital System Design 21EE303

5. Parallel In Serial Out Operation:

Logic Diagram:

Function Table:
Data: 1010
Clk Mode A B C D QA QB QC QD
↓ 1 1 0 1 0 1 0 1 0
↓ 0 x x x x x 1 0 1
↓ 0 x x x x x x 1 0
↓ 0 x x x x x x x 1

6. Parallel in parallel out Operation :

Logic Diagram:

Function Table:
Data: 1011
Clk2 Mode A B C D QA QB QC QD
↓ 1 1 0 1 1 1 0 1 1

Viva Questions:

1.What is Register? What is a difference between register and Counter?

2. Explain the working of shift register.

3.List different types of shift registers.

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 Digital System Design 21EE303

Result/Inference:

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